1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <asm/arch/cpu.h> 14 #include <asm/unaligned.h> 15 #include <asm/io.h> 16 #include <linux/list.h> 17 #include <linux/media-bus-format.h> 18 #include <clk.h> 19 #include <asm/arch/clock.h> 20 #include <linux/err.h> 21 #include <linux/ioport.h> 22 #include <dm/device.h> 23 #include <dm/read.h> 24 #include <fixp-arith.h> 25 #include <syscon.h> 26 27 #include "rockchip_display.h" 28 #include "rockchip_crtc.h" 29 #include "rockchip_connector.h" 30 31 /* System registers definition */ 32 #define RK3568_REG_CFG_DONE 0x000 33 #define CFG_DONE_EN BIT(15) 34 35 #define RK3568_VERSION_INFO 0x004 36 #define EN_MASK 1 37 38 #define RK3568_AUTO_GATING_CTRL 0x008 39 40 #define RK3568_SYS_AXI_LUT_CTRL 0x024 41 #define LUT_DMA_EN_SHIFT 0 42 43 #define RK3568_DSP_IF_EN 0x028 44 #define RGB_EN_SHIFT 0 45 #define HDMI0_EN_SHIFT 1 46 #define EDP0_EN_SHIFT 3 47 #define MIPI0_EN_SHIFT 4 48 #define MIPI1_EN_SHIFT 20 49 #define LVDS0_EN_SHIFT 5 50 #define LVDS1_EN_SHIFT 24 51 #define BT1120_EN_SHIFT 6 52 #define BT656_EN_SHIFT 7 53 #define IF_MUX_MASK 3 54 #define RGB_MUX_SHIFT 8 55 #define HDMI0_MUX_SHIFT 10 56 #define EDP0_MUX_SHIFT 14 57 #define MIPI0_MUX_SHIFT 16 58 #define MIPI1_MUX_SHIFT 21 59 #define LVDS0_MUX_SHIFT 18 60 #define LVDS1_MUX_SHIFT 25 61 62 #define RK3568_DSP_IF_CTRL 0x02c 63 #define LVDS_DUAL_EN_SHIFT 0 64 #define LVDS_DUAL_LEFT_RIGHT_EN_SHIFT 1 65 #define LVDS_DUAL_SWAP_EN_SHIFT 2 66 #define RK3568_DSP_IF_POL 0x030 67 #define IF_CTRL_REG_DONE_IMD_MASK 1 68 #define IF_CTRL_REG_DONE_IMD_SHIFT 28 69 #define IF_CRTL_MIPI_DCLK_POL_SHIT 19 70 #define IF_CRTL_EDP_DCLK_POL_SHIT 15 71 #define IF_CRTL_HDMI_DCLK_POL_SHIT 7 72 #define IF_CRTL_HDMI_PIN_POL_MASK 0x7 73 #define IF_CRTL_HDMI_PIN_POL_SHIT 4 74 #define IF_CRTL_RGB_LVDS_DCLK_POL_SHIT 3 75 #define RK3568_SYS_OTP_WIN_EN 0x50 76 #define OTP_WIN_EN_SHIFT 0 77 #define RK3568_SYS_LUT_PORT_SEL 0x58 78 #define GAMMA_PORT_SEL_MASK 0x3 79 #define GAMMA_PORT_SEL_SHIFT 0 80 81 #define RK3568_VP0_LINE_FLAG 0x70 82 #define RK3568_VP1_LINE_FLAG 0x74 83 #define RK3568_VP2_LINE_FLAG 0x78 84 #define RK3568_SYS0_INT_EN 0x80 85 #define RK3568_SYS0_INT_CLR 0x84 86 #define RK3568_SYS0_INT_STATUS 0x88 87 #define RK3568_SYS1_INT_EN 0x90 88 #define RK3568_SYS1_INT_CLR 0x94 89 #define RK3568_SYS1_INT_STATUS 0x98 90 #define RK3568_VP0_INT_EN 0xA0 91 #define RK3568_VP0_INT_CLR 0xA4 92 #define RK3568_VP0_INT_STATUS 0xA8 93 #define RK3568_VP1_INT_EN 0xB0 94 #define RK3568_VP1_INT_CLR 0xB4 95 #define RK3568_VP1_INT_STATUS 0xB8 96 #define RK3568_VP2_INT_EN 0xC0 97 #define RK3568_VP2_INT_CLR 0xC4 98 #define RK3568_VP2_INT_STATUS 0xC8 99 100 /* Overlay registers definition */ 101 #define RK3568_OVL_CTRL 0x600 102 #define OVL_PORT_MUX_REG_DONE_IMD_SHIFT 28 103 #define RK3568_OVL_LAYER_SEL 0x604 104 #define LAYER_SEL_MASK 0xf 105 106 #define RK3568_OVL_PORT_SEL 0x608 107 #define PORT_MUX_MASK 0xf 108 #define PORT_MUX_SHIFT 0 109 #define LAYER_SEL_PORT_MASK 0x3 110 #define LAYER_SEL_PORT_SHIFT 16 111 112 #define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610 113 #define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614 114 #define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618 115 #define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C 116 #define RK3568_MIX0_SRC_COLOR_CTRL 0x650 117 #define RK3568_MIX0_DST_COLOR_CTRL 0x654 118 #define RK3568_MIX0_SRC_ALPHA_CTRL 0x658 119 #define RK3568_MIX0_DST_ALPHA_CTRL 0x65C 120 #define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0 121 #define RK3568_HDR0_DST_COLOR_CTRL 0x6C4 122 #define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8 123 #define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC 124 #define RK3568_VP0_BG_MIX_CTRL 0x6E0 125 #define BG_MIX_CTRL_MASK 0xff 126 #define BG_MIX_CTRL_SHIFT 24 127 #define RK3568_VP1_BG_MIX_CTRL 0x6E4 128 #define RK3568_VP2_BG_MIX_CTRL 0x6E8 129 #define RK3568_CLUSTER_DLY_NUM 0x6F0 130 #define RK3568_SMART_DLY_NUM 0x6F8 131 132 /* Video Port registers definition */ 133 #define RK3568_VP0_DSP_CTRL 0xC00 134 #define OUT_MODE_MASK 0xf 135 #define OUT_MODE_SHIFT 0 136 #define DATA_SWAP_MASK 0x1f 137 #define DATA_SWAP_SHIFT 8 138 #define DSP_RB_SWAP 2 139 #define CORE_DCLK_DIV_EN_SHIFT 4 140 #define P2I_EN_SHIFT 5 141 #define DSP_FILED_POL 6 142 #define INTERLACE_EN_SHIFT 7 143 #define POST_DSP_OUT_R2Y_SHIFT 15 144 #define PRE_DITHER_DOWN_EN_SHIFT 16 145 #define DITHER_DOWN_EN_SHIFT 17 146 #define DSP_LUT_EN_SHIFT 28 147 148 #define STANDBY_EN_SHIFT 31 149 150 #define RK3568_VP0_MIPI_CTRL 0xC04 151 #define DCLK_DIV2_SHIFT 4 152 #define DCLK_DIV2_MASK 0x3 153 #define MIPI_DUAL_EN_SHIFT 20 154 #define MIPI_DUAL_SWAP_EN_SHIFT 21 155 156 #define RK3568_VP0_COLOR_BAR_CTRL 0xC08 157 #define RK3568_VP0_3D_LUT_CTRL 0xC10 158 #define VP0_3D_LUT_EN_SHIFT 0 159 #define VP0_3D_LUT_UPDATE_SHIFT 2 160 161 #define RK3568_VP0_3D_LUT_MST 0xC20 162 163 #define RK3568_VP0_DSP_BG 0xC2C 164 #define RK3568_VP0_PRE_SCAN_HTIMING 0xC30 165 #define RK3568_VP0_POST_DSP_HACT_INFO 0xC34 166 #define RK3568_VP0_POST_DSP_VACT_INFO 0xC38 167 #define RK3568_VP0_POST_SCL_FACTOR_YRGB 0xC3C 168 #define RK3568_VP0_POST_SCL_CTRL 0xC40 169 #define RK3568_VP0_POST_DSP_VACT_INFO_F1 0xC44 170 #define RK3568_VP0_DSP_HTOTAL_HS_END 0xC48 171 #define RK3568_VP0_DSP_HACT_ST_END 0xC4C 172 #define RK3568_VP0_DSP_VTOTAL_VS_END 0xC50 173 #define RK3568_VP0_DSP_VACT_ST_END 0xC54 174 #define RK3568_VP0_DSP_VS_ST_END_F1 0xC58 175 #define RK3568_VP0_DSP_VACT_ST_END_F1 0xC5C 176 177 #define RK3568_VP0_BCSH_CTRL 0xC60 178 #define BCSH_CTRL_Y2R_SHIFT 0 179 #define BCSH_CTRL_Y2R_MASK 0x1 180 #define BCSH_CTRL_Y2R_CSC_MODE_SHIFT 2 181 #define BCSH_CTRL_Y2R_CSC_MODE_MASK 0x3 182 #define BCSH_CTRL_R2Y_SHIFT 4 183 #define BCSH_CTRL_R2Y_MASK 0x1 184 #define BCSH_CTRL_R2Y_CSC_MODE_SHIFT 6 185 #define BCSH_CTRL_R2Y_CSC_MODE_MASK 0x3 186 187 #define RK3568_VP0_BCSH_BCS 0xC64 188 #define BCSH_BRIGHTNESS_SHIFT 0 189 #define BCSH_BRIGHTNESS_MASK 0xFF 190 #define BCSH_CONTRAST_SHIFT 8 191 #define BCSH_CONTRAST_MASK 0x1FF 192 #define BCSH_SATURATION_SHIFT 20 193 #define BCSH_SATURATION_MASK 0x3FF 194 #define BCSH_OUT_MODE_SHIFT 30 195 #define BCSH_OUT_MODE_MASK 0x3 196 197 #define RK3568_VP0_BCSH_H 0xC68 198 #define BCSH_SIN_HUE_SHIFT 0 199 #define BCSH_SIN_HUE_MASK 0x1FF 200 #define BCSH_COS_HUE_SHIFT 16 201 #define BCSH_COS_HUE_MASK 0x1FF 202 203 #define RK3568_VP0_BCSH_COLOR 0xC6C 204 #define BCSH_EN_SHIFT 31 205 #define BCSH_EN_MASK 1 206 207 #define RK3568_VP1_DSP_CTRL 0xD00 208 #define RK3568_VP1_MIPI_CTRL 0xD04 209 #define RK3568_VP1_COLOR_BAR_CTRL 0xD08 210 #define RK3568_VP1_PRE_SCAN_HTIMING 0xD30 211 #define RK3568_VP1_POST_DSP_HACT_INFO 0xD34 212 #define RK3568_VP1_POST_DSP_VACT_INFO 0xD38 213 #define RK3568_VP1_POST_SCL_FACTOR_YRGB 0xD3C 214 #define RK3568_VP1_POST_SCL_CTRL 0xD40 215 #define RK3568_VP1_DSP_HACT_INFO 0xD34 216 #define RK3568_VP1_DSP_VACT_INFO 0xD38 217 #define RK3568_VP1_POST_DSP_VACT_INFO_F1 0xD44 218 #define RK3568_VP1_DSP_HTOTAL_HS_END 0xD48 219 #define RK3568_VP1_DSP_HACT_ST_END 0xD4C 220 #define RK3568_VP1_DSP_VTOTAL_VS_END 0xD50 221 #define RK3568_VP1_DSP_VACT_ST_END 0xD54 222 #define RK3568_VP1_DSP_VS_ST_END_F1 0xD58 223 #define RK3568_VP1_DSP_VACT_ST_END_F1 0xD5C 224 225 #define RK3568_VP2_DSP_CTRL 0xE00 226 #define RK3568_VP2_MIPI_CTRL 0xE04 227 #define RK3568_VP2_COLOR_BAR_CTRL 0xE08 228 #define RK3568_VP2_PRE_SCAN_HTIMING 0xE30 229 #define RK3568_VP2_POST_DSP_HACT_INFO 0xE34 230 #define RK3568_VP2_POST_DSP_VACT_INFO 0xE38 231 #define RK3568_VP2_POST_SCL_FACTOR_YRGB 0xE3C 232 #define RK3568_VP2_POST_SCL_CTRL 0xE40 233 #define RK3568_VP2_DSP_HACT_INFO 0xE34 234 #define RK3568_VP2_DSP_VACT_INFO 0xE38 235 #define RK3568_VP2_POST_DSP_VACT_INFO_F1 0xE44 236 #define RK3568_VP2_DSP_HTOTAL_HS_END 0xE48 237 #define RK3568_VP2_DSP_HACT_ST_END 0xE4C 238 #define RK3568_VP2_DSP_VTOTAL_VS_END 0xE50 239 #define RK3568_VP2_DSP_VACT_ST_END 0xE54 240 #define RK3568_VP2_DSP_VS_ST_END_F1 0xE58 241 #define RK3568_VP2_DSP_VACT_ST_END_F1 0xE5C 242 243 /* Cluster0 register definition */ 244 #define RK3568_CLUSTER0_WIN0_CTRL0 0x1000 245 #define RK3568_CLUSTER0_WIN0_CTRL1 0x1004 246 #define RK3568_CLUSTER0_WIN0_YRGB_MST 0x1010 247 #define RK3568_CLUSTER0_WIN0_CBR_MST 0x1014 248 #define RK3568_CLUSTER0_WIN0_VIR 0x1018 249 #define RK3568_CLUSTER0_WIN0_ACT_INFO 0x1020 250 #define RK3568_CLUSTER0_WIN0_DSP_INFO 0x1024 251 #define RK3568_CLUSTER0_WIN0_DSP_ST 0x1028 252 #define RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB 0x1030 253 #define RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE 0x1054 254 #define RK3568_CLUSTER0_WIN0_AFBCD_HDR_PTR 0x1058 255 #define RK3568_CLUSTER0_WIN0_AFBCD_VIR_WIDTH 0x105C 256 #define RK3568_CLUSTER0_WIN0_AFBCD_PIC_SIZE 0x1060 257 #define RK3568_CLUSTER0_WIN0_AFBCD_PIC_OFFSET 0x1064 258 #define RK3568_CLUSTER0_WIN0_AFBCD_DSP_OFFSET 0x1068 259 #define RK3568_CLUSTER0_WIN0_AFBCD_CTRL 0x106C 260 261 #define RK3568_CLUSTER0_WIN1_CTRL0 0x1080 262 #define RK3568_CLUSTER0_WIN1_CTRL1 0x1084 263 #define RK3568_CLUSTER0_WIN1_YRGB_MST 0x1090 264 #define RK3568_CLUSTER0_WIN1_CBR_MST 0x1094 265 #define RK3568_CLUSTER0_WIN1_VIR 0x1098 266 #define RK3568_CLUSTER0_WIN1_ACT_INFO 0x10A0 267 #define RK3568_CLUSTER0_WIN1_DSP_INFO 0x10A4 268 #define RK3568_CLUSTER0_WIN1_DSP_ST 0x10A8 269 #define RK3568_CLUSTER0_WIN1_SCL_FACTOR_YRGB 0x10B0 270 #define RK3568_CLUSTER0_WIN1_AFBCD_ROTATE_MODE 0x10D4 271 #define RK3568_CLUSTER0_WIN1_AFBCD_HDR_PTR 0x10D8 272 #define RK3568_CLUSTER0_WIN1_AFBCD_VIR_WIDTH 0x10DC 273 #define RK3568_CLUSTER0_WIN1_AFBCD_PIC_SIZE 0x10E0 274 #define RK3568_CLUSTER0_WIN1_AFBCD_PIC_OFFSET 0x10E4 275 #define RK3568_CLUSTER0_WIN1_AFBCD_DSP_OFFSET 0x10E8 276 #define RK3568_CLUSTER0_WIN1_AFBCD_CTRL 0x10EC 277 278 #define RK3568_CLUSTER0_CTRL 0x1100 279 280 #define RK3568_CLUSTER1_WIN0_CTRL0 0x1200 281 #define RK3568_CLUSTER1_WIN0_CTRL1 0x1204 282 #define RK3568_CLUSTER1_WIN0_YRGB_MST 0x1210 283 #define RK3568_CLUSTER1_WIN0_CBR_MST 0x1214 284 #define RK3568_CLUSTER1_WIN0_VIR 0x1218 285 #define RK3568_CLUSTER1_WIN0_ACT_INFO 0x1220 286 #define RK3568_CLUSTER1_WIN0_DSP_INFO 0x1224 287 #define RK3568_CLUSTER1_WIN0_DSP_ST 0x1228 288 #define RK3568_CLUSTER1_WIN0_SCL_FACTOR_YRGB 0x1230 289 #define RK3568_CLUSTER1_WIN0_AFBCD_ROTATE_MODE 0x1254 290 #define RK3568_CLUSTER1_WIN0_AFBCD_HDR_PTR 0x1258 291 #define RK3568_CLUSTER1_WIN0_AFBCD_VIR_WIDTH 0x125C 292 #define RK3568_CLUSTER1_WIN0_AFBCD_PIC_SIZE 0x1260 293 #define RK3568_CLUSTER1_WIN0_AFBCD_PIC_OFFSET 0x1264 294 #define RK3568_CLUSTER1_WIN0_AFBCD_DSP_OFFSET 0x1268 295 #define RK3568_CLUSTER1_WIN0_AFBCD_CTRL 0x126C 296 297 #define RK3568_CLUSTER1_WIN1_CTRL0 0x1280 298 #define RK3568_CLUSTER1_WIN1_CTRL1 0x1284 299 #define RK3568_CLUSTER1_WIN1_YRGB_MST 0x1290 300 #define RK3568_CLUSTER1_WIN1_CBR_MST 0x1294 301 #define RK3568_CLUSTER1_WIN1_VIR 0x1298 302 #define RK3568_CLUSTER1_WIN1_ACT_INFO 0x12A0 303 #define RK3568_CLUSTER1_WIN1_DSP_INFO 0x12A4 304 #define RK3568_CLUSTER1_WIN1_DSP_ST 0x12A8 305 #define RK3568_CLUSTER1_WIN1_SCL_FACTOR_YRGB 0x12B0 306 #define RK3568_CLUSTER1_WIN1_AFBCD_ROTATE_MODE 0x12D4 307 #define RK3568_CLUSTER1_WIN1_AFBCD_HDR_PTR 0x12D8 308 #define RK3568_CLUSTER1_WIN1_AFBCD_VIR_WIDTH 0x12DC 309 #define RK3568_CLUSTER1_WIN1_AFBCD_PIC_SIZE 0x12E0 310 #define RK3568_CLUSTER1_WIN1_AFBCD_PIC_OFFSET 0x12E4 311 #define RK3568_CLUSTER1_WIN1_AFBCD_DSP_OFFSET 0x12E8 312 #define RK3568_CLUSTER1_WIN1_AFBCD_CTRL 0x12EC 313 314 #define RK3568_CLUSTER1_CTRL 0x1300 315 316 /* Esmart register definition */ 317 #define RK3568_ESMART0_CTRL0 0x1800 318 #define RGB2YUV_EN_SHIFT 1 319 #define CSC_MODE_SHIFT 2 320 #define CSC_MODE_MASK 0x3 321 322 #define RK3568_ESMART0_CTRL1 0x1804 323 #define YMIRROR_EN_SHIFT 31 324 #define RK3568_ESMART0_REGION0_CTRL 0x1810 325 #define REGION0_RB_SWAP_SHIFT 14 326 #define WIN_EN_SHIFT 0 327 #define WIN_FORMAT_MASK 0x1f 328 #define WIN_FORMAT_SHIFT 1 329 330 #define RK3568_ESMART0_REGION0_YRGB_MST 0x1814 331 #define RK3568_ESMART0_REGION0_CBR_MST 0x1818 332 #define RK3568_ESMART0_REGION0_VIR 0x181C 333 #define RK3568_ESMART0_REGION0_ACT_INFO 0x1820 334 #define RK3568_ESMART0_REGION0_DSP_INFO 0x1824 335 #define RK3568_ESMART0_REGION0_DSP_ST 0x1828 336 #define RK3568_ESMART0_REGION0_SCL_CTRL 0x1830 337 #define YRGB_XSCL_MODE_MASK 0x3 338 #define YRGB_XSCL_MODE_SHIFT 0 339 #define YRGB_XSCL_FILTER_MODE_MASK 0x3 340 #define YRGB_XSCL_FILTER_MODE_SHIFT 2 341 #define YRGB_YSCL_MODE_MASK 0x3 342 #define YRGB_YSCL_MODE_SHIFT 4 343 #define YRGB_YSCL_FILTER_MODE_MASK 0x3 344 #define YRGB_YSCL_FILTER_MODE_SHIFT 6 345 346 #define RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB 0x1834 347 #define RK3568_ESMART0_REGION0_SCL_FACTOR_CBR 0x1838 348 #define RK3568_ESMART0_REGION0_SCL_OFFSET 0x183C 349 #define RK3568_ESMART0_REGION1_CTRL 0x1840 350 #define YRGB_GT2_MASK 0x1 351 #define YRGB_GT2_SHIFT 8 352 #define YRGB_GT4_MASK 0x1 353 #define YRGB_GT4_SHIFT 9 354 355 #define RK3568_ESMART0_REGION1_YRGB_MST 0x1844 356 #define RK3568_ESMART0_REGION1_CBR_MST 0x1848 357 #define RK3568_ESMART0_REGION1_VIR 0x184C 358 #define RK3568_ESMART0_REGION1_ACT_INFO 0x1850 359 #define RK3568_ESMART0_REGION1_DSP_INFO 0x1854 360 #define RK3568_ESMART0_REGION1_DSP_ST 0x1858 361 #define RK3568_ESMART0_REGION1_SCL_CTRL 0x1860 362 #define RK3568_ESMART0_REGION1_SCL_FACTOR_YRGB 0x1864 363 #define RK3568_ESMART0_REGION1_SCL_FACTOR_CBR 0x1868 364 #define RK3568_ESMART0_REGION1_SCL_OFFSET 0x186C 365 #define RK3568_ESMART0_REGION2_CTRL 0x1870 366 #define RK3568_ESMART0_REGION2_YRGB_MST 0x1874 367 #define RK3568_ESMART0_REGION2_CBR_MST 0x1878 368 #define RK3568_ESMART0_REGION2_VIR 0x187C 369 #define RK3568_ESMART0_REGION2_ACT_INFO 0x1880 370 #define RK3568_ESMART0_REGION2_DSP_INFO 0x1884 371 #define RK3568_ESMART0_REGION2_DSP_ST 0x1888 372 #define RK3568_ESMART0_REGION2_SCL_CTRL 0x1890 373 #define RK3568_ESMART0_REGION2_SCL_FACTOR_YRGB 0x1894 374 #define RK3568_ESMART0_REGION2_SCL_FACTOR_CBR 0x1898 375 #define RK3568_ESMART0_REGION2_SCL_OFFSET 0x189C 376 #define RK3568_ESMART0_REGION3_CTRL 0x18A0 377 #define RK3568_ESMART0_REGION3_YRGB_MST 0x18A4 378 #define RK3568_ESMART0_REGION3_CBR_MST 0x18A8 379 #define RK3568_ESMART0_REGION3_VIR 0x18AC 380 #define RK3568_ESMART0_REGION3_ACT_INFO 0x18B0 381 #define RK3568_ESMART0_REGION3_DSP_INFO 0x18B4 382 #define RK3568_ESMART0_REGION3_DSP_ST 0x18B8 383 #define RK3568_ESMART0_REGION3_SCL_CTRL 0x18C0 384 #define RK3568_ESMART0_REGION3_SCL_FACTOR_YRGB 0x18C4 385 #define RK3568_ESMART0_REGION3_SCL_FACTOR_CBR 0x18C8 386 #define RK3568_ESMART0_REGION3_SCL_OFFSET 0x18CC 387 388 #define RK3568_ESMART1_CTRL0 0x1A00 389 #define RK3568_ESMART1_CTRL1 0x1A04 390 #define RK3568_ESMART1_REGION0_CTRL 0x1A10 391 #define RK3568_ESMART1_REGION0_YRGB_MST 0x1A14 392 #define RK3568_ESMART1_REGION0_CBR_MST 0x1A18 393 #define RK3568_ESMART1_REGION0_VIR 0x1A1C 394 #define RK3568_ESMART1_REGION0_ACT_INFO 0x1A20 395 #define RK3568_ESMART1_REGION0_DSP_INFO 0x1A24 396 #define RK3568_ESMART1_REGION0_DSP_ST 0x1A28 397 #define RK3568_ESMART1_REGION0_SCL_CTRL 0x1A30 398 #define RK3568_ESMART1_REGION0_SCL_FACTOR_YRGB 0x1A34 399 #define RK3568_ESMART1_REGION0_SCL_FACTOR_CBR 0x1A38 400 #define RK3568_ESMART1_REGION0_SCL_OFFSET 0x1A3C 401 #define RK3568_ESMART1_REGION1_CTRL 0x1A40 402 #define RK3568_ESMART1_REGION1_YRGB_MST 0x1A44 403 #define RK3568_ESMART1_REGION1_CBR_MST 0x1A48 404 #define RK3568_ESMART1_REGION1_VIR 0x1A4C 405 #define RK3568_ESMART1_REGION1_ACT_INFO 0x1A50 406 #define RK3568_ESMART1_REGION1_DSP_INFO 0x1A54 407 #define RK3568_ESMART1_REGION1_DSP_ST 0x1A58 408 #define RK3568_ESMART1_REGION1_SCL_CTRL 0x1A60 409 #define RK3568_ESMART1_REGION1_SCL_FACTOR_YRGB 0x1A64 410 #define RK3568_ESMART1_REGION1_SCL_FACTOR_CBR 0x1A68 411 #define RK3568_ESMART1_REGION1_SCL_OFFSET 0x1A6C 412 #define RK3568_ESMART1_REGION2_CTRL 0x1A70 413 #define RK3568_ESMART1_REGION2_YRGB_MST 0x1A74 414 #define RK3568_ESMART1_REGION2_CBR_MST 0x1A78 415 #define RK3568_ESMART1_REGION2_VIR 0x1A7C 416 #define RK3568_ESMART1_REGION2_ACT_INFO 0x1A80 417 #define RK3568_ESMART1_REGION2_DSP_INFO 0x1A84 418 #define RK3568_ESMART1_REGION2_DSP_ST 0x1A88 419 #define RK3568_ESMART1_REGION2_SCL_CTRL 0x1A90 420 #define RK3568_ESMART1_REGION2_SCL_FACTOR_YRGB 0x1A94 421 #define RK3568_ESMART1_REGION2_SCL_FACTOR_CBR 0x1A98 422 #define RK3568_ESMART1_REGION2_SCL_OFFSET 0x1A9C 423 #define RK3568_ESMART1_REGION3_CTRL 0x1AA0 424 #define RK3568_ESMART1_REGION3_YRGB_MST 0x1AA4 425 #define RK3568_ESMART1_REGION3_CBR_MST 0x1AA8 426 #define RK3568_ESMART1_REGION3_VIR 0x1AAC 427 #define RK3568_ESMART1_REGION3_ACT_INFO 0x1AB0 428 #define RK3568_ESMART1_REGION3_DSP_INFO 0x1AB4 429 #define RK3568_ESMART1_REGION3_DSP_ST 0x1AB8 430 #define RK3568_ESMART1_REGION3_SCL_CTRL 0x1AC0 431 #define RK3568_ESMART1_REGION3_SCL_FACTOR_YRGB 0x1AC4 432 #define RK3568_ESMART1_REGION3_SCL_FACTOR_CBR 0x1AC8 433 #define RK3568_ESMART1_REGION3_SCL_OFFSET 0x1ACC 434 435 #define RK3568_SMART0_CTRL0 0x1C00 436 #define RK3568_SMART0_CTRL1 0x1C04 437 #define RK3568_SMART0_REGION0_CTRL 0x1C10 438 #define RK3568_SMART0_REGION0_YRGB_MST 0x1C14 439 #define RK3568_SMART0_REGION0_CBR_MST 0x1C18 440 #define RK3568_SMART0_REGION0_VIR 0x1C1C 441 #define RK3568_SMART0_REGION0_ACT_INFO 0x1C20 442 #define RK3568_SMART0_REGION0_DSP_INFO 0x1C24 443 #define RK3568_SMART0_REGION0_DSP_ST 0x1C28 444 #define RK3568_SMART0_REGION0_SCL_CTRL 0x1C30 445 #define RK3568_SMART0_REGION0_SCL_FACTOR_YRGB 0x1C34 446 #define RK3568_SMART0_REGION0_SCL_FACTOR_CBR 0x1C38 447 #define RK3568_SMART0_REGION0_SCL_OFFSET 0x1C3C 448 #define RK3568_SMART0_REGION1_CTRL 0x1C40 449 #define RK3568_SMART0_REGION1_YRGB_MST 0x1C44 450 #define RK3568_SMART0_REGION1_CBR_MST 0x1C48 451 #define RK3568_SMART0_REGION1_VIR 0x1C4C 452 #define RK3568_SMART0_REGION1_ACT_INFO 0x1C50 453 #define RK3568_SMART0_REGION1_DSP_INFO 0x1C54 454 #define RK3568_SMART0_REGION1_DSP_ST 0x1C58 455 #define RK3568_SMART0_REGION1_SCL_CTRL 0x1C60 456 #define RK3568_SMART0_REGION1_SCL_FACTOR_YRGB 0x1C64 457 #define RK3568_SMART0_REGION1_SCL_FACTOR_CBR 0x1C68 458 #define RK3568_SMART0_REGION1_SCL_OFFSET 0x1C6C 459 #define RK3568_SMART0_REGION2_CTRL 0x1C70 460 #define RK3568_SMART0_REGION2_YRGB_MST 0x1C74 461 #define RK3568_SMART0_REGION2_CBR_MST 0x1C78 462 #define RK3568_SMART0_REGION2_VIR 0x1C7C 463 #define RK3568_SMART0_REGION2_ACT_INFO 0x1C80 464 #define RK3568_SMART0_REGION2_DSP_INFO 0x1C84 465 #define RK3568_SMART0_REGION2_DSP_ST 0x1C88 466 #define RK3568_SMART0_REGION2_SCL_CTRL 0x1C90 467 #define RK3568_SMART0_REGION2_SCL_FACTOR_YRGB 0x1C94 468 #define RK3568_SMART0_REGION2_SCL_FACTOR_CBR 0x1C98 469 #define RK3568_SMART0_REGION2_SCL_OFFSET 0x1C9C 470 #define RK3568_SMART0_REGION3_CTRL 0x1CA0 471 #define RK3568_SMART0_REGION3_YRGB_MST 0x1CA4 472 #define RK3568_SMART0_REGION3_CBR_MST 0x1CA8 473 #define RK3568_SMART0_REGION3_VIR 0x1CAC 474 #define RK3568_SMART0_REGION3_ACT_INFO 0x1CB0 475 #define RK3568_SMART0_REGION3_DSP_INFO 0x1CB4 476 #define RK3568_SMART0_REGION3_DSP_ST 0x1CB8 477 #define RK3568_SMART0_REGION3_SCL_CTRL 0x1CC0 478 #define RK3568_SMART0_REGION3_SCL_FACTOR_YRGB 0x1CC4 479 #define RK3568_SMART0_REGION3_SCL_FACTOR_CBR 0x1CC8 480 #define RK3568_SMART0_REGION3_SCL_OFFSET 0x1CCC 481 482 #define RK3568_SMART1_CTRL0 0x1E00 483 #define RK3568_SMART1_CTRL1 0x1E04 484 #define RK3568_SMART1_REGION0_CTRL 0x1E10 485 #define RK3568_SMART1_REGION0_YRGB_MST 0x1E14 486 #define RK3568_SMART1_REGION0_CBR_MST 0x1E18 487 #define RK3568_SMART1_REGION0_VIR 0x1E1C 488 #define RK3568_SMART1_REGION0_ACT_INFO 0x1E20 489 #define RK3568_SMART1_REGION0_DSP_INFO 0x1E24 490 #define RK3568_SMART1_REGION0_DSP_ST 0x1E28 491 #define RK3568_SMART1_REGION0_SCL_CTRL 0x1E30 492 #define RK3568_SMART1_REGION0_SCL_FACTOR_YRGB 0x1E34 493 #define RK3568_SMART1_REGION0_SCL_FACTOR_CBR 0x1E38 494 #define RK3568_SMART1_REGION0_SCL_OFFSET 0x1E3C 495 #define RK3568_SMART1_REGION1_CTRL 0x1E40 496 #define RK3568_SMART1_REGION1_YRGB_MST 0x1E44 497 #define RK3568_SMART1_REGION1_CBR_MST 0x1E48 498 #define RK3568_SMART1_REGION1_VIR 0x1E4C 499 #define RK3568_SMART1_REGION1_ACT_INFO 0x1E50 500 #define RK3568_SMART1_REGION1_DSP_INFO 0x1E54 501 #define RK3568_SMART1_REGION1_DSP_ST 0x1E58 502 #define RK3568_SMART1_REGION1_SCL_CTRL 0x1E60 503 #define RK3568_SMART1_REGION1_SCL_FACTOR_YRGB 0x1E64 504 #define RK3568_SMART1_REGION1_SCL_FACTOR_CBR 0x1E68 505 #define RK3568_SMART1_REGION1_SCL_OFFSET 0x1E6C 506 #define RK3568_SMART1_REGION2_CTRL 0x1E70 507 #define RK3568_SMART1_REGION2_YRGB_MST 0x1E74 508 #define RK3568_SMART1_REGION2_CBR_MST 0x1E78 509 #define RK3568_SMART1_REGION2_VIR 0x1E7C 510 #define RK3568_SMART1_REGION2_ACT_INFO 0x1E80 511 #define RK3568_SMART1_REGION2_DSP_INFO 0x1E84 512 #define RK3568_SMART1_REGION2_DSP_ST 0x1E88 513 #define RK3568_SMART1_REGION2_SCL_CTRL 0x1E90 514 #define RK3568_SMART1_REGION2_SCL_FACTOR_YRGB 0x1E94 515 #define RK3568_SMART1_REGION2_SCL_FACTOR_CBR 0x1E98 516 #define RK3568_SMART1_REGION2_SCL_OFFSET 0x1E9C 517 #define RK3568_SMART1_REGION3_CTRL 0x1EA0 518 #define RK3568_SMART1_REGION3_YRGB_MST 0x1EA4 519 #define RK3568_SMART1_REGION3_CBR_MST 0x1EA8 520 #define RK3568_SMART1_REGION3_VIR 0x1EAC 521 #define RK3568_SMART1_REGION3_ACT_INFO 0x1EB0 522 #define RK3568_SMART1_REGION3_DSP_INFO 0x1EB4 523 #define RK3568_SMART1_REGION3_DSP_ST 0x1EB8 524 #define RK3568_SMART1_REGION3_SCL_CTRL 0x1EC0 525 #define RK3568_SMART1_REGION3_SCL_FACTOR_YRGB 0x1EC4 526 #define RK3568_SMART1_REGION3_SCL_FACTOR_CBR 0x1EC8 527 #define RK3568_SMART1_REGION3_SCL_OFFSET 0x1ECC 528 529 #define RK3568_MAX_REG 0x1ED0 530 531 #define RK3568_GRF_VO_CON1 0x0364 532 #define GRF_BT656_CLK_INV_SHIFT 1 533 #define GRF_BT1120_CLK_INV_SHIFT 2 534 #define GRF_RGB_DCLK_INV_SHIFT 3 535 536 #define VOP2_LAYER_MAX 8 537 538 #define VOP_FEATURE_OUTPUT_10BIT BIT(0) 539 540 enum vop2_csc_format { 541 CSC_BT601L, 542 CSC_BT709L, 543 CSC_BT601F, 544 CSC_BT2020, 545 }; 546 547 enum vop2_pol { 548 HSYNC_POSITIVE = 0, 549 VSYNC_POSITIVE = 1, 550 DEN_NEGATIVE = 2, 551 DCLK_INVERT = 3 552 }; 553 554 enum vop2_bcsh_out_mode { 555 BCSH_OUT_MODE_BLACK, 556 BCSH_OUT_MODE_BLUE, 557 BCSH_OUT_MODE_COLOR_BAR, 558 BCSH_OUT_MODE_NORMAL_VIDEO, 559 }; 560 561 #define _VOP_REG(off, _mask, _shift, _write_mask) \ 562 { \ 563 .offset = off, \ 564 .mask = _mask, \ 565 .shift = _shift, \ 566 .write_mask = _write_mask, \ 567 } 568 569 #define VOP_REG(off, _mask, _shift) \ 570 _VOP_REG(off, _mask, _shift, false) 571 enum dither_down_mode { 572 RGB888_TO_RGB565 = 0x0, 573 RGB888_TO_RGB666 = 0x1 574 }; 575 576 enum vop2_video_ports_id { 577 VOP2_VP0, 578 VOP2_VP1, 579 VOP2_VP2, 580 VOP2_VP3, 581 VOP2_VP_MAX, 582 }; 583 584 /* This define must same with kernel win phy id */ 585 enum vop2_layer_phy_id { 586 ROCKCHIP_VOP2_CLUSTER0 = 0, 587 ROCKCHIP_VOP2_CLUSTER1, 588 ROCKCHIP_VOP2_ESMART0, 589 ROCKCHIP_VOP2_ESMART1, 590 ROCKCHIP_VOP2_SMART0, 591 ROCKCHIP_VOP2_SMART1, 592 ROCKCHIP_VOP2_CLUSTER2, 593 ROCKCHIP_VOP2_CLUSTER3, 594 ROCKCHIP_VOP2_ESMART2, 595 ROCKCHIP_VOP2_ESMART3, 596 }; 597 598 enum vop2_scale_up_mode { 599 VOP2_SCALE_UP_NRST_NBOR, 600 VOP2_SCALE_UP_BIL, 601 VOP2_SCALE_UP_BIC, 602 }; 603 604 enum vop2_scale_down_mode { 605 VOP2_SCALE_DOWN_NRST_NBOR, 606 VOP2_SCALE_DOWN_BIL, 607 VOP2_SCALE_DOWN_AVG, 608 }; 609 610 enum scale_mode { 611 SCALE_NONE = 0x0, 612 SCALE_UP = 0x1, 613 SCALE_DOWN = 0x2 614 }; 615 616 struct vop2_layer { 617 u8 id; 618 /** 619 * @win_phys_id: window id of the layer selected. 620 * Every layer must make sure to select different 621 * windows of others. 622 */ 623 u8 win_phys_id; 624 }; 625 626 struct vop2_win_data { 627 char *name; 628 u8 phys_id; 629 u8 win_sel_port_offset; 630 u8 layer_sel_win_id; 631 u32 reg_offset; 632 }; 633 634 struct vop2_vp_data { 635 u32 feature; 636 u8 pre_scan_max_dly; 637 struct vop_rect max_output; 638 }; 639 640 struct vop2_vp_plane_mask { 641 u8 primary_plane_id; /* use this win to show logo */ 642 u8 attached_layers_nr; /* number layers attach to this vp */ 643 u8 attached_layers[VOP2_LAYER_MAX]; /* the layers attached to this vp */ 644 u32 plane_mask; 645 }; 646 647 struct vop2_data { 648 u32 version; 649 struct vop2_vp_data *vp_data; 650 struct vop2_win_data *win_data; 651 struct vop2_vp_plane_mask *plane_mask; 652 u8 nr_vps; 653 u8 nr_layers; 654 u8 nr_mixers; 655 u8 nr_gammas; 656 }; 657 658 struct vop2 { 659 u32 *regsbak; 660 void *regs; 661 void *grf; 662 u32 reg_len; 663 u32 version; 664 bool global_init; 665 const struct vop2_data *data; 666 struct vop2_vp_plane_mask vp_plane_mask[VOP2_VP_MAX]; 667 }; 668 669 static struct vop2 *rockchip_vop2; 670 /* 671 * bli_sd_factor = (src - 1) / (dst - 1) << 12; 672 * avg_sd_factor: 673 * bli_su_factor: 674 * bic_su_factor: 675 * = (src - 1) / (dst - 1) << 16; 676 * 677 * gt2 enable: dst get one line from two line of the src 678 * gt4 enable: dst get one line from four line of the src. 679 * 680 */ 681 #define VOP2_BILI_SCL_DN(src, dst) (((src - 1) << 12) / (dst - 1)) 682 #define VOP2_COMMON_SCL(src, dst) (((src - 1) << 16) / (dst - 1)) 683 684 #define VOP2_BILI_SCL_FAC_CHECK(src, dst, fac) \ 685 (fac * (dst - 1) >> 12 < (src - 1)) 686 #define VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac) \ 687 (fac * (dst - 1) >> 16 < (src - 1)) 688 689 static uint16_t vop2_scale_factor(enum scale_mode mode, 690 int32_t filter_mode, 691 uint32_t src, uint32_t dst) 692 { 693 uint32_t fac = 0; 694 int i = 0; 695 696 if (mode == SCALE_NONE) 697 return 0; 698 699 /* 700 * A workaround to avoid zero div. 701 */ 702 if ((dst == 1) || (src == 1)) { 703 dst = dst + 1; 704 src = src + 1; 705 } 706 707 if ((mode == SCALE_DOWN) && (filter_mode == VOP2_SCALE_DOWN_BIL)) { 708 fac = VOP2_BILI_SCL_DN(src, dst); 709 for (i = 0; i < 100; i++) { 710 if (VOP2_BILI_SCL_FAC_CHECK(src, dst, fac)) 711 break; 712 fac -= 1; 713 printf("down fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac); 714 } 715 } else { 716 fac = VOP2_COMMON_SCL(src, dst); 717 for (i = 0; i < 100; i++) { 718 if (VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac)) 719 break; 720 fac -= 1; 721 printf("up fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac); 722 } 723 } 724 725 return fac; 726 } 727 728 static inline enum scale_mode scl_get_scl_mode(int src, int dst) 729 { 730 if (src < dst) 731 return SCALE_UP; 732 else if (src > dst) 733 return SCALE_DOWN; 734 735 return SCALE_NONE; 736 } 737 738 static u8 vop2_vp_primary_plane_order[VOP2_VP_MAX] = { 739 ROCKCHIP_VOP2_SMART0, 740 ROCKCHIP_VOP2_SMART1, 741 ROCKCHIP_VOP2_ESMART1, 742 }; 743 744 static inline int interpolate(int x1, int y1, int x2, int y2, int x) 745 { 746 return y1 + (y2 - y1) * (x - x1) / (x2 - x1); 747 } 748 749 static int vop2_get_primary_plane(struct vop2 *vop2, u32 plane_mask) 750 { 751 int i = 0; 752 753 for (i = 0; i < vop2->data->nr_vps; i++) { 754 if (plane_mask & BIT(vop2_vp_primary_plane_order[i])) 755 return vop2_vp_primary_plane_order[i]; 756 } 757 758 return ROCKCHIP_VOP2_SMART0; 759 } 760 761 static inline u16 scl_cal_scale(int src, int dst, int shift) 762 { 763 return ((src * 2 - 3) << (shift - 1)) / (dst - 1); 764 } 765 766 static inline u16 scl_cal_scale2(int src, int dst) 767 { 768 return ((src - 1) << 12) / (dst - 1); 769 } 770 771 static inline void vop2_writel(struct vop2 *vop2, u32 offset, u32 v) 772 { 773 writel(v, vop2->regs + offset); 774 vop2->regsbak[offset >> 2] = v; 775 } 776 777 static inline u32 vop2_readl(struct vop2 *vop2, u32 offset) 778 { 779 return readl(vop2->regs + offset); 780 } 781 782 static inline void vop2_mask_write(struct vop2 *vop2, u32 offset, 783 u32 mask, u32 shift, u32 v, 784 bool write_mask) 785 { 786 if (!mask) 787 return; 788 789 if (write_mask) { 790 v = ((v & mask) << shift) | (mask << (shift + 16)); 791 } else { 792 u32 cached_val = vop2->regsbak[offset >> 2]; 793 794 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 795 vop2->regsbak[offset >> 2] = v; 796 } 797 798 writel(v, vop2->regs + offset); 799 } 800 801 static inline void vop2_grf_writel(struct vop2 *vop, u32 offset, 802 u32 mask, u32 shift, u32 v) 803 { 804 u32 val = 0; 805 806 val = (v << shift) | (mask << (shift + 16)); 807 writel(val, vop->grf + offset); 808 } 809 810 static inline int us_to_vertical_line(struct drm_display_mode *mode, int us) 811 { 812 return us * mode->clock / mode->htotal / 1000; 813 } 814 815 static bool is_yuv_output(u32 bus_format) 816 { 817 switch (bus_format) { 818 case MEDIA_BUS_FMT_YUV8_1X24: 819 case MEDIA_BUS_FMT_YUV10_1X30: 820 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 821 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 822 return true; 823 default: 824 return false; 825 } 826 } 827 828 static int vop2_convert_csc_mode(int csc_mode) 829 { 830 switch (csc_mode) { 831 case V4L2_COLORSPACE_SMPTE170M: 832 case V4L2_COLORSPACE_470_SYSTEM_M: 833 case V4L2_COLORSPACE_470_SYSTEM_BG: 834 return CSC_BT601L; 835 case V4L2_COLORSPACE_REC709: 836 case V4L2_COLORSPACE_SMPTE240M: 837 case V4L2_COLORSPACE_DEFAULT: 838 return CSC_BT709L; 839 case V4L2_COLORSPACE_JPEG: 840 return CSC_BT601F; 841 case V4L2_COLORSPACE_BT2020: 842 return CSC_BT2020; 843 default: 844 return CSC_BT709L; 845 } 846 } 847 848 static bool is_uv_swap(u32 bus_format, u32 output_mode) 849 { 850 /* 851 * FIXME: 852 * 853 * There is no media type for YUV444 output, 854 * so when out_mode is AAAA or P888, assume output is YUV444 on 855 * yuv format. 856 * 857 * From H/W testing, YUV444 mode need a rb swap. 858 */ 859 if ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 860 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 861 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 862 output_mode == ROCKCHIP_OUT_MODE_P888)) 863 return true; 864 else 865 return false; 866 } 867 868 static inline bool is_hot_plug_devices(int output_type) 869 { 870 switch (output_type) { 871 case DRM_MODE_CONNECTOR_HDMIA: 872 case DRM_MODE_CONNECTOR_HDMIB: 873 case DRM_MODE_CONNECTOR_TV: 874 case DRM_MODE_CONNECTOR_DisplayPort: 875 case DRM_MODE_CONNECTOR_VGA: 876 case DRM_MODE_CONNECTOR_Unknown: 877 return true; 878 default: 879 return false; 880 } 881 } 882 883 static int rockchip_vop2_gamma_lut_init(struct vop2 *vop2, 884 struct display_state *state) 885 { 886 struct connector_state *conn_state = &state->conn_state; 887 struct crtc_state *cstate = &state->crtc_state; 888 struct resource gamma_res; 889 fdt_size_t lut_size; 890 int i, lut_len, ret = 0; 891 u32 *lut_regs; 892 u32 *lut_val; 893 u32 r, g, b; 894 u32 vp_offset = cstate->crtc_id * 0x100; 895 struct base2_disp_info *disp_info = conn_state->disp_info; 896 static int gamma_lut_en_num = 1; 897 898 if (gamma_lut_en_num > vop2->data->nr_gammas) { 899 printf("warn: only %d vp support gamma\n", vop2->data->nr_gammas); 900 return 0; 901 } 902 903 if (!disp_info) 904 return 0; 905 906 if (!disp_info->gamma_lut_data.size) 907 return 0; 908 909 ret = ofnode_read_resource_byname(cstate->node, "gamma_lut", &gamma_res); 910 if (ret) 911 printf("failed to get gamma lut res\n"); 912 lut_regs = (u32 *)gamma_res.start; 913 lut_size = gamma_res.end - gamma_res.start + 1; 914 if (lut_regs == (u32 *)FDT_ADDR_T_NONE) { 915 printf("failed to get gamma lut register\n"); 916 return 0; 917 } 918 lut_len = lut_size / 4; 919 if (lut_len != 256 && lut_len != 1024) { 920 printf("Warning: unsupport gamma lut table[%d]\n", lut_len); 921 return 0; 922 } 923 lut_val = (u32 *)calloc(1, lut_size); 924 for (i = 0; i < lut_len; i++) { 925 r = disp_info->gamma_lut_data.lred[i] * (lut_len - 1) / 0xffff; 926 g = disp_info->gamma_lut_data.lgreen[i] * (lut_len - 1) / 0xffff; 927 b = disp_info->gamma_lut_data.lblue[i] * (lut_len - 1) / 0xffff; 928 929 lut_val[i] = b * lut_len * lut_len + g * lut_len + r; 930 } 931 932 for (i = 0; i < lut_len; i++) 933 writel(lut_val[i], lut_regs + i); 934 935 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, 936 GAMMA_PORT_SEL_MASK, GAMMA_PORT_SEL_SHIFT, 937 cstate->crtc_id , false); 938 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 939 EN_MASK, DSP_LUT_EN_SHIFT, 1, false); 940 gamma_lut_en_num++; 941 942 return 0; 943 } 944 945 static int rockchip_vop2_cubic_lut_init(struct vop2 *vop2, 946 struct display_state *state) 947 { 948 struct connector_state *conn_state = &state->conn_state; 949 struct crtc_state *cstate = &state->crtc_state; 950 int i, cubic_lut_len; 951 u32 vp_offset = cstate->crtc_id * 0x100; 952 struct base2_disp_info *disp_info = conn_state->disp_info; 953 struct base2_cubic_lut_data *lut = &conn_state->disp_info->cubic_lut_data; 954 u32 *cubic_lut_addr; 955 956 if (!disp_info || CONFIG_ROCKCHIP_CUBIC_LUT_SIZE == 0) 957 return 0; 958 959 if (!disp_info->cubic_lut_data.size) 960 return 0; 961 962 cubic_lut_addr = (u32 *)get_cubic_lut_buffer(cstate->crtc_id); 963 cubic_lut_len = disp_info->cubic_lut_data.size; 964 965 for (i = 0; i < cubic_lut_len / 2; i++) { 966 *cubic_lut_addr++ = ((lut->lred[2 * i]) & 0xfff) + 967 ((lut->lgreen[2 * i] & 0xfff) << 12) + 968 ((lut->lblue[2 * i] & 0xff) << 24); 969 *cubic_lut_addr++ = ((lut->lblue[2 * i] & 0xf00) >> 8) + 970 ((lut->lred[2 * i + 1] & 0xfff) << 4) + 971 ((lut->lgreen[2 * i + 1] & 0xfff) << 16) + 972 ((lut->lblue[2 * i + 1] & 0xf) << 28); 973 *cubic_lut_addr++ = (lut->lblue[2 * i + 1] & 0xff0) >> 4; 974 *cubic_lut_addr++ = 0; 975 } 976 977 if (cubic_lut_len % 2) { 978 *cubic_lut_addr++ = (lut->lred[2 * i] & 0xfff) + 979 ((lut->lgreen[2 * i] & 0xfff) << 12) + 980 ((lut->lblue[2 * i] & 0xff) << 24); 981 *cubic_lut_addr++ = (lut->lblue[2 * i] & 0xf00) >> 8; 982 *cubic_lut_addr++ = 0; 983 *cubic_lut_addr = 0; 984 } 985 986 vop2_writel(vop2, RK3568_VP0_3D_LUT_MST + vp_offset, 987 get_cubic_lut_buffer(cstate->crtc_id)); 988 vop2_mask_write(vop2, RK3568_SYS_AXI_LUT_CTRL, 989 EN_MASK, LUT_DMA_EN_SHIFT, 1, false); 990 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, 991 EN_MASK, VP0_3D_LUT_EN_SHIFT, 1, false); 992 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, 993 EN_MASK, VP0_3D_LUT_UPDATE_SHIFT, 1, false); 994 995 return 0; 996 } 997 998 static void vop2_tv_config_update(struct display_state *state, struct vop2 *vop2) 999 { 1000 struct connector_state *conn_state = &state->conn_state; 1001 struct base_bcsh_info *bcsh_info; 1002 struct crtc_state *cstate = &state->crtc_state; 1003 int brightness, contrast, saturation, hue, sin_hue, cos_hue; 1004 bool bcsh_en = false, post_r2y_en = false, post_y2r_en = false; 1005 u32 vp_offset = (cstate->crtc_id * 0x100); 1006 int post_csc_mode; 1007 1008 if (!conn_state->disp_info) 1009 return; 1010 bcsh_info = &conn_state->disp_info->bcsh_info; 1011 if (!bcsh_info) 1012 return; 1013 1014 if (bcsh_info->brightness != 50 || 1015 bcsh_info->contrast != 50 || 1016 bcsh_info->saturation != 50 || bcsh_info->hue != 50) 1017 bcsh_en = true; 1018 1019 if (bcsh_en) { 1020 if (!cstate->yuv_overlay) 1021 post_r2y_en = 1; 1022 if (!is_yuv_output(conn_state->bus_format)) 1023 post_y2r_en = 1; 1024 } else { 1025 if (!cstate->yuv_overlay && is_yuv_output(conn_state->bus_format)) 1026 post_r2y_en = 1; 1027 if (cstate->yuv_overlay && !is_yuv_output(conn_state->bus_format)) 1028 post_y2r_en = 1; 1029 } 1030 1031 post_csc_mode = vop2_convert_csc_mode(conn_state->color_space); 1032 1033 1034 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_MASK, 1035 BCSH_CTRL_R2Y_SHIFT, post_r2y_en, false); 1036 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_MASK, 1037 BCSH_CTRL_Y2R_SHIFT, post_y2r_en, false); 1038 1039 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_CSC_MODE_MASK, 1040 BCSH_CTRL_R2Y_CSC_MODE_SHIFT, post_csc_mode, false); 1041 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_CSC_MODE_MASK, 1042 BCSH_CTRL_Y2R_CSC_MODE_SHIFT, post_csc_mode, false); 1043 if (!bcsh_en) { 1044 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, 1045 BCSH_EN_MASK, BCSH_EN_SHIFT, 0, false); 1046 return; 1047 } 1048 1049 if (cstate->feature & VOP_FEATURE_OUTPUT_10BIT) 1050 brightness = interpolate(0, -128, 100, 127, 1051 bcsh_info->brightness); 1052 else 1053 brightness = interpolate(0, -32, 100, 31, 1054 bcsh_info->brightness); 1055 contrast = interpolate(0, 0, 100, 511, bcsh_info->contrast); 1056 saturation = interpolate(0, 0, 100, 511, bcsh_info->saturation); 1057 hue = interpolate(0, -30, 100, 30, bcsh_info->hue); 1058 1059 1060 /* 1061 * a:[-30~0): 1062 * sin_hue = 0x100 - sin(a)*256; 1063 * cos_hue = cos(a)*256; 1064 * a:[0~30] 1065 * sin_hue = sin(a)*256; 1066 * cos_hue = cos(a)*256; 1067 */ 1068 sin_hue = fixp_sin32(hue) >> 23; 1069 cos_hue = fixp_cos32(hue) >> 23; 1070 1071 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1072 BCSH_BRIGHTNESS_MASK, BCSH_BRIGHTNESS_SHIFT, 1073 brightness, false); 1074 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1075 BCSH_CONTRAST_MASK, BCSH_CONTRAST_SHIFT, contrast, false); 1076 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1077 BCSH_SATURATION_MASK, BCSH_SATURATION_SHIFT, 1078 saturation * contrast / 0x100, false); 1079 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, 1080 BCSH_SIN_HUE_MASK, BCSH_SIN_HUE_SHIFT, sin_hue, false); 1081 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, 1082 BCSH_COS_HUE_MASK, BCSH_COS_HUE_SHIFT, cos_hue, false); 1083 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1084 BCSH_OUT_MODE_MASK, BCSH_OUT_MODE_SHIFT, 1085 BCSH_OUT_MODE_NORMAL_VIDEO, false); 1086 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, 1087 BCSH_EN_MASK, BCSH_EN_SHIFT, 1, false); 1088 } 1089 1090 static void vop2_post_config(struct display_state *state, struct vop2 *vop2) 1091 { 1092 struct connector_state *conn_state = &state->conn_state; 1093 struct drm_display_mode *mode = &conn_state->mode; 1094 struct crtc_state *cstate = &state->crtc_state; 1095 u32 vp_offset = (cstate->crtc_id * 0x100); 1096 u16 vtotal = mode->crtc_vtotal; 1097 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 1098 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 1099 u16 hdisplay = mode->crtc_hdisplay; 1100 u16 vdisplay = mode->crtc_vdisplay; 1101 u16 hsize = 1102 hdisplay * (conn_state->overscan.left_margin + 1103 conn_state->overscan.right_margin) / 200; 1104 u16 vsize = 1105 vdisplay * (conn_state->overscan.top_margin + 1106 conn_state->overscan.bottom_margin) / 200; 1107 u16 hact_end, vact_end; 1108 u32 val; 1109 u32 bg_ovl_dly, bg_dly, pre_scan_dly; 1110 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 1111 1112 hsize = round_down(hsize, 2); 1113 vsize = round_down(vsize, 2); 1114 1115 hact_st += hdisplay * (100 - conn_state->overscan.left_margin) / 200; 1116 hact_end = hact_st + hsize; 1117 val = hact_st << 16; 1118 val |= hact_end; 1119 1120 vop2_writel(vop2, RK3568_VP0_POST_DSP_HACT_INFO + vp_offset, val); 1121 vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200; 1122 vact_end = vact_st + vsize; 1123 val = vact_st << 16; 1124 val |= vact_end; 1125 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO + vp_offset, val); 1126 val = scl_cal_scale2(vdisplay, vsize) << 16; 1127 val |= scl_cal_scale2(hdisplay, hsize); 1128 vop2_writel(vop2, RK3568_VP0_POST_SCL_FACTOR_YRGB + vp_offset, val); 1129 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0) 1130 #define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1) 1131 vop2_writel(vop2, RK3568_VP0_POST_SCL_CTRL + vp_offset, 1132 POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) | 1133 POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize)); 1134 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1135 u16 vact_st_f1 = vtotal + vact_st + 1; 1136 u16 vact_end_f1 = vact_st_f1 + vsize; 1137 1138 val = vact_st_f1 << 16 | vact_end_f1; 1139 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO_F1 + vp_offset, val); 1140 } 1141 1142 bg_ovl_dly = cstate->crtc->vps[cstate->crtc_id].bg_ovl_dly; 1143 bg_dly = vop2->data->vp_data[cstate->crtc_id].pre_scan_max_dly; 1144 bg_dly -= bg_ovl_dly; 1145 pre_scan_dly = bg_dly + (hdisplay >> 1) - 1; 1146 pre_scan_dly = (pre_scan_dly << 16) | hsync_len; 1147 vop2_mask_write(vop2, RK3568_VP0_BG_MIX_CTRL + cstate->crtc_id * 4, 1148 BG_MIX_CTRL_MASK, BG_MIX_CTRL_SHIFT, bg_dly, false); 1149 vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + vp_offset, pre_scan_dly); 1150 } 1151 1152 static void vop2_global_initial(struct vop2 *vop2, struct display_state *state) 1153 { 1154 struct crtc_state *cstate = &state->crtc_state; 1155 int i, j, port_mux = 0, total_used_layer = 0; 1156 u8 shift = 0; 1157 int layer_phy_id = 0; 1158 u32 layer_nr = 0; 1159 struct vop2_win_data *win_data; 1160 struct vop2_vp_plane_mask *plane_mask; 1161 1162 if (vop2->global_init) 1163 return; 1164 1165 /* OTP must enable at the first time, otherwise mirror layer register is error */ 1166 if (soc_is_rk3566()) 1167 vop2_mask_write(vop2, RK3568_SYS_OTP_WIN_EN, EN_MASK, 1168 OTP_WIN_EN_SHIFT, 1, false); 1169 1170 memcpy(vop2->regsbak, vop2->regs, vop2->reg_len); 1171 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, 1172 OVL_PORT_MUX_REG_DONE_IMD_SHIFT, 1, false); 1173 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1174 IF_CTRL_REG_DONE_IMD_SHIFT, 1, false); 1175 1176 if (cstate->crtc->assign_plane) {/* dts assign plane */ 1177 u32 plane_mask; 1178 int primary_plane_id; 1179 1180 for (i = 0; i < vop2->data->nr_vps; i++) { 1181 plane_mask = cstate->crtc->vps[i].plane_mask; 1182 vop2->vp_plane_mask[i].plane_mask = plane_mask; 1183 layer_nr = hweight32(plane_mask); /* use bitmap to store plane mask */ 1184 vop2->vp_plane_mask[i].attached_layers_nr = layer_nr; 1185 primary_plane_id = vop2_get_primary_plane(vop2, plane_mask); 1186 vop2->vp_plane_mask[i].primary_plane_id = primary_plane_id; 1187 vop2->vp_plane_mask[i].plane_mask = plane_mask; 1188 1189 /* plane mask[bitmap] convert into layer phy id[enum vop2_layer_phy_id]*/ 1190 for (j = 0; j < layer_nr; j++) { 1191 vop2->vp_plane_mask[i].attached_layers[j] = ffs(plane_mask) - 1; 1192 plane_mask &= ~BIT(vop2->vp_plane_mask[i].attached_layers[j]); 1193 } 1194 } 1195 } else {/* need soft assign plane mask */ 1196 /* find the first unplug devices and set it as main display */ 1197 int main_vp_index = -1; 1198 int active_vp_num = 0; 1199 1200 for (i = 0; i < vop2->data->nr_vps; i++) { 1201 if (cstate->crtc->vps[i].enable) 1202 active_vp_num++; 1203 } 1204 printf("VOP have %d active VP\n", active_vp_num); 1205 1206 if (soc_is_rk3566() && active_vp_num > 2) 1207 printf("ERROR: rk3566 only support 2 display output!!\n"); 1208 plane_mask = vop2->data->plane_mask; 1209 plane_mask += (active_vp_num - 1) * VOP2_VP_MAX; 1210 1211 for (i = 0; i < vop2->data->nr_vps; i++) { 1212 if (!is_hot_plug_devices(cstate->crtc->vps[i].output_type)) { 1213 vop2->vp_plane_mask[i] = plane_mask[0]; /* the first store main display plane mask*/ 1214 main_vp_index = i; 1215 } 1216 } 1217 1218 /* if no find unplug devices, use vp0 as main display */ 1219 if (main_vp_index < 0) { 1220 main_vp_index = 0; 1221 vop2->vp_plane_mask[0] = plane_mask[0]; 1222 } 1223 1224 j = 1; /* plane_mask[0] store main display, so we from plane_mask[1] */ 1225 1226 /* init other display except main display */ 1227 for (i = 0; i < vop2->data->nr_vps; i++) { 1228 if (i == main_vp_index || !cstate->crtc->vps[i].enable) /* main display or no connect devices */ 1229 continue; 1230 vop2->vp_plane_mask[i] = plane_mask[j++]; 1231 } 1232 1233 /* store plane mask for vop2_fixup_dts */ 1234 for (i = 0; i < vop2->data->nr_vps; i++) { 1235 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1236 /* rk3566 only support 3+3 policy */ 1237 if (soc_is_rk3566() && active_vp_num == 1) { 1238 if (cstate->crtc->vps[i].enable) { 1239 for (j = 0; j < 3; j++) { 1240 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1241 vop2->vp_plane_mask[i].plane_mask |= BIT(layer_phy_id); 1242 } 1243 } 1244 } else { 1245 for (j = 0; j < layer_nr; j++) { 1246 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1247 vop2->vp_plane_mask[i].plane_mask |= BIT(layer_phy_id); 1248 } 1249 } 1250 } 1251 } 1252 1253 for (i = 0; i < vop2->data->nr_vps; i++) { 1254 printf("vp%d have layer nr:%d[", i, vop2->vp_plane_mask[i].attached_layers_nr); 1255 for (j = 0; j < vop2->vp_plane_mask[i].attached_layers_nr; j++) 1256 printf("%d ", vop2->vp_plane_mask[i].attached_layers[j]); 1257 printf("], primary plane: %d\n", vop2->vp_plane_mask[i].primary_plane_id); 1258 } 1259 1260 shift = 0; 1261 /* layer sel win id */ 1262 for (i = 0; i < vop2->data->nr_vps; i++) { 1263 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1264 for (j = 0; j < layer_nr; j++) { 1265 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1266 win_data = &vop2->data->win_data[layer_phy_id]; 1267 vop2_mask_write(vop2, RK3568_OVL_LAYER_SEL, LAYER_SEL_MASK, 1268 shift, win_data->layer_sel_win_id, false); 1269 shift += 4; 1270 } 1271 } 1272 1273 /* win sel port */ 1274 for (i = 0; i < vop2->data->nr_vps; i++) { 1275 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1276 for (j = 0; j < layer_nr; j++) { 1277 if (!cstate->crtc->vps[i].enable) 1278 continue; 1279 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1280 win_data = &vop2->data->win_data[layer_phy_id]; 1281 shift = win_data->win_sel_port_offset * 2; 1282 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, LAYER_SEL_PORT_MASK, 1283 LAYER_SEL_PORT_SHIFT + shift, i, false); 1284 } 1285 } 1286 1287 /** 1288 * port mux config 1289 */ 1290 for (i = 0; i < vop2->data->nr_vps; i++) { 1291 shift = i * 4; 1292 if (cstate->crtc->vps[i].enable) { 1293 total_used_layer += vop2->vp_plane_mask[i].attached_layers_nr; 1294 port_mux = total_used_layer - 1; 1295 } else { 1296 port_mux = 8; 1297 } 1298 1299 if (i == vop2->data->nr_vps - 1) 1300 port_mux = vop2->data->nr_mixers; 1301 1302 cstate->crtc->vps[i].bg_ovl_dly = (vop2->data->nr_mixers - port_mux) << 1; 1303 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, PORT_MUX_MASK, 1304 PORT_MUX_SHIFT + shift, port_mux, false); 1305 } 1306 1307 vop2_writel(vop2, RK3568_AUTO_GATING_CTRL, 0); 1308 1309 vop2->global_init = true; 1310 } 1311 1312 static int vop2_initial(struct vop2 *vop2, struct display_state *state) 1313 { 1314 struct crtc_state *cstate = &state->crtc_state; 1315 struct connector_state *conn_state = &state->conn_state; 1316 struct drm_display_mode *mode = &conn_state->mode; 1317 char dclk_name[9]; 1318 struct clk dclk; 1319 int ret; 1320 1321 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1322 ret = clk_set_defaults(cstate->dev); 1323 if (ret) 1324 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1325 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", cstate->crtc_id); 1326 ret = clk_get_by_name(cstate->dev, dclk_name, &dclk); 1327 if (!ret) 1328 ret = clk_set_rate(&dclk, mode->clock * 1000); 1329 if (IS_ERR_VALUE(ret)) { 1330 printf("%s: Failed to set vp%d dclk[%d khz]: ret=%d\n", 1331 __func__, cstate->crtc_id, mode->clock, ret); 1332 return ret; 1333 } 1334 1335 vop2_global_initial(vop2, state); 1336 rockchip_vop2_gamma_lut_init(vop2, state); 1337 rockchip_vop2_cubic_lut_init(vop2, state); 1338 1339 return 0; 1340 } 1341 1342 /* 1343 * VOP2 have multi video ports. 1344 * video port ------- crtc 1345 */ 1346 static int rockchip_vop2_preinit(struct display_state *state) 1347 { 1348 struct crtc_state *cstate = &state->crtc_state; 1349 const struct vop2_data *vop2_data = cstate->crtc->data; 1350 1351 if (!rockchip_vop2) { 1352 rockchip_vop2 = calloc(1, sizeof(struct vop2)); 1353 if (!rockchip_vop2) 1354 return -ENOMEM; 1355 rockchip_vop2->regs = dev_read_addr_ptr(cstate->dev); 1356 rockchip_vop2->regsbak = malloc(RK3568_MAX_REG); 1357 rockchip_vop2->reg_len = RK3568_MAX_REG; 1358 rockchip_vop2->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1359 if (rockchip_vop2->grf <= 0) 1360 printf("%s: Get syscon grf failed (ret=%p)\n", __func__, rockchip_vop2->grf); 1361 1362 rockchip_vop2->version = vop2_data->version; 1363 rockchip_vop2->data = vop2_data; 1364 } 1365 1366 cstate->private = rockchip_vop2; 1367 cstate->max_output = vop2_data->vp_data[cstate->crtc_id].max_output; 1368 cstate->feature = vop2_data->vp_data[cstate->crtc_id].feature; 1369 1370 return 0; 1371 } 1372 1373 static int rockchip_vop2_init(struct display_state *state) 1374 { 1375 struct crtc_state *cstate = &state->crtc_state; 1376 struct connector_state *conn_state = &state->conn_state; 1377 struct drm_display_mode *mode = &conn_state->mode; 1378 struct vop2 *vop2 = cstate->private; 1379 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 1380 u16 hdisplay = mode->crtc_hdisplay; 1381 u16 htotal = mode->crtc_htotal; 1382 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 1383 u16 hact_end = hact_st + hdisplay; 1384 u16 vdisplay = mode->crtc_vdisplay; 1385 u16 vtotal = mode->crtc_vtotal; 1386 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 1387 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 1388 u16 vact_end = vact_st + vdisplay; 1389 bool yuv_overlay = false; 1390 u32 vp_offset = (cstate->crtc_id * 0x100); 1391 u32 val; 1392 bool dclk_inv; 1393 u8 dither_down_en = 0; 1394 u8 pre_dither_down_en = 0; 1395 1396 vop2_initial(vop2, state); 1397 dclk_inv = (mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1; 1398 val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE); 1399 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE); 1400 1401 if (conn_state->output_if & VOP_OUTPUT_IF_RGB) { 1402 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, 1403 1, false); 1404 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1405 RGB_MUX_SHIFT, cstate->crtc_id, false); 1406 vop2_grf_writel(vop2, RK3568_GRF_VO_CON1, EN_MASK, 1407 GRF_RGB_DCLK_INV_SHIFT, dclk_inv); 1408 } 1409 1410 if (conn_state->output_if & VOP_OUTPUT_IF_BT1120) { 1411 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, 1412 1, false); 1413 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, 1414 BT1120_EN_SHIFT, 1, false); 1415 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1416 RGB_MUX_SHIFT, cstate->crtc_id, false); 1417 vop2_grf_writel(vop2, RK3568_GRF_VO_CON1, EN_MASK, 1418 GRF_BT1120_CLK_INV_SHIFT, !dclk_inv); 1419 } 1420 1421 if (conn_state->output_if & VOP_OUTPUT_IF_BT656) { 1422 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT, 1423 1, false); 1424 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1425 RGB_MUX_SHIFT, cstate->crtc_id, false); 1426 vop2_grf_writel(vop2, RK3568_GRF_VO_CON1, EN_MASK, 1427 GRF_BT656_CLK_INV_SHIFT, !dclk_inv); 1428 } 1429 1430 if (conn_state->output_if & VOP_OUTPUT_IF_LVDS0) { 1431 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT, 1432 1, false); 1433 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1434 LVDS0_MUX_SHIFT, cstate->crtc_id, false); 1435 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1436 IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false); 1437 } 1438 1439 if (conn_state->output_if & VOP_OUTPUT_IF_LVDS1) { 1440 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS1_EN_SHIFT, 1441 1, false); 1442 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1443 LVDS1_MUX_SHIFT, cstate->crtc_id, false); 1444 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1445 IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false); 1446 } 1447 1448 if (conn_state->output_flags & 1449 (ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE | 1450 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)) { 1451 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 1452 LVDS_DUAL_EN_SHIFT, 1, false); 1453 if (conn_state->output_flags & 1454 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 1455 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 1456 LVDS_DUAL_LEFT_RIGHT_EN_SHIFT, 1, 1457 false); 1458 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) 1459 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 1460 LVDS_DUAL_SWAP_EN_SHIFT, 1, false); 1461 } 1462 1463 if (conn_state->output_if & VOP_OUTPUT_IF_MIPI0) { 1464 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT, 1465 1, false); 1466 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1467 MIPI0_MUX_SHIFT, cstate->crtc_id, false); 1468 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1469 IF_CRTL_MIPI_DCLK_POL_SHIT, dclk_inv, false); 1470 } 1471 1472 if (conn_state->output_if & VOP_OUTPUT_IF_MIPI1) { 1473 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI1_EN_SHIFT, 1474 1, false); 1475 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1476 MIPI1_MUX_SHIFT, cstate->crtc_id, false); 1477 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1478 IF_CRTL_MIPI_DCLK_POL_SHIT, dclk_inv, false); 1479 } 1480 1481 if (conn_state->output_flags & 1482 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { 1483 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, 1484 MIPI_DUAL_EN_SHIFT, 1, false); 1485 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) 1486 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 1487 EN_MASK, MIPI_DUAL_SWAP_EN_SHIFT, 1, 1488 false); 1489 } 1490 1491 if (conn_state->output_if & VOP_OUTPUT_IF_eDP0) { 1492 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, EDP0_EN_SHIFT, 1493 1, false); 1494 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1495 EDP0_MUX_SHIFT, cstate->crtc_id, false); 1496 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1497 IF_CRTL_EDP_DCLK_POL_SHIT, dclk_inv, false); 1498 } 1499 1500 if (conn_state->output_if & VOP_OUTPUT_IF_HDMI0) { 1501 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT, 1502 1, false); 1503 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1504 HDMI0_MUX_SHIFT, cstate->crtc_id, false); 1505 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1506 IF_CRTL_HDMI_DCLK_POL_SHIT, 1, false); 1507 vop2_mask_write(vop2, RK3568_DSP_IF_POL, 1508 IF_CRTL_HDMI_PIN_POL_MASK, 1509 IF_CRTL_HDMI_PIN_POL_SHIT, val, false); 1510 } 1511 1512 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1513 !(cstate->feature & VOP_FEATURE_OUTPUT_10BIT)) 1514 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 1515 1516 if (is_uv_swap(conn_state->bus_format, conn_state->output_mode)) 1517 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 1518 DATA_SWAP_MASK, DATA_SWAP_SHIFT, DSP_RB_SWAP, 1519 false); 1520 else 1521 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 1522 DATA_SWAP_MASK, DATA_SWAP_SHIFT, 0, 1523 false); 1524 1525 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, OUT_MODE_MASK, 1526 OUT_MODE_SHIFT, conn_state->output_mode, false); 1527 1528 switch (conn_state->bus_format) { 1529 case MEDIA_BUS_FMT_RGB565_1X16: 1530 dither_down_en = 1; 1531 break; 1532 case MEDIA_BUS_FMT_RGB666_1X18: 1533 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 1534 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 1535 case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA: 1536 dither_down_en = 1; 1537 break; 1538 case MEDIA_BUS_FMT_YUV8_1X24: 1539 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1540 dither_down_en = 0; 1541 pre_dither_down_en = 1; 1542 break; 1543 case MEDIA_BUS_FMT_YUV10_1X30: 1544 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1545 case MEDIA_BUS_FMT_RGB888_1X24: 1546 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 1547 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 1548 default: 1549 dither_down_en = 0; 1550 pre_dither_down_en = 0; 1551 break; 1552 } 1553 1554 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA) 1555 pre_dither_down_en = 0; 1556 else 1557 pre_dither_down_en = 1; 1558 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1559 DITHER_DOWN_EN_SHIFT, dither_down_en, false); 1560 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1561 PRE_DITHER_DOWN_EN_SHIFT, pre_dither_down_en, false); 1562 1563 yuv_overlay = is_yuv_output(conn_state->bus_format) ? 1 : 0; 1564 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, cstate->crtc_id, 1565 yuv_overlay, false); 1566 1567 cstate->yuv_overlay = yuv_overlay; 1568 1569 vop2_writel(vop2, RK3568_VP0_DSP_HTOTAL_HS_END + vp_offset, 1570 (htotal << 16) | hsync_len); 1571 val = hact_st << 16; 1572 val |= hact_end; 1573 vop2_writel(vop2, RK3568_VP0_DSP_HACT_ST_END + vp_offset, val); 1574 val = vact_st << 16; 1575 val |= vact_end; 1576 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END + vp_offset, val); 1577 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1578 u16 vact_st_f1 = vtotal + vact_st + 1; 1579 u16 vact_end_f1 = vact_st_f1 + vdisplay; 1580 1581 val = vact_st_f1 << 16 | vact_end_f1; 1582 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END_F1 + vp_offset, 1583 val); 1584 1585 val = vtotal << 16 | (vtotal + vsync_len); 1586 vop2_writel(vop2, RK3568_VP0_DSP_VS_ST_END_F1 + vp_offset, val); 1587 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1588 INTERLACE_EN_SHIFT, 1, false); 1589 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1590 DSP_FILED_POL, 1, false); 1591 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1592 P2I_EN_SHIFT, 1, false); 1593 vtotal += vtotal + 1; 1594 } else { 1595 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1596 INTERLACE_EN_SHIFT, 0, false); 1597 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1598 P2I_EN_SHIFT, 0, false); 1599 } 1600 vop2_writel(vop2, RK3568_VP0_DSP_VTOTAL_VS_END + vp_offset, 1601 (vtotal << 16) | vsync_len); 1602 val = !!(mode->flags & DRM_MODE_FLAG_DBLCLK); 1603 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1604 CORE_DCLK_DIV_EN_SHIFT, val, false); 1605 1606 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420) 1607 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 1608 DCLK_DIV2_MASK, DCLK_DIV2_SHIFT, 0x3, false); 1609 else 1610 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 1611 DCLK_DIV2_MASK, DCLK_DIV2_SHIFT, 0, false); 1612 1613 if (yuv_overlay) 1614 val = 0x20010200; 1615 else 1616 val = 0; 1617 vop2_writel(vop2, RK3568_VP0_DSP_BG + vp_offset, val); 1618 1619 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1620 POST_DSP_OUT_R2Y_SHIFT, yuv_overlay, false); 1621 1622 vop2_tv_config_update(state, vop2); 1623 vop2_post_config(state, vop2); 1624 1625 return 0; 1626 } 1627 1628 static void vop2_setup_scale(struct vop2 *vop2, uint32_t win_offset, 1629 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 1630 uint32_t dst_h) 1631 { 1632 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 1633 uint16_t hscl_filter_mode, vscl_filter_mode; 1634 uint8_t gt2 = 0, gt4 = 0; 1635 uint32_t xfac = 0, yfac = 0; 1636 uint16_t hsu_filter_mode = VOP2_SCALE_UP_BIC; 1637 uint16_t hsd_filter_mode = VOP2_SCALE_DOWN_BIL; 1638 uint16_t vsu_filter_mode = VOP2_SCALE_UP_BIL; 1639 uint16_t vsd_filter_mode = VOP2_SCALE_DOWN_BIL; 1640 1641 if (src_h >= (4 * dst_h)) 1642 gt4 = 1; 1643 else if (src_h >= (2 * dst_h)) 1644 gt2 = 1; 1645 1646 if (gt4) 1647 src_h >>= 2; 1648 else if (gt2) 1649 src_h >>= 1; 1650 1651 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 1652 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 1653 1654 if (yrgb_hor_scl_mode == SCALE_UP) 1655 hscl_filter_mode = hsu_filter_mode; 1656 else 1657 hscl_filter_mode = hsd_filter_mode; 1658 1659 if (yrgb_ver_scl_mode == SCALE_UP) 1660 vscl_filter_mode = vsu_filter_mode; 1661 else 1662 vscl_filter_mode = vsd_filter_mode; 1663 1664 /* 1665 * RK3568 VOP Esmart/Smart dsp_w should be even pixel 1666 * at scale down mode 1667 */ 1668 if ((yrgb_hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) { 1669 printf("win dst_w[%d] should align as 2 pixel\n", dst_w); 1670 dst_w += 1; 1671 } 1672 1673 xfac = vop2_scale_factor(yrgb_hor_scl_mode, hscl_filter_mode, src_w, dst_w); 1674 yfac = vop2_scale_factor(yrgb_ver_scl_mode, vscl_filter_mode, src_h, dst_h); 1675 vop2_writel(vop2, RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB + win_offset, 1676 yfac << 16 | xfac); 1677 1678 vop2_mask_write(vop2, RK3568_ESMART0_REGION1_CTRL + win_offset, 1679 YRGB_GT2_MASK, YRGB_GT2_SHIFT, gt2, false); 1680 vop2_mask_write(vop2, RK3568_ESMART0_REGION1_CTRL + win_offset, 1681 YRGB_GT4_MASK, YRGB_GT4_SHIFT, gt4, false); 1682 1683 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 1684 YRGB_XSCL_MODE_MASK, YRGB_XSCL_MODE_SHIFT, yrgb_hor_scl_mode, false); 1685 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 1686 YRGB_YSCL_MODE_MASK, YRGB_YSCL_MODE_SHIFT, yrgb_ver_scl_mode, false); 1687 1688 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 1689 YRGB_XSCL_FILTER_MODE_MASK, YRGB_XSCL_FILTER_MODE_SHIFT, 1690 hscl_filter_mode, false); 1691 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 1692 YRGB_YSCL_FILTER_MODE_MASK, YRGB_YSCL_FILTER_MODE_SHIFT, 1693 vscl_filter_mode, false); 1694 } 1695 1696 static int rockchip_vop2_set_plane(struct display_state *state) 1697 { 1698 struct crtc_state *cstate = &state->crtc_state; 1699 struct connector_state *conn_state = &state->conn_state; 1700 struct drm_display_mode *mode = &conn_state->mode; 1701 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 1702 struct vop2 *vop2 = cstate->private; 1703 int src_w = cstate->src_w; 1704 int src_h = cstate->src_h; 1705 int crtc_x = cstate->crtc_x; 1706 int crtc_y = cstate->crtc_y; 1707 int crtc_w = cstate->crtc_w; 1708 int crtc_h = cstate->crtc_h; 1709 int xvir = cstate->xvir; 1710 int y_mirror = 0; 1711 int csc_mode; 1712 u32 win_offset; 1713 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id); 1714 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; 1715 1716 win_offset = vop2->data->win_data[primary_plane_id].reg_offset; 1717 if (crtc_w > cstate->max_output.width) { 1718 printf("ERROR: output w[%d] exceeded max width[%d]\n", 1719 crtc_w, cstate->max_output.width); 1720 return -EINVAL; 1721 } 1722 1723 /* 1724 * This is workaround solution for IC design: 1725 * esmart can't support scale down when actual_w % 16 == 1. 1726 */ 1727 if (src_w > crtc_w && (src_w & 0xf) == 1) { 1728 printf("WARN: vp%d unsupported act_w[%d] mode 16 = 1 when scale down\n", cstate->crtc_id, src_w); 1729 src_w -= 1; 1730 } 1731 1732 act_info = (src_h - 1) << 16; 1733 act_info |= (src_w - 1) & 0xffff; 1734 1735 dsp_info = (crtc_h - 1) << 16; 1736 dsp_info |= (crtc_w - 1) & 0xffff; 1737 1738 dsp_stx = crtc_x; 1739 dsp_sty = crtc_y; 1740 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 1741 1742 if (mode->flags & DRM_MODE_FLAG_YMIRROR) 1743 y_mirror = 1; 1744 else 1745 y_mirror = 0; 1746 1747 vop2_setup_scale(vop2, win_offset, src_w, src_h, crtc_w, crtc_h); 1748 1749 if (y_mirror) 1750 cstate->dma_addr += (src_h - 1) * xvir * 4; 1751 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, EN_MASK, 1752 YMIRROR_EN_SHIFT, y_mirror, false); 1753 1754 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, 1755 WIN_FORMAT_MASK, WIN_FORMAT_SHIFT, cstate->format, 1756 false); 1757 vop2_writel(vop2, RK3568_ESMART0_REGION0_VIR + win_offset, xvir); 1758 vop2_writel(vop2, RK3568_ESMART0_REGION0_YRGB_MST + win_offset, 1759 cstate->dma_addr); 1760 1761 vop2_writel(vop2, RK3568_ESMART0_REGION0_ACT_INFO + win_offset, 1762 act_info); 1763 vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_INFO + win_offset, 1764 dsp_info); 1765 vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_ST + win_offset, dsp_st); 1766 1767 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK, 1768 WIN_EN_SHIFT, 1, false); 1769 1770 csc_mode = vop2_convert_csc_mode(conn_state->color_space); 1771 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, EN_MASK, 1772 RGB2YUV_EN_SHIFT, 1773 is_yuv_output(conn_state->bus_format), false); 1774 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, CSC_MODE_MASK, 1775 CSC_MODE_SHIFT, csc_mode, false); 1776 1777 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 1778 return 0; 1779 } 1780 1781 static int rockchip_vop2_prepare(struct display_state *state) 1782 { 1783 return 0; 1784 } 1785 1786 static int rockchip_vop2_enable(struct display_state *state) 1787 { 1788 struct crtc_state *cstate = &state->crtc_state; 1789 struct vop2 *vop2 = cstate->private; 1790 u32 vp_offset = (cstate->crtc_id * 0x100); 1791 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id); 1792 1793 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1794 STANDBY_EN_SHIFT, 0, false); 1795 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 1796 1797 return 0; 1798 } 1799 1800 static int rockchip_vop2_disable(struct display_state *state) 1801 { 1802 struct crtc_state *cstate = &state->crtc_state; 1803 struct vop2 *vop2 = cstate->private; 1804 u32 vp_offset = (cstate->crtc_id * 0x100); 1805 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id); 1806 1807 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1808 STANDBY_EN_SHIFT, 1, false); 1809 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 1810 1811 return 0; 1812 } 1813 1814 static int rockchip_vop2_fixup_dts(struct display_state *state, void *blob) 1815 { 1816 struct crtc_state *cstate = &state->crtc_state; 1817 struct vop2 *vop2 = cstate->private; 1818 ofnode vp_node; 1819 struct device_node *port_parent_node = cstate->ports_node; 1820 static bool vop_fix_dts; 1821 const char *path; 1822 u32 plane_mask = 0; 1823 int vp_id = 0; 1824 1825 if (vop_fix_dts) 1826 return 0; 1827 1828 ofnode_for_each_subnode(vp_node, np_to_ofnode(port_parent_node)) { 1829 path = vp_node.np->full_name; 1830 plane_mask = vop2->vp_plane_mask[vp_id].plane_mask; 1831 1832 printf("vp%d, plane_mask:0x%x, primary-id:%d\n", 1833 vp_id, plane_mask, 1834 vop2->vp_plane_mask[vp_id].primary_plane_id); 1835 1836 do_fixup_by_path_u32(blob, path, "rockchip,plane-mask", 1837 plane_mask, 1); 1838 do_fixup_by_path_u32(blob, path, "rockchip,primary-plane", 1839 vop2->vp_plane_mask[vp_id].primary_plane_id, 1); 1840 vp_id++; 1841 } 1842 1843 vop_fix_dts = true; 1844 1845 return 0; 1846 } 1847 1848 static struct vop2_vp_plane_mask rk356x_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = { 1849 { /* one display policy */ 1850 {/* main display */ 1851 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 1852 .attached_layers_nr = 6, 1853 .attached_layers = { 1854 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0, 1855 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_SMART1 1856 }, 1857 }, 1858 {/* second display */}, 1859 {/* third display */}, 1860 {/* fourth display */}, 1861 }, 1862 1863 { /* two display policy */ 1864 {/* main display */ 1865 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 1866 .attached_layers_nr = 3, 1867 .attached_layers = { 1868 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0 1869 }, 1870 }, 1871 1872 {/* second display */ 1873 .primary_plane_id = ROCKCHIP_VOP2_SMART1, 1874 .attached_layers_nr = 3, 1875 .attached_layers = { 1876 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_SMART1 1877 }, 1878 }, 1879 {/* third display */}, 1880 {/* fourth display */}, 1881 }, 1882 1883 { /* three display policy */ 1884 {/* main display */ 1885 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 1886 .attached_layers_nr = 3, 1887 .attached_layers = { 1888 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0 1889 }, 1890 }, 1891 1892 {/* second display */ 1893 .primary_plane_id = ROCKCHIP_VOP2_SMART1, 1894 .attached_layers_nr = 2, 1895 .attached_layers = { 1896 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_SMART1 1897 }, 1898 }, 1899 1900 {/* third display */ 1901 .primary_plane_id = ROCKCHIP_VOP2_ESMART1, 1902 .attached_layers_nr = 1, 1903 .attached_layers = { ROCKCHIP_VOP2_ESMART1 }, 1904 }, 1905 1906 {/* fourth display */}, 1907 }, 1908 1909 {/* reserved for four display policy */}, 1910 }; 1911 1912 static struct vop2_win_data rk3568_win_data[6] = { 1913 { 1914 .name = "Cluster0", 1915 .phys_id = ROCKCHIP_VOP2_CLUSTER0, 1916 .win_sel_port_offset = 0, 1917 .layer_sel_win_id = 0, 1918 .reg_offset = 0, 1919 }, 1920 1921 { 1922 .name = "Cluster1", 1923 .phys_id = ROCKCHIP_VOP2_CLUSTER1, 1924 .win_sel_port_offset = 1, 1925 .layer_sel_win_id = 1, 1926 .reg_offset = 0x200, 1927 }, 1928 1929 { 1930 .name = "Esmart0", 1931 .phys_id = ROCKCHIP_VOP2_ESMART0, 1932 .win_sel_port_offset = 4, 1933 .layer_sel_win_id = 2, 1934 .reg_offset = 0, 1935 }, 1936 1937 { 1938 .name = "Esmart1", 1939 .phys_id = ROCKCHIP_VOP2_ESMART1, 1940 .win_sel_port_offset = 5, 1941 .layer_sel_win_id = 6, 1942 .reg_offset = 0x200, 1943 }, 1944 1945 { 1946 .name = "Smart0", 1947 .phys_id = ROCKCHIP_VOP2_SMART0, 1948 .win_sel_port_offset = 6, 1949 .layer_sel_win_id = 3, 1950 .reg_offset = 0x400, 1951 }, 1952 1953 { 1954 .name = "Smart1", 1955 .phys_id = ROCKCHIP_VOP2_SMART1, 1956 .win_sel_port_offset = 7, 1957 .layer_sel_win_id = 7, 1958 .reg_offset = 0x600, 1959 }, 1960 }; 1961 1962 static struct vop2_vp_data rk3568_vp_data[3] = { 1963 { 1964 .feature = VOP_FEATURE_OUTPUT_10BIT, 1965 .pre_scan_max_dly = 42, 1966 .max_output = {4096, 2304}, 1967 }, 1968 { 1969 .feature = 0, 1970 .pre_scan_max_dly = 40, 1971 .max_output = {2048, 1536}, 1972 }, 1973 { 1974 .feature = 0, 1975 .pre_scan_max_dly = 40, 1976 .max_output = {1920, 1080}, 1977 }, 1978 }; 1979 1980 const struct vop2_data rk3568_vop = { 1981 .nr_vps = 3, 1982 .vp_data = rk3568_vp_data, 1983 .win_data = rk3568_win_data, 1984 .plane_mask = rk356x_vp_plane_mask[0], 1985 .nr_layers = 6, 1986 .nr_mixers = 5, 1987 .nr_gammas = 1, 1988 }; 1989 1990 const struct rockchip_crtc_funcs rockchip_vop2_funcs = { 1991 .preinit = rockchip_vop2_preinit, 1992 .prepare = rockchip_vop2_prepare, 1993 .init = rockchip_vop2_init, 1994 .set_plane = rockchip_vop2_set_plane, 1995 .enable = rockchip_vop2_enable, 1996 .disable = rockchip_vop2_disable, 1997 .fixup_dts = rockchip_vop2_fixup_dts, 1998 }; 1999