1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <asm/arch/cpu.h> 14 #include <asm/unaligned.h> 15 #include <asm/io.h> 16 #include <linux/list.h> 17 #include <linux/media-bus-format.h> 18 #include <clk.h> 19 #include <asm/arch/clock.h> 20 #include <linux/err.h> 21 #include <linux/ioport.h> 22 #include <dm/device.h> 23 #include <dm/read.h> 24 #include <fixp-arith.h> 25 #include <syscon.h> 26 27 #include "rockchip_display.h" 28 #include "rockchip_crtc.h" 29 #include "rockchip_connector.h" 30 31 /* System registers definition */ 32 #define RK3568_REG_CFG_DONE 0x000 33 #define CFG_DONE_EN BIT(15) 34 35 #define RK3568_VERSION_INFO 0x004 36 #define EN_MASK 1 37 38 #define RK3568_AUTO_GATING_CTRL 0x008 39 40 #define RK3568_SYS_AXI_LUT_CTRL 0x024 41 #define LUT_DMA_EN_SHIFT 0 42 43 #define RK3568_DSP_IF_EN 0x028 44 #define RGB_EN_SHIFT 0 45 #define HDMI0_EN_SHIFT 1 46 #define EDP0_EN_SHIFT 3 47 #define MIPI0_EN_SHIFT 4 48 #define MIPI1_EN_SHIFT 20 49 #define LVDS0_EN_SHIFT 5 50 #define LVDS1_EN_SHIFT 24 51 #define BT1120_EN_SHIFT 6 52 #define BT656_EN_SHIFT 7 53 #define IF_MUX_MASK 3 54 #define RGB_MUX_SHIFT 8 55 #define HDMI0_MUX_SHIFT 10 56 #define EDP0_MUX_SHIFT 14 57 #define MIPI0_MUX_SHIFT 16 58 #define MIPI1_MUX_SHIFT 21 59 #define LVDS0_MUX_SHIFT 18 60 #define LVDS1_MUX_SHIFT 25 61 62 #define RK3568_DSP_IF_CTRL 0x02c 63 #define LVDS_DUAL_EN_SHIFT 0 64 #define LVDS_DUAL_LEFT_RIGHT_EN_SHIFT 1 65 #define LVDS_DUAL_SWAP_EN_SHIFT 2 66 #define RK3568_DSP_IF_POL 0x030 67 #define IF_CTRL_REG_DONE_IMD_MASK 1 68 #define IF_CTRL_REG_DONE_IMD_SHIFT 28 69 #define IF_CRTL_MIPI_DCLK_POL_SHIT 19 70 #define IF_CRTL_EDP_DCLK_POL_SHIT 15 71 #define IF_CRTL_HDMI_DCLK_POL_SHIT 7 72 #define IF_CRTL_HDMI_PIN_POL_MASK 0x7 73 #define IF_CRTL_HDMI_PIN_POL_SHIT 4 74 #define IF_CRTL_RGB_LVDS_DCLK_POL_SHIT 3 75 #define RK3568_SYS_OTP_WIN_EN 0x50 76 #define OTP_WIN_EN_SHIFT 0 77 #define RK3568_SYS_LUT_PORT_SEL 0x58 78 #define GAMMA_PORT_SEL_MASK 0x3 79 #define GAMMA_PORT_SEL_SHIFT 0 80 81 #define RK3568_VP0_LINE_FLAG 0x70 82 #define RK3568_VP1_LINE_FLAG 0x74 83 #define RK3568_VP2_LINE_FLAG 0x78 84 #define RK3568_SYS0_INT_EN 0x80 85 #define RK3568_SYS0_INT_CLR 0x84 86 #define RK3568_SYS0_INT_STATUS 0x88 87 #define RK3568_SYS1_INT_EN 0x90 88 #define RK3568_SYS1_INT_CLR 0x94 89 #define RK3568_SYS1_INT_STATUS 0x98 90 #define RK3568_VP0_INT_EN 0xA0 91 #define RK3568_VP0_INT_CLR 0xA4 92 #define RK3568_VP0_INT_STATUS 0xA8 93 #define RK3568_VP1_INT_EN 0xB0 94 #define RK3568_VP1_INT_CLR 0xB4 95 #define RK3568_VP1_INT_STATUS 0xB8 96 #define RK3568_VP2_INT_EN 0xC0 97 #define RK3568_VP2_INT_CLR 0xC4 98 #define RK3568_VP2_INT_STATUS 0xC8 99 100 /* Overlay registers definition */ 101 #define RK3568_OVL_CTRL 0x600 102 #define OVL_PORT_MUX_REG_DONE_IMD_SHIFT 28 103 #define RK3568_OVL_LAYER_SEL 0x604 104 #define LAYER_SEL_MASK 0xf 105 106 #define RK3568_OVL_PORT_SEL 0x608 107 #define PORT_MUX_MASK 0xf 108 #define PORT_MUX_SHIFT 0 109 #define LAYER_SEL_PORT_MASK 0x3 110 #define LAYER_SEL_PORT_SHIFT 16 111 112 #define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610 113 #define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614 114 #define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618 115 #define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C 116 #define RK3568_MIX0_SRC_COLOR_CTRL 0x650 117 #define RK3568_MIX0_DST_COLOR_CTRL 0x654 118 #define RK3568_MIX0_SRC_ALPHA_CTRL 0x658 119 #define RK3568_MIX0_DST_ALPHA_CTRL 0x65C 120 #define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0 121 #define RK3568_HDR0_DST_COLOR_CTRL 0x6C4 122 #define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8 123 #define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC 124 #define RK3568_VP0_BG_MIX_CTRL 0x6E0 125 #define BG_MIX_CTRL_MASK 0xff 126 #define BG_MIX_CTRL_SHIFT 24 127 #define RK3568_VP1_BG_MIX_CTRL 0x6E4 128 #define RK3568_VP2_BG_MIX_CTRL 0x6E8 129 #define RK3568_CLUSTER_DLY_NUM 0x6F0 130 #define RK3568_SMART_DLY_NUM 0x6F8 131 132 /* Video Port registers definition */ 133 #define RK3568_VP0_DSP_CTRL 0xC00 134 #define OUT_MODE_MASK 0xf 135 #define OUT_MODE_SHIFT 0 136 #define DATA_SWAP_MASK 0x1f 137 #define DATA_SWAP_SHIFT 8 138 #define DSP_RB_SWAP 2 139 #define CORE_DCLK_DIV_EN_SHIFT 4 140 #define P2I_EN_SHIFT 5 141 #define INTERLACE_EN_SHIFT 7 142 #define POST_DSP_OUT_R2Y_SHIFT 15 143 #define PRE_DITHER_DOWN_EN_SHIFT 16 144 #define DITHER_DOWN_EN_SHIFT 17 145 #define DSP_LUT_EN_SHIFT 28 146 147 #define STANDBY_EN_SHIFT 31 148 149 #define RK3568_VP0_MIPI_CTRL 0xC04 150 #define DCLK_DIV2_SHIFT 4 151 #define DCLK_DIV2_MASK 0x3 152 #define MIPI_DUAL_EN_SHIFT 20 153 #define MIPI_DUAL_SWAP_EN_SHIFT 21 154 155 #define RK3568_VP0_COLOR_BAR_CTRL 0xC08 156 #define RK3568_VP0_3D_LUT_CTRL 0xC10 157 #define VP0_3D_LUT_EN_SHIFT 0 158 #define VP0_3D_LUT_UPDATE_SHIFT 2 159 160 #define RK3568_VP0_3D_LUT_MST 0xC20 161 162 #define RK3568_VP0_DSP_BG 0xC2C 163 #define RK3568_VP0_PRE_SCAN_HTIMING 0xC30 164 #define RK3568_VP0_POST_DSP_HACT_INFO 0xC34 165 #define RK3568_VP0_POST_DSP_VACT_INFO 0xC38 166 #define RK3568_VP0_POST_SCL_FACTOR_YRGB 0xC3C 167 #define RK3568_VP0_POST_SCL_CTRL 0xC40 168 #define RK3568_VP0_POST_DSP_VACT_INFO_F1 0xC44 169 #define RK3568_VP0_DSP_HTOTAL_HS_END 0xC48 170 #define RK3568_VP0_DSP_HACT_ST_END 0xC4C 171 #define RK3568_VP0_DSP_VTOTAL_VS_END 0xC50 172 #define RK3568_VP0_DSP_VACT_ST_END 0xC54 173 #define RK3568_VP0_DSP_VS_ST_END_F1 0xC58 174 #define RK3568_VP0_DSP_VACT_ST_END_F1 0xC5C 175 176 #define RK3568_VP0_BCSH_CTRL 0xC60 177 #define BCSH_CTRL_Y2R_SHIFT 0 178 #define BCSH_CTRL_Y2R_MASK 0x1 179 #define BCSH_CTRL_Y2R_CSC_MODE_SHIFT 2 180 #define BCSH_CTRL_Y2R_CSC_MODE_MASK 0x3 181 #define BCSH_CTRL_R2Y_SHIFT 4 182 #define BCSH_CTRL_R2Y_MASK 0x1 183 #define BCSH_CTRL_R2Y_CSC_MODE_SHIFT 6 184 #define BCSH_CTRL_R2Y_CSC_MODE_MASK 0x3 185 186 #define RK3568_VP0_BCSH_BCS 0xC64 187 #define BCSH_BRIGHTNESS_SHIFT 0 188 #define BCSH_BRIGHTNESS_MASK 0xFF 189 #define BCSH_CONTRAST_SHIFT 8 190 #define BCSH_CONTRAST_MASK 0x1FF 191 #define BCSH_SATURATION_SHIFT 20 192 #define BCSH_SATURATION_MASK 0x3FF 193 #define BCSH_OUT_MODE_SHIFT 30 194 #define BCSH_OUT_MODE_MASK 0x3 195 196 #define RK3568_VP0_BCSH_H 0xC68 197 #define BCSH_SIN_HUE_SHIFT 0 198 #define BCSH_SIN_HUE_MASK 0x1FF 199 #define BCSH_COS_HUE_SHIFT 16 200 #define BCSH_COS_HUE_MASK 0x1FF 201 202 #define RK3568_VP0_BCSH_COLOR 0xC6C 203 #define BCSH_EN_SHIFT 31 204 #define BCSH_EN_MASK 1 205 206 #define RK3568_VP1_DSP_CTRL 0xD00 207 #define RK3568_VP1_MIPI_CTRL 0xD04 208 #define RK3568_VP1_COLOR_BAR_CTRL 0xD08 209 #define RK3568_VP1_PRE_SCAN_HTIMING 0xD30 210 #define RK3568_VP1_POST_DSP_HACT_INFO 0xD34 211 #define RK3568_VP1_POST_DSP_VACT_INFO 0xD38 212 #define RK3568_VP1_POST_SCL_FACTOR_YRGB 0xD3C 213 #define RK3568_VP1_POST_SCL_CTRL 0xD40 214 #define RK3568_VP1_DSP_HACT_INFO 0xD34 215 #define RK3568_VP1_DSP_VACT_INFO 0xD38 216 #define RK3568_VP1_POST_DSP_VACT_INFO_F1 0xD44 217 #define RK3568_VP1_DSP_HTOTAL_HS_END 0xD48 218 #define RK3568_VP1_DSP_HACT_ST_END 0xD4C 219 #define RK3568_VP1_DSP_VTOTAL_VS_END 0xD50 220 #define RK3568_VP1_DSP_VACT_ST_END 0xD54 221 #define RK3568_VP1_DSP_VS_ST_END_F1 0xD58 222 #define RK3568_VP1_DSP_VACT_ST_END_F1 0xD5C 223 224 #define RK3568_VP2_DSP_CTRL 0xE00 225 #define RK3568_VP2_MIPI_CTRL 0xE04 226 #define RK3568_VP2_COLOR_BAR_CTRL 0xE08 227 #define RK3568_VP2_PRE_SCAN_HTIMING 0xE30 228 #define RK3568_VP2_POST_DSP_HACT_INFO 0xE34 229 #define RK3568_VP2_POST_DSP_VACT_INFO 0xE38 230 #define RK3568_VP2_POST_SCL_FACTOR_YRGB 0xE3C 231 #define RK3568_VP2_POST_SCL_CTRL 0xE40 232 #define RK3568_VP2_DSP_HACT_INFO 0xE34 233 #define RK3568_VP2_DSP_VACT_INFO 0xE38 234 #define RK3568_VP2_POST_DSP_VACT_INFO_F1 0xE44 235 #define RK3568_VP2_DSP_HTOTAL_HS_END 0xE48 236 #define RK3568_VP2_DSP_HACT_ST_END 0xE4C 237 #define RK3568_VP2_DSP_VTOTAL_VS_END 0xE50 238 #define RK3568_VP2_DSP_VACT_ST_END 0xE54 239 #define RK3568_VP2_DSP_VS_ST_END_F1 0xE58 240 #define RK3568_VP2_DSP_VACT_ST_END_F1 0xE5C 241 242 /* Cluster0 register definition */ 243 #define RK3568_CLUSTER0_WIN0_CTRL0 0x1000 244 #define RK3568_CLUSTER0_WIN0_CTRL1 0x1004 245 #define RK3568_CLUSTER0_WIN0_YRGB_MST 0x1010 246 #define RK3568_CLUSTER0_WIN0_CBR_MST 0x1014 247 #define RK3568_CLUSTER0_WIN0_VIR 0x1018 248 #define RK3568_CLUSTER0_WIN0_ACT_INFO 0x1020 249 #define RK3568_CLUSTER0_WIN0_DSP_INFO 0x1024 250 #define RK3568_CLUSTER0_WIN0_DSP_ST 0x1028 251 #define RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB 0x1030 252 #define RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE 0x1054 253 #define RK3568_CLUSTER0_WIN0_AFBCD_HDR_PTR 0x1058 254 #define RK3568_CLUSTER0_WIN0_AFBCD_VIR_WIDTH 0x105C 255 #define RK3568_CLUSTER0_WIN0_AFBCD_PIC_SIZE 0x1060 256 #define RK3568_CLUSTER0_WIN0_AFBCD_PIC_OFFSET 0x1064 257 #define RK3568_CLUSTER0_WIN0_AFBCD_DSP_OFFSET 0x1068 258 #define RK3568_CLUSTER0_WIN0_AFBCD_CTRL 0x106C 259 260 #define RK3568_CLUSTER0_WIN1_CTRL0 0x1080 261 #define RK3568_CLUSTER0_WIN1_CTRL1 0x1084 262 #define RK3568_CLUSTER0_WIN1_YRGB_MST 0x1090 263 #define RK3568_CLUSTER0_WIN1_CBR_MST 0x1094 264 #define RK3568_CLUSTER0_WIN1_VIR 0x1098 265 #define RK3568_CLUSTER0_WIN1_ACT_INFO 0x10A0 266 #define RK3568_CLUSTER0_WIN1_DSP_INFO 0x10A4 267 #define RK3568_CLUSTER0_WIN1_DSP_ST 0x10A8 268 #define RK3568_CLUSTER0_WIN1_SCL_FACTOR_YRGB 0x10B0 269 #define RK3568_CLUSTER0_WIN1_AFBCD_ROTATE_MODE 0x10D4 270 #define RK3568_CLUSTER0_WIN1_AFBCD_HDR_PTR 0x10D8 271 #define RK3568_CLUSTER0_WIN1_AFBCD_VIR_WIDTH 0x10DC 272 #define RK3568_CLUSTER0_WIN1_AFBCD_PIC_SIZE 0x10E0 273 #define RK3568_CLUSTER0_WIN1_AFBCD_PIC_OFFSET 0x10E4 274 #define RK3568_CLUSTER0_WIN1_AFBCD_DSP_OFFSET 0x10E8 275 #define RK3568_CLUSTER0_WIN1_AFBCD_CTRL 0x10EC 276 277 #define RK3568_CLUSTER0_CTRL 0x1100 278 279 #define RK3568_CLUSTER1_WIN0_CTRL0 0x1200 280 #define RK3568_CLUSTER1_WIN0_CTRL1 0x1204 281 #define RK3568_CLUSTER1_WIN0_YRGB_MST 0x1210 282 #define RK3568_CLUSTER1_WIN0_CBR_MST 0x1214 283 #define RK3568_CLUSTER1_WIN0_VIR 0x1218 284 #define RK3568_CLUSTER1_WIN0_ACT_INFO 0x1220 285 #define RK3568_CLUSTER1_WIN0_DSP_INFO 0x1224 286 #define RK3568_CLUSTER1_WIN0_DSP_ST 0x1228 287 #define RK3568_CLUSTER1_WIN0_SCL_FACTOR_YRGB 0x1230 288 #define RK3568_CLUSTER1_WIN0_AFBCD_ROTATE_MODE 0x1254 289 #define RK3568_CLUSTER1_WIN0_AFBCD_HDR_PTR 0x1258 290 #define RK3568_CLUSTER1_WIN0_AFBCD_VIR_WIDTH 0x125C 291 #define RK3568_CLUSTER1_WIN0_AFBCD_PIC_SIZE 0x1260 292 #define RK3568_CLUSTER1_WIN0_AFBCD_PIC_OFFSET 0x1264 293 #define RK3568_CLUSTER1_WIN0_AFBCD_DSP_OFFSET 0x1268 294 #define RK3568_CLUSTER1_WIN0_AFBCD_CTRL 0x126C 295 296 #define RK3568_CLUSTER1_WIN1_CTRL0 0x1280 297 #define RK3568_CLUSTER1_WIN1_CTRL1 0x1284 298 #define RK3568_CLUSTER1_WIN1_YRGB_MST 0x1290 299 #define RK3568_CLUSTER1_WIN1_CBR_MST 0x1294 300 #define RK3568_CLUSTER1_WIN1_VIR 0x1298 301 #define RK3568_CLUSTER1_WIN1_ACT_INFO 0x12A0 302 #define RK3568_CLUSTER1_WIN1_DSP_INFO 0x12A4 303 #define RK3568_CLUSTER1_WIN1_DSP_ST 0x12A8 304 #define RK3568_CLUSTER1_WIN1_SCL_FACTOR_YRGB 0x12B0 305 #define RK3568_CLUSTER1_WIN1_AFBCD_ROTATE_MODE 0x12D4 306 #define RK3568_CLUSTER1_WIN1_AFBCD_HDR_PTR 0x12D8 307 #define RK3568_CLUSTER1_WIN1_AFBCD_VIR_WIDTH 0x12DC 308 #define RK3568_CLUSTER1_WIN1_AFBCD_PIC_SIZE 0x12E0 309 #define RK3568_CLUSTER1_WIN1_AFBCD_PIC_OFFSET 0x12E4 310 #define RK3568_CLUSTER1_WIN1_AFBCD_DSP_OFFSET 0x12E8 311 #define RK3568_CLUSTER1_WIN1_AFBCD_CTRL 0x12EC 312 313 #define RK3568_CLUSTER1_CTRL 0x1300 314 315 /* Esmart register definition */ 316 #define RK3568_ESMART0_CTRL0 0x1800 317 #define RGB2YUV_EN_SHIFT 1 318 #define CSC_MODE_SHIFT 2 319 #define CSC_MODE_MASK 0x3 320 321 #define RK3568_ESMART0_CTRL1 0x1804 322 #define YMIRROR_EN_SHIFT 31 323 #define RK3568_ESMART0_REGION0_CTRL 0x1810 324 #define REGION0_RB_SWAP_SHIFT 14 325 #define WIN_EN_SHIFT 0 326 #define WIN_FORMAT_MASK 0x1f 327 #define WIN_FORMAT_SHIFT 1 328 329 #define RK3568_ESMART0_REGION0_YRGB_MST 0x1814 330 #define RK3568_ESMART0_REGION0_CBR_MST 0x1818 331 #define RK3568_ESMART0_REGION0_VIR 0x181C 332 #define RK3568_ESMART0_REGION0_ACT_INFO 0x1820 333 #define RK3568_ESMART0_REGION0_DSP_INFO 0x1824 334 #define RK3568_ESMART0_REGION0_DSP_ST 0x1828 335 #define RK3568_ESMART0_REGION0_SCL_CTRL 0x1830 336 #define YRGB_XSCL_MODE_MASK 0x3 337 #define YRGB_XSCL_MODE_SHIFT 0 338 #define YRGB_XSCL_FILTER_MODE_MASK 0x3 339 #define YRGB_XSCL_FILTER_MODE_SHIFT 2 340 #define YRGB_YSCL_MODE_MASK 0x3 341 #define YRGB_YSCL_MODE_SHIFT 4 342 #define YRGB_YSCL_FILTER_MODE_MASK 0x3 343 #define YRGB_YSCL_FILTER_MODE_SHIFT 6 344 345 #define RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB 0x1834 346 #define RK3568_ESMART0_REGION0_SCL_FACTOR_CBR 0x1838 347 #define RK3568_ESMART0_REGION0_SCL_OFFSET 0x183C 348 #define RK3568_ESMART0_REGION1_CTRL 0x1840 349 #define YRGB_GT2_MASK 0x1 350 #define YRGB_GT2_SHIFT 8 351 #define YRGB_GT4_MASK 0x1 352 #define YRGB_GT4_SHIFT 9 353 354 #define RK3568_ESMART0_REGION1_YRGB_MST 0x1844 355 #define RK3568_ESMART0_REGION1_CBR_MST 0x1848 356 #define RK3568_ESMART0_REGION1_VIR 0x184C 357 #define RK3568_ESMART0_REGION1_ACT_INFO 0x1850 358 #define RK3568_ESMART0_REGION1_DSP_INFO 0x1854 359 #define RK3568_ESMART0_REGION1_DSP_ST 0x1858 360 #define RK3568_ESMART0_REGION1_SCL_CTRL 0x1860 361 #define RK3568_ESMART0_REGION1_SCL_FACTOR_YRGB 0x1864 362 #define RK3568_ESMART0_REGION1_SCL_FACTOR_CBR 0x1868 363 #define RK3568_ESMART0_REGION1_SCL_OFFSET 0x186C 364 #define RK3568_ESMART0_REGION2_CTRL 0x1870 365 #define RK3568_ESMART0_REGION2_YRGB_MST 0x1874 366 #define RK3568_ESMART0_REGION2_CBR_MST 0x1878 367 #define RK3568_ESMART0_REGION2_VIR 0x187C 368 #define RK3568_ESMART0_REGION2_ACT_INFO 0x1880 369 #define RK3568_ESMART0_REGION2_DSP_INFO 0x1884 370 #define RK3568_ESMART0_REGION2_DSP_ST 0x1888 371 #define RK3568_ESMART0_REGION2_SCL_CTRL 0x1890 372 #define RK3568_ESMART0_REGION2_SCL_FACTOR_YRGB 0x1894 373 #define RK3568_ESMART0_REGION2_SCL_FACTOR_CBR 0x1898 374 #define RK3568_ESMART0_REGION2_SCL_OFFSET 0x189C 375 #define RK3568_ESMART0_REGION3_CTRL 0x18A0 376 #define RK3568_ESMART0_REGION3_YRGB_MST 0x18A4 377 #define RK3568_ESMART0_REGION3_CBR_MST 0x18A8 378 #define RK3568_ESMART0_REGION3_VIR 0x18AC 379 #define RK3568_ESMART0_REGION3_ACT_INFO 0x18B0 380 #define RK3568_ESMART0_REGION3_DSP_INFO 0x18B4 381 #define RK3568_ESMART0_REGION3_DSP_ST 0x18B8 382 #define RK3568_ESMART0_REGION3_SCL_CTRL 0x18C0 383 #define RK3568_ESMART0_REGION3_SCL_FACTOR_YRGB 0x18C4 384 #define RK3568_ESMART0_REGION3_SCL_FACTOR_CBR 0x18C8 385 #define RK3568_ESMART0_REGION3_SCL_OFFSET 0x18CC 386 387 #define RK3568_ESMART1_CTRL0 0x1A00 388 #define RK3568_ESMART1_CTRL1 0x1A04 389 #define RK3568_ESMART1_REGION0_CTRL 0x1A10 390 #define RK3568_ESMART1_REGION0_YRGB_MST 0x1A14 391 #define RK3568_ESMART1_REGION0_CBR_MST 0x1A18 392 #define RK3568_ESMART1_REGION0_VIR 0x1A1C 393 #define RK3568_ESMART1_REGION0_ACT_INFO 0x1A20 394 #define RK3568_ESMART1_REGION0_DSP_INFO 0x1A24 395 #define RK3568_ESMART1_REGION0_DSP_ST 0x1A28 396 #define RK3568_ESMART1_REGION0_SCL_CTRL 0x1A30 397 #define RK3568_ESMART1_REGION0_SCL_FACTOR_YRGB 0x1A34 398 #define RK3568_ESMART1_REGION0_SCL_FACTOR_CBR 0x1A38 399 #define RK3568_ESMART1_REGION0_SCL_OFFSET 0x1A3C 400 #define RK3568_ESMART1_REGION1_CTRL 0x1A40 401 #define RK3568_ESMART1_REGION1_YRGB_MST 0x1A44 402 #define RK3568_ESMART1_REGION1_CBR_MST 0x1A48 403 #define RK3568_ESMART1_REGION1_VIR 0x1A4C 404 #define RK3568_ESMART1_REGION1_ACT_INFO 0x1A50 405 #define RK3568_ESMART1_REGION1_DSP_INFO 0x1A54 406 #define RK3568_ESMART1_REGION1_DSP_ST 0x1A58 407 #define RK3568_ESMART1_REGION1_SCL_CTRL 0x1A60 408 #define RK3568_ESMART1_REGION1_SCL_FACTOR_YRGB 0x1A64 409 #define RK3568_ESMART1_REGION1_SCL_FACTOR_CBR 0x1A68 410 #define RK3568_ESMART1_REGION1_SCL_OFFSET 0x1A6C 411 #define RK3568_ESMART1_REGION2_CTRL 0x1A70 412 #define RK3568_ESMART1_REGION2_YRGB_MST 0x1A74 413 #define RK3568_ESMART1_REGION2_CBR_MST 0x1A78 414 #define RK3568_ESMART1_REGION2_VIR 0x1A7C 415 #define RK3568_ESMART1_REGION2_ACT_INFO 0x1A80 416 #define RK3568_ESMART1_REGION2_DSP_INFO 0x1A84 417 #define RK3568_ESMART1_REGION2_DSP_ST 0x1A88 418 #define RK3568_ESMART1_REGION2_SCL_CTRL 0x1A90 419 #define RK3568_ESMART1_REGION2_SCL_FACTOR_YRGB 0x1A94 420 #define RK3568_ESMART1_REGION2_SCL_FACTOR_CBR 0x1A98 421 #define RK3568_ESMART1_REGION2_SCL_OFFSET 0x1A9C 422 #define RK3568_ESMART1_REGION3_CTRL 0x1AA0 423 #define RK3568_ESMART1_REGION3_YRGB_MST 0x1AA4 424 #define RK3568_ESMART1_REGION3_CBR_MST 0x1AA8 425 #define RK3568_ESMART1_REGION3_VIR 0x1AAC 426 #define RK3568_ESMART1_REGION3_ACT_INFO 0x1AB0 427 #define RK3568_ESMART1_REGION3_DSP_INFO 0x1AB4 428 #define RK3568_ESMART1_REGION3_DSP_ST 0x1AB8 429 #define RK3568_ESMART1_REGION3_SCL_CTRL 0x1AC0 430 #define RK3568_ESMART1_REGION3_SCL_FACTOR_YRGB 0x1AC4 431 #define RK3568_ESMART1_REGION3_SCL_FACTOR_CBR 0x1AC8 432 #define RK3568_ESMART1_REGION3_SCL_OFFSET 0x1ACC 433 434 #define RK3568_SMART0_CTRL0 0x1C00 435 #define RK3568_SMART0_CTRL1 0x1C04 436 #define RK3568_SMART0_REGION0_CTRL 0x1C10 437 #define RK3568_SMART0_REGION0_YRGB_MST 0x1C14 438 #define RK3568_SMART0_REGION0_CBR_MST 0x1C18 439 #define RK3568_SMART0_REGION0_VIR 0x1C1C 440 #define RK3568_SMART0_REGION0_ACT_INFO 0x1C20 441 #define RK3568_SMART0_REGION0_DSP_INFO 0x1C24 442 #define RK3568_SMART0_REGION0_DSP_ST 0x1C28 443 #define RK3568_SMART0_REGION0_SCL_CTRL 0x1C30 444 #define RK3568_SMART0_REGION0_SCL_FACTOR_YRGB 0x1C34 445 #define RK3568_SMART0_REGION0_SCL_FACTOR_CBR 0x1C38 446 #define RK3568_SMART0_REGION0_SCL_OFFSET 0x1C3C 447 #define RK3568_SMART0_REGION1_CTRL 0x1C40 448 #define RK3568_SMART0_REGION1_YRGB_MST 0x1C44 449 #define RK3568_SMART0_REGION1_CBR_MST 0x1C48 450 #define RK3568_SMART0_REGION1_VIR 0x1C4C 451 #define RK3568_SMART0_REGION1_ACT_INFO 0x1C50 452 #define RK3568_SMART0_REGION1_DSP_INFO 0x1C54 453 #define RK3568_SMART0_REGION1_DSP_ST 0x1C58 454 #define RK3568_SMART0_REGION1_SCL_CTRL 0x1C60 455 #define RK3568_SMART0_REGION1_SCL_FACTOR_YRGB 0x1C64 456 #define RK3568_SMART0_REGION1_SCL_FACTOR_CBR 0x1C68 457 #define RK3568_SMART0_REGION1_SCL_OFFSET 0x1C6C 458 #define RK3568_SMART0_REGION2_CTRL 0x1C70 459 #define RK3568_SMART0_REGION2_YRGB_MST 0x1C74 460 #define RK3568_SMART0_REGION2_CBR_MST 0x1C78 461 #define RK3568_SMART0_REGION2_VIR 0x1C7C 462 #define RK3568_SMART0_REGION2_ACT_INFO 0x1C80 463 #define RK3568_SMART0_REGION2_DSP_INFO 0x1C84 464 #define RK3568_SMART0_REGION2_DSP_ST 0x1C88 465 #define RK3568_SMART0_REGION2_SCL_CTRL 0x1C90 466 #define RK3568_SMART0_REGION2_SCL_FACTOR_YRGB 0x1C94 467 #define RK3568_SMART0_REGION2_SCL_FACTOR_CBR 0x1C98 468 #define RK3568_SMART0_REGION2_SCL_OFFSET 0x1C9C 469 #define RK3568_SMART0_REGION3_CTRL 0x1CA0 470 #define RK3568_SMART0_REGION3_YRGB_MST 0x1CA4 471 #define RK3568_SMART0_REGION3_CBR_MST 0x1CA8 472 #define RK3568_SMART0_REGION3_VIR 0x1CAC 473 #define RK3568_SMART0_REGION3_ACT_INFO 0x1CB0 474 #define RK3568_SMART0_REGION3_DSP_INFO 0x1CB4 475 #define RK3568_SMART0_REGION3_DSP_ST 0x1CB8 476 #define RK3568_SMART0_REGION3_SCL_CTRL 0x1CC0 477 #define RK3568_SMART0_REGION3_SCL_FACTOR_YRGB 0x1CC4 478 #define RK3568_SMART0_REGION3_SCL_FACTOR_CBR 0x1CC8 479 #define RK3568_SMART0_REGION3_SCL_OFFSET 0x1CCC 480 481 #define RK3568_SMART1_CTRL0 0x1E00 482 #define RK3568_SMART1_CTRL1 0x1E04 483 #define RK3568_SMART1_REGION0_CTRL 0x1E10 484 #define RK3568_SMART1_REGION0_YRGB_MST 0x1E14 485 #define RK3568_SMART1_REGION0_CBR_MST 0x1E18 486 #define RK3568_SMART1_REGION0_VIR 0x1E1C 487 #define RK3568_SMART1_REGION0_ACT_INFO 0x1E20 488 #define RK3568_SMART1_REGION0_DSP_INFO 0x1E24 489 #define RK3568_SMART1_REGION0_DSP_ST 0x1E28 490 #define RK3568_SMART1_REGION0_SCL_CTRL 0x1E30 491 #define RK3568_SMART1_REGION0_SCL_FACTOR_YRGB 0x1E34 492 #define RK3568_SMART1_REGION0_SCL_FACTOR_CBR 0x1E38 493 #define RK3568_SMART1_REGION0_SCL_OFFSET 0x1E3C 494 #define RK3568_SMART1_REGION1_CTRL 0x1E40 495 #define RK3568_SMART1_REGION1_YRGB_MST 0x1E44 496 #define RK3568_SMART1_REGION1_CBR_MST 0x1E48 497 #define RK3568_SMART1_REGION1_VIR 0x1E4C 498 #define RK3568_SMART1_REGION1_ACT_INFO 0x1E50 499 #define RK3568_SMART1_REGION1_DSP_INFO 0x1E54 500 #define RK3568_SMART1_REGION1_DSP_ST 0x1E58 501 #define RK3568_SMART1_REGION1_SCL_CTRL 0x1E60 502 #define RK3568_SMART1_REGION1_SCL_FACTOR_YRGB 0x1E64 503 #define RK3568_SMART1_REGION1_SCL_FACTOR_CBR 0x1E68 504 #define RK3568_SMART1_REGION1_SCL_OFFSET 0x1E6C 505 #define RK3568_SMART1_REGION2_CTRL 0x1E70 506 #define RK3568_SMART1_REGION2_YRGB_MST 0x1E74 507 #define RK3568_SMART1_REGION2_CBR_MST 0x1E78 508 #define RK3568_SMART1_REGION2_VIR 0x1E7C 509 #define RK3568_SMART1_REGION2_ACT_INFO 0x1E80 510 #define RK3568_SMART1_REGION2_DSP_INFO 0x1E84 511 #define RK3568_SMART1_REGION2_DSP_ST 0x1E88 512 #define RK3568_SMART1_REGION2_SCL_CTRL 0x1E90 513 #define RK3568_SMART1_REGION2_SCL_FACTOR_YRGB 0x1E94 514 #define RK3568_SMART1_REGION2_SCL_FACTOR_CBR 0x1E98 515 #define RK3568_SMART1_REGION2_SCL_OFFSET 0x1E9C 516 #define RK3568_SMART1_REGION3_CTRL 0x1EA0 517 #define RK3568_SMART1_REGION3_YRGB_MST 0x1EA4 518 #define RK3568_SMART1_REGION3_CBR_MST 0x1EA8 519 #define RK3568_SMART1_REGION3_VIR 0x1EAC 520 #define RK3568_SMART1_REGION3_ACT_INFO 0x1EB0 521 #define RK3568_SMART1_REGION3_DSP_INFO 0x1EB4 522 #define RK3568_SMART1_REGION3_DSP_ST 0x1EB8 523 #define RK3568_SMART1_REGION3_SCL_CTRL 0x1EC0 524 #define RK3568_SMART1_REGION3_SCL_FACTOR_YRGB 0x1EC4 525 #define RK3568_SMART1_REGION3_SCL_FACTOR_CBR 0x1EC8 526 #define RK3568_SMART1_REGION3_SCL_OFFSET 0x1ECC 527 528 #define RK3568_MAX_REG 0x1ED0 529 530 #define RK3568_GRF_VO_CON1 0x0364 531 #define GRF_BT656_CLK_INV_SHIFT 1 532 #define GRF_BT1120_CLK_INV_SHIFT 2 533 #define GRF_RGB_DCLK_INV_SHIFT 3 534 535 #define VOP2_LAYER_MAX 8 536 537 #define VOP_FEATURE_OUTPUT_10BIT BIT(0) 538 539 enum vop2_csc_format { 540 CSC_BT601L, 541 CSC_BT709L, 542 CSC_BT601F, 543 CSC_BT2020, 544 }; 545 546 enum vop2_pol { 547 HSYNC_POSITIVE = 0, 548 VSYNC_POSITIVE = 1, 549 DEN_NEGATIVE = 2, 550 DCLK_INVERT = 3 551 }; 552 553 enum vop2_bcsh_out_mode { 554 BCSH_OUT_MODE_BLACK, 555 BCSH_OUT_MODE_BLUE, 556 BCSH_OUT_MODE_COLOR_BAR, 557 BCSH_OUT_MODE_NORMAL_VIDEO, 558 }; 559 560 #define _VOP_REG(off, _mask, _shift, _write_mask) \ 561 { \ 562 .offset = off, \ 563 .mask = _mask, \ 564 .shift = _shift, \ 565 .write_mask = _write_mask, \ 566 } 567 568 #define VOP_REG(off, _mask, _shift) \ 569 _VOP_REG(off, _mask, _shift, false) 570 enum dither_down_mode { 571 RGB888_TO_RGB565 = 0x0, 572 RGB888_TO_RGB666 = 0x1 573 }; 574 575 enum vop2_video_ports_id { 576 VOP2_VP0, 577 VOP2_VP1, 578 VOP2_VP2, 579 VOP2_VP3, 580 VOP2_VP_MAX, 581 }; 582 583 /* This define must same with kernel win phy id */ 584 enum vop2_layer_phy_id { 585 ROCKCHIP_VOP2_CLUSTER0 = 0, 586 ROCKCHIP_VOP2_CLUSTER1, 587 ROCKCHIP_VOP2_ESMART0, 588 ROCKCHIP_VOP2_ESMART1, 589 ROCKCHIP_VOP2_SMART0, 590 ROCKCHIP_VOP2_SMART1, 591 ROCKCHIP_VOP2_CLUSTER2, 592 ROCKCHIP_VOP2_CLUSTER3, 593 ROCKCHIP_VOP2_ESMART2, 594 ROCKCHIP_VOP2_ESMART3, 595 }; 596 597 enum vop2_scale_up_mode { 598 VOP2_SCALE_UP_NRST_NBOR, 599 VOP2_SCALE_UP_BIL, 600 VOP2_SCALE_UP_BIC, 601 }; 602 603 enum vop2_scale_down_mode { 604 VOP2_SCALE_DOWN_NRST_NBOR, 605 VOP2_SCALE_DOWN_BIL, 606 VOP2_SCALE_DOWN_AVG, 607 }; 608 609 enum scale_mode { 610 SCALE_NONE = 0x0, 611 SCALE_UP = 0x1, 612 SCALE_DOWN = 0x2 613 }; 614 615 struct vop2_layer { 616 u8 id; 617 /** 618 * @win_phys_id: window id of the layer selected. 619 * Every layer must make sure to select different 620 * windows of others. 621 */ 622 u8 win_phys_id; 623 }; 624 625 struct vop2_win_data { 626 char *name; 627 u8 phys_id; 628 u8 win_sel_port_offset; 629 u8 layer_sel_win_id; 630 u32 reg_offset; 631 }; 632 633 struct vop2_vp_data { 634 u32 feature; 635 u8 pre_scan_max_dly; 636 struct vop_rect max_output; 637 }; 638 639 struct vop2_vp_plane_mask { 640 u8 primary_plane_id; /* use this win to show logo */ 641 u8 attached_layers_nr; /* number layers attach to this vp */ 642 u8 attached_layers[VOP2_LAYER_MAX]; /* the layers attached to this vp */ 643 u32 plane_mask; 644 }; 645 646 struct vop2_data { 647 u32 version; 648 struct vop2_vp_data *vp_data; 649 struct vop2_win_data *win_data; 650 struct vop2_vp_plane_mask *plane_mask; 651 u8 nr_vps; 652 u8 nr_layers; 653 u8 nr_mixers; 654 u8 nr_gammas; 655 }; 656 657 struct vop2 { 658 u32 *regsbak; 659 void *regs; 660 void *grf; 661 u32 reg_len; 662 u32 version; 663 bool global_init; 664 const struct vop2_data *data; 665 struct vop2_vp_plane_mask vp_plane_mask[VOP2_VP_MAX]; 666 }; 667 668 static struct vop2 *rockchip_vop2; 669 /* 670 * bli_sd_factor = (src - 1) / (dst - 1) << 12; 671 * avg_sd_factor: 672 * bli_su_factor: 673 * bic_su_factor: 674 * = (src - 1) / (dst - 1) << 16; 675 * 676 * gt2 enable: dst get one line from two line of the src 677 * gt4 enable: dst get one line from four line of the src. 678 * 679 */ 680 #define VOP2_BILI_SCL_DN(src, dst) (((src - 1) << 12) / (dst - 1)) 681 #define VOP2_COMMON_SCL(src, dst) (((src - 1) << 16) / (dst - 1)) 682 683 #define VOP2_BILI_SCL_FAC_CHECK(src, dst, fac) \ 684 (fac * (dst - 1) >> 12 < (src - 1)) 685 #define VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac) \ 686 (fac * (dst - 1) >> 16 < (src - 1)) 687 688 static uint16_t vop2_scale_factor(enum scale_mode mode, 689 int32_t filter_mode, 690 uint32_t src, uint32_t dst) 691 { 692 uint32_t fac = 0; 693 int i = 0; 694 695 if (mode == SCALE_NONE) 696 return 0; 697 698 /* 699 * A workaround to avoid zero div. 700 */ 701 if ((dst == 1) || (src == 1)) { 702 dst = dst + 1; 703 src = src + 1; 704 } 705 706 if ((mode == SCALE_DOWN) && (filter_mode == VOP2_SCALE_DOWN_BIL)) { 707 fac = VOP2_BILI_SCL_DN(src, dst); 708 for (i = 0; i < 100; i++) { 709 if (VOP2_BILI_SCL_FAC_CHECK(src, dst, fac)) 710 break; 711 fac -= 1; 712 printf("down fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac); 713 } 714 } else { 715 fac = VOP2_COMMON_SCL(src, dst); 716 for (i = 0; i < 100; i++) { 717 if (VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac)) 718 break; 719 fac -= 1; 720 printf("up fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac); 721 } 722 } 723 724 return fac; 725 } 726 727 static inline enum scale_mode scl_get_scl_mode(int src, int dst) 728 { 729 if (src < dst) 730 return SCALE_UP; 731 else if (src > dst) 732 return SCALE_DOWN; 733 734 return SCALE_NONE; 735 } 736 737 static u8 vop2_vp_primary_plane_order[VOP2_VP_MAX] = { 738 ROCKCHIP_VOP2_SMART0, 739 ROCKCHIP_VOP2_SMART1, 740 ROCKCHIP_VOP2_ESMART1, 741 }; 742 743 static inline int interpolate(int x1, int y1, int x2, int y2, int x) 744 { 745 return y1 + (y2 - y1) * (x - x1) / (x2 - x1); 746 } 747 748 static int vop2_get_primary_plane(struct vop2 *vop2, u32 plane_mask) 749 { 750 int i = 0; 751 752 for (i = 0; i < vop2->data->nr_vps; i++) { 753 if (plane_mask & BIT(vop2_vp_primary_plane_order[i])) 754 return vop2_vp_primary_plane_order[i]; 755 } 756 757 return ROCKCHIP_VOP2_SMART0; 758 } 759 760 static inline u16 scl_cal_scale(int src, int dst, int shift) 761 { 762 return ((src * 2 - 3) << (shift - 1)) / (dst - 1); 763 } 764 765 static inline u16 scl_cal_scale2(int src, int dst) 766 { 767 return ((src - 1) << 12) / (dst - 1); 768 } 769 770 static inline void vop2_writel(struct vop2 *vop2, u32 offset, u32 v) 771 { 772 writel(v, vop2->regs + offset); 773 vop2->regsbak[offset >> 2] = v; 774 } 775 776 static inline u32 vop2_readl(struct vop2 *vop2, u32 offset) 777 { 778 return readl(vop2->regs + offset); 779 } 780 781 static inline void vop2_mask_write(struct vop2 *vop2, u32 offset, 782 u32 mask, u32 shift, u32 v, 783 bool write_mask) 784 { 785 if (!mask) 786 return; 787 788 if (write_mask) { 789 v = ((v & mask) << shift) | (mask << (shift + 16)); 790 } else { 791 u32 cached_val = vop2->regsbak[offset >> 2]; 792 793 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 794 vop2->regsbak[offset >> 2] = v; 795 } 796 797 writel(v, vop2->regs + offset); 798 } 799 800 static inline void vop2_grf_writel(struct vop2 *vop, u32 offset, 801 u32 mask, u32 shift, u32 v) 802 { 803 u32 val = 0; 804 805 val = (v << shift) | (mask << (shift + 16)); 806 writel(val, vop->grf + offset); 807 } 808 809 static inline int us_to_vertical_line(struct drm_display_mode *mode, int us) 810 { 811 return us * mode->clock / mode->htotal / 1000; 812 } 813 814 static bool is_yuv_output(u32 bus_format) 815 { 816 switch (bus_format) { 817 case MEDIA_BUS_FMT_YUV8_1X24: 818 case MEDIA_BUS_FMT_YUV10_1X30: 819 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 820 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 821 return true; 822 default: 823 return false; 824 } 825 } 826 827 static int vop2_convert_csc_mode(int csc_mode) 828 { 829 switch (csc_mode) { 830 case V4L2_COLORSPACE_SMPTE170M: 831 case V4L2_COLORSPACE_470_SYSTEM_M: 832 case V4L2_COLORSPACE_470_SYSTEM_BG: 833 return CSC_BT601L; 834 case V4L2_COLORSPACE_REC709: 835 case V4L2_COLORSPACE_SMPTE240M: 836 case V4L2_COLORSPACE_DEFAULT: 837 return CSC_BT709L; 838 case V4L2_COLORSPACE_JPEG: 839 return CSC_BT601F; 840 case V4L2_COLORSPACE_BT2020: 841 return CSC_BT2020; 842 default: 843 return CSC_BT709L; 844 } 845 } 846 847 static bool is_uv_swap(u32 bus_format, u32 output_mode) 848 { 849 /* 850 * FIXME: 851 * 852 * There is no media type for YUV444 output, 853 * so when out_mode is AAAA or P888, assume output is YUV444 on 854 * yuv format. 855 * 856 * From H/W testing, YUV444 mode need a rb swap. 857 */ 858 if ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 859 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 860 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 861 output_mode == ROCKCHIP_OUT_MODE_P888)) 862 return true; 863 else 864 return false; 865 } 866 867 static inline bool is_hot_plug_devices(int output_type) 868 { 869 switch (output_type) { 870 case DRM_MODE_CONNECTOR_HDMIA: 871 case DRM_MODE_CONNECTOR_HDMIB: 872 case DRM_MODE_CONNECTOR_TV: 873 case DRM_MODE_CONNECTOR_DisplayPort: 874 case DRM_MODE_CONNECTOR_VGA: 875 case DRM_MODE_CONNECTOR_Unknown: 876 return true; 877 default: 878 return false; 879 } 880 } 881 882 static int rockchip_vop2_gamma_lut_init(struct vop2 *vop2, 883 struct display_state *state) 884 { 885 struct connector_state *conn_state = &state->conn_state; 886 struct crtc_state *cstate = &state->crtc_state; 887 struct resource gamma_res; 888 fdt_size_t lut_size; 889 int i, lut_len, ret = 0; 890 u32 *lut_regs; 891 u32 *lut_val; 892 u32 r, g, b; 893 u32 vp_offset = cstate->crtc_id * 0x100; 894 struct base2_disp_info *disp_info = conn_state->disp_info; 895 static int gamma_lut_en_num = 1; 896 897 if (gamma_lut_en_num > vop2->data->nr_gammas) { 898 printf("warn: only %d vp support gamma\n", vop2->data->nr_gammas); 899 return 0; 900 } 901 902 if (!disp_info) 903 return 0; 904 905 if (!disp_info->gamma_lut_data.size) 906 return 0; 907 908 ret = ofnode_read_resource_byname(cstate->node, "gamma_lut", &gamma_res); 909 if (ret) 910 printf("failed to get gamma lut res\n"); 911 lut_regs = (u32 *)gamma_res.start; 912 lut_size = gamma_res.end - gamma_res.start + 1; 913 if (lut_regs == (u32 *)FDT_ADDR_T_NONE) { 914 printf("failed to get gamma lut register\n"); 915 return 0; 916 } 917 lut_len = lut_size / 4; 918 if (lut_len != 256 && lut_len != 1024) { 919 printf("Warning: unsupport gamma lut table[%d]\n", lut_len); 920 return 0; 921 } 922 lut_val = (u32 *)calloc(1, lut_size); 923 for (i = 0; i < lut_len; i++) { 924 r = disp_info->gamma_lut_data.lred[i] * (lut_len - 1) / 0xffff; 925 g = disp_info->gamma_lut_data.lgreen[i] * (lut_len - 1) / 0xffff; 926 b = disp_info->gamma_lut_data.lblue[i] * (lut_len - 1) / 0xffff; 927 928 lut_val[i] = b * lut_len * lut_len + g * lut_len + r; 929 } 930 931 for (i = 0; i < lut_len; i++) 932 writel(lut_val[i], lut_regs + i); 933 934 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, 935 GAMMA_PORT_SEL_MASK, GAMMA_PORT_SEL_SHIFT, 936 cstate->crtc_id , false); 937 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 938 EN_MASK, DSP_LUT_EN_SHIFT, 1, false); 939 gamma_lut_en_num++; 940 941 return 0; 942 } 943 944 static int rockchip_vop2_cubic_lut_init(struct vop2 *vop2, 945 struct display_state *state) 946 { 947 struct connector_state *conn_state = &state->conn_state; 948 struct crtc_state *cstate = &state->crtc_state; 949 int i, cubic_lut_len; 950 u32 vp_offset = cstate->crtc_id * 0x100; 951 struct base2_disp_info *disp_info = conn_state->disp_info; 952 struct base2_cubic_lut_data *lut = &conn_state->disp_info->cubic_lut_data; 953 u32 *cubic_lut_addr; 954 955 if (!disp_info || CONFIG_ROCKCHIP_CUBIC_LUT_SIZE == 0) 956 return 0; 957 958 if (!disp_info->cubic_lut_data.size) 959 return 0; 960 961 cubic_lut_addr = (u32 *)get_cubic_lut_buffer(cstate->crtc_id); 962 cubic_lut_len = disp_info->cubic_lut_data.size; 963 964 for (i = 0; i < cubic_lut_len / 2; i++) { 965 *cubic_lut_addr++ = ((lut->lred[2 * i]) & 0xfff) + 966 ((lut->lgreen[2 * i] & 0xfff) << 12) + 967 ((lut->lblue[2 * i] & 0xff) << 24); 968 *cubic_lut_addr++ = ((lut->lblue[2 * i] & 0xf00) >> 8) + 969 ((lut->lred[2 * i + 1] & 0xfff) << 4) + 970 ((lut->lgreen[2 * i + 1] & 0xfff) << 16) + 971 ((lut->lblue[2 * i + 1] & 0xf) << 28); 972 *cubic_lut_addr++ = (lut->lblue[2 * i + 1] & 0xff0) >> 4; 973 *cubic_lut_addr++ = 0; 974 } 975 976 if (cubic_lut_len % 2) { 977 *cubic_lut_addr++ = (lut->lred[2 * i] & 0xfff) + 978 ((lut->lgreen[2 * i] & 0xfff) << 12) + 979 ((lut->lblue[2 * i] & 0xff) << 24); 980 *cubic_lut_addr++ = (lut->lblue[2 * i] & 0xf00) >> 8; 981 *cubic_lut_addr++ = 0; 982 *cubic_lut_addr = 0; 983 } 984 985 vop2_writel(vop2, RK3568_VP0_3D_LUT_MST + vp_offset, 986 get_cubic_lut_buffer(cstate->crtc_id)); 987 vop2_mask_write(vop2, RK3568_SYS_AXI_LUT_CTRL, 988 EN_MASK, LUT_DMA_EN_SHIFT, 1, false); 989 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, 990 EN_MASK, VP0_3D_LUT_EN_SHIFT, 1, false); 991 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, 992 EN_MASK, VP0_3D_LUT_UPDATE_SHIFT, 1, false); 993 994 return 0; 995 } 996 997 static void vop2_tv_config_update(struct display_state *state, struct vop2 *vop2) 998 { 999 struct connector_state *conn_state = &state->conn_state; 1000 struct base_bcsh_info *bcsh_info; 1001 struct crtc_state *cstate = &state->crtc_state; 1002 int brightness, contrast, saturation, hue, sin_hue, cos_hue; 1003 bool bcsh_en = false, post_r2y_en = false, post_y2r_en = false; 1004 u32 vp_offset = (cstate->crtc_id * 0x100); 1005 int post_csc_mode; 1006 1007 if (!conn_state->disp_info) 1008 return; 1009 bcsh_info = &conn_state->disp_info->bcsh_info; 1010 if (!bcsh_info) 1011 return; 1012 1013 if (bcsh_info->brightness != 50 || 1014 bcsh_info->contrast != 50 || 1015 bcsh_info->saturation != 50 || bcsh_info->hue != 50) 1016 bcsh_en = true; 1017 1018 if (bcsh_en) { 1019 if (!cstate->yuv_overlay) 1020 post_r2y_en = 1; 1021 if (!is_yuv_output(conn_state->bus_format)) 1022 post_y2r_en = 1; 1023 } else { 1024 if (!cstate->yuv_overlay && is_yuv_output(conn_state->bus_format)) 1025 post_r2y_en = 1; 1026 if (cstate->yuv_overlay && !is_yuv_output(conn_state->bus_format)) 1027 post_y2r_en = 1; 1028 } 1029 1030 post_csc_mode = vop2_convert_csc_mode(conn_state->color_space); 1031 1032 1033 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_MASK, 1034 BCSH_CTRL_R2Y_SHIFT, post_r2y_en, false); 1035 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_MASK, 1036 BCSH_CTRL_Y2R_SHIFT, post_y2r_en, false); 1037 1038 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_CSC_MODE_MASK, 1039 BCSH_CTRL_R2Y_CSC_MODE_SHIFT, post_csc_mode, false); 1040 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_CSC_MODE_MASK, 1041 BCSH_CTRL_Y2R_CSC_MODE_SHIFT, post_csc_mode, false); 1042 if (!bcsh_en) { 1043 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, 1044 BCSH_EN_MASK, BCSH_EN_SHIFT, 0, false); 1045 return; 1046 } 1047 1048 if (cstate->feature & VOP_FEATURE_OUTPUT_10BIT) 1049 brightness = interpolate(0, -128, 100, 127, 1050 bcsh_info->brightness); 1051 else 1052 brightness = interpolate(0, -32, 100, 31, 1053 bcsh_info->brightness); 1054 contrast = interpolate(0, 0, 100, 511, bcsh_info->contrast); 1055 saturation = interpolate(0, 0, 100, 511, bcsh_info->saturation); 1056 hue = interpolate(0, -30, 100, 30, bcsh_info->hue); 1057 1058 1059 /* 1060 * a:[-30~0): 1061 * sin_hue = 0x100 - sin(a)*256; 1062 * cos_hue = cos(a)*256; 1063 * a:[0~30] 1064 * sin_hue = sin(a)*256; 1065 * cos_hue = cos(a)*256; 1066 */ 1067 sin_hue = fixp_sin32(hue) >> 23; 1068 cos_hue = fixp_cos32(hue) >> 23; 1069 1070 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1071 BCSH_BRIGHTNESS_MASK, BCSH_BRIGHTNESS_SHIFT, 1072 brightness, false); 1073 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1074 BCSH_CONTRAST_MASK, BCSH_CONTRAST_SHIFT, contrast, false); 1075 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1076 BCSH_SATURATION_MASK, BCSH_SATURATION_SHIFT, 1077 saturation * contrast / 0x100, false); 1078 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, 1079 BCSH_SIN_HUE_MASK, BCSH_SIN_HUE_SHIFT, sin_hue, false); 1080 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, 1081 BCSH_COS_HUE_MASK, BCSH_COS_HUE_SHIFT, cos_hue, false); 1082 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1083 BCSH_OUT_MODE_MASK, BCSH_OUT_MODE_SHIFT, 1084 BCSH_OUT_MODE_NORMAL_VIDEO, false); 1085 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, 1086 BCSH_EN_MASK, BCSH_EN_SHIFT, 1, false); 1087 } 1088 1089 static void vop2_post_config(struct display_state *state, struct vop2 *vop2) 1090 { 1091 struct connector_state *conn_state = &state->conn_state; 1092 struct drm_display_mode *mode = &conn_state->mode; 1093 struct crtc_state *cstate = &state->crtc_state; 1094 u32 vp_offset = (cstate->crtc_id * 0x100); 1095 u16 vtotal = mode->crtc_vtotal; 1096 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 1097 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 1098 u16 hdisplay = mode->crtc_hdisplay; 1099 u16 vdisplay = mode->crtc_vdisplay; 1100 u16 hsize = 1101 hdisplay * (conn_state->overscan.left_margin + 1102 conn_state->overscan.right_margin) / 200; 1103 u16 vsize = 1104 vdisplay * (conn_state->overscan.top_margin + 1105 conn_state->overscan.bottom_margin) / 200; 1106 u16 hact_end, vact_end; 1107 u32 val; 1108 u32 bg_ovl_dly, bg_dly, pre_scan_dly; 1109 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 1110 1111 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1112 vsize = round_down(vsize, 2); 1113 1114 hact_st += hdisplay * (100 - conn_state->overscan.left_margin) / 200; 1115 hact_end = hact_st + hsize; 1116 val = hact_st << 16; 1117 val |= hact_end; 1118 1119 vop2_writel(vop2, RK3568_VP0_POST_DSP_HACT_INFO + vp_offset, val); 1120 vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200; 1121 vact_end = vact_st + vsize; 1122 val = vact_st << 16; 1123 val |= vact_end; 1124 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO + vp_offset, val); 1125 val = scl_cal_scale2(vdisplay, vsize) << 16; 1126 val |= scl_cal_scale2(hdisplay, hsize); 1127 vop2_writel(vop2, RK3568_VP0_POST_SCL_FACTOR_YRGB + vp_offset, val); 1128 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0) 1129 #define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1) 1130 vop2_writel(vop2, RK3568_VP0_POST_SCL_CTRL + vp_offset, 1131 POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) | 1132 POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize)); 1133 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1134 u16 vact_st_f1 = vtotal + vact_st + 1; 1135 u16 vact_end_f1 = vact_st_f1 + vsize; 1136 1137 val = vact_st_f1 << 16 | vact_end_f1; 1138 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO_F1 + vp_offset, val); 1139 } 1140 1141 bg_ovl_dly = cstate->crtc->vps[cstate->crtc_id].bg_ovl_dly; 1142 bg_dly = vop2->data->vp_data[cstate->crtc_id].pre_scan_max_dly; 1143 bg_dly -= bg_ovl_dly; 1144 pre_scan_dly = bg_dly + (hdisplay >> 1) - 1; 1145 pre_scan_dly = (pre_scan_dly << 16) | hsync_len; 1146 vop2_mask_write(vop2, RK3568_VP0_BG_MIX_CTRL + cstate->crtc_id * 4, 1147 BG_MIX_CTRL_MASK, BG_MIX_CTRL_SHIFT, bg_dly, false); 1148 vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + vp_offset, pre_scan_dly); 1149 } 1150 1151 static void vop2_global_initial(struct vop2 *vop2, struct display_state *state) 1152 { 1153 struct crtc_state *cstate = &state->crtc_state; 1154 int i, j, port_mux = 0, total_used_layer = 0; 1155 u8 shift = 0; 1156 int layer_phy_id = 0; 1157 u32 layer_nr = 0; 1158 struct vop2_win_data *win_data; 1159 struct vop2_vp_plane_mask *plane_mask; 1160 1161 if (vop2->global_init) 1162 return; 1163 1164 /* OTP must enable at the first time, otherwise mirror layer register is error */ 1165 if (soc_is_rk3566()) 1166 vop2_mask_write(vop2, RK3568_SYS_OTP_WIN_EN, EN_MASK, 1167 OTP_WIN_EN_SHIFT, 1, false); 1168 1169 memcpy(vop2->regsbak, vop2->regs, vop2->reg_len); 1170 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, 1171 OVL_PORT_MUX_REG_DONE_IMD_SHIFT, 1, false); 1172 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1173 IF_CTRL_REG_DONE_IMD_SHIFT, 1, false); 1174 1175 if (cstate->crtc->assign_plane) {/* dts assign plane */ 1176 u32 plane_mask; 1177 int primary_plane_id; 1178 1179 for (i = 0; i < vop2->data->nr_vps; i++) { 1180 plane_mask = cstate->crtc->vps[i].plane_mask; 1181 vop2->vp_plane_mask[i].plane_mask = plane_mask; 1182 layer_nr = hweight32(plane_mask); /* use bitmap to store plane mask */ 1183 vop2->vp_plane_mask[i].attached_layers_nr = layer_nr; 1184 primary_plane_id = vop2_get_primary_plane(vop2, plane_mask); 1185 vop2->vp_plane_mask[i].primary_plane_id = primary_plane_id; 1186 vop2->vp_plane_mask[i].plane_mask = plane_mask; 1187 1188 /* plane mask[bitmap] convert into layer phy id[enum vop2_layer_phy_id]*/ 1189 for (j = 0; j < layer_nr; j++) { 1190 vop2->vp_plane_mask[i].attached_layers[j] = ffs(plane_mask) - 1; 1191 plane_mask &= ~BIT(vop2->vp_plane_mask[i].attached_layers[j]); 1192 } 1193 } 1194 } else {/* need soft assign plane mask */ 1195 /* find the first unplug devices and set it as main display */ 1196 int main_vp_index = -1; 1197 int active_vp_num = 0; 1198 1199 for (i = 0; i < vop2->data->nr_vps; i++) { 1200 if (cstate->crtc->vps[i].enable) 1201 active_vp_num++; 1202 } 1203 printf("VOP have %d active VP\n", active_vp_num); 1204 1205 if (soc_is_rk3566() && active_vp_num > 2) 1206 printf("ERROR: rk3566 only support 2 display output!!\n"); 1207 plane_mask = vop2->data->plane_mask; 1208 plane_mask += (active_vp_num - 1) * VOP2_VP_MAX; 1209 1210 for (i = 0; i < vop2->data->nr_vps; i++) { 1211 if (!is_hot_plug_devices(cstate->crtc->vps[i].output_type)) { 1212 vop2->vp_plane_mask[i] = plane_mask[0]; /* the first store main display plane mask*/ 1213 main_vp_index = i; 1214 } 1215 } 1216 1217 /* if no find unplug devices, use vp0 as main display */ 1218 if (main_vp_index < 0) { 1219 main_vp_index = 0; 1220 vop2->vp_plane_mask[0] = plane_mask[0]; 1221 } 1222 1223 j = 1; /* plane_mask[0] store main display, so we from plane_mask[1] */ 1224 1225 /* init other display except main display */ 1226 for (i = 0; i < vop2->data->nr_vps; i++) { 1227 if (i == main_vp_index || !cstate->crtc->vps[i].enable) /* main display or no connect devices */ 1228 continue; 1229 vop2->vp_plane_mask[i] = plane_mask[j++]; 1230 } 1231 1232 /* store plane mask for vop2_fixup_dts */ 1233 for (i = 0; i < vop2->data->nr_vps; i++) { 1234 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1235 for (j = 0; j < layer_nr; j++) { 1236 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1237 vop2->vp_plane_mask[i].plane_mask |= BIT(layer_phy_id); 1238 } 1239 } 1240 } 1241 1242 for (i = 0; i < vop2->data->nr_vps; i++) { 1243 printf("vp%d have layer nr:%d[", i, vop2->vp_plane_mask[i].attached_layers_nr); 1244 for (j = 0; j < vop2->vp_plane_mask[i].attached_layers_nr; j++) 1245 printf("%d ", vop2->vp_plane_mask[i].attached_layers[j]); 1246 printf("], primary plane: %d\n", vop2->vp_plane_mask[i].primary_plane_id); 1247 } 1248 1249 shift = 0; 1250 /* layer sel win id */ 1251 for (i = 0; i < vop2->data->nr_vps; i++) { 1252 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1253 for (j = 0; j < layer_nr; j++) { 1254 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1255 win_data = &vop2->data->win_data[layer_phy_id]; 1256 vop2_mask_write(vop2, RK3568_OVL_LAYER_SEL, LAYER_SEL_MASK, 1257 shift, win_data->layer_sel_win_id, false); 1258 shift += 4; 1259 } 1260 } 1261 1262 /* win sel port */ 1263 for (i = 0; i < vop2->data->nr_vps; i++) { 1264 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1265 for (j = 0; j < layer_nr; j++) { 1266 if (!cstate->crtc->vps[i].enable) 1267 continue; 1268 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1269 win_data = &vop2->data->win_data[layer_phy_id]; 1270 shift = win_data->win_sel_port_offset * 2; 1271 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, LAYER_SEL_PORT_MASK, 1272 LAYER_SEL_PORT_SHIFT + shift, i, false); 1273 } 1274 } 1275 1276 /** 1277 * port mux config 1278 */ 1279 for (i = 0; i < vop2->data->nr_vps; i++) { 1280 shift = i * 4; 1281 if (cstate->crtc->vps[i].enable) { 1282 total_used_layer += vop2->vp_plane_mask[i].attached_layers_nr; 1283 port_mux = total_used_layer - 1; 1284 } else { 1285 port_mux = 8; 1286 } 1287 1288 if (i == vop2->data->nr_vps - 1) 1289 port_mux = vop2->data->nr_mixers; 1290 1291 cstate->crtc->vps[i].bg_ovl_dly = (vop2->data->nr_mixers - port_mux) << 1; 1292 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, PORT_MUX_MASK, 1293 PORT_MUX_SHIFT + shift, port_mux, false); 1294 } 1295 1296 vop2_writel(vop2, RK3568_AUTO_GATING_CTRL, 0); 1297 1298 vop2->global_init = true; 1299 } 1300 1301 static int vop2_initial(struct vop2 *vop2, struct display_state *state) 1302 { 1303 struct crtc_state *cstate = &state->crtc_state; 1304 struct connector_state *conn_state = &state->conn_state; 1305 struct drm_display_mode *mode = &conn_state->mode; 1306 char dclk_name[9]; 1307 struct clk dclk; 1308 int ret; 1309 1310 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1311 ret = clk_set_defaults(cstate->dev); 1312 if (ret) 1313 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1314 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", cstate->crtc_id); 1315 ret = clk_get_by_name(cstate->dev, dclk_name, &dclk); 1316 if (!ret) 1317 ret = clk_set_rate(&dclk, mode->clock * 1000); 1318 if (IS_ERR_VALUE(ret)) { 1319 printf("%s: Failed to set vp%d dclk[%d khz]: ret=%d\n", 1320 __func__, cstate->crtc_id, mode->clock, ret); 1321 return ret; 1322 } 1323 1324 vop2_global_initial(vop2, state); 1325 rockchip_vop2_gamma_lut_init(vop2, state); 1326 rockchip_vop2_cubic_lut_init(vop2, state); 1327 1328 return 0; 1329 } 1330 1331 /* 1332 * VOP2 have multi video ports. 1333 * video port ------- crtc 1334 */ 1335 static int rockchip_vop2_preinit(struct display_state *state) 1336 { 1337 struct crtc_state *cstate = &state->crtc_state; 1338 const struct vop2_data *vop2_data = cstate->crtc->data; 1339 1340 if (!rockchip_vop2) { 1341 rockchip_vop2 = calloc(1, sizeof(struct vop2)); 1342 if (!rockchip_vop2) 1343 return -ENOMEM; 1344 rockchip_vop2->regs = dev_read_addr_ptr(cstate->dev); 1345 rockchip_vop2->regsbak = malloc(RK3568_MAX_REG); 1346 rockchip_vop2->reg_len = RK3568_MAX_REG; 1347 rockchip_vop2->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1348 if (rockchip_vop2->grf <= 0) 1349 printf("%s: Get syscon grf failed (ret=%p)\n", __func__, rockchip_vop2->grf); 1350 1351 rockchip_vop2->version = vop2_data->version; 1352 rockchip_vop2->data = vop2_data; 1353 } 1354 1355 cstate->private = rockchip_vop2; 1356 cstate->max_output = vop2_data->vp_data[cstate->crtc_id].max_output; 1357 cstate->feature = vop2_data->vp_data[cstate->crtc_id].feature; 1358 1359 return 0; 1360 } 1361 1362 static int rockchip_vop2_init(struct display_state *state) 1363 { 1364 struct crtc_state *cstate = &state->crtc_state; 1365 struct connector_state *conn_state = &state->conn_state; 1366 struct drm_display_mode *mode = &conn_state->mode; 1367 struct vop2 *vop2 = cstate->private; 1368 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 1369 u16 hdisplay = mode->crtc_hdisplay; 1370 u16 htotal = mode->crtc_htotal; 1371 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 1372 u16 hact_end = hact_st + hdisplay; 1373 u16 vdisplay = mode->crtc_vdisplay; 1374 u16 vtotal = mode->crtc_vtotal; 1375 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 1376 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 1377 u16 vact_end = vact_st + vdisplay; 1378 bool yuv_overlay = false; 1379 u32 vp_offset = (cstate->crtc_id * 0x100); 1380 u32 val; 1381 bool dclk_inv; 1382 u8 dither_down_en = 0; 1383 u8 pre_dither_down_en = 0; 1384 1385 vop2_initial(vop2, state); 1386 dclk_inv = (mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1; 1387 val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE); 1388 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE); 1389 1390 if (conn_state->output_if & VOP_OUTPUT_IF_RGB) { 1391 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, 1392 1, false); 1393 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1394 RGB_MUX_SHIFT, cstate->crtc_id, false); 1395 vop2_grf_writel(vop2, RK3568_GRF_VO_CON1, EN_MASK, 1396 GRF_RGB_DCLK_INV_SHIFT, dclk_inv); 1397 } 1398 1399 if (conn_state->output_if & VOP_OUTPUT_IF_BT1120) { 1400 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, 1401 1, false); 1402 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, 1403 BT1120_EN_SHIFT, 1, false); 1404 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1405 RGB_MUX_SHIFT, cstate->crtc_id, false); 1406 vop2_grf_writel(vop2, RK3568_GRF_VO_CON1, EN_MASK, 1407 GRF_BT1120_CLK_INV_SHIFT, !dclk_inv); 1408 } 1409 1410 if (conn_state->output_if & VOP_OUTPUT_IF_BT656) { 1411 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT, 1412 1, false); 1413 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1414 RGB_MUX_SHIFT, cstate->crtc_id, false); 1415 vop2_grf_writel(vop2, RK3568_GRF_VO_CON1, EN_MASK, 1416 GRF_BT656_CLK_INV_SHIFT, !dclk_inv); 1417 } 1418 1419 if (conn_state->output_if & VOP_OUTPUT_IF_LVDS0) { 1420 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT, 1421 1, false); 1422 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1423 LVDS0_MUX_SHIFT, cstate->crtc_id, false); 1424 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1425 IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false); 1426 } 1427 1428 if (conn_state->output_if & VOP_OUTPUT_IF_LVDS1) { 1429 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS1_EN_SHIFT, 1430 1, false); 1431 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1432 LVDS1_MUX_SHIFT, cstate->crtc_id, false); 1433 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1434 IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false); 1435 } 1436 1437 if (conn_state->output_flags & 1438 (ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE | 1439 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)) { 1440 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 1441 LVDS_DUAL_EN_SHIFT, 1, false); 1442 if (conn_state->output_flags & 1443 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 1444 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 1445 LVDS_DUAL_LEFT_RIGHT_EN_SHIFT, 1, 1446 false); 1447 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) 1448 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 1449 LVDS_DUAL_SWAP_EN_SHIFT, 1, false); 1450 } 1451 1452 if (conn_state->output_if & VOP_OUTPUT_IF_MIPI0) { 1453 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT, 1454 1, false); 1455 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1456 MIPI0_MUX_SHIFT, cstate->crtc_id, false); 1457 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1458 IF_CRTL_MIPI_DCLK_POL_SHIT, dclk_inv, false); 1459 } 1460 1461 if (conn_state->output_if & VOP_OUTPUT_IF_MIPI1) { 1462 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI1_EN_SHIFT, 1463 1, false); 1464 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1465 MIPI1_MUX_SHIFT, cstate->crtc_id, false); 1466 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1467 IF_CRTL_MIPI_DCLK_POL_SHIT, dclk_inv, false); 1468 } 1469 1470 if (conn_state->output_flags & 1471 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { 1472 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, 1473 MIPI_DUAL_EN_SHIFT, 1, false); 1474 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) 1475 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 1476 EN_MASK, MIPI_DUAL_SWAP_EN_SHIFT, 1, 1477 false); 1478 } 1479 1480 if (conn_state->output_if & VOP_OUTPUT_IF_eDP0) { 1481 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, EDP0_EN_SHIFT, 1482 1, false); 1483 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1484 EDP0_MUX_SHIFT, cstate->crtc_id, false); 1485 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1486 IF_CRTL_EDP_DCLK_POL_SHIT, dclk_inv, false); 1487 } 1488 1489 if (conn_state->output_if & VOP_OUTPUT_IF_HDMI0) { 1490 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT, 1491 1, false); 1492 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1493 HDMI0_MUX_SHIFT, cstate->crtc_id, false); 1494 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1495 IF_CRTL_HDMI_DCLK_POL_SHIT, 1, false); 1496 vop2_mask_write(vop2, RK3568_DSP_IF_POL, 1497 IF_CRTL_HDMI_PIN_POL_MASK, 1498 IF_CRTL_HDMI_PIN_POL_SHIT, val, false); 1499 } 1500 1501 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1502 !(cstate->feature & VOP_FEATURE_OUTPUT_10BIT)) 1503 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 1504 1505 if (is_uv_swap(conn_state->bus_format, conn_state->output_mode)) 1506 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 1507 DATA_SWAP_MASK, DATA_SWAP_SHIFT, DSP_RB_SWAP, 1508 false); 1509 else 1510 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 1511 DATA_SWAP_MASK, DATA_SWAP_SHIFT, 0, 1512 false); 1513 1514 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, OUT_MODE_MASK, 1515 OUT_MODE_SHIFT, conn_state->output_mode, false); 1516 1517 switch (conn_state->bus_format) { 1518 case MEDIA_BUS_FMT_RGB565_1X16: 1519 dither_down_en = 1; 1520 break; 1521 case MEDIA_BUS_FMT_RGB666_1X18: 1522 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 1523 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 1524 case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA: 1525 dither_down_en = 1; 1526 break; 1527 case MEDIA_BUS_FMT_YUV8_1X24: 1528 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1529 dither_down_en = 0; 1530 pre_dither_down_en = 1; 1531 break; 1532 case MEDIA_BUS_FMT_YUV10_1X30: 1533 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1534 case MEDIA_BUS_FMT_RGB888_1X24: 1535 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 1536 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 1537 default: 1538 dither_down_en = 0; 1539 pre_dither_down_en = 0; 1540 break; 1541 } 1542 1543 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA) 1544 pre_dither_down_en = 0; 1545 else 1546 pre_dither_down_en = 1; 1547 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1548 DITHER_DOWN_EN_SHIFT, dither_down_en, false); 1549 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1550 PRE_DITHER_DOWN_EN_SHIFT, pre_dither_down_en, false); 1551 1552 yuv_overlay = is_yuv_output(conn_state->bus_format) ? 1 : 0; 1553 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, cstate->crtc_id, 1554 yuv_overlay, false); 1555 1556 cstate->yuv_overlay = yuv_overlay; 1557 1558 vop2_writel(vop2, RK3568_VP0_DSP_HTOTAL_HS_END + vp_offset, 1559 (htotal << 16) | hsync_len); 1560 val = hact_st << 16; 1561 val |= hact_end; 1562 vop2_writel(vop2, RK3568_VP0_DSP_HACT_ST_END + vp_offset, val); 1563 val = vact_st << 16; 1564 val |= vact_end; 1565 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END + vp_offset, val); 1566 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1567 u16 vact_st_f1 = vtotal + vact_st + 1; 1568 u16 vact_end_f1 = vact_st_f1 + vdisplay; 1569 1570 val = vact_st_f1 << 16 | vact_end_f1; 1571 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END_F1 + vp_offset, 1572 val); 1573 1574 val = vtotal << 16 | (vtotal + vsync_len); 1575 vop2_writel(vop2, RK3568_VP0_DSP_VS_ST_END_F1 + vp_offset, val); 1576 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1577 INTERLACE_EN_SHIFT, 1, false); 1578 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1579 P2I_EN_SHIFT, 1, false); 1580 vtotal += vtotal + 1; 1581 } else { 1582 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1583 INTERLACE_EN_SHIFT, 0, false); 1584 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1585 P2I_EN_SHIFT, 0, false); 1586 } 1587 vop2_writel(vop2, RK3568_VP0_DSP_VTOTAL_VS_END + vp_offset, 1588 (vtotal << 16) | vsync_len); 1589 val = !!(mode->flags & DRM_MODE_FLAG_DBLCLK); 1590 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1591 CORE_DCLK_DIV_EN_SHIFT, val, false); 1592 1593 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420) 1594 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 1595 DCLK_DIV2_MASK, DCLK_DIV2_SHIFT, 0x3, false); 1596 else 1597 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 1598 DCLK_DIV2_MASK, DCLK_DIV2_SHIFT, 0, false); 1599 1600 if (yuv_overlay) 1601 val = 0x20010200; 1602 else 1603 val = 0; 1604 vop2_writel(vop2, RK3568_VP0_DSP_BG + vp_offset, val); 1605 1606 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1607 POST_DSP_OUT_R2Y_SHIFT, yuv_overlay, false); 1608 1609 vop2_tv_config_update(state, vop2); 1610 vop2_post_config(state, vop2); 1611 1612 return 0; 1613 } 1614 1615 static void vop2_setup_scale(struct vop2 *vop2, uint32_t win_offset, 1616 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 1617 uint32_t dst_h) 1618 { 1619 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 1620 uint16_t hscl_filter_mode, vscl_filter_mode; 1621 uint8_t gt2 = 0, gt4 = 0; 1622 uint32_t xfac = 0, yfac = 0; 1623 uint16_t hsu_filter_mode = VOP2_SCALE_UP_BIC; 1624 uint16_t hsd_filter_mode = VOP2_SCALE_DOWN_BIL; 1625 uint16_t vsu_filter_mode = VOP2_SCALE_UP_BIL; 1626 uint16_t vsd_filter_mode = VOP2_SCALE_DOWN_BIL; 1627 1628 if (src_h >= (4 * dst_h)) 1629 gt4 = 1; 1630 else if (src_h >= (2 * dst_h)) 1631 gt2 = 1; 1632 1633 if (gt4) 1634 src_h >>= 2; 1635 else if (gt2) 1636 src_h >>= 1; 1637 1638 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 1639 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 1640 1641 if (yrgb_hor_scl_mode == SCALE_UP) 1642 hscl_filter_mode = hsu_filter_mode; 1643 else 1644 hscl_filter_mode = hsd_filter_mode; 1645 1646 if (yrgb_ver_scl_mode == SCALE_UP) 1647 vscl_filter_mode = vsu_filter_mode; 1648 else 1649 vscl_filter_mode = vsd_filter_mode; 1650 1651 /* 1652 * RK3568 VOP Esmart/Smart dsp_w should be even pixel 1653 * at scale down mode 1654 */ 1655 if ((yrgb_hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) { 1656 printf("win dst_w[%d] should align as 2 pixel\n", dst_w); 1657 dst_w += 1; 1658 } 1659 1660 xfac = vop2_scale_factor(yrgb_hor_scl_mode, hscl_filter_mode, src_w, dst_w); 1661 yfac = vop2_scale_factor(yrgb_ver_scl_mode, vscl_filter_mode, src_h, dst_h); 1662 vop2_writel(vop2, RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB + win_offset, 1663 yfac << 16 | xfac); 1664 1665 vop2_mask_write(vop2, RK3568_ESMART0_REGION1_CTRL + win_offset, 1666 YRGB_GT2_MASK, YRGB_GT2_SHIFT, gt2, false); 1667 vop2_mask_write(vop2, RK3568_ESMART0_REGION1_CTRL + win_offset, 1668 YRGB_GT4_MASK, YRGB_GT4_SHIFT, gt4, false); 1669 1670 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 1671 YRGB_XSCL_MODE_MASK, YRGB_XSCL_MODE_SHIFT, yrgb_hor_scl_mode, false); 1672 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 1673 YRGB_YSCL_MODE_MASK, YRGB_YSCL_MODE_SHIFT, yrgb_ver_scl_mode, false); 1674 1675 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 1676 YRGB_XSCL_FILTER_MODE_MASK, YRGB_XSCL_FILTER_MODE_SHIFT, 1677 hscl_filter_mode, false); 1678 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 1679 YRGB_YSCL_FILTER_MODE_MASK, YRGB_YSCL_FILTER_MODE_SHIFT, 1680 vscl_filter_mode, false); 1681 } 1682 1683 static int rockchip_vop2_set_plane(struct display_state *state) 1684 { 1685 struct crtc_state *cstate = &state->crtc_state; 1686 struct connector_state *conn_state = &state->conn_state; 1687 struct drm_display_mode *mode = &conn_state->mode; 1688 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 1689 struct vop2 *vop2 = cstate->private; 1690 int src_w = cstate->src_w; 1691 int src_h = cstate->src_h; 1692 int crtc_x = cstate->crtc_x; 1693 int crtc_y = cstate->crtc_y; 1694 int crtc_w = cstate->crtc_w; 1695 int crtc_h = cstate->crtc_h; 1696 int xvir = cstate->xvir; 1697 int y_mirror = 0; 1698 int csc_mode; 1699 u32 win_offset; 1700 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id); 1701 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; 1702 1703 win_offset = vop2->data->win_data[primary_plane_id].reg_offset; 1704 if (crtc_w > cstate->max_output.width) { 1705 printf("ERROR: output w[%d] exceeded max width[%d]\n", 1706 crtc_w, cstate->max_output.width); 1707 return -EINVAL; 1708 } 1709 1710 act_info = (src_h - 1) << 16; 1711 act_info |= (src_w - 1) & 0xffff; 1712 1713 dsp_info = (crtc_h - 1) << 16; 1714 dsp_info |= (crtc_w - 1) & 0xffff; 1715 1716 dsp_stx = crtc_x; 1717 dsp_sty = crtc_y; 1718 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 1719 1720 if (mode->flags & DRM_MODE_FLAG_YMIRROR) 1721 y_mirror = 1; 1722 else 1723 y_mirror = 0; 1724 1725 vop2_setup_scale(vop2, win_offset, src_w, src_h, crtc_w, crtc_h); 1726 1727 if (y_mirror) 1728 cstate->dma_addr += (src_h - 1) * xvir * 4; 1729 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, EN_MASK, 1730 YMIRROR_EN_SHIFT, y_mirror, false); 1731 1732 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, 1733 WIN_FORMAT_MASK, WIN_FORMAT_SHIFT, cstate->format, 1734 false); 1735 vop2_writel(vop2, RK3568_ESMART0_REGION0_VIR + win_offset, xvir); 1736 vop2_writel(vop2, RK3568_ESMART0_REGION0_YRGB_MST + win_offset, 1737 cstate->dma_addr); 1738 1739 vop2_writel(vop2, RK3568_ESMART0_REGION0_ACT_INFO + win_offset, 1740 act_info); 1741 vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_INFO + win_offset, 1742 dsp_info); 1743 vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_ST + win_offset, dsp_st); 1744 1745 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK, 1746 WIN_EN_SHIFT, 1, false); 1747 1748 csc_mode = vop2_convert_csc_mode(conn_state->color_space); 1749 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, EN_MASK, 1750 RGB2YUV_EN_SHIFT, 1751 is_yuv_output(conn_state->bus_format), false); 1752 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, CSC_MODE_MASK, 1753 CSC_MODE_SHIFT, csc_mode, false); 1754 1755 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 1756 return 0; 1757 } 1758 1759 static int rockchip_vop2_prepare(struct display_state *state) 1760 { 1761 return 0; 1762 } 1763 1764 static int rockchip_vop2_enable(struct display_state *state) 1765 { 1766 struct crtc_state *cstate = &state->crtc_state; 1767 struct vop2 *vop2 = cstate->private; 1768 u32 vp_offset = (cstate->crtc_id * 0x100); 1769 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id); 1770 1771 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1772 STANDBY_EN_SHIFT, 0, false); 1773 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 1774 1775 return 0; 1776 } 1777 1778 static int rockchip_vop2_disable(struct display_state *state) 1779 { 1780 struct crtc_state *cstate = &state->crtc_state; 1781 struct vop2 *vop2 = cstate->private; 1782 u32 vp_offset = (cstate->crtc_id * 0x100); 1783 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id); 1784 1785 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1786 STANDBY_EN_SHIFT, 1, false); 1787 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 1788 1789 return 0; 1790 } 1791 1792 static int rockchip_vop2_fixup_dts(struct display_state *state, void *blob) 1793 { 1794 struct crtc_state *cstate = &state->crtc_state; 1795 struct vop2 *vop2 = cstate->private; 1796 ofnode vp_node; 1797 struct device_node *port_parent_node = cstate->ports_node; 1798 static bool vop_fix_dts; 1799 const char *path; 1800 u32 plane_mask = 0; 1801 int vp_id = 0; 1802 1803 if (vop_fix_dts) 1804 return 0; 1805 1806 ofnode_for_each_subnode(vp_node, np_to_ofnode(port_parent_node)) { 1807 path = vp_node.np->full_name; 1808 plane_mask = vop2->vp_plane_mask[vp_id].plane_mask; 1809 1810 printf("vp%d, plane_mask:0x%x, primary-id:%d\n", 1811 vp_id, plane_mask, 1812 vop2->vp_plane_mask[vp_id].primary_plane_id); 1813 1814 do_fixup_by_path_u32(blob, path, "rockchip,plane-mask", 1815 plane_mask, 1); 1816 do_fixup_by_path_u32(blob, path, "rockchip,primary-plane", 1817 vop2->vp_plane_mask[vp_id].primary_plane_id, 1); 1818 vp_id++; 1819 } 1820 1821 vop_fix_dts = true; 1822 1823 return 0; 1824 } 1825 1826 static struct vop2_vp_plane_mask rk356x_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = { 1827 { /* one display policy */ 1828 {/* main display */ 1829 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 1830 .attached_layers_nr = 6, 1831 .attached_layers = { 1832 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0, 1833 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_SMART1 1834 }, 1835 }, 1836 {/* second display */}, 1837 {/* third display */}, 1838 {/* fourth display */}, 1839 }, 1840 1841 { /* two display policy */ 1842 {/* main display */ 1843 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 1844 .attached_layers_nr = 3, 1845 .attached_layers = { 1846 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0 1847 }, 1848 }, 1849 1850 {/* second display */ 1851 .primary_plane_id = ROCKCHIP_VOP2_SMART1, 1852 .attached_layers_nr = 3, 1853 .attached_layers = { 1854 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_SMART1 1855 }, 1856 }, 1857 {/* third display */}, 1858 {/* fourth display */}, 1859 }, 1860 1861 { /* three display policy */ 1862 {/* main display */ 1863 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 1864 .attached_layers_nr = 3, 1865 .attached_layers = { 1866 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0 1867 }, 1868 }, 1869 1870 {/* second display */ 1871 .primary_plane_id = ROCKCHIP_VOP2_SMART1, 1872 .attached_layers_nr = 2, 1873 .attached_layers = { 1874 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_SMART1 1875 }, 1876 }, 1877 1878 {/* third display */ 1879 .primary_plane_id = ROCKCHIP_VOP2_ESMART1, 1880 .attached_layers_nr = 1, 1881 .attached_layers = { ROCKCHIP_VOP2_ESMART1 }, 1882 }, 1883 1884 {/* fourth display */}, 1885 }, 1886 1887 {/* reserved for four display policy */}, 1888 }; 1889 1890 static struct vop2_win_data rk3568_win_data[6] = { 1891 { 1892 .name = "Cluster0", 1893 .phys_id = ROCKCHIP_VOP2_CLUSTER0, 1894 .win_sel_port_offset = 0, 1895 .layer_sel_win_id = 0, 1896 .reg_offset = 0, 1897 }, 1898 1899 { 1900 .name = "Cluster1", 1901 .phys_id = ROCKCHIP_VOP2_CLUSTER1, 1902 .win_sel_port_offset = 1, 1903 .layer_sel_win_id = 1, 1904 .reg_offset = 0x200, 1905 }, 1906 1907 { 1908 .name = "Esmart0", 1909 .phys_id = ROCKCHIP_VOP2_ESMART0, 1910 .win_sel_port_offset = 4, 1911 .layer_sel_win_id = 2, 1912 .reg_offset = 0, 1913 }, 1914 1915 { 1916 .name = "Esmart1", 1917 .phys_id = ROCKCHIP_VOP2_ESMART1, 1918 .win_sel_port_offset = 5, 1919 .layer_sel_win_id = 6, 1920 .reg_offset = 0x200, 1921 }, 1922 1923 { 1924 .name = "Smart0", 1925 .phys_id = ROCKCHIP_VOP2_SMART0, 1926 .win_sel_port_offset = 6, 1927 .layer_sel_win_id = 3, 1928 .reg_offset = 0x400, 1929 }, 1930 1931 { 1932 .name = "Smart1", 1933 .phys_id = ROCKCHIP_VOP2_SMART1, 1934 .win_sel_port_offset = 7, 1935 .layer_sel_win_id = 7, 1936 .reg_offset = 0x600, 1937 }, 1938 }; 1939 1940 static struct vop2_vp_data rk3568_vp_data[3] = { 1941 { 1942 .feature = VOP_FEATURE_OUTPUT_10BIT, 1943 .pre_scan_max_dly = 42, 1944 .max_output = {4096, 2304}, 1945 }, 1946 { 1947 .feature = 0, 1948 .pre_scan_max_dly = 40, 1949 .max_output = {2048, 1536}, 1950 }, 1951 { 1952 .feature = 0, 1953 .pre_scan_max_dly = 40, 1954 .max_output = {1920, 1080}, 1955 }, 1956 }; 1957 1958 const struct vop2_data rk3568_vop = { 1959 .nr_vps = 3, 1960 .vp_data = rk3568_vp_data, 1961 .win_data = rk3568_win_data, 1962 .plane_mask = rk356x_vp_plane_mask[0], 1963 .nr_layers = 6, 1964 .nr_mixers = 5, 1965 .nr_gammas = 1, 1966 }; 1967 1968 const struct rockchip_crtc_funcs rockchip_vop2_funcs = { 1969 .preinit = rockchip_vop2_preinit, 1970 .prepare = rockchip_vop2_prepare, 1971 .init = rockchip_vop2_init, 1972 .set_plane = rockchip_vop2_set_plane, 1973 .enable = rockchip_vop2_enable, 1974 .disable = rockchip_vop2_disable, 1975 .fixup_dts = rockchip_vop2_fixup_dts, 1976 }; 1977