1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <regmap.h> 14 #include <asm/arch/cpu.h> 15 #include <asm/unaligned.h> 16 #include <asm/io.h> 17 #include <linux/list.h> 18 #include <linux/log2.h> 19 #include <linux/media-bus-format.h> 20 #include <clk.h> 21 #include <asm/arch/clock.h> 22 #include <linux/err.h> 23 #include <linux/ioport.h> 24 #include <dm/device.h> 25 #include <dm/read.h> 26 #include <fixp-arith.h> 27 #include <syscon.h> 28 #include <linux/iopoll.h> 29 #include <dm/uclass-internal.h> 30 31 #include "rockchip_display.h" 32 #include "rockchip_crtc.h" 33 #include "rockchip_connector.h" 34 35 /* System registers definition */ 36 #define RK3568_REG_CFG_DONE 0x000 37 #define CFG_DONE_EN BIT(15) 38 39 #define RK3568_VERSION_INFO 0x004 40 #define EN_MASK 1 41 42 #define RK3568_AUTO_GATING_CTRL 0x008 43 44 #define RK3568_SYS_AXI_LUT_CTRL 0x024 45 #define LUT_DMA_EN_SHIFT 0 46 47 #define RK3568_DSP_IF_EN 0x028 48 #define RGB_EN_SHIFT 0 49 #define RK3588_DP0_EN_SHIFT 0 50 #define RK3588_DP1_EN_SHIFT 1 51 #define RK3588_RGB_EN_SHIFT 8 52 #define HDMI0_EN_SHIFT 1 53 #define EDP0_EN_SHIFT 3 54 #define RK3588_EDP0_EN_SHIFT 2 55 #define RK3588_HDMI0_EN_SHIFT 3 56 #define MIPI0_EN_SHIFT 4 57 #define RK3588_EDP1_EN_SHIFT 4 58 #define RK3588_HDMI1_EN_SHIFT 5 59 #define RK3588_MIPI0_EN_SHIFT 6 60 #define MIPI1_EN_SHIFT 20 61 #define RK3588_MIPI1_EN_SHIFT 7 62 #define LVDS0_EN_SHIFT 5 63 #define LVDS1_EN_SHIFT 24 64 #define BT1120_EN_SHIFT 6 65 #define BT656_EN_SHIFT 7 66 #define IF_MUX_MASK 3 67 #define RGB_MUX_SHIFT 8 68 #define HDMI0_MUX_SHIFT 10 69 #define RK3588_DP0_MUX_SHIFT 12 70 #define RK3588_DP1_MUX_SHIFT 14 71 #define EDP0_MUX_SHIFT 14 72 #define RK3588_HDMI_EDP0_MUX_SHIFT 16 73 #define RK3588_HDMI_EDP1_MUX_SHIFT 18 74 #define MIPI0_MUX_SHIFT 16 75 #define RK3588_MIPI0_MUX_SHIFT 20 76 #define MIPI1_MUX_SHIFT 21 77 #define LVDS0_MUX_SHIFT 18 78 #define LVDS1_MUX_SHIFT 25 79 80 #define RK3568_DSP_IF_CTRL 0x02c 81 #define LVDS_DUAL_EN_SHIFT 0 82 #define LVDS_DUAL_LEFT_RIGHT_EN_SHIFT 1 83 #define LVDS_DUAL_SWAP_EN_SHIFT 2 84 #define RK3588_HDMI_DUAL_EN_SHIFT 8 85 #define RK3588_EDP_DUAL_EN_SHIFT 8 86 #define RK3588_DP_DUAL_EN_SHIFT 9 87 #define RK3568_MIPI_DUAL_EN_SHIFT 10 88 #define RK3588_MIPI_DSI0_MODE_SEL_SHIFT 11 89 #define RK3588_MIPI_DSI1_MODE_SEL_SHIFT 12 90 91 #define RK3568_DSP_IF_POL 0x030 92 #define IF_CTRL_REG_DONE_IMD_MASK 1 93 #define IF_CTRL_REG_DONE_IMD_SHIFT 28 94 #define IF_CRTL_MIPI_DCLK_POL_SHIT 19 95 #define IF_CRTL_EDP_DCLK_POL_SHIT 15 96 #define IF_CRTL_HDMI_DCLK_POL_SHIT 7 97 #define IF_CRTL_HDMI_PIN_POL_MASK 0x7 98 #define IF_CRTL_HDMI_PIN_POL_SHIT 4 99 100 #define RK3588_DP0_PIN_POL_SHIFT 8 101 #define RK3588_DP1_PIN_POL_SHIFT 12 102 #define RK3588_IF_PIN_POL_MASK 0x7 103 104 #define IF_CRTL_RGB_LVDS_DCLK_POL_SHIT 3 105 106 #define HDMI_EDP0_DCLK_DIV_SHIFT 16 107 #define HDMI_EDP0_PIXCLK_DIV_SHIFT 18 108 #define HDMI_EDP1_DCLK_DIV_SHIFT 20 109 #define HDMI_EDP1_PIXCLK_DIV_SHIFT 22 110 #define MIPI0_PIXCLK_DIV_SHIFT 24 111 #define MIPI1_PIXCLK_DIV_SHIFT 26 112 113 #define RK3568_SYS_OTP_WIN_EN 0x50 114 #define OTP_WIN_EN_SHIFT 0 115 #define RK3568_SYS_LUT_PORT_SEL 0x58 116 #define GAMMA_PORT_SEL_MASK 0x3 117 #define GAMMA_PORT_SEL_SHIFT 0 118 #define GAMMA_AHB_WRITE_SEL_MASK 0x3 119 #define GAMMA_AHB_WRITE_SEL_SHIFT 12 120 #define PORT_MERGE_EN_SHIFT 16 121 122 #define RK3568_SYS_PD_CTRL 0x034 123 #define RK3568_VP0_LINE_FLAG 0x70 124 #define RK3568_VP1_LINE_FLAG 0x74 125 #define RK3568_VP2_LINE_FLAG 0x78 126 #define RK3568_SYS0_INT_EN 0x80 127 #define RK3568_SYS0_INT_CLR 0x84 128 #define RK3568_SYS0_INT_STATUS 0x88 129 #define RK3568_SYS1_INT_EN 0x90 130 #define RK3568_SYS1_INT_CLR 0x94 131 #define RK3568_SYS1_INT_STATUS 0x98 132 #define RK3568_VP0_INT_EN 0xA0 133 #define RK3568_VP0_INT_CLR 0xA4 134 #define RK3568_VP0_INT_STATUS 0xA8 135 #define RK3568_VP1_INT_EN 0xB0 136 #define RK3568_VP1_INT_CLR 0xB4 137 #define RK3568_VP1_INT_STATUS 0xB8 138 #define RK3568_VP2_INT_EN 0xC0 139 #define RK3568_VP2_INT_CLR 0xC4 140 #define RK3568_VP2_INT_STATUS 0xC8 141 #define RK3588_CLUSTER0_PD_EN_SHIFT 0 142 #define RK3588_CLUSTER1_PD_EN_SHIFT 1 143 #define RK3588_CLUSTER2_PD_EN_SHIFT 2 144 #define RK3588_CLUSTER3_PD_EN_SHIFT 3 145 #define RK3588_DSC_8K_PD_EN_SHIFT 5 146 #define RK3588_DSC_4K_PD_EN_SHIFT 6 147 #define RK3588_ESMART_PD_EN_SHIFT 7 148 149 #define RK3568_SYS_STATUS0 0x60 150 #define RK3588_CLUSTER0_PD_STATUS_SHIFT 8 151 #define RK3588_CLUSTER1_PD_STATUS_SHIFT 9 152 #define RK3588_CLUSTER2_PD_STATUS_SHIFT 10 153 #define RK3588_CLUSTER3_PD_STATUS_SHIFT 11 154 #define RK3588_DSC_8K_PD_STATUS_SHIFT 13 155 #define RK3588_DSC_4K_PD_STATUS_SHIFT 14 156 #define RK3588_ESMART_PD_STATUS_SHIFT 15 157 158 #define RK3568_SYS_CTRL_LINE_FLAG0 0x70 159 #define LINE_FLAG_NUM_MASK 0x1fff 160 #define RK3568_DSP_LINE_FLAG_NUM0_SHIFT 0 161 #define RK3568_DSP_LINE_FLAG_NUM1_SHIFT 16 162 163 /* DSC CTRL registers definition */ 164 #define RK3588_DSC_8K_SYS_CTRL 0x200 165 #define DSC_PORT_SEL_MASK 0x3 166 #define DSC_PORT_SEL_SHIFT 0 167 #define DSC_MAN_MODE_MASK 0x1 168 #define DSC_MAN_MODE_SHIFT 2 169 #define DSC_INTERFACE_MODE_MASK 0x3 170 #define DSC_INTERFACE_MODE_SHIFT 4 171 #define DSC_PIXEL_NUM_MASK 0x3 172 #define DSC_PIXEL_NUM_SHIFT 6 173 #define DSC_PXL_CLK_DIV_MASK 0x1 174 #define DSC_PXL_CLK_DIV_SHIFT 8 175 #define DSC_CDS_CLK_DIV_MASK 0x3 176 #define DSC_CDS_CLK_DIV_SHIFT 12 177 #define DSC_TXP_CLK_DIV_MASK 0x3 178 #define DSC_TXP_CLK_DIV_SHIFT 14 179 #define DSC_INIT_DLY_MODE_MASK 0x1 180 #define DSC_INIT_DLY_MODE_SHIFT 16 181 #define DSC_SCAN_EN_SHIFT 17 182 #define DSC_HALT_EN_SHIFT 18 183 184 #define RK3588_DSC_8K_RST 0x204 185 #define RST_DEASSERT_MASK 0x1 186 #define RST_DEASSERT_SHIFT 0 187 188 #define RK3588_DSC_8K_CFG_DONE 0x208 189 #define DSC_CFG_DONE_SHIFT 0 190 191 #define RK3588_DSC_8K_INIT_DLY 0x20C 192 #define DSC_INIT_DLY_NUM_MASK 0xffff 193 #define DSC_INIT_DLY_NUM_SHIFT 0 194 #define SCAN_TIMING_PARA_IMD_EN_SHIFT 16 195 196 #define RK3588_DSC_8K_HTOTAL_HS_END 0x210 197 #define DSC_HTOTAL_PW_MASK 0xffffffff 198 #define DSC_HTOTAL_PW_SHIFT 0 199 200 #define RK3588_DSC_8K_HACT_ST_END 0x214 201 #define DSC_HACT_ST_END_MASK 0xffffffff 202 #define DSC_HACT_ST_END_SHIFT 0 203 204 #define RK3588_DSC_8K_VTOTAL_VS_END 0x218 205 #define DSC_VTOTAL_PW_MASK 0xffffffff 206 #define DSC_VTOTAL_PW_SHIFT 0 207 208 #define RK3588_DSC_8K_VACT_ST_END 0x21C 209 #define DSC_VACT_ST_END_MASK 0xffffffff 210 #define DSC_VACT_ST_END_SHIFT 0 211 212 #define RK3588_DSC_8K_STATUS 0x220 213 214 /* Overlay registers definition */ 215 #define RK3568_OVL_CTRL 0x600 216 #define OVL_MODE_SEL_MASK 0x1 217 #define OVL_MODE_SEL_SHIFT 0 218 #define OVL_PORT_MUX_REG_DONE_IMD_SHIFT 28 219 #define RK3568_OVL_LAYER_SEL 0x604 220 #define LAYER_SEL_MASK 0xf 221 222 #define RK3568_OVL_PORT_SEL 0x608 223 #define PORT_MUX_MASK 0xf 224 #define PORT_MUX_SHIFT 0 225 #define LAYER_SEL_PORT_MASK 0x3 226 #define LAYER_SEL_PORT_SHIFT 16 227 228 #define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610 229 #define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614 230 #define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618 231 #define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C 232 #define RK3568_MIX0_SRC_COLOR_CTRL 0x650 233 #define RK3568_MIX0_DST_COLOR_CTRL 0x654 234 #define RK3568_MIX0_SRC_ALPHA_CTRL 0x658 235 #define RK3568_MIX0_DST_ALPHA_CTRL 0x65C 236 #define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0 237 #define RK3568_HDR0_DST_COLOR_CTRL 0x6C4 238 #define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8 239 #define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC 240 #define RK3568_VP0_BG_MIX_CTRL 0x6E0 241 #define BG_MIX_CTRL_MASK 0xff 242 #define BG_MIX_CTRL_SHIFT 24 243 #define RK3568_VP1_BG_MIX_CTRL 0x6E4 244 #define RK3568_VP2_BG_MIX_CTRL 0x6E8 245 #define RK3568_CLUSTER_DLY_NUM 0x6F0 246 #define RK3568_SMART_DLY_NUM 0x6F8 247 248 /* Video Port registers definition */ 249 #define RK3568_VP0_DSP_CTRL 0xC00 250 #define OUT_MODE_MASK 0xf 251 #define OUT_MODE_SHIFT 0 252 #define DATA_SWAP_MASK 0x1f 253 #define DATA_SWAP_SHIFT 8 254 #define DSP_BG_SWAP 0x1 255 #define DSP_RB_SWAP 0x2 256 #define DSP_RG_SWAP 0x4 257 #define DSP_DELTA_SWAP 0x8 258 #define CORE_DCLK_DIV_EN_SHIFT 4 259 #define P2I_EN_SHIFT 5 260 #define DSP_FILED_POL 6 261 #define INTERLACE_EN_SHIFT 7 262 #define DSP_X_MIR_EN_SHIFT 13 263 #define POST_DSP_OUT_R2Y_SHIFT 15 264 #define PRE_DITHER_DOWN_EN_SHIFT 16 265 #define DITHER_DOWN_EN_SHIFT 17 266 #define GAMMA_UPDATE_EN_SHIFT 22 267 #define DSP_LUT_EN_SHIFT 28 268 269 #define STANDBY_EN_SHIFT 31 270 271 #define RK3568_VP0_MIPI_CTRL 0xC04 272 #define DCLK_DIV2_SHIFT 4 273 #define DCLK_DIV2_MASK 0x3 274 #define MIPI_DUAL_EN_SHIFT 20 275 #define MIPI_DUAL_SWAP_EN_SHIFT 21 276 #define EDPI_TE_EN 28 277 #define EDPI_WMS_HOLD_EN 30 278 #define EDPI_WMS_FS 31 279 280 281 #define RK3568_VP0_COLOR_BAR_CTRL 0xC08 282 #define RK3568_VP0_3D_LUT_CTRL 0xC10 283 #define VP0_3D_LUT_EN_SHIFT 0 284 #define VP0_3D_LUT_UPDATE_SHIFT 2 285 286 #define RK3588_VP0_CLK_CTRL 0xC0C 287 #define DCLK_CORE_DIV_SHIFT 0 288 #define DCLK_OUT_DIV_SHIFT 2 289 290 #define RK3568_VP0_3D_LUT_MST 0xC20 291 292 #define RK3568_VP0_DSP_BG 0xC2C 293 #define RK3568_VP0_PRE_SCAN_HTIMING 0xC30 294 #define RK3568_VP0_POST_DSP_HACT_INFO 0xC34 295 #define RK3568_VP0_POST_DSP_VACT_INFO 0xC38 296 #define RK3568_VP0_POST_SCL_FACTOR_YRGB 0xC3C 297 #define RK3568_VP0_POST_SCL_CTRL 0xC40 298 #define RK3568_VP0_POST_DSP_VACT_INFO_F1 0xC44 299 #define RK3568_VP0_DSP_HTOTAL_HS_END 0xC48 300 #define RK3568_VP0_DSP_HACT_ST_END 0xC4C 301 #define RK3568_VP0_DSP_VTOTAL_VS_END 0xC50 302 #define RK3568_VP0_DSP_VACT_ST_END 0xC54 303 #define RK3568_VP0_DSP_VS_ST_END_F1 0xC58 304 #define RK3568_VP0_DSP_VACT_ST_END_F1 0xC5C 305 306 #define RK3568_VP0_BCSH_CTRL 0xC60 307 #define BCSH_CTRL_Y2R_SHIFT 0 308 #define BCSH_CTRL_Y2R_MASK 0x1 309 #define BCSH_CTRL_Y2R_CSC_MODE_SHIFT 2 310 #define BCSH_CTRL_Y2R_CSC_MODE_MASK 0x3 311 #define BCSH_CTRL_R2Y_SHIFT 4 312 #define BCSH_CTRL_R2Y_MASK 0x1 313 #define BCSH_CTRL_R2Y_CSC_MODE_SHIFT 6 314 #define BCSH_CTRL_R2Y_CSC_MODE_MASK 0x3 315 316 #define RK3568_VP0_BCSH_BCS 0xC64 317 #define BCSH_BRIGHTNESS_SHIFT 0 318 #define BCSH_BRIGHTNESS_MASK 0xFF 319 #define BCSH_CONTRAST_SHIFT 8 320 #define BCSH_CONTRAST_MASK 0x1FF 321 #define BCSH_SATURATION_SHIFT 20 322 #define BCSH_SATURATION_MASK 0x3FF 323 #define BCSH_OUT_MODE_SHIFT 30 324 #define BCSH_OUT_MODE_MASK 0x3 325 326 #define RK3568_VP0_BCSH_H 0xC68 327 #define BCSH_SIN_HUE_SHIFT 0 328 #define BCSH_SIN_HUE_MASK 0x1FF 329 #define BCSH_COS_HUE_SHIFT 16 330 #define BCSH_COS_HUE_MASK 0x1FF 331 332 #define RK3568_VP0_BCSH_COLOR 0xC6C 333 #define BCSH_EN_SHIFT 31 334 #define BCSH_EN_MASK 1 335 336 #define RK3568_VP1_DSP_CTRL 0xD00 337 #define RK3568_VP1_MIPI_CTRL 0xD04 338 #define RK3568_VP1_COLOR_BAR_CTRL 0xD08 339 #define RK3568_VP1_PRE_SCAN_HTIMING 0xD30 340 #define RK3568_VP1_POST_DSP_HACT_INFO 0xD34 341 #define RK3568_VP1_POST_DSP_VACT_INFO 0xD38 342 #define RK3568_VP1_POST_SCL_FACTOR_YRGB 0xD3C 343 #define RK3568_VP1_POST_SCL_CTRL 0xD40 344 #define RK3568_VP1_DSP_HACT_INFO 0xD34 345 #define RK3568_VP1_DSP_VACT_INFO 0xD38 346 #define RK3568_VP1_POST_DSP_VACT_INFO_F1 0xD44 347 #define RK3568_VP1_DSP_HTOTAL_HS_END 0xD48 348 #define RK3568_VP1_DSP_HACT_ST_END 0xD4C 349 #define RK3568_VP1_DSP_VTOTAL_VS_END 0xD50 350 #define RK3568_VP1_DSP_VACT_ST_END 0xD54 351 #define RK3568_VP1_DSP_VS_ST_END_F1 0xD58 352 #define RK3568_VP1_DSP_VACT_ST_END_F1 0xD5C 353 354 #define RK3568_VP2_DSP_CTRL 0xE00 355 #define RK3568_VP2_MIPI_CTRL 0xE04 356 #define RK3568_VP2_COLOR_BAR_CTRL 0xE08 357 #define RK3568_VP2_PRE_SCAN_HTIMING 0xE30 358 #define RK3568_VP2_POST_DSP_HACT_INFO 0xE34 359 #define RK3568_VP2_POST_DSP_VACT_INFO 0xE38 360 #define RK3568_VP2_POST_SCL_FACTOR_YRGB 0xE3C 361 #define RK3568_VP2_POST_SCL_CTRL 0xE40 362 #define RK3568_VP2_DSP_HACT_INFO 0xE34 363 #define RK3568_VP2_DSP_VACT_INFO 0xE38 364 #define RK3568_VP2_POST_DSP_VACT_INFO_F1 0xE44 365 #define RK3568_VP2_DSP_HTOTAL_HS_END 0xE48 366 #define RK3568_VP2_DSP_HACT_ST_END 0xE4C 367 #define RK3568_VP2_DSP_VTOTAL_VS_END 0xE50 368 #define RK3568_VP2_DSP_VACT_ST_END 0xE54 369 #define RK3568_VP2_DSP_VS_ST_END_F1 0xE58 370 #define RK3568_VP2_DSP_VACT_ST_END_F1 0xE5C 371 372 /* Cluster0 register definition */ 373 #define RK3568_CLUSTER0_WIN0_CTRL0 0x1000 374 #define CLUSTER_YUV2RGB_EN_SHIFT 8 375 #define CLUSTER_RGB2YUV_EN_SHIFT 9 376 #define CLUSTER_CSC_MODE_SHIFT 10 377 #define CLUSTER_YRGB_XSCL_MODE_SHIFT 12 378 #define CLUSTER_YRGB_YSCL_MODE_SHIFT 14 379 #define RK3568_CLUSTER0_WIN0_CTRL1 0x1004 380 #define CLUSTER_YRGB_GT2_SHIFT 28 381 #define CLUSTER_YRGB_GT4_SHIFT 29 382 #define RK3568_CLUSTER0_WIN0_CTRL2 0x1008 383 #define CLUSTER_AXI_YRGB_ID_MASK 0x1f 384 #define CLUSTER_AXI_YRGB_ID_SHIFT 0 385 #define CLUSTER_AXI_UV_ID_MASK 0x1f 386 #define CLUSTER_AXI_UV_ID_SHIFT 5 387 388 #define RK3568_CLUSTER0_WIN0_YRGB_MST 0x1010 389 #define RK3568_CLUSTER0_WIN0_CBR_MST 0x1014 390 #define RK3568_CLUSTER0_WIN0_VIR 0x1018 391 #define RK3568_CLUSTER0_WIN0_ACT_INFO 0x1020 392 #define RK3568_CLUSTER0_WIN0_DSP_INFO 0x1024 393 #define RK3568_CLUSTER0_WIN0_DSP_ST 0x1028 394 #define RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB 0x1030 395 #define RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE 0x1054 396 #define RK3568_CLUSTER0_WIN0_AFBCD_HDR_PTR 0x1058 397 #define RK3568_CLUSTER0_WIN0_AFBCD_VIR_WIDTH 0x105C 398 #define RK3568_CLUSTER0_WIN0_AFBCD_PIC_SIZE 0x1060 399 #define RK3568_CLUSTER0_WIN0_AFBCD_PIC_OFFSET 0x1064 400 #define RK3568_CLUSTER0_WIN0_AFBCD_DSP_OFFSET 0x1068 401 #define RK3568_CLUSTER0_WIN0_AFBCD_CTRL 0x106C 402 403 #define RK3568_CLUSTER0_WIN1_CTRL0 0x1080 404 #define RK3568_CLUSTER0_WIN1_CTRL1 0x1084 405 #define RK3568_CLUSTER0_WIN1_YRGB_MST 0x1090 406 #define RK3568_CLUSTER0_WIN1_CBR_MST 0x1094 407 #define RK3568_CLUSTER0_WIN1_VIR 0x1098 408 #define RK3568_CLUSTER0_WIN1_ACT_INFO 0x10A0 409 #define RK3568_CLUSTER0_WIN1_DSP_INFO 0x10A4 410 #define RK3568_CLUSTER0_WIN1_DSP_ST 0x10A8 411 #define RK3568_CLUSTER0_WIN1_SCL_FACTOR_YRGB 0x10B0 412 #define RK3568_CLUSTER0_WIN1_AFBCD_ROTATE_MODE 0x10D4 413 #define RK3568_CLUSTER0_WIN1_AFBCD_HDR_PTR 0x10D8 414 #define RK3568_CLUSTER0_WIN1_AFBCD_VIR_WIDTH 0x10DC 415 #define RK3568_CLUSTER0_WIN1_AFBCD_PIC_SIZE 0x10E0 416 #define RK3568_CLUSTER0_WIN1_AFBCD_PIC_OFFSET 0x10E4 417 #define RK3568_CLUSTER0_WIN1_AFBCD_DSP_OFFSET 0x10E8 418 #define RK3568_CLUSTER0_WIN1_AFBCD_CTRL 0x10EC 419 420 #define RK3568_CLUSTER0_CTRL 0x1100 421 #define CLUSTER_EN_SHIFT 0 422 #define CLUSTER_AXI_ID_MASK 0x1 423 #define CLUSTER_AXI_ID_SHIFT 13 424 425 #define RK3568_CLUSTER1_WIN0_CTRL0 0x1200 426 #define RK3568_CLUSTER1_WIN0_CTRL1 0x1204 427 #define RK3568_CLUSTER1_WIN0_YRGB_MST 0x1210 428 #define RK3568_CLUSTER1_WIN0_CBR_MST 0x1214 429 #define RK3568_CLUSTER1_WIN0_VIR 0x1218 430 #define RK3568_CLUSTER1_WIN0_ACT_INFO 0x1220 431 #define RK3568_CLUSTER1_WIN0_DSP_INFO 0x1224 432 #define RK3568_CLUSTER1_WIN0_DSP_ST 0x1228 433 #define RK3568_CLUSTER1_WIN0_SCL_FACTOR_YRGB 0x1230 434 #define RK3568_CLUSTER1_WIN0_AFBCD_ROTATE_MODE 0x1254 435 #define RK3568_CLUSTER1_WIN0_AFBCD_HDR_PTR 0x1258 436 #define RK3568_CLUSTER1_WIN0_AFBCD_VIR_WIDTH 0x125C 437 #define RK3568_CLUSTER1_WIN0_AFBCD_PIC_SIZE 0x1260 438 #define RK3568_CLUSTER1_WIN0_AFBCD_PIC_OFFSET 0x1264 439 #define RK3568_CLUSTER1_WIN0_AFBCD_DSP_OFFSET 0x1268 440 #define RK3568_CLUSTER1_WIN0_AFBCD_CTRL 0x126C 441 442 #define RK3568_CLUSTER1_WIN1_CTRL0 0x1280 443 #define RK3568_CLUSTER1_WIN1_CTRL1 0x1284 444 #define RK3568_CLUSTER1_WIN1_YRGB_MST 0x1290 445 #define RK3568_CLUSTER1_WIN1_CBR_MST 0x1294 446 #define RK3568_CLUSTER1_WIN1_VIR 0x1298 447 #define RK3568_CLUSTER1_WIN1_ACT_INFO 0x12A0 448 #define RK3568_CLUSTER1_WIN1_DSP_INFO 0x12A4 449 #define RK3568_CLUSTER1_WIN1_DSP_ST 0x12A8 450 #define RK3568_CLUSTER1_WIN1_SCL_FACTOR_YRGB 0x12B0 451 #define RK3568_CLUSTER1_WIN1_AFBCD_ROTATE_MODE 0x12D4 452 #define RK3568_CLUSTER1_WIN1_AFBCD_HDR_PTR 0x12D8 453 #define RK3568_CLUSTER1_WIN1_AFBCD_VIR_WIDTH 0x12DC 454 #define RK3568_CLUSTER1_WIN1_AFBCD_PIC_SIZE 0x12E0 455 #define RK3568_CLUSTER1_WIN1_AFBCD_PIC_OFFSET 0x12E4 456 #define RK3568_CLUSTER1_WIN1_AFBCD_DSP_OFFSET 0x12E8 457 #define RK3568_CLUSTER1_WIN1_AFBCD_CTRL 0x12EC 458 459 #define RK3568_CLUSTER1_CTRL 0x1300 460 461 /* Esmart register definition */ 462 #define RK3568_ESMART0_CTRL0 0x1800 463 #define RGB2YUV_EN_SHIFT 1 464 #define CSC_MODE_SHIFT 2 465 #define CSC_MODE_MASK 0x3 466 467 #define RK3568_ESMART0_CTRL1 0x1804 468 #define ESMART_AXI_YRGB_ID_MASK 0x1f 469 #define ESMART_AXI_YRGB_ID_SHIFT 4 470 #define ESMART_AXI_UV_ID_MASK 0x1f 471 #define ESMART_AXI_UV_ID_SHIFT 12 472 #define YMIRROR_EN_SHIFT 31 473 474 #define RK3568_ESMART0_AXI_CTRL 0x1808 475 #define ESMART_AXI_ID_MASK 0x1 476 #define ESMART_AXI_ID_SHIFT 1 477 478 #define RK3568_ESMART0_REGION0_CTRL 0x1810 479 #define REGION0_RB_SWAP_SHIFT 14 480 #define WIN_EN_SHIFT 0 481 #define WIN_FORMAT_MASK 0x1f 482 #define WIN_FORMAT_SHIFT 1 483 484 #define RK3568_ESMART0_REGION0_YRGB_MST 0x1814 485 #define RK3568_ESMART0_REGION0_CBR_MST 0x1818 486 #define RK3568_ESMART0_REGION0_VIR 0x181C 487 #define RK3568_ESMART0_REGION0_ACT_INFO 0x1820 488 #define RK3568_ESMART0_REGION0_DSP_INFO 0x1824 489 #define RK3568_ESMART0_REGION0_DSP_ST 0x1828 490 #define RK3568_ESMART0_REGION0_SCL_CTRL 0x1830 491 #define YRGB_XSCL_MODE_MASK 0x3 492 #define YRGB_XSCL_MODE_SHIFT 0 493 #define YRGB_XSCL_FILTER_MODE_MASK 0x3 494 #define YRGB_XSCL_FILTER_MODE_SHIFT 2 495 #define YRGB_YSCL_MODE_MASK 0x3 496 #define YRGB_YSCL_MODE_SHIFT 4 497 #define YRGB_YSCL_FILTER_MODE_MASK 0x3 498 #define YRGB_YSCL_FILTER_MODE_SHIFT 6 499 500 #define RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB 0x1834 501 #define RK3568_ESMART0_REGION0_SCL_FACTOR_CBR 0x1838 502 #define RK3568_ESMART0_REGION0_SCL_OFFSET 0x183C 503 #define RK3568_ESMART0_REGION1_CTRL 0x1840 504 #define YRGB_GT2_MASK 0x1 505 #define YRGB_GT2_SHIFT 8 506 #define YRGB_GT4_MASK 0x1 507 #define YRGB_GT4_SHIFT 9 508 509 #define RK3568_ESMART0_REGION1_YRGB_MST 0x1844 510 #define RK3568_ESMART0_REGION1_CBR_MST 0x1848 511 #define RK3568_ESMART0_REGION1_VIR 0x184C 512 #define RK3568_ESMART0_REGION1_ACT_INFO 0x1850 513 #define RK3568_ESMART0_REGION1_DSP_INFO 0x1854 514 #define RK3568_ESMART0_REGION1_DSP_ST 0x1858 515 #define RK3568_ESMART0_REGION1_SCL_CTRL 0x1860 516 #define RK3568_ESMART0_REGION1_SCL_FACTOR_YRGB 0x1864 517 #define RK3568_ESMART0_REGION1_SCL_FACTOR_CBR 0x1868 518 #define RK3568_ESMART0_REGION1_SCL_OFFSET 0x186C 519 #define RK3568_ESMART0_REGION2_CTRL 0x1870 520 #define RK3568_ESMART0_REGION2_YRGB_MST 0x1874 521 #define RK3568_ESMART0_REGION2_CBR_MST 0x1878 522 #define RK3568_ESMART0_REGION2_VIR 0x187C 523 #define RK3568_ESMART0_REGION2_ACT_INFO 0x1880 524 #define RK3568_ESMART0_REGION2_DSP_INFO 0x1884 525 #define RK3568_ESMART0_REGION2_DSP_ST 0x1888 526 #define RK3568_ESMART0_REGION2_SCL_CTRL 0x1890 527 #define RK3568_ESMART0_REGION2_SCL_FACTOR_YRGB 0x1894 528 #define RK3568_ESMART0_REGION2_SCL_FACTOR_CBR 0x1898 529 #define RK3568_ESMART0_REGION2_SCL_OFFSET 0x189C 530 #define RK3568_ESMART0_REGION3_CTRL 0x18A0 531 #define RK3568_ESMART0_REGION3_YRGB_MST 0x18A4 532 #define RK3568_ESMART0_REGION3_CBR_MST 0x18A8 533 #define RK3568_ESMART0_REGION3_VIR 0x18AC 534 #define RK3568_ESMART0_REGION3_ACT_INFO 0x18B0 535 #define RK3568_ESMART0_REGION3_DSP_INFO 0x18B4 536 #define RK3568_ESMART0_REGION3_DSP_ST 0x18B8 537 #define RK3568_ESMART0_REGION3_SCL_CTRL 0x18C0 538 #define RK3568_ESMART0_REGION3_SCL_FACTOR_YRGB 0x18C4 539 #define RK3568_ESMART0_REGION3_SCL_FACTOR_CBR 0x18C8 540 #define RK3568_ESMART0_REGION3_SCL_OFFSET 0x18CC 541 542 #define RK3568_ESMART1_CTRL0 0x1A00 543 #define RK3568_ESMART1_CTRL1 0x1A04 544 #define RK3568_ESMART1_REGION0_CTRL 0x1A10 545 #define RK3568_ESMART1_REGION0_YRGB_MST 0x1A14 546 #define RK3568_ESMART1_REGION0_CBR_MST 0x1A18 547 #define RK3568_ESMART1_REGION0_VIR 0x1A1C 548 #define RK3568_ESMART1_REGION0_ACT_INFO 0x1A20 549 #define RK3568_ESMART1_REGION0_DSP_INFO 0x1A24 550 #define RK3568_ESMART1_REGION0_DSP_ST 0x1A28 551 #define RK3568_ESMART1_REGION0_SCL_CTRL 0x1A30 552 #define RK3568_ESMART1_REGION0_SCL_FACTOR_YRGB 0x1A34 553 #define RK3568_ESMART1_REGION0_SCL_FACTOR_CBR 0x1A38 554 #define RK3568_ESMART1_REGION0_SCL_OFFSET 0x1A3C 555 #define RK3568_ESMART1_REGION1_CTRL 0x1A40 556 #define RK3568_ESMART1_REGION1_YRGB_MST 0x1A44 557 #define RK3568_ESMART1_REGION1_CBR_MST 0x1A48 558 #define RK3568_ESMART1_REGION1_VIR 0x1A4C 559 #define RK3568_ESMART1_REGION1_ACT_INFO 0x1A50 560 #define RK3568_ESMART1_REGION1_DSP_INFO 0x1A54 561 #define RK3568_ESMART1_REGION1_DSP_ST 0x1A58 562 #define RK3568_ESMART1_REGION1_SCL_CTRL 0x1A60 563 #define RK3568_ESMART1_REGION1_SCL_FACTOR_YRGB 0x1A64 564 #define RK3568_ESMART1_REGION1_SCL_FACTOR_CBR 0x1A68 565 #define RK3568_ESMART1_REGION1_SCL_OFFSET 0x1A6C 566 #define RK3568_ESMART1_REGION2_CTRL 0x1A70 567 #define RK3568_ESMART1_REGION2_YRGB_MST 0x1A74 568 #define RK3568_ESMART1_REGION2_CBR_MST 0x1A78 569 #define RK3568_ESMART1_REGION2_VIR 0x1A7C 570 #define RK3568_ESMART1_REGION2_ACT_INFO 0x1A80 571 #define RK3568_ESMART1_REGION2_DSP_INFO 0x1A84 572 #define RK3568_ESMART1_REGION2_DSP_ST 0x1A88 573 #define RK3568_ESMART1_REGION2_SCL_CTRL 0x1A90 574 #define RK3568_ESMART1_REGION2_SCL_FACTOR_YRGB 0x1A94 575 #define RK3568_ESMART1_REGION2_SCL_FACTOR_CBR 0x1A98 576 #define RK3568_ESMART1_REGION2_SCL_OFFSET 0x1A9C 577 #define RK3568_ESMART1_REGION3_CTRL 0x1AA0 578 #define RK3568_ESMART1_REGION3_YRGB_MST 0x1AA4 579 #define RK3568_ESMART1_REGION3_CBR_MST 0x1AA8 580 #define RK3568_ESMART1_REGION3_VIR 0x1AAC 581 #define RK3568_ESMART1_REGION3_ACT_INFO 0x1AB0 582 #define RK3568_ESMART1_REGION3_DSP_INFO 0x1AB4 583 #define RK3568_ESMART1_REGION3_DSP_ST 0x1AB8 584 #define RK3568_ESMART1_REGION3_SCL_CTRL 0x1AC0 585 #define RK3568_ESMART1_REGION3_SCL_FACTOR_YRGB 0x1AC4 586 #define RK3568_ESMART1_REGION3_SCL_FACTOR_CBR 0x1AC8 587 #define RK3568_ESMART1_REGION3_SCL_OFFSET 0x1ACC 588 589 #define RK3568_SMART0_CTRL0 0x1C00 590 #define RK3568_SMART0_CTRL1 0x1C04 591 #define RK3568_SMART0_REGION0_CTRL 0x1C10 592 #define RK3568_SMART0_REGION0_YRGB_MST 0x1C14 593 #define RK3568_SMART0_REGION0_CBR_MST 0x1C18 594 #define RK3568_SMART0_REGION0_VIR 0x1C1C 595 #define RK3568_SMART0_REGION0_ACT_INFO 0x1C20 596 #define RK3568_SMART0_REGION0_DSP_INFO 0x1C24 597 #define RK3568_SMART0_REGION0_DSP_ST 0x1C28 598 #define RK3568_SMART0_REGION0_SCL_CTRL 0x1C30 599 #define RK3568_SMART0_REGION0_SCL_FACTOR_YRGB 0x1C34 600 #define RK3568_SMART0_REGION0_SCL_FACTOR_CBR 0x1C38 601 #define RK3568_SMART0_REGION0_SCL_OFFSET 0x1C3C 602 #define RK3568_SMART0_REGION1_CTRL 0x1C40 603 #define RK3568_SMART0_REGION1_YRGB_MST 0x1C44 604 #define RK3568_SMART0_REGION1_CBR_MST 0x1C48 605 #define RK3568_SMART0_REGION1_VIR 0x1C4C 606 #define RK3568_SMART0_REGION1_ACT_INFO 0x1C50 607 #define RK3568_SMART0_REGION1_DSP_INFO 0x1C54 608 #define RK3568_SMART0_REGION1_DSP_ST 0x1C58 609 #define RK3568_SMART0_REGION1_SCL_CTRL 0x1C60 610 #define RK3568_SMART0_REGION1_SCL_FACTOR_YRGB 0x1C64 611 #define RK3568_SMART0_REGION1_SCL_FACTOR_CBR 0x1C68 612 #define RK3568_SMART0_REGION1_SCL_OFFSET 0x1C6C 613 #define RK3568_SMART0_REGION2_CTRL 0x1C70 614 #define RK3568_SMART0_REGION2_YRGB_MST 0x1C74 615 #define RK3568_SMART0_REGION2_CBR_MST 0x1C78 616 #define RK3568_SMART0_REGION2_VIR 0x1C7C 617 #define RK3568_SMART0_REGION2_ACT_INFO 0x1C80 618 #define RK3568_SMART0_REGION2_DSP_INFO 0x1C84 619 #define RK3568_SMART0_REGION2_DSP_ST 0x1C88 620 #define RK3568_SMART0_REGION2_SCL_CTRL 0x1C90 621 #define RK3568_SMART0_REGION2_SCL_FACTOR_YRGB 0x1C94 622 #define RK3568_SMART0_REGION2_SCL_FACTOR_CBR 0x1C98 623 #define RK3568_SMART0_REGION2_SCL_OFFSET 0x1C9C 624 #define RK3568_SMART0_REGION3_CTRL 0x1CA0 625 #define RK3568_SMART0_REGION3_YRGB_MST 0x1CA4 626 #define RK3568_SMART0_REGION3_CBR_MST 0x1CA8 627 #define RK3568_SMART0_REGION3_VIR 0x1CAC 628 #define RK3568_SMART0_REGION3_ACT_INFO 0x1CB0 629 #define RK3568_SMART0_REGION3_DSP_INFO 0x1CB4 630 #define RK3568_SMART0_REGION3_DSP_ST 0x1CB8 631 #define RK3568_SMART0_REGION3_SCL_CTRL 0x1CC0 632 #define RK3568_SMART0_REGION3_SCL_FACTOR_YRGB 0x1CC4 633 #define RK3568_SMART0_REGION3_SCL_FACTOR_CBR 0x1CC8 634 #define RK3568_SMART0_REGION3_SCL_OFFSET 0x1CCC 635 636 #define RK3568_SMART1_CTRL0 0x1E00 637 #define RK3568_SMART1_CTRL1 0x1E04 638 #define RK3568_SMART1_REGION0_CTRL 0x1E10 639 #define RK3568_SMART1_REGION0_YRGB_MST 0x1E14 640 #define RK3568_SMART1_REGION0_CBR_MST 0x1E18 641 #define RK3568_SMART1_REGION0_VIR 0x1E1C 642 #define RK3568_SMART1_REGION0_ACT_INFO 0x1E20 643 #define RK3568_SMART1_REGION0_DSP_INFO 0x1E24 644 #define RK3568_SMART1_REGION0_DSP_ST 0x1E28 645 #define RK3568_SMART1_REGION0_SCL_CTRL 0x1E30 646 #define RK3568_SMART1_REGION0_SCL_FACTOR_YRGB 0x1E34 647 #define RK3568_SMART1_REGION0_SCL_FACTOR_CBR 0x1E38 648 #define RK3568_SMART1_REGION0_SCL_OFFSET 0x1E3C 649 #define RK3568_SMART1_REGION1_CTRL 0x1E40 650 #define RK3568_SMART1_REGION1_YRGB_MST 0x1E44 651 #define RK3568_SMART1_REGION1_CBR_MST 0x1E48 652 #define RK3568_SMART1_REGION1_VIR 0x1E4C 653 #define RK3568_SMART1_REGION1_ACT_INFO 0x1E50 654 #define RK3568_SMART1_REGION1_DSP_INFO 0x1E54 655 #define RK3568_SMART1_REGION1_DSP_ST 0x1E58 656 #define RK3568_SMART1_REGION1_SCL_CTRL 0x1E60 657 #define RK3568_SMART1_REGION1_SCL_FACTOR_YRGB 0x1E64 658 #define RK3568_SMART1_REGION1_SCL_FACTOR_CBR 0x1E68 659 #define RK3568_SMART1_REGION1_SCL_OFFSET 0x1E6C 660 #define RK3568_SMART1_REGION2_CTRL 0x1E70 661 #define RK3568_SMART1_REGION2_YRGB_MST 0x1E74 662 #define RK3568_SMART1_REGION2_CBR_MST 0x1E78 663 #define RK3568_SMART1_REGION2_VIR 0x1E7C 664 #define RK3568_SMART1_REGION2_ACT_INFO 0x1E80 665 #define RK3568_SMART1_REGION2_DSP_INFO 0x1E84 666 #define RK3568_SMART1_REGION2_DSP_ST 0x1E88 667 #define RK3568_SMART1_REGION2_SCL_CTRL 0x1E90 668 #define RK3568_SMART1_REGION2_SCL_FACTOR_YRGB 0x1E94 669 #define RK3568_SMART1_REGION2_SCL_FACTOR_CBR 0x1E98 670 #define RK3568_SMART1_REGION2_SCL_OFFSET 0x1E9C 671 #define RK3568_SMART1_REGION3_CTRL 0x1EA0 672 #define RK3568_SMART1_REGION3_YRGB_MST 0x1EA4 673 #define RK3568_SMART1_REGION3_CBR_MST 0x1EA8 674 #define RK3568_SMART1_REGION3_VIR 0x1EAC 675 #define RK3568_SMART1_REGION3_ACT_INFO 0x1EB0 676 #define RK3568_SMART1_REGION3_DSP_INFO 0x1EB4 677 #define RK3568_SMART1_REGION3_DSP_ST 0x1EB8 678 #define RK3568_SMART1_REGION3_SCL_CTRL 0x1EC0 679 #define RK3568_SMART1_REGION3_SCL_FACTOR_YRGB 0x1EC4 680 #define RK3568_SMART1_REGION3_SCL_FACTOR_CBR 0x1EC8 681 #define RK3568_SMART1_REGION3_SCL_OFFSET 0x1ECC 682 683 /* DSC 8K/4K register definition */ 684 #define RK3588_DSC_8K_PPS0_3 0x4000 685 #define RK3588_DSC_8K_CTRL0 0x40A0 686 #define DSC_EN_SHIFT 0 687 #define DSC_RBIT_SHIFT 2 688 #define DSC_RBYT_SHIFT 3 689 #define DSC_FLAL_SHIFT 4 690 #define DSC_MER_SHIFT 5 691 #define DSC_EPB_SHIFT 6 692 #define DSC_EPL_SHIFT 7 693 #define DSC_NSLC_SHIFT 16 694 #define DSC_SBO_SHIFT 28 695 #define DSC_IFEP_SHIFT 29 696 #define DSC_PPS_UPD_SHIFT 31 697 698 #define RK3588_DSC_8K_CTRL1 0x40A4 699 #define RK3588_DSC_8K_STS0 0x40A8 700 #define RK3588_DSC_8K_ERS 0x40C4 701 702 #define RK3588_DSC_4K_PPS0_3 0x4100 703 #define RK3588_DSC_4K_CTRL0 0x41A0 704 #define RK3588_DSC_4K_CTRL1 0x41A4 705 #define RK3588_DSC_4K_STS0 0x41A8 706 #define RK3588_DSC_4K_ERS 0x41C4 707 708 #define RK3568_MAX_REG 0x1ED0 709 710 #define RK3568_GRF_VO_CON1 0x0364 711 #define GRF_BT656_CLK_INV_SHIFT 1 712 #define GRF_BT1120_CLK_INV_SHIFT 2 713 #define GRF_RGB_DCLK_INV_SHIFT 3 714 715 #define RK3588_GRF_VOP_CON2 0x0008 716 #define RK3588_GRF_EDP0_ENABLE_SHIFT 0 717 #define RK3588_GRF_HDMITX0_ENABLE_SHIFT 1 718 #define RK3588_GRF_EDP1_ENABLE_SHIFT 3 719 #define RK3588_GRF_HDMITX1_ENABLE_SHIFT 4 720 721 #define RK3588_GRF_VO1_CON0 0x0000 722 #define HDMI_SYNC_POL_MASK 0x3 723 #define HDMI0_SYNC_POL_SHIFT 5 724 #define HDMI1_SYNC_POL_SHIFT 7 725 726 #define RK3588_PMU_BISR_CON3 0x20C 727 #define RK3588_PD_CLUSTER0_REPAIR_EN_SHIFT 9 728 #define RK3588_PD_CLUSTER1_REPAIR_EN_SHIFT 10 729 #define RK3588_PD_CLUSTER2_REPAIR_EN_SHIFT 11 730 #define RK3588_PD_CLUSTER3_REPAIR_EN_SHIFT 12 731 #define RK3588_PD_DSC_8K_REPAIR_EN_SHIFT 13 732 #define RK3588_PD_DSC_4K_REPAIR_EN_SHIFT 14 733 #define RK3588_PD_ESMART_REPAIR_EN_SHIFT 15 734 735 #define RK3588_PMU_BISR_STATUS5 0x294 736 #define RK3588_PD_CLUSTER0_PWR_STAT_SHIFI 9 737 #define RK3588_PD_CLUSTER1_PWR_STAT_SHIFI 10 738 #define RK3588_PD_CLUSTER2_PWR_STAT_SHIFI 11 739 #define RK3588_PD_CLUSTER3_PWR_STAT_SHIFI 12 740 #define RK3588_PD_DSC_8K_PWR_STAT_SHIFI 13 741 #define RK3588_PD_DSC_4K_PWR_STAT_SHIFI 14 742 #define RK3588_PD_ESMART_PWR_STAT_SHIFI 15 743 744 #define VOP2_LAYER_MAX 8 745 746 #define VOP2_MAX_VP_OUTPUT_WIDTH 4096 747 748 #define VOP_FEATURE_OUTPUT_10BIT BIT(0) 749 750 /* KHz */ 751 #define VOP2_MAX_DCLK_RATE 600000 752 753 /* 754 * vop2 dsc id 755 */ 756 #define ROCKCHIP_VOP2_DSC_8K 0 757 #define ROCKCHIP_VOP2_DSC_4K 1 758 759 /* 760 * vop2 internal power domain id, 761 * should be all none zero, 0 will be 762 * treat as invalid; 763 */ 764 #define VOP2_PD_CLUSTER0 BIT(0) 765 #define VOP2_PD_CLUSTER1 BIT(1) 766 #define VOP2_PD_CLUSTER2 BIT(2) 767 #define VOP2_PD_CLUSTER3 BIT(3) 768 #define VOP2_PD_DSC_8K BIT(5) 769 #define VOP2_PD_DSC_4K BIT(6) 770 #define VOP2_PD_ESMART BIT(7) 771 772 #define VOP2_PLANE_NO_SCALING BIT(16) 773 774 enum vop2_csc_format { 775 CSC_BT601L, 776 CSC_BT709L, 777 CSC_BT601F, 778 CSC_BT2020, 779 }; 780 781 enum vop2_pol { 782 HSYNC_POSITIVE = 0, 783 VSYNC_POSITIVE = 1, 784 DEN_NEGATIVE = 2, 785 DCLK_INVERT = 3 786 }; 787 788 enum vop2_bcsh_out_mode { 789 BCSH_OUT_MODE_BLACK, 790 BCSH_OUT_MODE_BLUE, 791 BCSH_OUT_MODE_COLOR_BAR, 792 BCSH_OUT_MODE_NORMAL_VIDEO, 793 }; 794 795 #define _VOP_REG(off, _mask, _shift, _write_mask) \ 796 { \ 797 .offset = off, \ 798 .mask = _mask, \ 799 .shift = _shift, \ 800 .write_mask = _write_mask, \ 801 } 802 803 #define VOP_REG(off, _mask, _shift) \ 804 _VOP_REG(off, _mask, _shift, false) 805 enum dither_down_mode { 806 RGB888_TO_RGB565 = 0x0, 807 RGB888_TO_RGB666 = 0x1 808 }; 809 810 enum vop2_video_ports_id { 811 VOP2_VP0, 812 VOP2_VP1, 813 VOP2_VP2, 814 VOP2_VP3, 815 VOP2_VP_MAX, 816 }; 817 818 enum vop2_layer_type { 819 CLUSTER_LAYER = 0, 820 ESMART_LAYER = 1, 821 SMART_LAYER = 2, 822 }; 823 824 /* This define must same with kernel win phy id */ 825 enum vop2_layer_phy_id { 826 ROCKCHIP_VOP2_CLUSTER0 = 0, 827 ROCKCHIP_VOP2_CLUSTER1, 828 ROCKCHIP_VOP2_ESMART0, 829 ROCKCHIP_VOP2_ESMART1, 830 ROCKCHIP_VOP2_SMART0, 831 ROCKCHIP_VOP2_SMART1, 832 ROCKCHIP_VOP2_CLUSTER2, 833 ROCKCHIP_VOP2_CLUSTER3, 834 ROCKCHIP_VOP2_ESMART2, 835 ROCKCHIP_VOP2_ESMART3, 836 ROCKCHIP_VOP2_LAYER_MAX, 837 }; 838 839 enum vop2_scale_up_mode { 840 VOP2_SCALE_UP_NRST_NBOR, 841 VOP2_SCALE_UP_BIL, 842 VOP2_SCALE_UP_BIC, 843 }; 844 845 enum vop2_scale_down_mode { 846 VOP2_SCALE_DOWN_NRST_NBOR, 847 VOP2_SCALE_DOWN_BIL, 848 VOP2_SCALE_DOWN_AVG, 849 }; 850 851 enum scale_mode { 852 SCALE_NONE = 0x0, 853 SCALE_UP = 0x1, 854 SCALE_DOWN = 0x2 855 }; 856 857 enum vop_dsc_interface_mode { 858 VOP_DSC_IF_DISABLE = 0, 859 VOP_DSC_IF_HDMI = 1, 860 VOP_DSC_IF_MIPI_DS_MODE = 2, 861 VOP_DSC_IF_MIPI_VIDEO_MODE = 3, 862 }; 863 864 struct vop2_layer { 865 u8 id; 866 /** 867 * @win_phys_id: window id of the layer selected. 868 * Every layer must make sure to select different 869 * windows of others. 870 */ 871 u8 win_phys_id; 872 }; 873 874 struct vop2_power_domain_data { 875 u8 id; 876 u8 parent_id; 877 /* 878 * @module_id_mask: module id of which module this power domain is belongs to. 879 * PD_CLUSTER0,1,2,3 only belongs to CLUSTER0/1/2/3, PD_Esmart0 shared by Esmart1/2/3 880 */ 881 u32 module_id_mask; 882 }; 883 884 struct vop2_win_data { 885 char *name; 886 u8 phys_id; 887 enum vop2_layer_type type; 888 u8 win_sel_port_offset; 889 u8 layer_sel_win_id; 890 u8 axi_id; 891 u8 axi_uv_id; 892 u8 axi_yrgb_id; 893 u8 splice_win_id; 894 u8 pd_id; 895 u32 reg_offset; 896 u32 max_upscale_factor; 897 u32 max_downscale_factor; 898 bool splice_mode_right; 899 }; 900 901 struct vop2_vp_data { 902 u32 feature; 903 u8 pre_scan_max_dly; 904 u8 splice_vp_id; 905 struct vop_rect max_output; 906 u32 max_dclk; 907 }; 908 909 struct vop2_plane_table { 910 enum vop2_layer_phy_id plane_id; 911 enum vop2_layer_type plane_type; 912 }; 913 914 struct vop2_vp_plane_mask { 915 u8 primary_plane_id; /* use this win to show logo */ 916 u8 attached_layers_nr; /* number layers attach to this vp */ 917 u8 attached_layers[VOP2_LAYER_MAX]; /* the layers attached to this vp */ 918 u32 plane_mask; 919 int cursor_plane_id; 920 }; 921 922 struct vop2_dsc_data { 923 u8 id; 924 u8 pd_id; 925 u8 max_slice_num; 926 u8 max_linebuf_depth; /* used to generate the bitstream */ 927 u8 min_bits_per_pixel; /* bit num after encoder compress */ 928 const char *dsc_txp_clk_src_name; 929 const char *dsc_txp_clk_name; 930 const char *dsc_pxl_clk_name; 931 const char *dsc_cds_clk_name; 932 }; 933 934 struct dsc_error_info { 935 u32 dsc_error_val; 936 char dsc_error_info[50]; 937 }; 938 939 struct vop2_data { 940 u32 version; 941 struct vop2_vp_data *vp_data; 942 struct vop2_win_data *win_data; 943 struct vop2_vp_plane_mask *plane_mask; 944 struct vop2_plane_table *plane_table; 945 struct vop2_power_domain_data *pd; 946 struct vop2_dsc_data *dsc; 947 struct dsc_error_info *dsc_error_ecw; 948 struct dsc_error_info *dsc_error_buffer_flow; 949 u8 nr_vps; 950 u8 nr_layers; 951 u8 nr_mixers; 952 u8 nr_gammas; 953 u8 nr_pd; 954 u8 nr_dscs; 955 u8 nr_dsc_ecw; 956 u8 nr_dsc_buffer_flow; 957 u32 reg_len; 958 }; 959 960 struct vop2 { 961 u32 *regsbak; 962 void *regs; 963 void *grf; 964 void *vop_grf; 965 void *vo1_grf; 966 void *sys_pmu; 967 u32 reg_len; 968 u32 version; 969 bool global_init; 970 const struct vop2_data *data; 971 struct vop2_vp_plane_mask vp_plane_mask[VOP2_VP_MAX]; 972 }; 973 974 static struct vop2 *rockchip_vop2; 975 /* 976 * bli_sd_factor = (src - 1) / (dst - 1) << 12; 977 * avg_sd_factor: 978 * bli_su_factor: 979 * bic_su_factor: 980 * = (src - 1) / (dst - 1) << 16; 981 * 982 * gt2 enable: dst get one line from two line of the src 983 * gt4 enable: dst get one line from four line of the src. 984 * 985 */ 986 #define VOP2_BILI_SCL_DN(src, dst) (((src - 1) << 12) / (dst - 1)) 987 #define VOP2_COMMON_SCL(src, dst) (((src - 1) << 16) / (dst - 1)) 988 989 #define VOP2_BILI_SCL_FAC_CHECK(src, dst, fac) \ 990 (fac * (dst - 1) >> 12 < (src - 1)) 991 #define VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac) \ 992 (fac * (dst - 1) >> 16 < (src - 1)) 993 994 static uint16_t vop2_scale_factor(enum scale_mode mode, 995 int32_t filter_mode, 996 uint32_t src, uint32_t dst) 997 { 998 uint32_t fac = 0; 999 int i = 0; 1000 1001 if (mode == SCALE_NONE) 1002 return 0; 1003 1004 /* 1005 * A workaround to avoid zero div. 1006 */ 1007 if ((dst == 1) || (src == 1)) { 1008 dst = dst + 1; 1009 src = src + 1; 1010 } 1011 1012 if ((mode == SCALE_DOWN) && (filter_mode == VOP2_SCALE_DOWN_BIL)) { 1013 fac = VOP2_BILI_SCL_DN(src, dst); 1014 for (i = 0; i < 100; i++) { 1015 if (VOP2_BILI_SCL_FAC_CHECK(src, dst, fac)) 1016 break; 1017 fac -= 1; 1018 printf("down fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac); 1019 } 1020 } else { 1021 fac = VOP2_COMMON_SCL(src, dst); 1022 for (i = 0; i < 100; i++) { 1023 if (VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac)) 1024 break; 1025 fac -= 1; 1026 printf("up fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac); 1027 } 1028 } 1029 1030 return fac; 1031 } 1032 1033 static inline enum scale_mode scl_get_scl_mode(int src, int dst) 1034 { 1035 if (src < dst) 1036 return SCALE_UP; 1037 else if (src > dst) 1038 return SCALE_DOWN; 1039 1040 return SCALE_NONE; 1041 } 1042 1043 static u8 rk3588_vop2_vp_primary_plane_order[VOP2_VP_MAX] = { 1044 ROCKCHIP_VOP2_ESMART0, 1045 ROCKCHIP_VOP2_ESMART1, 1046 ROCKCHIP_VOP2_ESMART2, 1047 ROCKCHIP_VOP2_ESMART3, 1048 }; 1049 1050 static u8 rk3568_vop2_vp_primary_plane_order[VOP2_VP_MAX] = { 1051 ROCKCHIP_VOP2_SMART0, 1052 ROCKCHIP_VOP2_SMART1, 1053 ROCKCHIP_VOP2_ESMART1, 1054 }; 1055 1056 static inline int interpolate(int x1, int y1, int x2, int y2, int x) 1057 { 1058 return y1 + (y2 - y1) * (x - x1) / (x2 - x1); 1059 } 1060 1061 static int vop2_get_primary_plane(struct vop2 *vop2, u32 plane_mask) 1062 { 1063 int i = 0; 1064 u8 *vop2_vp_primary_plane_order; 1065 u8 default_primary_plane; 1066 1067 if (vop2->version == VOP_VERSION_RK3588) { 1068 vop2_vp_primary_plane_order = rk3588_vop2_vp_primary_plane_order; 1069 default_primary_plane = ROCKCHIP_VOP2_ESMART0; 1070 } else { 1071 vop2_vp_primary_plane_order = rk3568_vop2_vp_primary_plane_order; 1072 default_primary_plane = ROCKCHIP_VOP2_SMART0; 1073 } 1074 1075 for (i = 0; i < vop2->data->nr_vps; i++) { 1076 if (plane_mask & BIT(vop2_vp_primary_plane_order[i])) 1077 return vop2_vp_primary_plane_order[i]; 1078 } 1079 1080 return default_primary_plane; 1081 } 1082 1083 static inline u16 scl_cal_scale(int src, int dst, int shift) 1084 { 1085 return ((src * 2 - 3) << (shift - 1)) / (dst - 1); 1086 } 1087 1088 static inline u16 scl_cal_scale2(int src, int dst) 1089 { 1090 return ((src - 1) << 12) / (dst - 1); 1091 } 1092 1093 static inline void vop2_writel(struct vop2 *vop2, u32 offset, u32 v) 1094 { 1095 writel(v, vop2->regs + offset); 1096 vop2->regsbak[offset >> 2] = v; 1097 } 1098 1099 static inline u32 vop2_readl(struct vop2 *vop2, u32 offset) 1100 { 1101 return readl(vop2->regs + offset); 1102 } 1103 1104 static inline void vop2_mask_write(struct vop2 *vop2, u32 offset, 1105 u32 mask, u32 shift, u32 v, 1106 bool write_mask) 1107 { 1108 if (!mask) 1109 return; 1110 1111 if (write_mask) { 1112 v = ((v & mask) << shift) | (mask << (shift + 16)); 1113 } else { 1114 u32 cached_val = vop2->regsbak[offset >> 2]; 1115 1116 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 1117 vop2->regsbak[offset >> 2] = v; 1118 } 1119 1120 writel(v, vop2->regs + offset); 1121 } 1122 1123 static inline void vop2_grf_writel(struct vop2 *vop, void *grf_base, u32 offset, 1124 u32 mask, u32 shift, u32 v) 1125 { 1126 u32 val = 0; 1127 1128 val = (v << shift) | (mask << (shift + 16)); 1129 writel(val, grf_base + offset); 1130 } 1131 1132 static inline u32 vop2_grf_readl(struct vop2 *vop, void *grf_base, u32 offset, 1133 u32 mask, u32 shift) 1134 { 1135 return (readl(grf_base + offset) >> shift) & mask; 1136 } 1137 1138 static char* get_output_if_name(u32 output_if, char *name) 1139 { 1140 if (output_if & VOP_OUTPUT_IF_RGB) 1141 strcat(name, " RGB"); 1142 if (output_if & VOP_OUTPUT_IF_BT1120) 1143 strcat(name, " BT1120"); 1144 if (output_if & VOP_OUTPUT_IF_BT656) 1145 strcat(name, " BT656"); 1146 if (output_if & VOP_OUTPUT_IF_LVDS0) 1147 strcat(name, " LVDS0"); 1148 if (output_if & VOP_OUTPUT_IF_LVDS1) 1149 strcat(name, " LVDS1"); 1150 if (output_if & VOP_OUTPUT_IF_MIPI0) 1151 strcat(name, " MIPI0"); 1152 if (output_if & VOP_OUTPUT_IF_MIPI1) 1153 strcat(name, " MIPI1"); 1154 if (output_if & VOP_OUTPUT_IF_eDP0) 1155 strcat(name, " eDP0"); 1156 if (output_if & VOP_OUTPUT_IF_eDP1) 1157 strcat(name, " eDP1"); 1158 if (output_if & VOP_OUTPUT_IF_DP0) 1159 strcat(name, " DP0"); 1160 if (output_if & VOP_OUTPUT_IF_DP1) 1161 strcat(name, " DP1"); 1162 if (output_if & VOP_OUTPUT_IF_HDMI0) 1163 strcat(name, " HDMI0"); 1164 if (output_if & VOP_OUTPUT_IF_HDMI1) 1165 strcat(name, " HDMI1"); 1166 1167 return name; 1168 } 1169 1170 static char *get_plane_name(int plane_id, char *name) 1171 { 1172 switch (plane_id) { 1173 case ROCKCHIP_VOP2_CLUSTER0: 1174 strcat(name, "Cluster0"); 1175 break; 1176 case ROCKCHIP_VOP2_CLUSTER1: 1177 strcat(name, "Cluster1"); 1178 break; 1179 case ROCKCHIP_VOP2_ESMART0: 1180 strcat(name, "Esmart0"); 1181 break; 1182 case ROCKCHIP_VOP2_ESMART1: 1183 strcat(name, "Esmart1"); 1184 break; 1185 case ROCKCHIP_VOP2_SMART0: 1186 strcat(name, "Smart0"); 1187 break; 1188 case ROCKCHIP_VOP2_SMART1: 1189 strcat(name, "Smart1"); 1190 break; 1191 case ROCKCHIP_VOP2_CLUSTER2: 1192 strcat(name, "Cluster2"); 1193 break; 1194 case ROCKCHIP_VOP2_CLUSTER3: 1195 strcat(name, "Cluster3"); 1196 break; 1197 case ROCKCHIP_VOP2_ESMART2: 1198 strcat(name, "Esmart2"); 1199 break; 1200 case ROCKCHIP_VOP2_ESMART3: 1201 strcat(name, "Esmart3"); 1202 break; 1203 } 1204 1205 return name; 1206 } 1207 1208 static bool is_yuv_output(u32 bus_format) 1209 { 1210 switch (bus_format) { 1211 case MEDIA_BUS_FMT_YUV8_1X24: 1212 case MEDIA_BUS_FMT_YUV10_1X30: 1213 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1214 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1215 case MEDIA_BUS_FMT_YUYV8_2X8: 1216 case MEDIA_BUS_FMT_YVYU8_2X8: 1217 case MEDIA_BUS_FMT_UYVY8_2X8: 1218 case MEDIA_BUS_FMT_VYUY8_2X8: 1219 case MEDIA_BUS_FMT_YUYV8_1X16: 1220 case MEDIA_BUS_FMT_YVYU8_1X16: 1221 case MEDIA_BUS_FMT_UYVY8_1X16: 1222 case MEDIA_BUS_FMT_VYUY8_1X16: 1223 return true; 1224 default: 1225 return false; 1226 } 1227 } 1228 1229 static int vop2_convert_csc_mode(int csc_mode) 1230 { 1231 switch (csc_mode) { 1232 case V4L2_COLORSPACE_SMPTE170M: 1233 case V4L2_COLORSPACE_470_SYSTEM_M: 1234 case V4L2_COLORSPACE_470_SYSTEM_BG: 1235 return CSC_BT601L; 1236 case V4L2_COLORSPACE_REC709: 1237 case V4L2_COLORSPACE_SMPTE240M: 1238 case V4L2_COLORSPACE_DEFAULT: 1239 return CSC_BT709L; 1240 case V4L2_COLORSPACE_JPEG: 1241 return CSC_BT601F; 1242 case V4L2_COLORSPACE_BT2020: 1243 return CSC_BT2020; 1244 default: 1245 return CSC_BT709L; 1246 } 1247 } 1248 1249 static bool is_uv_swap(u32 bus_format, u32 output_mode) 1250 { 1251 /* 1252 * FIXME: 1253 * 1254 * There is no media type for YUV444 output, 1255 * so when out_mode is AAAA or P888, assume output is YUV444 on 1256 * yuv format. 1257 * 1258 * From H/W testing, YUV444 mode need a rb swap. 1259 */ 1260 if (bus_format == MEDIA_BUS_FMT_YVYU8_1X16 || 1261 bus_format == MEDIA_BUS_FMT_VYUY8_1X16 || 1262 bus_format == MEDIA_BUS_FMT_YVYU8_2X8 || 1263 bus_format == MEDIA_BUS_FMT_VYUY8_2X8 || 1264 ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 1265 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 1266 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 1267 output_mode == ROCKCHIP_OUT_MODE_P888))) 1268 return true; 1269 else 1270 return false; 1271 } 1272 1273 static inline bool is_hot_plug_devices(int output_type) 1274 { 1275 switch (output_type) { 1276 case DRM_MODE_CONNECTOR_HDMIA: 1277 case DRM_MODE_CONNECTOR_HDMIB: 1278 case DRM_MODE_CONNECTOR_TV: 1279 case DRM_MODE_CONNECTOR_DisplayPort: 1280 case DRM_MODE_CONNECTOR_VGA: 1281 case DRM_MODE_CONNECTOR_Unknown: 1282 return true; 1283 default: 1284 return false; 1285 } 1286 } 1287 1288 static struct vop2_win_data *vop2_find_win_by_phys_id(struct vop2 *vop2, int phys_id) 1289 { 1290 int i = 0; 1291 1292 for (i = 0; i < vop2->data->nr_layers; i++) { 1293 if (vop2->data->win_data[i].phys_id == phys_id) 1294 return &vop2->data->win_data[i]; 1295 } 1296 1297 return NULL; 1298 } 1299 1300 static struct vop2_power_domain_data *vop2_find_pd_data_by_id(struct vop2 *vop2, int pd_id) 1301 { 1302 int i = 0; 1303 1304 for (i = 0; i < vop2->data->nr_pd; i++) { 1305 if (vop2->data->pd[i].id == pd_id) 1306 return &vop2->data->pd[i]; 1307 } 1308 1309 return NULL; 1310 } 1311 1312 static void rk3568_vop2_load_lut(struct vop2 *vop2, int crtc_id, 1313 u32 *lut_regs, u32 *lut_val, int lut_len) 1314 { 1315 u32 vp_offset = crtc_id * 0x100; 1316 int i; 1317 1318 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, 1319 GAMMA_PORT_SEL_MASK, GAMMA_PORT_SEL_SHIFT, 1320 crtc_id, false); 1321 1322 for (i = 0; i < lut_len; i++) 1323 writel(lut_val[i], lut_regs + i); 1324 1325 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 1326 EN_MASK, DSP_LUT_EN_SHIFT, 1, false); 1327 } 1328 1329 static void rk3588_vop2_load_lut(struct vop2 *vop2, int crtc_id, 1330 u32 *lut_regs, u32 *lut_val, int lut_len) 1331 { 1332 u32 vp_offset = crtc_id * 0x100; 1333 int i; 1334 1335 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, 1336 GAMMA_AHB_WRITE_SEL_MASK, GAMMA_AHB_WRITE_SEL_SHIFT, 1337 crtc_id, false); 1338 1339 for (i = 0; i < lut_len; i++) 1340 writel(lut_val[i], lut_regs + i); 1341 1342 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 1343 EN_MASK, DSP_LUT_EN_SHIFT, 1, false); 1344 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 1345 EN_MASK, GAMMA_UPDATE_EN_SHIFT, 1, false); 1346 } 1347 1348 static int rockchip_vop2_gamma_lut_init(struct vop2 *vop2, 1349 struct display_state *state) 1350 { 1351 struct connector_state *conn_state = &state->conn_state; 1352 struct crtc_state *cstate = &state->crtc_state; 1353 struct resource gamma_res; 1354 fdt_size_t lut_size; 1355 int i, lut_len, ret = 0; 1356 u32 *lut_regs; 1357 u32 *lut_val; 1358 u32 r, g, b; 1359 struct base2_disp_info *disp_info = conn_state->disp_info; 1360 static int gamma_lut_en_num = 1; 1361 1362 if (gamma_lut_en_num > vop2->data->nr_gammas) { 1363 printf("warn: only %d vp support gamma\n", vop2->data->nr_gammas); 1364 return 0; 1365 } 1366 1367 if (!disp_info) 1368 return 0; 1369 1370 if (!disp_info->gamma_lut_data.size) 1371 return 0; 1372 1373 ret = ofnode_read_resource_byname(cstate->node, "gamma_lut", &gamma_res); 1374 if (ret) 1375 printf("failed to get gamma lut res\n"); 1376 lut_regs = (u32 *)gamma_res.start; 1377 lut_size = gamma_res.end - gamma_res.start + 1; 1378 if (lut_regs == (u32 *)FDT_ADDR_T_NONE) { 1379 printf("failed to get gamma lut register\n"); 1380 return 0; 1381 } 1382 lut_len = lut_size / 4; 1383 if (lut_len != 256 && lut_len != 1024) { 1384 printf("Warning: unsupport gamma lut table[%d]\n", lut_len); 1385 return 0; 1386 } 1387 lut_val = (u32 *)calloc(1, lut_size); 1388 for (i = 0; i < lut_len; i++) { 1389 r = disp_info->gamma_lut_data.lred[i] * (lut_len - 1) / 0xffff; 1390 g = disp_info->gamma_lut_data.lgreen[i] * (lut_len - 1) / 0xffff; 1391 b = disp_info->gamma_lut_data.lblue[i] * (lut_len - 1) / 0xffff; 1392 1393 lut_val[i] = b * lut_len * lut_len + g * lut_len + r; 1394 } 1395 1396 if (vop2->version == VOP_VERSION_RK3568) { 1397 rk3568_vop2_load_lut(vop2, cstate->crtc_id, lut_regs, lut_val, lut_len); 1398 gamma_lut_en_num++; 1399 } else if (vop2->version == VOP_VERSION_RK3588) { 1400 rk3588_vop2_load_lut(vop2, cstate->crtc_id, lut_regs, lut_val, lut_len); 1401 if (cstate->splice_mode) { 1402 rk3588_vop2_load_lut(vop2, cstate->splice_crtc_id, lut_regs, lut_val, lut_len); 1403 gamma_lut_en_num++; 1404 } 1405 gamma_lut_en_num++; 1406 } 1407 1408 return 0; 1409 } 1410 1411 static int rockchip_vop2_cubic_lut_init(struct vop2 *vop2, 1412 struct display_state *state) 1413 { 1414 struct connector_state *conn_state = &state->conn_state; 1415 struct crtc_state *cstate = &state->crtc_state; 1416 int i, cubic_lut_len; 1417 u32 vp_offset = cstate->crtc_id * 0x100; 1418 struct base2_disp_info *disp_info = conn_state->disp_info; 1419 struct base2_cubic_lut_data *lut = &conn_state->disp_info->cubic_lut_data; 1420 u32 *cubic_lut_addr; 1421 1422 if (!disp_info || CONFIG_ROCKCHIP_CUBIC_LUT_SIZE == 0) 1423 return 0; 1424 1425 if (!disp_info->cubic_lut_data.size) 1426 return 0; 1427 1428 cubic_lut_addr = (u32 *)get_cubic_lut_buffer(cstate->crtc_id); 1429 cubic_lut_len = disp_info->cubic_lut_data.size; 1430 1431 for (i = 0; i < cubic_lut_len / 2; i++) { 1432 *cubic_lut_addr++ = ((lut->lred[2 * i]) & 0xfff) + 1433 ((lut->lgreen[2 * i] & 0xfff) << 12) + 1434 ((lut->lblue[2 * i] & 0xff) << 24); 1435 *cubic_lut_addr++ = ((lut->lblue[2 * i] & 0xf00) >> 8) + 1436 ((lut->lred[2 * i + 1] & 0xfff) << 4) + 1437 ((lut->lgreen[2 * i + 1] & 0xfff) << 16) + 1438 ((lut->lblue[2 * i + 1] & 0xf) << 28); 1439 *cubic_lut_addr++ = (lut->lblue[2 * i + 1] & 0xff0) >> 4; 1440 *cubic_lut_addr++ = 0; 1441 } 1442 1443 if (cubic_lut_len % 2) { 1444 *cubic_lut_addr++ = (lut->lred[2 * i] & 0xfff) + 1445 ((lut->lgreen[2 * i] & 0xfff) << 12) + 1446 ((lut->lblue[2 * i] & 0xff) << 24); 1447 *cubic_lut_addr++ = (lut->lblue[2 * i] & 0xf00) >> 8; 1448 *cubic_lut_addr++ = 0; 1449 *cubic_lut_addr = 0; 1450 } 1451 1452 vop2_writel(vop2, RK3568_VP0_3D_LUT_MST + vp_offset, 1453 get_cubic_lut_buffer(cstate->crtc_id)); 1454 vop2_mask_write(vop2, RK3568_SYS_AXI_LUT_CTRL, 1455 EN_MASK, LUT_DMA_EN_SHIFT, 1, false); 1456 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, 1457 EN_MASK, VP0_3D_LUT_EN_SHIFT, 1, false); 1458 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, 1459 EN_MASK, VP0_3D_LUT_UPDATE_SHIFT, 1, false); 1460 1461 return 0; 1462 } 1463 1464 static void vop2_bcsh_reg_update(struct display_state *state, struct vop2 *vop2, 1465 struct bcsh_state *bcsh_state, int crtc_id) 1466 { 1467 struct crtc_state *cstate = &state->crtc_state; 1468 u32 vp_offset = crtc_id * 0x100; 1469 1470 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_MASK, 1471 BCSH_CTRL_R2Y_SHIFT, cstate->post_r2y_en, false); 1472 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_MASK, 1473 BCSH_CTRL_Y2R_SHIFT, cstate->post_y2r_en, false); 1474 1475 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_CSC_MODE_MASK, 1476 BCSH_CTRL_R2Y_CSC_MODE_SHIFT, cstate->post_csc_mode, false); 1477 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_CSC_MODE_MASK, 1478 BCSH_CTRL_Y2R_CSC_MODE_SHIFT, cstate->post_csc_mode, false); 1479 1480 if (!cstate->bcsh_en) { 1481 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, 1482 BCSH_EN_MASK, BCSH_EN_SHIFT, 0, false); 1483 return; 1484 } 1485 1486 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1487 BCSH_BRIGHTNESS_MASK, BCSH_BRIGHTNESS_SHIFT, 1488 bcsh_state->brightness, false); 1489 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1490 BCSH_CONTRAST_MASK, BCSH_CONTRAST_SHIFT, bcsh_state->contrast, false); 1491 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1492 BCSH_SATURATION_MASK, BCSH_SATURATION_SHIFT, 1493 bcsh_state->saturation * bcsh_state->contrast / 0x100, false); 1494 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, 1495 BCSH_SIN_HUE_MASK, BCSH_SIN_HUE_SHIFT, bcsh_state->sin_hue, false); 1496 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, 1497 BCSH_COS_HUE_MASK, BCSH_COS_HUE_SHIFT, bcsh_state->cos_hue, false); 1498 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1499 BCSH_OUT_MODE_MASK, BCSH_OUT_MODE_SHIFT, 1500 BCSH_OUT_MODE_NORMAL_VIDEO, false); 1501 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, 1502 BCSH_EN_MASK, BCSH_EN_SHIFT, 1, false); 1503 } 1504 1505 static void vop2_tv_config_update(struct display_state *state, struct vop2 *vop2) 1506 { 1507 struct connector_state *conn_state = &state->conn_state; 1508 struct base_bcsh_info *bcsh_info; 1509 struct crtc_state *cstate = &state->crtc_state; 1510 struct bcsh_state bcsh_state; 1511 int brightness, contrast, saturation, hue, sin_hue, cos_hue; 1512 1513 if (!conn_state->disp_info) 1514 return; 1515 bcsh_info = &conn_state->disp_info->bcsh_info; 1516 if (!bcsh_info) 1517 return; 1518 1519 if (bcsh_info->brightness != 50 || 1520 bcsh_info->contrast != 50 || 1521 bcsh_info->saturation != 50 || bcsh_info->hue != 50) 1522 cstate->bcsh_en = true; 1523 1524 if (cstate->bcsh_en) { 1525 if (!cstate->yuv_overlay) 1526 cstate->post_r2y_en = 1; 1527 if (!is_yuv_output(conn_state->bus_format)) 1528 cstate->post_y2r_en = 1; 1529 } else { 1530 if (!cstate->yuv_overlay && is_yuv_output(conn_state->bus_format)) 1531 cstate->post_r2y_en = 1; 1532 if (cstate->yuv_overlay && !is_yuv_output(conn_state->bus_format)) 1533 cstate->post_y2r_en = 1; 1534 } 1535 1536 cstate->post_csc_mode = vop2_convert_csc_mode(conn_state->color_space); 1537 1538 if (cstate->feature & VOP_FEATURE_OUTPUT_10BIT) 1539 brightness = interpolate(0, -128, 100, 127, 1540 bcsh_info->brightness); 1541 else 1542 brightness = interpolate(0, -32, 100, 31, 1543 bcsh_info->brightness); 1544 contrast = interpolate(0, 0, 100, 511, bcsh_info->contrast); 1545 saturation = interpolate(0, 0, 100, 511, bcsh_info->saturation); 1546 hue = interpolate(0, -30, 100, 30, bcsh_info->hue); 1547 1548 1549 /* 1550 * a:[-30~0): 1551 * sin_hue = 0x100 - sin(a)*256; 1552 * cos_hue = cos(a)*256; 1553 * a:[0~30] 1554 * sin_hue = sin(a)*256; 1555 * cos_hue = cos(a)*256; 1556 */ 1557 sin_hue = fixp_sin32(hue) >> 23; 1558 cos_hue = fixp_cos32(hue) >> 23; 1559 1560 bcsh_state.brightness = brightness; 1561 bcsh_state.contrast = contrast; 1562 bcsh_state.saturation = saturation; 1563 bcsh_state.sin_hue = sin_hue; 1564 bcsh_state.cos_hue = cos_hue; 1565 1566 vop2_bcsh_reg_update(state, vop2, &bcsh_state, cstate->crtc_id); 1567 if (cstate->splice_mode) 1568 vop2_bcsh_reg_update(state, vop2, &bcsh_state, cstate->splice_crtc_id); 1569 } 1570 1571 static void vop2_setup_dly_for_vp(struct display_state *state, struct vop2 *vop2, int crtc_id) 1572 { 1573 struct connector_state *conn_state = &state->conn_state; 1574 struct drm_display_mode *mode = &conn_state->mode; 1575 struct crtc_state *cstate = &state->crtc_state; 1576 u32 bg_ovl_dly, bg_dly, pre_scan_dly; 1577 u16 hdisplay = mode->crtc_hdisplay; 1578 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 1579 1580 bg_ovl_dly = cstate->crtc->vps[crtc_id].bg_ovl_dly; 1581 bg_dly = vop2->data->vp_data[crtc_id].pre_scan_max_dly; 1582 bg_dly -= bg_ovl_dly; 1583 1584 if (cstate->splice_mode) 1585 pre_scan_dly = bg_dly + (hdisplay >> 2) - 1; 1586 else 1587 pre_scan_dly = bg_dly + (hdisplay >> 1) - 1; 1588 1589 if (vop2->version == VOP_VERSION_RK3588 && hsync_len < 8) 1590 hsync_len = 8; 1591 pre_scan_dly = (pre_scan_dly << 16) | hsync_len; 1592 vop2_mask_write(vop2, RK3568_VP0_BG_MIX_CTRL + crtc_id * 4, 1593 BG_MIX_CTRL_MASK, BG_MIX_CTRL_SHIFT, bg_dly, false); 1594 vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly); 1595 } 1596 1597 static void vop2_post_config(struct display_state *state, struct vop2 *vop2) 1598 { 1599 struct connector_state *conn_state = &state->conn_state; 1600 struct drm_display_mode *mode = &conn_state->mode; 1601 struct crtc_state *cstate = &state->crtc_state; 1602 u32 vp_offset = (cstate->crtc_id * 0x100); 1603 u16 vtotal = mode->crtc_vtotal; 1604 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 1605 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 1606 u16 hdisplay = mode->crtc_hdisplay; 1607 u16 vdisplay = mode->crtc_vdisplay; 1608 u16 hsize = 1609 hdisplay * (conn_state->overscan.left_margin + 1610 conn_state->overscan.right_margin) / 200; 1611 u16 vsize = 1612 vdisplay * (conn_state->overscan.top_margin + 1613 conn_state->overscan.bottom_margin) / 200; 1614 u16 hact_end, vact_end; 1615 u32 val; 1616 1617 hsize = round_down(hsize, 2); 1618 vsize = round_down(vsize, 2); 1619 1620 hact_st += hdisplay * (100 - conn_state->overscan.left_margin) / 200; 1621 hact_end = hact_st + hsize; 1622 val = hact_st << 16; 1623 val |= hact_end; 1624 1625 vop2_writel(vop2, RK3568_VP0_POST_DSP_HACT_INFO + vp_offset, val); 1626 vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200; 1627 vact_end = vact_st + vsize; 1628 val = vact_st << 16; 1629 val |= vact_end; 1630 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO + vp_offset, val); 1631 val = scl_cal_scale2(vdisplay, vsize) << 16; 1632 val |= scl_cal_scale2(hdisplay, hsize); 1633 vop2_writel(vop2, RK3568_VP0_POST_SCL_FACTOR_YRGB + vp_offset, val); 1634 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0) 1635 #define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1) 1636 vop2_writel(vop2, RK3568_VP0_POST_SCL_CTRL + vp_offset, 1637 POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) | 1638 POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize)); 1639 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1640 u16 vact_st_f1 = vtotal + vact_st + 1; 1641 u16 vact_end_f1 = vact_st_f1 + vsize; 1642 1643 val = vact_st_f1 << 16 | vact_end_f1; 1644 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO_F1 + vp_offset, val); 1645 } 1646 1647 vop2_setup_dly_for_vp(state, vop2, cstate->crtc_id); 1648 if (cstate->splice_mode) 1649 vop2_setup_dly_for_vp(state, vop2, cstate->splice_crtc_id); 1650 } 1651 1652 /* 1653 * Read VOP internal power domain on/off status. 1654 * We should query BISR_STS register in PMU for 1655 * power up/down status when memory repair is enabled. 1656 * Return value: 1 for power on, 0 for power off; 1657 */ 1658 static int vop2_wait_power_domain_on(struct vop2 *vop2, struct vop2_power_domain_data *pd_data) 1659 { 1660 int val = 0; 1661 int shift = 0; 1662 int shift_factor = 0; 1663 bool is_bisr_en = false; 1664 1665 /* 1666 * The order of pd status bits in BISR_STS register 1667 * is different from that in VOP SYS_STS register. 1668 */ 1669 if (pd_data->id == VOP2_PD_DSC_8K || 1670 pd_data->id == VOP2_PD_DSC_4K || 1671 pd_data->id == VOP2_PD_ESMART) 1672 shift_factor = 1; 1673 1674 shift = RK3588_PD_CLUSTER0_REPAIR_EN_SHIFT + generic_ffs(pd_data->id) - 1 - shift_factor; 1675 is_bisr_en = vop2_grf_readl(vop2, vop2->sys_pmu, RK3588_PMU_BISR_CON3, EN_MASK, shift); 1676 if (is_bisr_en) { 1677 shift = RK3588_PD_CLUSTER0_PWR_STAT_SHIFI + generic_ffs(pd_data->id) - 1 - shift_factor; 1678 1679 return readl_poll_timeout(vop2->sys_pmu + RK3588_PMU_BISR_STATUS5, val, 1680 ((val >> shift) & 0x1), 50 * 1000); 1681 } else { 1682 shift = RK3588_CLUSTER0_PD_STATUS_SHIFT + generic_ffs(pd_data->id) - 1; 1683 1684 return readl_poll_timeout(vop2->regs + RK3568_SYS_STATUS0, val, 1685 !((val >> shift) & 0x1), 50 * 1000); 1686 } 1687 } 1688 1689 static int vop2_power_domain_on(struct vop2 *vop2, int pd_id) 1690 { 1691 struct vop2_power_domain_data *pd_data; 1692 int ret = 0; 1693 1694 if (!pd_id) 1695 return 0; 1696 1697 pd_data = vop2_find_pd_data_by_id(vop2, pd_id); 1698 if (!pd_data) { 1699 printf("can't find pd_data by id\n"); 1700 return -EINVAL; 1701 } 1702 1703 if (pd_data->parent_id) { 1704 ret = vop2_power_domain_on(vop2, pd_data->parent_id); 1705 if (ret) { 1706 printf("can't open parent power domain\n"); 1707 return -EINVAL; 1708 } 1709 } 1710 1711 vop2_mask_write(vop2, RK3568_SYS_PD_CTRL, EN_MASK, 1712 RK3588_CLUSTER0_PD_EN_SHIFT + generic_ffs(pd_id) - 1, 0, false); 1713 ret = vop2_wait_power_domain_on(vop2, pd_data); 1714 if (ret) { 1715 printf("wait vop2 power domain timeout\n"); 1716 return ret; 1717 } 1718 1719 return 0; 1720 } 1721 1722 static void rk3588_vop2_regsbak(struct vop2 *vop2) 1723 { 1724 u32 *base = vop2->regs; 1725 int i = 0; 1726 1727 /* 1728 * No need to backup HDR/DSC/GAMMA_LUT/BPP_LUT/MMU 1729 */ 1730 for (i = 0; i < (vop2->reg_len >> 2); i++) 1731 vop2->regsbak[i] = base[i]; 1732 } 1733 1734 static void vop2_global_initial(struct vop2 *vop2, struct display_state *state) 1735 { 1736 struct crtc_state *cstate = &state->crtc_state; 1737 int i, j, port_mux = 0, total_used_layer = 0; 1738 u8 shift = 0; 1739 int layer_phy_id = 0; 1740 u32 layer_nr = 0; 1741 struct vop2_win_data *win_data; 1742 struct vop2_vp_plane_mask *plane_mask; 1743 1744 if (vop2->global_init) 1745 return; 1746 1747 /* OTP must enable at the first time, otherwise mirror layer register is error */ 1748 if (soc_is_rk3566()) 1749 vop2_mask_write(vop2, RK3568_SYS_OTP_WIN_EN, EN_MASK, 1750 OTP_WIN_EN_SHIFT, 1, false); 1751 1752 if (cstate->crtc->assign_plane) {/* dts assign plane */ 1753 u32 plane_mask; 1754 int primary_plane_id; 1755 1756 for (i = 0; i < vop2->data->nr_vps; i++) { 1757 plane_mask = cstate->crtc->vps[i].plane_mask; 1758 vop2->vp_plane_mask[i].plane_mask = plane_mask; 1759 layer_nr = hweight32(plane_mask); /* use bitmap to store plane mask */ 1760 vop2->vp_plane_mask[i].attached_layers_nr = layer_nr; 1761 primary_plane_id = cstate->crtc->vps[i].primary_plane_id; 1762 if (primary_plane_id < 0) 1763 primary_plane_id = vop2_get_primary_plane(vop2, plane_mask); 1764 vop2->vp_plane_mask[i].primary_plane_id = primary_plane_id; 1765 vop2->vp_plane_mask[i].plane_mask = plane_mask; 1766 1767 /* plane mask[bitmap] convert into layer phy id[enum vop2_layer_phy_id]*/ 1768 for (j = 0; j < layer_nr; j++) { 1769 vop2->vp_plane_mask[i].attached_layers[j] = ffs(plane_mask) - 1; 1770 plane_mask &= ~BIT(vop2->vp_plane_mask[i].attached_layers[j]); 1771 } 1772 } 1773 } else {/* need soft assign plane mask */ 1774 /* find the first unplug devices and set it as main display */ 1775 int main_vp_index = -1; 1776 int active_vp_num = 0; 1777 1778 for (i = 0; i < vop2->data->nr_vps; i++) { 1779 if (cstate->crtc->vps[i].enable) 1780 active_vp_num++; 1781 } 1782 printf("VOP have %d active VP\n", active_vp_num); 1783 1784 if (soc_is_rk3566() && active_vp_num > 2) 1785 printf("ERROR: rk3566 only support 2 display output!!\n"); 1786 plane_mask = vop2->data->plane_mask; 1787 plane_mask += (active_vp_num - 1) * VOP2_VP_MAX; 1788 1789 for (i = 0; i < vop2->data->nr_vps; i++) { 1790 if (!is_hot_plug_devices(cstate->crtc->vps[i].output_type)) { 1791 vop2->vp_plane_mask[i] = plane_mask[0]; /* the first store main display plane mask*/ 1792 main_vp_index = i; 1793 break; 1794 } 1795 } 1796 1797 /* if no find unplug devices, use vp0 as main display */ 1798 if (main_vp_index < 0) { 1799 main_vp_index = 0; 1800 vop2->vp_plane_mask[0] = plane_mask[0]; 1801 } 1802 1803 j = 1; /* plane_mask[0] store main display, so we from plane_mask[1] */ 1804 1805 /* init other display except main display */ 1806 for (i = 0; i < vop2->data->nr_vps; i++) { 1807 if (i == main_vp_index || !cstate->crtc->vps[i].enable) /* main display or no connect devices */ 1808 continue; 1809 vop2->vp_plane_mask[i] = plane_mask[j++]; 1810 } 1811 1812 /* store plane mask for vop2_fixup_dts */ 1813 for (i = 0; i < vop2->data->nr_vps; i++) { 1814 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1815 for (j = 0; j < layer_nr; j++) { 1816 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1817 vop2->vp_plane_mask[i].plane_mask |= BIT(layer_phy_id); 1818 } 1819 } 1820 } 1821 1822 if (vop2->version == VOP_VERSION_RK3588) 1823 rk3588_vop2_regsbak(vop2); 1824 else 1825 memcpy(vop2->regsbak, vop2->regs, vop2->reg_len); 1826 1827 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, 1828 OVL_PORT_MUX_REG_DONE_IMD_SHIFT, 1, false); 1829 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1830 IF_CTRL_REG_DONE_IMD_SHIFT, 1, false); 1831 1832 for (i = 0; i < vop2->data->nr_vps; i++) { 1833 printf("vp%d have layer nr:%d[", i, vop2->vp_plane_mask[i].attached_layers_nr); 1834 for (j = 0; j < vop2->vp_plane_mask[i].attached_layers_nr; j++) 1835 printf("%d ", vop2->vp_plane_mask[i].attached_layers[j]); 1836 printf("], primary plane: %d\n", vop2->vp_plane_mask[i].primary_plane_id); 1837 } 1838 1839 shift = 0; 1840 /* layer sel win id */ 1841 for (i = 0; i < vop2->data->nr_vps; i++) { 1842 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1843 for (j = 0; j < layer_nr; j++) { 1844 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1845 win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id); 1846 vop2_mask_write(vop2, RK3568_OVL_LAYER_SEL, LAYER_SEL_MASK, 1847 shift, win_data->layer_sel_win_id, false); 1848 shift += 4; 1849 } 1850 } 1851 1852 /* win sel port */ 1853 for (i = 0; i < vop2->data->nr_vps; i++) { 1854 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1855 for (j = 0; j < layer_nr; j++) { 1856 if (!vop2->vp_plane_mask[i].attached_layers[j]) 1857 continue; 1858 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1859 win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id); 1860 shift = win_data->win_sel_port_offset * 2; 1861 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, LAYER_SEL_PORT_MASK, 1862 LAYER_SEL_PORT_SHIFT + shift, i, false); 1863 } 1864 } 1865 1866 /** 1867 * port mux config 1868 */ 1869 for (i = 0; i < vop2->data->nr_vps; i++) { 1870 shift = i * 4; 1871 if (vop2->vp_plane_mask[i].attached_layers_nr) { 1872 total_used_layer += vop2->vp_plane_mask[i].attached_layers_nr; 1873 port_mux = total_used_layer - 1; 1874 } else { 1875 port_mux = 8; 1876 } 1877 1878 if (i == vop2->data->nr_vps - 1) 1879 port_mux = vop2->data->nr_mixers; 1880 1881 cstate->crtc->vps[i].bg_ovl_dly = (vop2->data->nr_mixers - port_mux) << 1; 1882 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, PORT_MUX_MASK, 1883 PORT_MUX_SHIFT + shift, port_mux, false); 1884 } 1885 1886 if (vop2->version == VOP_VERSION_RK3568) 1887 vop2_writel(vop2, RK3568_AUTO_GATING_CTRL, 0); 1888 1889 vop2->global_init = true; 1890 } 1891 1892 static int vop2_initial(struct vop2 *vop2, struct display_state *state) 1893 { 1894 struct crtc_state *cstate = &state->crtc_state; 1895 int ret; 1896 1897 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1898 ret = clk_set_defaults(cstate->dev); 1899 if (ret) 1900 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1901 1902 rockchip_vop2_gamma_lut_init(vop2, state); 1903 rockchip_vop2_cubic_lut_init(vop2, state); 1904 1905 return 0; 1906 } 1907 1908 /* 1909 * VOP2 have multi video ports. 1910 * video port ------- crtc 1911 */ 1912 static int rockchip_vop2_preinit(struct display_state *state) 1913 { 1914 struct crtc_state *cstate = &state->crtc_state; 1915 const struct vop2_data *vop2_data = cstate->crtc->data; 1916 1917 if (!rockchip_vop2) { 1918 rockchip_vop2 = calloc(1, sizeof(struct vop2)); 1919 if (!rockchip_vop2) 1920 return -ENOMEM; 1921 rockchip_vop2->regs = dev_read_addr_ptr(cstate->dev); 1922 rockchip_vop2->regsbak = malloc(RK3568_MAX_REG); 1923 rockchip_vop2->reg_len = RK3568_MAX_REG; 1924 rockchip_vop2->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1925 if (rockchip_vop2->grf <= 0) 1926 printf("%s: Get syscon grf failed (ret=%p)\n", __func__, rockchip_vop2->grf); 1927 rockchip_vop2->version = vop2_data->version; 1928 rockchip_vop2->data = vop2_data; 1929 if (rockchip_vop2->version == VOP_VERSION_RK3588) { 1930 struct regmap *map; 1931 1932 rockchip_vop2->vop_grf = syscon_get_first_range(ROCKCHIP_SYSCON_VOP_GRF); 1933 if (rockchip_vop2->vop_grf <= 0) 1934 printf("%s: Get syscon vop_grf failed (ret=%p)\n", __func__, rockchip_vop2->vop_grf); 1935 map = syscon_regmap_lookup_by_phandle(cstate->dev, "rockchip,vo1-grf"); 1936 rockchip_vop2->vo1_grf = regmap_get_range(map, 0); 1937 if (rockchip_vop2->vo1_grf <= 0) 1938 printf("%s: Get syscon vo1_grf failed (ret=%p)\n", __func__, rockchip_vop2->vo1_grf); 1939 rockchip_vop2->sys_pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); 1940 if (rockchip_vop2->sys_pmu <= 0) 1941 printf("%s: Get syscon sys_pmu failed (ret=%p)\n", __func__, rockchip_vop2->sys_pmu); 1942 } 1943 } 1944 1945 cstate->private = rockchip_vop2; 1946 cstate->max_output = vop2_data->vp_data[cstate->crtc_id].max_output; 1947 cstate->feature = vop2_data->vp_data[cstate->crtc_id].feature; 1948 1949 vop2_global_initial(rockchip_vop2, state); 1950 1951 return 0; 1952 } 1953 1954 /* 1955 * calc the dclk on rk3588 1956 * the available div of dclk is 1, 2, 4 1957 * 1958 */ 1959 static unsigned long vop2_calc_dclk(unsigned long child_clk, unsigned long max_dclk) 1960 { 1961 if (child_clk * 4 <= max_dclk) 1962 return child_clk * 4; 1963 else if (child_clk * 2 <= max_dclk) 1964 return child_clk * 2; 1965 else if (child_clk <= max_dclk) 1966 return child_clk; 1967 else 1968 return 0; 1969 } 1970 1971 /* 1972 * 4 pixclk/cycle on rk3588 1973 * RGB/eDP/HDMI: if_pixclk >= dclk_core 1974 * DP: dp_pixclk = dclk_out <= dclk_core 1975 * DSI: mipi_pixclk <= dclk_out <= dclk_core 1976 */ 1977 static unsigned long vop2_calc_cru_cfg(struct display_state *state, 1978 int *dclk_core_div, int *dclk_out_div, 1979 int *if_pixclk_div, int *if_dclk_div) 1980 { 1981 struct crtc_state *cstate = &state->crtc_state; 1982 struct connector_state *conn_state = &state->conn_state; 1983 struct drm_display_mode *mode = &conn_state->mode; 1984 struct vop2 *vop2 = cstate->private; 1985 unsigned long v_pixclk = mode->crtc_clock; 1986 unsigned long dclk_core_rate = v_pixclk >> 2; 1987 unsigned long dclk_rate = v_pixclk; 1988 unsigned long dclk_out_rate; 1989 u64 if_dclk_rate; 1990 u64 if_pixclk_rate; 1991 int output_type = conn_state->type; 1992 int output_mode = conn_state->output_mode; 1993 int K = 1; 1994 1995 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE && 1996 output_mode == ROCKCHIP_OUT_MODE_YUV420) { 1997 printf("Dual channel and YUV420 can't work together\n"); 1998 return -EINVAL; 1999 } 2000 2001 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE || 2002 output_mode == ROCKCHIP_OUT_MODE_YUV420) 2003 K = 2; 2004 2005 if (output_type == DRM_MODE_CONNECTOR_HDMIA) { 2006 /* 2007 * K = 2: dclk_core = if_pixclk_rate > if_dclk_rate 2008 * K = 1: dclk_core = hdmie_edp_dclk > if_pixclk_rate 2009 */ 2010 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE || 2011 output_mode == ROCKCHIP_OUT_MODE_YUV420) { 2012 dclk_rate = dclk_rate >> 1; 2013 K = 2; 2014 } 2015 if (cstate->dsc_enable) { 2016 if_pixclk_rate = cstate->dsc_cds_clk_rate << 1; 2017 if_dclk_rate = cstate->dsc_cds_clk_rate; 2018 } else { 2019 if_pixclk_rate = (dclk_core_rate << 1) / K; 2020 if_dclk_rate = dclk_core_rate / K; 2021 } 2022 2023 if (v_pixclk > VOP2_MAX_DCLK_RATE) 2024 dclk_rate = vop2_calc_dclk(dclk_core_rate, vop2->data->vp_data->max_dclk); 2025 2026 if (!dclk_rate) { 2027 printf("DP if_pixclk_rate out of range(max_dclk: %d KHZ, dclk_core: %lld KHZ)\n", 2028 vop2->data->vp_data->max_dclk, if_pixclk_rate); 2029 return -EINVAL; 2030 } 2031 *if_pixclk_div = dclk_rate / if_pixclk_rate; 2032 *if_dclk_div = dclk_rate / if_dclk_rate; 2033 *dclk_core_div = dclk_rate / dclk_core_rate; 2034 printf("dclk:%lu,if_pixclk_div;%d,if_dclk_div:%d\n", 2035 dclk_rate, *if_pixclk_div, *if_dclk_div); 2036 } else if (output_type == DRM_MODE_CONNECTOR_eDP) { 2037 /* edp_pixclk = edp_dclk > dclk_core */ 2038 if_pixclk_rate = v_pixclk / K; 2039 if_dclk_rate = v_pixclk / K; 2040 dclk_rate = if_pixclk_rate * K; 2041 *dclk_core_div = dclk_rate / dclk_core_rate; 2042 *if_pixclk_div = dclk_rate / if_pixclk_rate; 2043 *if_dclk_div = *if_pixclk_div; 2044 } else if (output_type == DRM_MODE_CONNECTOR_DisplayPort) { 2045 dclk_out_rate = v_pixclk >> 2; 2046 dclk_out_rate = dclk_out_rate / K; 2047 2048 dclk_rate = vop2_calc_dclk(dclk_out_rate, vop2->data->vp_data->max_dclk); 2049 if (!dclk_rate) { 2050 printf("DP dclk_core out of range(max_dclk: %d KHZ, dclk_core: %ld KHZ)\n", 2051 vop2->data->vp_data->max_dclk, dclk_core_rate); 2052 return -EINVAL; 2053 } 2054 *dclk_out_div = dclk_rate / dclk_out_rate; 2055 *dclk_core_div = dclk_rate / dclk_core_rate; 2056 } else if (output_type == DRM_MODE_CONNECTOR_DSI) { 2057 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2058 K = 2; 2059 if (cstate->dsc_enable) 2060 /* dsc output is 96bit, dsi input is 192 bit */ 2061 if_pixclk_rate = cstate->dsc_cds_clk_rate >> 1; 2062 else 2063 if_pixclk_rate = dclk_core_rate / K; 2064 /* dclk_core = dclk_out * K = if_pixclk * K = v_pixclk / 4 */ 2065 dclk_out_rate = dclk_core_rate / K; 2066 /* dclk_rate = N * dclk_core_rate N = (1,2,4 ), we get a little factor here */ 2067 dclk_rate = vop2_calc_dclk(dclk_out_rate, vop2->data->vp_data->max_dclk); 2068 if (!dclk_rate) { 2069 printf("MIPI dclk out of range(max_dclk: %d KHZ, dclk_rate: %ld KHZ)\n", 2070 vop2->data->vp_data->max_dclk, dclk_rate); 2071 return -EINVAL; 2072 } 2073 2074 if (cstate->dsc_enable) 2075 dclk_rate = dclk_rate >> 1; 2076 2077 *dclk_out_div = dclk_rate / dclk_out_rate; 2078 *dclk_core_div = dclk_rate / dclk_core_rate; 2079 *if_pixclk_div = 1; /*mipi pixclk == dclk_out*/ 2080 if (cstate->dsc_enable) 2081 *if_pixclk_div = dclk_out_rate / if_pixclk_rate; 2082 2083 } else if (output_type == DRM_MODE_CONNECTOR_DPI) { 2084 dclk_rate = v_pixclk; 2085 *dclk_core_div = dclk_rate / dclk_core_rate; 2086 } 2087 2088 *if_pixclk_div = ilog2(*if_pixclk_div); 2089 *if_dclk_div = ilog2(*if_dclk_div); 2090 *dclk_core_div = ilog2(*dclk_core_div); 2091 *dclk_out_div = ilog2(*dclk_out_div); 2092 2093 return dclk_rate; 2094 } 2095 2096 static int vop2_calc_dsc_clk(struct display_state *state) 2097 { 2098 struct connector_state *conn_state = &state->conn_state; 2099 struct drm_display_mode *mode = &conn_state->mode; 2100 struct crtc_state *cstate = &state->crtc_state; 2101 u64 v_pixclk = mode->clock; /* video timing pixclk */ 2102 u8 k = 1; 2103 2104 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2105 k = 2; 2106 2107 cstate->dsc_txp_clk_rate = v_pixclk; 2108 do_div(cstate->dsc_txp_clk_rate, (cstate->dsc_pixel_num * k)); 2109 2110 cstate->dsc_pxl_clk_rate = v_pixclk; 2111 do_div(cstate->dsc_pxl_clk_rate, (cstate->dsc_slice_num * k)); 2112 2113 /* dsc_cds = crtc_clock / (cds_dat_width / bits_per_pixel) 2114 * cds_dat_width = 96; 2115 * bits_per_pixel = [8-12]; 2116 * As cds clk is div from txp clk and only support 1/2/4 div, 2117 * so when txp_clk is equal to v_pixclk, we set dsc_cds = crtc_clock / 4, 2118 * otherwise dsc_cds = crtc_clock / 8; 2119 */ 2120 cstate->dsc_cds_clk_rate = v_pixclk / (cstate->dsc_txp_clk_rate == v_pixclk ? 4 : 8); 2121 2122 return 0; 2123 } 2124 2125 static unsigned long rk3588_vop2_if_cfg(struct display_state *state) 2126 { 2127 struct crtc_state *cstate = &state->crtc_state; 2128 struct connector_state *conn_state = &state->conn_state; 2129 struct drm_display_mode *mode = &conn_state->mode; 2130 struct rockchip_dsc_sink_cap *dsc_sink_cap = &cstate->dsc_sink_cap; 2131 struct vop2 *vop2 = cstate->private; 2132 u32 vp_offset = (cstate->crtc_id * 0x100); 2133 u16 hdisplay = mode->crtc_hdisplay; 2134 int output_if = conn_state->output_if; 2135 int if_pixclk_div = 0; 2136 int if_dclk_div = 0; 2137 unsigned long dclk_rate; 2138 u32 val; 2139 2140 if (output_if & (VOP_OUTPUT_IF_HDMI0 | VOP_OUTPUT_IF_HDMI1)) { 2141 val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? BIT(HSYNC_POSITIVE) : 0; 2142 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? BIT(VSYNC_POSITIVE) : 0; 2143 } else { 2144 val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE); 2145 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE); 2146 } 2147 2148 if (cstate->dsc_enable) { 2149 int k = 1; 2150 2151 if (!vop2->data->nr_dscs) { 2152 printf("Unsupported DSC\n"); 2153 return 0; 2154 } 2155 2156 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2157 k = 2; 2158 2159 cstate->dsc_id = output_if & (VOP_OUTPUT_IF_MIPI0 | VOP_OUTPUT_IF_HDMI0) ? 0 : 1; 2160 cstate->dsc_slice_num = hdisplay / dsc_sink_cap->slice_width / k; 2161 cstate->dsc_pixel_num = cstate->dsc_slice_num > 4 ? 4 : cstate->dsc_slice_num; 2162 2163 vop2_calc_dsc_clk(state); 2164 printf("Enable DSC%d slice:%dx%d, slice num:%d\n", 2165 cstate->dsc_id, dsc_sink_cap->slice_width, 2166 dsc_sink_cap->slice_height, cstate->dsc_slice_num); 2167 } 2168 2169 dclk_rate = vop2_calc_cru_cfg(state, &cstate->dclk_core_div, &cstate->dclk_out_div, &if_pixclk_div, &if_dclk_div); 2170 2171 if (output_if & VOP_OUTPUT_IF_RGB) { 2172 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, 2173 4, false); 2174 } 2175 2176 if (output_if & VOP_OUTPUT_IF_BT1120) { 2177 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, 2178 3, false); 2179 } 2180 2181 if (output_if & VOP_OUTPUT_IF_BT656) { 2182 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, 2183 2, false); 2184 } 2185 2186 if (output_if & VOP_OUTPUT_IF_MIPI0) { 2187 if (cstate->crtc_id == 2) 2188 val = 0; 2189 else 2190 val = 1; 2191 2192 if (conn_state->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE) 2193 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2194 RK3588_MIPI_DSI0_MODE_SEL_SHIFT, 1, false); 2195 2196 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_MIPI0_EN_SHIFT, 2197 1, false); 2198 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 1, RK3588_MIPI0_MUX_SHIFT, val, false); 2199 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, MIPI0_PIXCLK_DIV_SHIFT, 2200 if_pixclk_div, false); 2201 2202 if (conn_state->hold_mode) { 2203 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2204 EN_MASK, EDPI_TE_EN, 1, false); 2205 2206 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2207 EN_MASK, EDPI_WMS_HOLD_EN, 1, false); 2208 } 2209 } 2210 2211 if (output_if & VOP_OUTPUT_IF_MIPI1) { 2212 if (cstate->crtc_id == 2) 2213 val = 0; 2214 else if (cstate->crtc_id == 3) 2215 val = 1; 2216 else 2217 val = 3; /*VP1*/ 2218 if (conn_state->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE) 2219 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2220 RK3588_MIPI_DSI1_MODE_SEL_SHIFT, 1, false); 2221 2222 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_MIPI1_EN_SHIFT, 2223 1, false); 2224 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, MIPI1_MUX_SHIFT, 2225 val, false); 2226 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, MIPI1_PIXCLK_DIV_SHIFT, 2227 if_pixclk_div, false); 2228 2229 if (conn_state->hold_mode) { 2230 /* UNDO: RK3588 VP1->DSC1->DSI1 only can support soft TE mode */ 2231 if (vop2->version == VOP_VERSION_RK3588 && val == 3) 2232 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2233 EN_MASK, EDPI_TE_EN, 0, false); 2234 else 2235 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2236 EN_MASK, EDPI_TE_EN, 1, false); 2237 2238 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2239 EN_MASK, EDPI_WMS_HOLD_EN, 1, false); 2240 } 2241 } 2242 2243 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { 2244 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, 2245 MIPI_DUAL_EN_SHIFT, 1, false); 2246 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) 2247 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2248 EN_MASK, MIPI_DUAL_SWAP_EN_SHIFT, 1, 2249 false); 2250 switch (conn_state->type) { 2251 case DRM_MODE_CONNECTOR_DisplayPort: 2252 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2253 RK3588_DP_DUAL_EN_SHIFT, 1, false); 2254 break; 2255 case DRM_MODE_CONNECTOR_eDP: 2256 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2257 RK3588_EDP_DUAL_EN_SHIFT, 1, false); 2258 break; 2259 case DRM_MODE_CONNECTOR_HDMIA: 2260 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2261 RK3588_HDMI_DUAL_EN_SHIFT, 1, false); 2262 break; 2263 case DRM_MODE_CONNECTOR_DSI: 2264 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2265 RK3568_MIPI_DUAL_EN_SHIFT, 1, false); 2266 break; 2267 default: 2268 break; 2269 } 2270 } 2271 2272 if (output_if & VOP_OUTPUT_IF_eDP0) { 2273 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_EDP0_EN_SHIFT, 2274 1, false); 2275 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP0_MUX_SHIFT, 2276 cstate->crtc_id, false); 2277 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_DCLK_DIV_SHIFT, 2278 if_dclk_div, false); 2279 2280 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_PIXCLK_DIV_SHIFT, 2281 if_pixclk_div, false); 2282 2283 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, 2284 RK3588_GRF_EDP0_ENABLE_SHIFT, 1); 2285 } 2286 2287 if (output_if & VOP_OUTPUT_IF_eDP1) { 2288 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_EDP1_EN_SHIFT, 2289 1, false); 2290 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP1_MUX_SHIFT, 2291 cstate->crtc_id, false); 2292 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_DCLK_DIV_SHIFT, 2293 if_dclk_div, false); 2294 2295 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_PIXCLK_DIV_SHIFT, 2296 if_pixclk_div, false); 2297 2298 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, 2299 RK3588_GRF_EDP1_ENABLE_SHIFT, 1); 2300 } 2301 2302 if (output_if & VOP_OUTPUT_IF_HDMI0) { 2303 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_HDMI0_EN_SHIFT, 2304 1, false); 2305 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP0_MUX_SHIFT, 2306 cstate->crtc_id, false); 2307 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_DCLK_DIV_SHIFT, 2308 if_dclk_div, false); 2309 2310 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_PIXCLK_DIV_SHIFT, 2311 if_pixclk_div, false); 2312 2313 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, 2314 RK3588_GRF_HDMITX0_ENABLE_SHIFT, 1); 2315 vop2_grf_writel(vop2, vop2->vo1_grf, RK3588_GRF_VO1_CON0, 2316 HDMI_SYNC_POL_MASK, 2317 HDMI0_SYNC_POL_SHIFT, val); 2318 } 2319 2320 if (output_if & VOP_OUTPUT_IF_HDMI1) { 2321 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_HDMI1_EN_SHIFT, 2322 1, false); 2323 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP1_MUX_SHIFT, 2324 cstate->crtc_id, false); 2325 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_DCLK_DIV_SHIFT, 2326 if_dclk_div, false); 2327 2328 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_PIXCLK_DIV_SHIFT, 2329 if_pixclk_div, false); 2330 2331 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, 2332 RK3588_GRF_HDMITX1_ENABLE_SHIFT, 1); 2333 vop2_grf_writel(vop2, vop2->vo1_grf, RK3588_GRF_VO1_CON0, 2334 HDMI_SYNC_POL_MASK, 2335 HDMI1_SYNC_POL_SHIFT, val); 2336 } 2337 2338 if (output_if & VOP_OUTPUT_IF_DP0) { 2339 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP0_EN_SHIFT, 2340 1, false); 2341 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_DP0_MUX_SHIFT, 2342 cstate->crtc_id, false); 2343 vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3588_IF_PIN_POL_MASK, 2344 RK3588_DP0_PIN_POL_SHIFT, val, false); 2345 } 2346 2347 if (output_if & VOP_OUTPUT_IF_DP1) { 2348 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP1_EN_SHIFT, 2349 1, false); 2350 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_DP1_MUX_SHIFT, 2351 cstate->crtc_id, false); 2352 vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3588_IF_PIN_POL_MASK, 2353 RK3588_DP1_PIN_POL_SHIFT, val, false); 2354 } 2355 2356 vop2_mask_write(vop2, RK3588_VP0_CLK_CTRL + vp_offset, 0x3, 2357 DCLK_CORE_DIV_SHIFT, cstate->dclk_core_div, false); 2358 vop2_mask_write(vop2, RK3588_VP0_CLK_CTRL + vp_offset, 0x3, 2359 DCLK_OUT_DIV_SHIFT, cstate->dclk_out_div, false); 2360 2361 return dclk_rate; 2362 } 2363 2364 static unsigned long rk3568_vop2_if_cfg(struct display_state *state) 2365 { 2366 struct crtc_state *cstate = &state->crtc_state; 2367 struct connector_state *conn_state = &state->conn_state; 2368 struct drm_display_mode *mode = &conn_state->mode; 2369 struct vop2 *vop2 = cstate->private; 2370 u32 vp_offset = (cstate->crtc_id * 0x100); 2371 bool dclk_inv; 2372 u32 val; 2373 2374 dclk_inv = (mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1; 2375 val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE); 2376 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE); 2377 2378 if (conn_state->output_if & VOP_OUTPUT_IF_RGB) { 2379 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, 2380 1, false); 2381 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2382 RGB_MUX_SHIFT, cstate->crtc_id, false); 2383 vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK, 2384 GRF_RGB_DCLK_INV_SHIFT, dclk_inv); 2385 } 2386 2387 if (conn_state->output_if & VOP_OUTPUT_IF_BT1120) { 2388 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, 2389 1, false); 2390 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, 2391 BT1120_EN_SHIFT, 1, false); 2392 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2393 RGB_MUX_SHIFT, cstate->crtc_id, false); 2394 vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK, 2395 GRF_BT1120_CLK_INV_SHIFT, !dclk_inv); 2396 } 2397 2398 if (conn_state->output_if & VOP_OUTPUT_IF_BT656) { 2399 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT, 2400 1, false); 2401 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2402 RGB_MUX_SHIFT, cstate->crtc_id, false); 2403 vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK, 2404 GRF_BT656_CLK_INV_SHIFT, !dclk_inv); 2405 } 2406 2407 if (conn_state->output_if & VOP_OUTPUT_IF_LVDS0) { 2408 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT, 2409 1, false); 2410 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2411 LVDS0_MUX_SHIFT, cstate->crtc_id, false); 2412 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2413 IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false); 2414 } 2415 2416 if (conn_state->output_if & VOP_OUTPUT_IF_LVDS1) { 2417 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS1_EN_SHIFT, 2418 1, false); 2419 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2420 LVDS1_MUX_SHIFT, cstate->crtc_id, false); 2421 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2422 IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false); 2423 } 2424 2425 if (conn_state->output_flags & 2426 (ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE | 2427 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)) { 2428 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2429 LVDS_DUAL_EN_SHIFT, 1, false); 2430 if (conn_state->output_flags & 2431 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2432 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2433 LVDS_DUAL_LEFT_RIGHT_EN_SHIFT, 1, 2434 false); 2435 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) 2436 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2437 LVDS_DUAL_SWAP_EN_SHIFT, 1, false); 2438 } 2439 2440 if (conn_state->output_if & VOP_OUTPUT_IF_MIPI0) { 2441 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT, 2442 1, false); 2443 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2444 MIPI0_MUX_SHIFT, cstate->crtc_id, false); 2445 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2446 IF_CRTL_MIPI_DCLK_POL_SHIT, dclk_inv, false); 2447 } 2448 2449 if (conn_state->output_if & VOP_OUTPUT_IF_MIPI1) { 2450 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI1_EN_SHIFT, 2451 1, false); 2452 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2453 MIPI1_MUX_SHIFT, cstate->crtc_id, false); 2454 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2455 IF_CRTL_MIPI_DCLK_POL_SHIT, dclk_inv, false); 2456 } 2457 2458 if (conn_state->output_flags & 2459 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { 2460 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, 2461 MIPI_DUAL_EN_SHIFT, 1, false); 2462 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) 2463 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2464 EN_MASK, MIPI_DUAL_SWAP_EN_SHIFT, 1, 2465 false); 2466 } 2467 2468 if (conn_state->output_if & VOP_OUTPUT_IF_eDP0) { 2469 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, EDP0_EN_SHIFT, 2470 1, false); 2471 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2472 EDP0_MUX_SHIFT, cstate->crtc_id, false); 2473 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2474 IF_CRTL_EDP_DCLK_POL_SHIT, dclk_inv, false); 2475 } 2476 2477 if (conn_state->output_if & VOP_OUTPUT_IF_HDMI0) { 2478 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT, 2479 1, false); 2480 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2481 HDMI0_MUX_SHIFT, cstate->crtc_id, false); 2482 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2483 IF_CRTL_HDMI_DCLK_POL_SHIT, 1, false); 2484 vop2_mask_write(vop2, RK3568_DSP_IF_POL, 2485 IF_CRTL_HDMI_PIN_POL_MASK, 2486 IF_CRTL_HDMI_PIN_POL_SHIT, val, false); 2487 } 2488 2489 return mode->clock; 2490 } 2491 2492 static void vop2_post_color_swap(struct display_state *state) 2493 { 2494 struct crtc_state *cstate = &state->crtc_state; 2495 struct connector_state *conn_state = &state->conn_state; 2496 struct vop2 *vop2 = cstate->private; 2497 u32 vp_offset = (cstate->crtc_id * 0x100); 2498 u32 output_type = conn_state->type; 2499 u32 data_swap = 0; 2500 2501 if (is_uv_swap(conn_state->bus_format, conn_state->output_mode)) 2502 data_swap = DSP_RB_SWAP; 2503 2504 if (vop2->version == VOP_VERSION_RK3588 && 2505 (output_type == DRM_MODE_CONNECTOR_HDMIA || 2506 output_type == DRM_MODE_CONNECTOR_eDP) && 2507 (conn_state->bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 2508 conn_state->bus_format == MEDIA_BUS_FMT_YUV10_1X30)) 2509 data_swap |= DSP_RG_SWAP; 2510 2511 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 2512 DATA_SWAP_MASK, DATA_SWAP_SHIFT, data_swap, false); 2513 } 2514 2515 static void vop2_clk_set_parent(struct clk *clk, struct clk *parent) 2516 { 2517 int ret = 0; 2518 2519 if (parent->dev) 2520 ret = clk_set_parent(clk, parent); 2521 if (ret < 0) 2522 debug("failed to set %s as parent for %s\n", 2523 parent->dev->name, clk->dev->name); 2524 } 2525 2526 static ulong vop2_clk_set_rate(struct clk *clk, ulong rate) 2527 { 2528 int ret = 0; 2529 2530 if (clk->dev) 2531 ret = clk_set_rate(clk, rate); 2532 if (ret < 0) 2533 debug("failed to set %s rate %lu \n", clk->dev->name, rate); 2534 2535 return ret; 2536 } 2537 2538 static void vop2_calc_dsc_cru_cfg(struct display_state *state, 2539 int *dsc_txp_clk_div, int *dsc_pxl_clk_div, 2540 int *dsc_cds_clk_div, u64 dclk_rate) 2541 { 2542 struct crtc_state *cstate = &state->crtc_state; 2543 2544 *dsc_txp_clk_div = dclk_rate / cstate->dsc_txp_clk_rate; 2545 *dsc_pxl_clk_div = dclk_rate / cstate->dsc_pxl_clk_rate; 2546 *dsc_cds_clk_div = dclk_rate / cstate->dsc_cds_clk_rate; 2547 2548 *dsc_txp_clk_div = ilog2(*dsc_txp_clk_div); 2549 *dsc_pxl_clk_div = ilog2(*dsc_pxl_clk_div); 2550 *dsc_cds_clk_div = ilog2(*dsc_cds_clk_div); 2551 } 2552 2553 static void vop2_load_pps(struct display_state *state, struct vop2 *vop2, u8 dsc_id) 2554 { 2555 struct crtc_state *cstate = &state->crtc_state; 2556 struct drm_dsc_picture_parameter_set *pps = &cstate->pps; 2557 struct drm_dsc_picture_parameter_set config_pps; 2558 const struct vop2_data *vop2_data = vop2->data; 2559 const struct vop2_dsc_data *dsc_data = &vop2_data->dsc[dsc_id]; 2560 u32 *pps_val = (u32 *)&config_pps; 2561 u32 decoder_regs_offset = (dsc_id * 0x100); 2562 int i = 0; 2563 2564 memcpy(&config_pps, pps, sizeof(config_pps)); 2565 2566 if ((config_pps.pps_3 & 0xf) > dsc_data->max_linebuf_depth) { 2567 config_pps.pps_3 &= 0xf0; 2568 config_pps.pps_3 |= dsc_data->max_linebuf_depth; 2569 printf("DSC%d max_linebuf_depth is: %d, current set value is: %d\n", 2570 dsc_id, dsc_data->max_linebuf_depth, config_pps.pps_3 & 0xf); 2571 } 2572 2573 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 2574 config_pps.rc_range_parameters[i] = 2575 (pps->rc_range_parameters[i] >> 3 & 0x1f) | 2576 ((pps->rc_range_parameters[i] >> 14 & 0x3) << 5) | 2577 ((pps->rc_range_parameters[i] >> 0 & 0x7) << 7) | 2578 ((pps->rc_range_parameters[i] >> 8 & 0x3f) << 10); 2579 } 2580 2581 for (i = 0; i < ROCKCHIP_DSC_PPS_SIZE_BYTE / 4; i++) 2582 vop2_writel(vop2, RK3588_DSC_8K_PPS0_3 + decoder_regs_offset + i * 4, *pps_val++); 2583 } 2584 2585 static void vop2_dsc_enable(struct display_state *state, struct vop2 *vop2, u8 dsc_id, u64 dclk_rate) 2586 { 2587 struct connector_state *conn_state = &state->conn_state; 2588 struct drm_display_mode *mode = &conn_state->mode; 2589 struct crtc_state *cstate = &state->crtc_state; 2590 struct rockchip_dsc_sink_cap *dsc_sink_cap = &cstate->dsc_sink_cap; 2591 const struct vop2_data *vop2_data = vop2->data; 2592 const struct vop2_dsc_data *dsc_data = &vop2_data->dsc[dsc_id]; 2593 bool mipi_ds_mode = false; 2594 u8 dsc_interface_mode = 0; 2595 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 2596 u16 hdisplay = mode->crtc_hdisplay; 2597 u16 htotal = mode->crtc_htotal; 2598 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 2599 u16 vdisplay = mode->crtc_vdisplay; 2600 u16 vtotal = mode->crtc_vtotal; 2601 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 2602 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 2603 u16 vact_end = vact_st + vdisplay; 2604 u32 ctrl_regs_offset = (dsc_id * 0x30); 2605 u32 decoder_regs_offset = (dsc_id * 0x100); 2606 u32 backup_regs_offset = 0; 2607 int dsc_txp_clk_div = 0; 2608 int dsc_pxl_clk_div = 0; 2609 int dsc_cds_clk_div = 0; 2610 2611 if (!vop2->data->nr_dscs) { 2612 printf("Unsupported DSC\n"); 2613 return; 2614 } 2615 2616 if (cstate->dsc_slice_num > dsc_data->max_slice_num) 2617 printf("DSC%d supported max slice is: %d, current is: %d\n", 2618 dsc_data->id, dsc_data->max_slice_num, cstate->dsc_slice_num); 2619 2620 if (dsc_data->pd_id) { 2621 if (vop2_power_domain_on(vop2, dsc_data->pd_id)) 2622 printf("open dsc%d pd fail\n", dsc_id); 2623 } 2624 2625 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, EN_MASK, 2626 SCAN_TIMING_PARA_IMD_EN_SHIFT, 1, false); 2627 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PORT_SEL_MASK, 2628 DSC_PORT_SEL_SHIFT, cstate->crtc_id, false); 2629 if (conn_state->output_if & (VOP_OUTPUT_IF_HDMI0 | VOP_OUTPUT_IF_HDMI1)) { 2630 dsc_interface_mode = VOP_DSC_IF_HDMI; 2631 } else { 2632 mipi_ds_mode = !!(conn_state->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE); 2633 if (mipi_ds_mode) 2634 dsc_interface_mode = VOP_DSC_IF_MIPI_DS_MODE; 2635 else 2636 dsc_interface_mode = VOP_DSC_IF_MIPI_VIDEO_MODE; 2637 } 2638 2639 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2640 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_MAN_MODE_MASK, 2641 DSC_MAN_MODE_SHIFT, 0, false); 2642 else 2643 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_MAN_MODE_MASK, 2644 DSC_MAN_MODE_SHIFT, 1, false); 2645 2646 vop2_calc_dsc_cru_cfg(state, &dsc_txp_clk_div, &dsc_pxl_clk_div, &dsc_cds_clk_div, dclk_rate); 2647 2648 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_INTERFACE_MODE_MASK, 2649 DSC_INTERFACE_MODE_SHIFT, dsc_interface_mode, false); 2650 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PIXEL_NUM_MASK, 2651 DSC_PIXEL_NUM_SHIFT, cstate->dsc_pixel_num >> 1, false); 2652 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_TXP_CLK_DIV_MASK, 2653 DSC_TXP_CLK_DIV_SHIFT, dsc_txp_clk_div, false); 2654 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PXL_CLK_DIV_MASK, 2655 DSC_PXL_CLK_DIV_SHIFT, dsc_pxl_clk_div, false); 2656 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_CDS_CLK_DIV_MASK, 2657 DSC_CDS_CLK_DIV_SHIFT, dsc_cds_clk_div, false); 2658 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, EN_MASK, 2659 DSC_SCAN_EN_SHIFT, !mipi_ds_mode, false); 2660 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_CDS_CLK_DIV_MASK, 2661 DSC_HALT_EN_SHIFT, mipi_ds_mode, false); 2662 2663 if (!mipi_ds_mode) { 2664 u16 dsc_hsync, dsc_htotal, dsc_hact_st, dsc_hact_end; 2665 u32 target_bpp = dsc_sink_cap->target_bits_per_pixel_x16; 2666 u64 dsc_cds_rate = cstate->dsc_cds_clk_rate; 2667 u32 v_pixclk_mhz = mode->crtc_clock / 1000; /* video timing pixclk */ 2668 u32 dly_num, dsc_cds_rate_mhz, val = 0; 2669 int k = 1; 2670 2671 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2672 k = 2; 2673 2674 if (target_bpp >> 4 < dsc_data->min_bits_per_pixel) 2675 printf("Unsupported bpp less than: %d\n", dsc_data->min_bits_per_pixel); 2676 2677 /* 2678 * dly_num = delay_line_num * T(one-line) / T (dsc_cds) 2679 * T (one-line) = 1/v_pixclk_mhz * htotal = htotal/v_pixclk_mhz 2680 * T (dsc_cds) = 1 / dsc_cds_rate_mhz 2681 * delay_line_num: according the pps initial_xmit_delay to adjust vop dsc delay 2682 * delay_line_num = 4 - BPP / 8 2683 * = (64 - target_bpp / 8) / 16 2684 * 2685 * dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16; 2686 */ 2687 do_div(dsc_cds_rate, 1000000); /* hz to Mhz */ 2688 dsc_cds_rate_mhz = dsc_cds_rate; 2689 dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16; 2690 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, DSC_INIT_DLY_MODE_MASK, 2691 DSC_INIT_DLY_MODE_SHIFT, 0, false); 2692 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, DSC_INIT_DLY_NUM_MASK, 2693 DSC_INIT_DLY_NUM_SHIFT, dly_num, false); 2694 2695 dsc_hsync = hsync_len / 2; 2696 /* 2697 * htotal / dclk_core = dsc_htotal /cds_clk 2698 * 2699 * dclk_core = DCLK / (1 << dclk_core->div_val) 2700 * cds_clk = txp_clk / (1 << dsc_cds_clk->div_val) 2701 * txp_clk = DCLK / (1 << dsc_txp_clk->div_val) 2702 * 2703 * dsc_htotal = htotal * (1 << dclk_core->div_val) / 2704 * ((1 << dsc_txp_clk->div_val) * (1 << dsc_cds_clk->div_val)) 2705 */ 2706 dsc_htotal = htotal * (1 << cstate->dclk_core_div) / 2707 ((1 << dsc_txp_clk_div) * (1 << dsc_cds_clk_div)); 2708 val = dsc_htotal << 16 | dsc_hsync; 2709 vop2_mask_write(vop2, RK3588_DSC_8K_HTOTAL_HS_END + ctrl_regs_offset, DSC_HTOTAL_PW_MASK, 2710 DSC_HTOTAL_PW_SHIFT, val, false); 2711 2712 dsc_hact_st = hact_st / 2; 2713 dsc_hact_end = (hdisplay / k * target_bpp >> 4) / 24 + dsc_hact_st; 2714 val = dsc_hact_end << 16 | dsc_hact_st; 2715 vop2_mask_write(vop2, RK3588_DSC_8K_HACT_ST_END + ctrl_regs_offset, DSC_HACT_ST_END_MASK, 2716 DSC_HACT_ST_END_SHIFT, val, false); 2717 2718 vop2_mask_write(vop2, RK3588_DSC_8K_VTOTAL_VS_END + ctrl_regs_offset, DSC_VTOTAL_PW_MASK, 2719 DSC_VTOTAL_PW_SHIFT, vtotal << 16 | vsync_len, false); 2720 vop2_mask_write(vop2, RK3588_DSC_8K_VACT_ST_END + ctrl_regs_offset, DSC_VACT_ST_END_MASK, 2721 DSC_VACT_ST_END_SHIFT, vact_end << 16 | vact_st, false); 2722 } 2723 2724 vop2_mask_write(vop2, RK3588_DSC_8K_RST + ctrl_regs_offset, RST_DEASSERT_MASK, 2725 RST_DEASSERT_SHIFT, 1, false); 2726 udelay(10); 2727 /* read current dsc core register and backup to regsbak */ 2728 backup_regs_offset = RK3588_DSC_8K_CTRL0; 2729 vop2->regsbak[backup_regs_offset >> 2] = vop2_readl(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset); 2730 2731 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2732 DSC_EN_SHIFT, 1, false); 2733 vop2_load_pps(state, vop2, dsc_id); 2734 2735 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2736 DSC_RBIT_SHIFT, 1, false); 2737 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2738 DSC_RBYT_SHIFT, 0, false); 2739 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2740 DSC_FLAL_SHIFT, 1, false); 2741 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2742 DSC_MER_SHIFT, 1, false); 2743 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2744 DSC_EPB_SHIFT, 0, false); 2745 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2746 DSC_EPL_SHIFT, 1, false); 2747 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2748 DSC_NSLC_SHIFT, ilog2(cstate->dsc_slice_num), false); 2749 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2750 DSC_SBO_SHIFT, 1, false); 2751 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2752 DSC_IFEP_SHIFT, dsc_sink_cap->version_minor == 2 ? 1 : 0, false); 2753 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2754 DSC_PPS_UPD_SHIFT, 1, false); 2755 2756 printf("DSC%d: txp:%lld div:%d, pxl:%lld div:%d, dsc:%lld div:%d\n", 2757 dsc_id, 2758 cstate->dsc_txp_clk_rate, dsc_txp_clk_div, 2759 cstate->dsc_pxl_clk_rate, dsc_pxl_clk_div, 2760 cstate->dsc_cds_clk_rate, dsc_cds_clk_div); 2761 } 2762 2763 static bool is_extend_pll(struct display_state *state, struct udevice **clk_dev) 2764 { 2765 struct crtc_state *cstate = &state->crtc_state; 2766 struct vop2 *vop2 = cstate->private; 2767 struct udevice *vp_dev, *dev; 2768 struct ofnode_phandle_args args; 2769 char vp_name[10]; 2770 int ret; 2771 2772 if (vop2->version != VOP_VERSION_RK3588) 2773 return false; 2774 2775 sprintf(vp_name, "port@%d", cstate->crtc_id); 2776 if (uclass_find_device_by_name(UCLASS_VIDEO_CRTC, vp_name, &vp_dev)) { 2777 debug("warn: can't get vp device\n"); 2778 return false; 2779 } 2780 2781 ret = dev_read_phandle_with_args(vp_dev, "assigned-clock-parents", "#clock-cells", 0, 2782 0, &args); 2783 if (ret) { 2784 debug("assigned-clock-parents's node not define\n"); 2785 return false; 2786 } 2787 2788 if (uclass_find_device_by_ofnode(UCLASS_CLK, args.node, &dev)) { 2789 debug("warn: can't get clk device\n"); 2790 return false; 2791 } 2792 2793 if (!strcmp(dev->name, "hdmiphypll_clk0") || !strcmp(dev->name, "hdmiphypll_clk1")) { 2794 printf("%s: clk dev :%s: vp port:%s\n", __func__, dev->name, vp_dev->name); 2795 if (clk_dev) 2796 *clk_dev = dev; 2797 return true; 2798 } 2799 2800 return false; 2801 } 2802 2803 static int rockchip_vop2_init(struct display_state *state) 2804 { 2805 struct crtc_state *cstate = &state->crtc_state; 2806 struct rockchip_vp *vp = &cstate->crtc->vps[cstate->crtc_id]; 2807 struct connector_state *conn_state = &state->conn_state; 2808 struct drm_display_mode *mode = &conn_state->mode; 2809 struct vop2 *vop2 = cstate->private; 2810 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 2811 u16 hdisplay = mode->crtc_hdisplay; 2812 u16 htotal = mode->crtc_htotal; 2813 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 2814 u16 hact_end = hact_st + hdisplay; 2815 u16 vdisplay = mode->crtc_vdisplay; 2816 u16 vtotal = mode->crtc_vtotal; 2817 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 2818 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 2819 u16 vact_end = vact_st + vdisplay; 2820 bool yuv_overlay = false; 2821 u32 vp_offset = (cstate->crtc_id * 0x100); 2822 u32 line_flag_offset = (cstate->crtc_id * 4); 2823 u32 val, act_end; 2824 u8 dither_down_en = 0; 2825 u8 pre_dither_down_en = 0; 2826 u8 dclk_div_factor = 0; 2827 char output_type_name[30] = {0}; 2828 char dclk_name[9]; 2829 struct clk dclk; 2830 struct clk hdmi0_phy_pll; 2831 struct clk hdmi1_phy_pll; 2832 struct clk hdmi_phy_pll; 2833 struct udevice *disp_dev; 2834 unsigned long dclk_rate; 2835 int ret; 2836 2837 printf("VOP update mode to: %dx%d%s%d, type:%s for VP%d\n", 2838 mode->crtc_hdisplay, mode->vdisplay, 2839 mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p", 2840 mode->vrefresh, 2841 get_output_if_name(conn_state->output_if, output_type_name), 2842 cstate->crtc_id); 2843 2844 if (mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) { 2845 cstate->splice_mode = true; 2846 cstate->splice_crtc_id = vop2->data->vp_data[cstate->crtc_id].splice_vp_id; 2847 if (!cstate->splice_crtc_id) { 2848 printf("%s: Splice mode is unsupported by vp%d\n", 2849 __func__, cstate->crtc_id); 2850 return -EINVAL; 2851 } 2852 2853 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, EN_MASK, 2854 PORT_MERGE_EN_SHIFT, 1, false); 2855 } 2856 2857 vop2_initial(vop2, state); 2858 if (vop2->version == VOP_VERSION_RK3588) 2859 dclk_rate = rk3588_vop2_if_cfg(state); 2860 else 2861 dclk_rate = rk3568_vop2_if_cfg(state); 2862 2863 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA && 2864 !(cstate->feature & VOP_FEATURE_OUTPUT_10BIT)) 2865 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 2866 2867 vop2_post_color_swap(state); 2868 2869 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, OUT_MODE_MASK, 2870 OUT_MODE_SHIFT, conn_state->output_mode, false); 2871 2872 switch (conn_state->bus_format) { 2873 case MEDIA_BUS_FMT_RGB565_1X16: 2874 dither_down_en = 1; 2875 break; 2876 case MEDIA_BUS_FMT_RGB666_1X18: 2877 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 2878 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 2879 case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA: 2880 dither_down_en = 1; 2881 break; 2882 case MEDIA_BUS_FMT_YUV8_1X24: 2883 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 2884 dither_down_en = 0; 2885 pre_dither_down_en = 1; 2886 break; 2887 case MEDIA_BUS_FMT_YUV10_1X30: 2888 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 2889 case MEDIA_BUS_FMT_RGB888_1X24: 2890 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 2891 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 2892 default: 2893 dither_down_en = 0; 2894 pre_dither_down_en = 0; 2895 break; 2896 } 2897 2898 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA) 2899 pre_dither_down_en = 0; 2900 else 2901 pre_dither_down_en = 1; 2902 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2903 DITHER_DOWN_EN_SHIFT, dither_down_en, false); 2904 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2905 PRE_DITHER_DOWN_EN_SHIFT, pre_dither_down_en, false); 2906 2907 yuv_overlay = is_yuv_output(conn_state->bus_format) ? 1 : 0; 2908 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, cstate->crtc_id, 2909 yuv_overlay, false); 2910 2911 cstate->yuv_overlay = yuv_overlay; 2912 2913 vop2_writel(vop2, RK3568_VP0_DSP_HTOTAL_HS_END + vp_offset, 2914 (htotal << 16) | hsync_len); 2915 val = hact_st << 16; 2916 val |= hact_end; 2917 vop2_writel(vop2, RK3568_VP0_DSP_HACT_ST_END + vp_offset, val); 2918 val = vact_st << 16; 2919 val |= vact_end; 2920 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END + vp_offset, val); 2921 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 2922 u16 vact_st_f1 = vtotal + vact_st + 1; 2923 u16 vact_end_f1 = vact_st_f1 + vdisplay; 2924 2925 val = vact_st_f1 << 16 | vact_end_f1; 2926 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END_F1 + vp_offset, 2927 val); 2928 2929 val = vtotal << 16 | (vtotal + vsync_len); 2930 vop2_writel(vop2, RK3568_VP0_DSP_VS_ST_END_F1 + vp_offset, val); 2931 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2932 INTERLACE_EN_SHIFT, 1, false); 2933 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2934 DSP_FILED_POL, 1, false); 2935 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2936 P2I_EN_SHIFT, 1, false); 2937 vtotal += vtotal + 1; 2938 act_end = vact_end_f1; 2939 } else { 2940 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2941 INTERLACE_EN_SHIFT, 0, false); 2942 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2943 P2I_EN_SHIFT, 0, false); 2944 act_end = vact_end; 2945 } 2946 vop2_writel(vop2, RK3568_VP0_DSP_VTOTAL_VS_END + vp_offset, 2947 (vtotal << 16) | vsync_len); 2948 2949 if (vop2->version == VOP_VERSION_RK3568) { 2950 if (mode->flags & DRM_MODE_FLAG_DBLCLK || 2951 conn_state->output_if & VOP_OUTPUT_IF_BT656) 2952 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2953 CORE_DCLK_DIV_EN_SHIFT, 1, false); 2954 else 2955 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2956 CORE_DCLK_DIV_EN_SHIFT, 0, false); 2957 } 2958 2959 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420) 2960 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2961 DCLK_DIV2_MASK, DCLK_DIV2_SHIFT, 0x3, false); 2962 else 2963 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2964 DCLK_DIV2_MASK, DCLK_DIV2_SHIFT, 0, false); 2965 2966 vop2_mask_write(vop2, RK3568_OVL_CTRL, OVL_MODE_SEL_MASK, 2967 OVL_MODE_SEL_SHIFT + cstate->crtc_id, yuv_overlay, false); 2968 2969 if (yuv_overlay) 2970 val = 0x20010200; 2971 else 2972 val = 0; 2973 vop2_writel(vop2, RK3568_VP0_DSP_BG + vp_offset, val); 2974 if (cstate->splice_mode) { 2975 vop2_mask_write(vop2, RK3568_OVL_CTRL, OVL_MODE_SEL_MASK, 2976 OVL_MODE_SEL_SHIFT + cstate->splice_crtc_id, 2977 yuv_overlay, false); 2978 vop2_writel(vop2, RK3568_VP0_DSP_BG + (cstate->splice_crtc_id * 0x100), val); 2979 } 2980 2981 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2982 POST_DSP_OUT_R2Y_SHIFT, yuv_overlay, false); 2983 2984 if (vp->xmirror_en) 2985 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2986 DSP_X_MIR_EN_SHIFT, 1, false); 2987 2988 vop2_tv_config_update(state, vop2); 2989 vop2_post_config(state, vop2); 2990 2991 if (cstate->dsc_enable) { 2992 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { 2993 vop2_dsc_enable(state, vop2, 0, dclk_rate); 2994 vop2_dsc_enable(state, vop2, 1, dclk_rate); 2995 } else { 2996 vop2_dsc_enable(state, vop2, cstate->dsc_id, dclk_rate); 2997 } 2998 } 2999 3000 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", cstate->crtc_id); 3001 ret = clk_get_by_name(cstate->dev, dclk_name, &dclk); 3002 if (ret) { 3003 printf("%s: Failed to get dclk ret=%d\n", __func__, ret); 3004 return ret; 3005 } 3006 3007 ret = uclass_get_device_by_name(UCLASS_VIDEO, "display-subsystem", &disp_dev); 3008 if (!ret) { 3009 ret = clk_get_by_name(disp_dev, "hdmi0_phy_pll", &hdmi0_phy_pll); 3010 if (ret) 3011 debug("%s: hdmi0_phy_pll may not define\n", __func__); 3012 ret = clk_get_by_name(disp_dev, "hdmi1_phy_pll", &hdmi1_phy_pll); 3013 if (ret) 3014 debug("%s: hdmi1_phy_pll may not define\n", __func__); 3015 } else { 3016 hdmi0_phy_pll.dev = NULL; 3017 hdmi1_phy_pll.dev = NULL; 3018 debug("%s: Faile to find display-subsystem node\n", __func__); 3019 } 3020 3021 if (mode->crtc_clock < VOP2_MAX_DCLK_RATE) { 3022 if (conn_state->output_if & VOP_OUTPUT_IF_HDMI0) 3023 vop2_clk_set_parent(&dclk, &hdmi0_phy_pll); 3024 else if (conn_state->output_if & VOP_OUTPUT_IF_HDMI1) 3025 vop2_clk_set_parent(&dclk, &hdmi1_phy_pll); 3026 3027 /* 3028 * uboot clk driver won't set dclk parent's rate when use 3029 * hdmi phypll as dclk source. 3030 * So set dclk rate is meaningless. Set hdmi phypll rate 3031 * directly. 3032 */ 3033 if ((conn_state->output_if & VOP_OUTPUT_IF_HDMI0) && hdmi0_phy_pll.dev) { 3034 ret = vop2_clk_set_rate(&hdmi0_phy_pll, dclk_rate * 1000); 3035 } else if ((conn_state->output_if & VOP_OUTPUT_IF_HDMI1) && hdmi1_phy_pll.dev) { 3036 ret = vop2_clk_set_rate(&hdmi1_phy_pll, dclk_rate * 1000); 3037 } else { 3038 if (is_extend_pll(state, &hdmi_phy_pll.dev)) 3039 ret = vop2_clk_set_rate(&hdmi_phy_pll, dclk_rate * 1000); 3040 else 3041 ret = vop2_clk_set_rate(&dclk, dclk_rate * 1000); 3042 } 3043 } else { 3044 if (is_extend_pll(state, &hdmi_phy_pll.dev)) 3045 ret = vop2_clk_set_rate(&hdmi_phy_pll, dclk_rate * 1000); 3046 else 3047 ret = vop2_clk_set_rate(&dclk, dclk_rate * 1000); 3048 } 3049 3050 if (IS_ERR_VALUE(ret)) { 3051 printf("%s: Failed to set vp%d dclk[%ld KHZ] ret=%d\n", 3052 __func__, cstate->crtc_id, dclk_rate, ret); 3053 return ret; 3054 } else { 3055 dclk_div_factor = mode->clock / dclk_rate; 3056 mode->crtc_clock = ret * dclk_div_factor / 1000; 3057 printf("VP%d set crtc_clock to %dKHz\n", cstate->crtc_id, mode->crtc_clock); 3058 } 3059 3060 vop2_mask_write(vop2, RK3568_SYS_CTRL_LINE_FLAG0 + line_flag_offset, LINE_FLAG_NUM_MASK, 3061 RK3568_DSP_LINE_FLAG_NUM0_SHIFT, act_end, false); 3062 vop2_mask_write(vop2, RK3568_SYS_CTRL_LINE_FLAG0 + line_flag_offset, LINE_FLAG_NUM_MASK, 3063 RK3568_DSP_LINE_FLAG_NUM1_SHIFT, act_end, false); 3064 3065 return 0; 3066 } 3067 3068 static void vop2_setup_scale(struct vop2 *vop2, struct vop2_win_data *win, 3069 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 3070 uint32_t dst_h) 3071 { 3072 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 3073 uint16_t hscl_filter_mode, vscl_filter_mode; 3074 uint8_t gt2 = 0, gt4 = 0; 3075 uint32_t xfac = 0, yfac = 0; 3076 uint16_t hsu_filter_mode = VOP2_SCALE_UP_BIC; 3077 uint16_t hsd_filter_mode = VOP2_SCALE_DOWN_BIL; 3078 uint16_t vsu_filter_mode = VOP2_SCALE_UP_BIL; 3079 uint16_t vsd_filter_mode = VOP2_SCALE_DOWN_BIL; 3080 u32 win_offset = win->reg_offset; 3081 3082 if (src_h >= (4 * dst_h)) 3083 gt4 = 1; 3084 else if (src_h >= (2 * dst_h)) 3085 gt2 = 1; 3086 3087 if (gt4) 3088 src_h >>= 2; 3089 else if (gt2) 3090 src_h >>= 1; 3091 3092 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 3093 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 3094 3095 if (yrgb_hor_scl_mode == SCALE_UP) 3096 hscl_filter_mode = hsu_filter_mode; 3097 else 3098 hscl_filter_mode = hsd_filter_mode; 3099 3100 if (yrgb_ver_scl_mode == SCALE_UP) 3101 vscl_filter_mode = vsu_filter_mode; 3102 else 3103 vscl_filter_mode = vsd_filter_mode; 3104 3105 /* 3106 * RK3568 VOP Esmart/Smart dsp_w should be even pixel 3107 * at scale down mode 3108 */ 3109 if ((yrgb_hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) { 3110 printf("win dst_w[%d] should align as 2 pixel\n", dst_w); 3111 dst_w += 1; 3112 } 3113 3114 xfac = vop2_scale_factor(yrgb_hor_scl_mode, hscl_filter_mode, src_w, dst_w); 3115 yfac = vop2_scale_factor(yrgb_ver_scl_mode, vscl_filter_mode, src_h, dst_h); 3116 3117 if (win->type == CLUSTER_LAYER) { 3118 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB + win_offset, 3119 yfac << 16 | xfac); 3120 3121 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, 3122 YRGB_GT2_MASK, CLUSTER_YRGB_GT2_SHIFT, gt2, false); 3123 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, 3124 YRGB_GT4_MASK, CLUSTER_YRGB_GT4_SHIFT, gt4, false); 3125 3126 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, 3127 YRGB_XSCL_MODE_MASK, CLUSTER_YRGB_XSCL_MODE_SHIFT, yrgb_hor_scl_mode, false); 3128 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, 3129 YRGB_YSCL_MODE_MASK, CLUSTER_YRGB_YSCL_MODE_SHIFT, yrgb_ver_scl_mode, false); 3130 3131 } else { 3132 vop2_writel(vop2, RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB + win_offset, 3133 yfac << 16 | xfac); 3134 3135 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, 3136 YRGB_GT2_MASK, YRGB_GT2_SHIFT, gt2, false); 3137 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, 3138 YRGB_GT4_MASK, YRGB_GT4_SHIFT, gt4, false); 3139 3140 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 3141 YRGB_XSCL_MODE_MASK, YRGB_XSCL_MODE_SHIFT, yrgb_hor_scl_mode, false); 3142 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 3143 YRGB_YSCL_MODE_MASK, YRGB_YSCL_MODE_SHIFT, yrgb_ver_scl_mode, false); 3144 3145 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 3146 YRGB_XSCL_FILTER_MODE_MASK, YRGB_XSCL_FILTER_MODE_SHIFT, 3147 hscl_filter_mode, false); 3148 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 3149 YRGB_YSCL_FILTER_MODE_MASK, YRGB_YSCL_FILTER_MODE_SHIFT, 3150 vscl_filter_mode, false); 3151 } 3152 } 3153 3154 static void vop2_axi_config(struct vop2 *vop2, struct vop2_win_data *win) 3155 { 3156 u32 win_offset = win->reg_offset; 3157 3158 if (win->type == CLUSTER_LAYER) { 3159 vop2_mask_write(vop2, RK3568_CLUSTER0_CTRL + win_offset, CLUSTER_AXI_ID_MASK, 3160 CLUSTER_AXI_ID_SHIFT, win->axi_id, false); 3161 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL2 + win_offset, CLUSTER_AXI_YRGB_ID_MASK, 3162 CLUSTER_AXI_YRGB_ID_SHIFT, win->axi_yrgb_id, false); 3163 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL2 + win_offset, CLUSTER_AXI_UV_ID_MASK, 3164 CLUSTER_AXI_UV_ID_SHIFT, win->axi_uv_id, false); 3165 } else { 3166 vop2_mask_write(vop2, RK3568_ESMART0_AXI_CTRL + win_offset, ESMART_AXI_ID_MASK, 3167 ESMART_AXI_ID_SHIFT, win->axi_id, false); 3168 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, ESMART_AXI_YRGB_ID_MASK, 3169 ESMART_AXI_YRGB_ID_SHIFT, win->axi_yrgb_id, false); 3170 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, ESMART_AXI_UV_ID_MASK, 3171 ESMART_AXI_UV_ID_SHIFT, win->axi_uv_id, false); 3172 } 3173 } 3174 3175 static void vop2_set_cluster_win(struct display_state *state, struct vop2_win_data *win) 3176 { 3177 struct crtc_state *cstate = &state->crtc_state; 3178 struct connector_state *conn_state = &state->conn_state; 3179 struct drm_display_mode *mode = &conn_state->mode; 3180 struct vop2 *vop2 = cstate->private; 3181 int src_w = cstate->src_rect.w; 3182 int src_h = cstate->src_rect.h; 3183 int crtc_x = cstate->crtc_rect.x; 3184 int crtc_y = cstate->crtc_rect.y; 3185 int crtc_w = cstate->crtc_rect.w; 3186 int crtc_h = cstate->crtc_rect.h; 3187 int xvir = cstate->xvir; 3188 int y_mirror = 0; 3189 int csc_mode; 3190 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 3191 /* offset of the right window in splice mode */ 3192 u32 splice_pixel_offset = 0; 3193 u32 splice_yrgb_offset = 0; 3194 u32 win_offset = win->reg_offset; 3195 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); 3196 3197 if (win->splice_mode_right) { 3198 src_w = cstate->right_src_rect.w; 3199 src_h = cstate->right_src_rect.h; 3200 crtc_x = cstate->right_crtc_rect.x; 3201 crtc_y = cstate->right_crtc_rect.y; 3202 crtc_w = cstate->right_crtc_rect.w; 3203 crtc_h = cstate->right_crtc_rect.h; 3204 splice_pixel_offset = cstate->right_src_rect.x - cstate->src_rect.x; 3205 splice_yrgb_offset = splice_pixel_offset * (state->logo.bpp >> 3); 3206 cfg_done = CFG_DONE_EN | BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); 3207 } 3208 3209 act_info = (src_h - 1) << 16; 3210 act_info |= (src_w - 1) & 0xffff; 3211 3212 dsp_info = (crtc_h - 1) << 16; 3213 dsp_info |= (crtc_w - 1) & 0xffff; 3214 3215 dsp_stx = crtc_x; 3216 dsp_sty = crtc_y; 3217 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 3218 3219 if (mode->flags & DRM_MODE_FLAG_YMIRROR) 3220 y_mirror = 1; 3221 else 3222 y_mirror = 0; 3223 3224 vop2_setup_scale(vop2, win, src_w, src_h, crtc_w, crtc_h); 3225 3226 if (vop2->version == VOP_VERSION_RK3588) 3227 vop2_axi_config(vop2, win); 3228 3229 if (y_mirror) 3230 printf("WARN: y mirror is unsupported by cluster window\n"); 3231 3232 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, 3233 WIN_FORMAT_MASK, WIN_FORMAT_SHIFT, cstate->format, 3234 false); 3235 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_VIR + win_offset, xvir); 3236 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_YRGB_MST + win_offset, 3237 cstate->dma_addr + splice_yrgb_offset); 3238 3239 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_ACT_INFO + win_offset, act_info); 3240 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_DSP_INFO + win_offset, dsp_info); 3241 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_DSP_ST + win_offset, dsp_st); 3242 3243 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, WIN_EN_SHIFT, 1, false); 3244 3245 csc_mode = vop2_convert_csc_mode(conn_state->color_space); 3246 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, 3247 CLUSTER_RGB2YUV_EN_SHIFT, 3248 is_yuv_output(conn_state->bus_format), false); 3249 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, CSC_MODE_MASK, 3250 CLUSTER_CSC_MODE_SHIFT, csc_mode, false); 3251 vop2_mask_write(vop2, RK3568_CLUSTER0_CTRL + win_offset, EN_MASK, CLUSTER_EN_SHIFT, 1, false); 3252 3253 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 3254 } 3255 3256 static void vop2_set_smart_win(struct display_state *state, struct vop2_win_data *win) 3257 { 3258 struct crtc_state *cstate = &state->crtc_state; 3259 struct connector_state *conn_state = &state->conn_state; 3260 struct drm_display_mode *mode = &conn_state->mode; 3261 struct vop2 *vop2 = cstate->private; 3262 int src_w = cstate->src_rect.w; 3263 int src_h = cstate->src_rect.h; 3264 int crtc_x = cstate->crtc_rect.x; 3265 int crtc_y = cstate->crtc_rect.y; 3266 int crtc_w = cstate->crtc_rect.w; 3267 int crtc_h = cstate->crtc_rect.h; 3268 int xvir = cstate->xvir; 3269 int y_mirror = 0; 3270 int csc_mode; 3271 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 3272 /* offset of the right window in splice mode */ 3273 u32 splice_pixel_offset = 0; 3274 u32 splice_yrgb_offset = 0; 3275 u32 win_offset = win->reg_offset; 3276 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); 3277 3278 if (win->splice_mode_right) { 3279 src_w = cstate->right_src_rect.w; 3280 src_h = cstate->right_src_rect.h; 3281 crtc_x = cstate->right_crtc_rect.x; 3282 crtc_y = cstate->right_crtc_rect.y; 3283 crtc_w = cstate->right_crtc_rect.w; 3284 crtc_h = cstate->right_crtc_rect.h; 3285 splice_pixel_offset = cstate->right_src_rect.x - cstate->src_rect.x; 3286 splice_yrgb_offset = splice_pixel_offset * (state->logo.bpp >> 3); 3287 cfg_done = CFG_DONE_EN | BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); 3288 } 3289 3290 /* 3291 * This is workaround solution for IC design: 3292 * esmart can't support scale down when actual_w % 16 == 1. 3293 */ 3294 if (src_w > crtc_w && (src_w & 0xf) == 1) { 3295 printf("WARN: vp%d unsupported act_w[%d] mode 16 = 1 when scale down\n", cstate->crtc_id, src_w); 3296 src_w -= 1; 3297 } 3298 3299 act_info = (src_h - 1) << 16; 3300 act_info |= (src_w - 1) & 0xffff; 3301 3302 dsp_info = (crtc_h - 1) << 16; 3303 dsp_info |= (crtc_w - 1) & 0xffff; 3304 3305 dsp_stx = crtc_x; 3306 dsp_sty = crtc_y; 3307 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 3308 3309 if (mode->flags & DRM_MODE_FLAG_YMIRROR) 3310 y_mirror = 1; 3311 else 3312 y_mirror = 0; 3313 3314 vop2_setup_scale(vop2, win, src_w, src_h, crtc_w, crtc_h); 3315 3316 if (vop2->version == VOP_VERSION_RK3588) 3317 vop2_axi_config(vop2, win); 3318 3319 if (y_mirror) 3320 cstate->dma_addr += (src_h - 1) * xvir * 4; 3321 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, EN_MASK, 3322 YMIRROR_EN_SHIFT, y_mirror, false); 3323 3324 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, 3325 WIN_FORMAT_MASK, WIN_FORMAT_SHIFT, cstate->format, 3326 false); 3327 vop2_writel(vop2, RK3568_ESMART0_REGION0_VIR + win_offset, xvir); 3328 vop2_writel(vop2, RK3568_ESMART0_REGION0_YRGB_MST + win_offset, 3329 cstate->dma_addr + splice_yrgb_offset); 3330 3331 vop2_writel(vop2, RK3568_ESMART0_REGION0_ACT_INFO + win_offset, 3332 act_info); 3333 vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_INFO + win_offset, 3334 dsp_info); 3335 vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_ST + win_offset, dsp_st); 3336 3337 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK, 3338 WIN_EN_SHIFT, 1, false); 3339 3340 csc_mode = vop2_convert_csc_mode(conn_state->color_space); 3341 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, EN_MASK, 3342 RGB2YUV_EN_SHIFT, 3343 is_yuv_output(conn_state->bus_format), false); 3344 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, CSC_MODE_MASK, 3345 CSC_MODE_SHIFT, csc_mode, false); 3346 3347 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 3348 } 3349 3350 static void vop2_calc_display_rect_for_splice(struct display_state *state) 3351 { 3352 struct crtc_state *cstate = &state->crtc_state; 3353 struct connector_state *conn_state = &state->conn_state; 3354 struct drm_display_mode *mode = &conn_state->mode; 3355 struct display_rect *src_rect = &cstate->src_rect; 3356 struct display_rect *dst_rect = &cstate->crtc_rect; 3357 struct display_rect left_src, left_dst, right_src, right_dst; 3358 u16 half_hdisplay = mode->crtc_hdisplay >> 1; 3359 int left_src_w, left_dst_w, right_dst_w; 3360 3361 left_dst_w = min_t(u16, half_hdisplay, dst_rect->x + dst_rect->w) - dst_rect->x; 3362 if (left_dst_w < 0) 3363 left_dst_w = 0; 3364 right_dst_w = dst_rect->w - left_dst_w; 3365 3366 if (!right_dst_w) 3367 left_src_w = src_rect->w; 3368 else 3369 left_src_w = src_rect->x + src_rect->w - src_rect->w / 2; 3370 3371 left_src.x = src_rect->x; 3372 left_src.w = left_src_w; 3373 left_dst.x = dst_rect->x; 3374 left_dst.w = left_dst_w; 3375 right_src.x = left_src.x + left_src.w; 3376 right_src.w = src_rect->x + src_rect->w - left_src.x - left_src.w; 3377 right_dst.x = dst_rect->x + left_dst_w - half_hdisplay; 3378 right_dst.w = right_dst_w; 3379 3380 left_src.y = src_rect->y; 3381 left_src.h = src_rect->h; 3382 left_dst.y = dst_rect->y; 3383 left_dst.h = dst_rect->h; 3384 right_src.y = src_rect->y; 3385 right_src.h = src_rect->h; 3386 right_dst.y = dst_rect->y; 3387 right_dst.h = dst_rect->h; 3388 3389 memcpy(&cstate->src_rect, &left_src, sizeof(struct display_rect)); 3390 memcpy(&cstate->crtc_rect, &left_dst, sizeof(struct display_rect)); 3391 memcpy(&cstate->right_src_rect, &right_src, sizeof(struct display_rect)); 3392 memcpy(&cstate->right_crtc_rect, &right_dst, sizeof(struct display_rect)); 3393 } 3394 3395 static int rockchip_vop2_set_plane(struct display_state *state) 3396 { 3397 struct crtc_state *cstate = &state->crtc_state; 3398 struct vop2 *vop2 = cstate->private; 3399 struct vop2_win_data *win_data; 3400 struct vop2_win_data *splice_win_data; 3401 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; 3402 char plane_name[10] = {0}; 3403 3404 if (cstate->crtc_rect.w > cstate->max_output.width) { 3405 printf("ERROR: output w[%d] exceeded max width[%d]\n", 3406 cstate->crtc_rect.w, cstate->max_output.width); 3407 return -EINVAL; 3408 } 3409 3410 win_data = vop2_find_win_by_phys_id(vop2, primary_plane_id); 3411 if (!win_data) { 3412 printf("invalid win id %d\n", primary_plane_id); 3413 return -ENODEV; 3414 } 3415 3416 if (vop2->version == VOP_VERSION_RK3588) { 3417 if (vop2_power_domain_on(vop2, win_data->pd_id)) 3418 printf("open vp%d plane pd fail\n", cstate->crtc_id); 3419 } 3420 3421 if (cstate->splice_mode) { 3422 if (win_data->splice_win_id) { 3423 splice_win_data = vop2_find_win_by_phys_id(vop2, win_data->splice_win_id); 3424 splice_win_data->splice_mode_right = true; 3425 3426 if (vop2_power_domain_on(vop2, splice_win_data->pd_id)) 3427 printf("splice mode: open vp%d plane pd fail\n", cstate->splice_crtc_id); 3428 3429 vop2_calc_display_rect_for_splice(state); 3430 if (win_data->type == CLUSTER_LAYER) 3431 vop2_set_cluster_win(state, splice_win_data); 3432 else 3433 vop2_set_smart_win(state, splice_win_data); 3434 } else { 3435 printf("ERROR: splice mode is unsupported by plane %s\n", 3436 get_plane_name(primary_plane_id, plane_name)); 3437 return -EINVAL; 3438 } 3439 } 3440 3441 if (win_data->type == CLUSTER_LAYER) 3442 vop2_set_cluster_win(state, win_data); 3443 else 3444 vop2_set_smart_win(state, win_data); 3445 3446 printf("VOP VP%d enable %s[%dx%d->%dx%d@%dx%d] fmt[%d] addr[0x%x]\n", 3447 cstate->crtc_id, get_plane_name(primary_plane_id, plane_name), 3448 cstate->src_rect.w, cstate->src_rect.h, cstate->crtc_rect.w, cstate->crtc_rect.h, 3449 cstate->crtc_rect.x, cstate->crtc_rect.y, cstate->format, 3450 cstate->dma_addr); 3451 3452 return 0; 3453 } 3454 3455 static int rockchip_vop2_prepare(struct display_state *state) 3456 { 3457 return 0; 3458 } 3459 3460 static void vop2_dsc_cfg_done(struct display_state *state) 3461 { 3462 struct connector_state *conn_state = &state->conn_state; 3463 struct crtc_state *cstate = &state->crtc_state; 3464 struct vop2 *vop2 = cstate->private; 3465 u8 dsc_id = cstate->dsc_id; 3466 u32 ctrl_regs_offset = (dsc_id * 0x30); 3467 3468 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { 3469 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE, EN_MASK, 3470 DSC_CFG_DONE_SHIFT, 1, false); 3471 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE + 0x30, EN_MASK, 3472 DSC_CFG_DONE_SHIFT, 1, false); 3473 } else { 3474 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE + ctrl_regs_offset, EN_MASK, 3475 DSC_CFG_DONE_SHIFT, 1, false); 3476 } 3477 } 3478 3479 static int rockchip_vop2_enable(struct display_state *state) 3480 { 3481 struct crtc_state *cstate = &state->crtc_state; 3482 struct vop2 *vop2 = cstate->private; 3483 u32 vp_offset = (cstate->crtc_id * 0x100); 3484 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); 3485 3486 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 3487 STANDBY_EN_SHIFT, 0, false); 3488 3489 if (cstate->splice_mode) 3490 cfg_done |= BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); 3491 3492 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 3493 3494 if (cstate->dsc_enable) 3495 vop2_dsc_cfg_done(state); 3496 3497 return 0; 3498 } 3499 3500 static int rockchip_vop2_disable(struct display_state *state) 3501 { 3502 struct crtc_state *cstate = &state->crtc_state; 3503 struct vop2 *vop2 = cstate->private; 3504 u32 vp_offset = (cstate->crtc_id * 0x100); 3505 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); 3506 3507 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 3508 STANDBY_EN_SHIFT, 1, false); 3509 3510 if (cstate->splice_mode) 3511 cfg_done |= BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); 3512 3513 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 3514 3515 return 0; 3516 } 3517 3518 static int rockchip_vop2_get_cursor_plane(struct display_state *state, u32 plane_mask, int cursor_plane) 3519 { 3520 struct crtc_state *cstate = &state->crtc_state; 3521 struct vop2 *vop2 = cstate->private; 3522 int i = 0; 3523 int correct_cursor_plane = -1; 3524 int plane_type = -1; 3525 3526 if (cursor_plane < 0) 3527 return -1; 3528 3529 if (plane_mask & (1 << cursor_plane)) 3530 return cursor_plane; 3531 3532 /* Get current cursor plane type */ 3533 for (i = 0; i < vop2->data->nr_layers; i++) { 3534 if (vop2->data->plane_table[i].plane_id == cursor_plane) { 3535 plane_type = vop2->data->plane_table[i].plane_type; 3536 break; 3537 } 3538 } 3539 3540 /* Get the other same plane type plane id */ 3541 for (i = 0; i < vop2->data->nr_layers; i++) { 3542 if (vop2->data->plane_table[i].plane_type == plane_type && 3543 vop2->data->plane_table[i].plane_id != cursor_plane) { 3544 correct_cursor_plane = vop2->data->plane_table[i].plane_id; 3545 break; 3546 } 3547 } 3548 3549 /* To check whether the new correct_cursor_plane is attach to current vp */ 3550 if (correct_cursor_plane < 0 || !(plane_mask & (1 << correct_cursor_plane))) { 3551 printf("error: faild to find correct plane as cursor plane\n"); 3552 return -1; 3553 } 3554 3555 printf("vp%d adjust cursor plane from %d to %d\n", 3556 cstate->crtc_id, cursor_plane, correct_cursor_plane); 3557 3558 return correct_cursor_plane; 3559 } 3560 3561 static int rockchip_vop2_fixup_dts(struct display_state *state, void *blob) 3562 { 3563 struct crtc_state *cstate = &state->crtc_state; 3564 struct vop2 *vop2 = cstate->private; 3565 ofnode vp_node; 3566 struct device_node *port_parent_node = cstate->ports_node; 3567 static bool vop_fix_dts; 3568 const char *path; 3569 u32 plane_mask = 0; 3570 int vp_id = 0; 3571 int cursor_plane_id = -1; 3572 3573 if (vop_fix_dts) 3574 return 0; 3575 3576 ofnode_for_each_subnode(vp_node, np_to_ofnode(port_parent_node)) { 3577 path = vp_node.np->full_name; 3578 plane_mask = vop2->vp_plane_mask[vp_id].plane_mask; 3579 3580 if (cstate->crtc->assign_plane) 3581 continue; 3582 cursor_plane_id = rockchip_vop2_get_cursor_plane(state, plane_mask, 3583 cstate->crtc->vps[vp_id].cursor_plane); 3584 printf("vp%d, plane_mask:0x%x, primary-id:%d, curser-id:%d\n", 3585 vp_id, plane_mask, 3586 vop2->vp_plane_mask[vp_id].primary_plane_id, 3587 cursor_plane_id); 3588 3589 do_fixup_by_path_u32(blob, path, "rockchip,plane-mask", 3590 plane_mask, 1); 3591 do_fixup_by_path_u32(blob, path, "rockchip,primary-plane", 3592 vop2->vp_plane_mask[vp_id].primary_plane_id, 1); 3593 if (cursor_plane_id >= 0) 3594 do_fixup_by_path_u32(blob, path, "cursor-win-id", 3595 cursor_plane_id, 1); 3596 vp_id++; 3597 } 3598 3599 vop_fix_dts = true; 3600 3601 return 0; 3602 } 3603 3604 static int rockchip_vop2_check(struct display_state *state) 3605 { 3606 struct crtc_state *cstate = &state->crtc_state; 3607 struct rockchip_crtc *crtc = cstate->crtc; 3608 3609 if (crtc->splice_mode && cstate->crtc_id == crtc->splice_crtc_id) { 3610 printf("WARN: VP%d is busy in splice mode\n", cstate->crtc_id); 3611 return -ENOTSUPP; 3612 } 3613 3614 if (cstate->splice_mode) { 3615 crtc->splice_mode = true; 3616 crtc->splice_crtc_id = cstate->splice_crtc_id; 3617 } 3618 3619 return 0; 3620 } 3621 3622 static int rockchip_vop2_mode_valid(struct display_state *state) 3623 { 3624 struct connector_state *conn_state = &state->conn_state; 3625 struct crtc_state *cstate = &state->crtc_state; 3626 struct drm_display_mode *mode = &conn_state->mode; 3627 struct videomode vm; 3628 3629 drm_display_mode_to_videomode(mode, &vm); 3630 3631 if (vm.hactive < 32 || vm.vactive < 32 || 3632 (vm.hfront_porch * vm.hsync_len * vm.hback_porch * 3633 vm.vfront_porch * vm.vsync_len * vm.vback_porch == 0)) { 3634 printf("ERROR: VP%d: unsupported display timing\n", cstate->crtc_id); 3635 return -EINVAL; 3636 } 3637 3638 return 0; 3639 } 3640 3641 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 3642 3643 static int rockchip_vop2_plane_check(struct display_state *state) 3644 { 3645 struct crtc_state *cstate = &state->crtc_state; 3646 struct vop2 *vop2 = cstate->private; 3647 struct display_rect *src = &cstate->src_rect; 3648 struct display_rect *dst = &cstate->crtc_rect; 3649 struct vop2_win_data *win_data; 3650 int min_scale, max_scale; 3651 int hscale, vscale; 3652 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; 3653 3654 win_data = vop2_find_win_by_phys_id(vop2, primary_plane_id); 3655 if (!win_data) { 3656 printf("ERROR: invalid win id %d\n", primary_plane_id); 3657 return -ENODEV; 3658 } 3659 3660 min_scale = FRAC_16_16(1, win_data->max_downscale_factor); 3661 max_scale = FRAC_16_16(win_data->max_upscale_factor, 1); 3662 3663 hscale = display_rect_calc_hscale(src, dst, min_scale, max_scale); 3664 vscale = display_rect_calc_vscale(src, dst, min_scale, max_scale); 3665 if (hscale < 0 || vscale < 0) { 3666 printf("ERROR: VP%d %s: scale factor is out of range\n", cstate->crtc_id, win_data->name); 3667 return -ERANGE; 3668 } 3669 3670 return 0; 3671 } 3672 static struct vop2_plane_table rk356x_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = { 3673 {ROCKCHIP_VOP2_CLUSTER0, CLUSTER_LAYER}, 3674 {ROCKCHIP_VOP2_CLUSTER1, CLUSTER_LAYER}, 3675 {ROCKCHIP_VOP2_ESMART0, ESMART_LAYER}, 3676 {ROCKCHIP_VOP2_ESMART1, ESMART_LAYER}, 3677 {ROCKCHIP_VOP2_SMART0, SMART_LAYER}, 3678 {ROCKCHIP_VOP2_SMART0, SMART_LAYER}, 3679 }; 3680 3681 static struct vop2_vp_plane_mask rk356x_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = { 3682 { /* one display policy */ 3683 {/* main display */ 3684 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 3685 .attached_layers_nr = 6, 3686 .attached_layers = { 3687 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0, 3688 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_SMART1 3689 }, 3690 }, 3691 {/* second display */}, 3692 {/* third display */}, 3693 {/* fourth display */}, 3694 }, 3695 3696 { /* two display policy */ 3697 {/* main display */ 3698 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 3699 .attached_layers_nr = 3, 3700 .attached_layers = { 3701 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0 3702 }, 3703 }, 3704 3705 {/* second display */ 3706 .primary_plane_id = ROCKCHIP_VOP2_SMART1, 3707 .attached_layers_nr = 3, 3708 .attached_layers = { 3709 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_SMART1 3710 }, 3711 }, 3712 {/* third display */}, 3713 {/* fourth display */}, 3714 }, 3715 3716 { /* three display policy */ 3717 {/* main display */ 3718 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 3719 .attached_layers_nr = 3, 3720 .attached_layers = { 3721 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0 3722 }, 3723 }, 3724 3725 {/* second display */ 3726 .primary_plane_id = ROCKCHIP_VOP2_SMART1, 3727 .attached_layers_nr = 2, 3728 .attached_layers = { 3729 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_SMART1 3730 }, 3731 }, 3732 3733 {/* third display */ 3734 .primary_plane_id = ROCKCHIP_VOP2_ESMART1, 3735 .attached_layers_nr = 1, 3736 .attached_layers = { ROCKCHIP_VOP2_ESMART1 }, 3737 }, 3738 3739 {/* fourth display */}, 3740 }, 3741 3742 {/* reserved for four display policy */}, 3743 }; 3744 3745 static struct vop2_win_data rk3568_win_data[6] = { 3746 { 3747 .name = "Cluster0", 3748 .phys_id = ROCKCHIP_VOP2_CLUSTER0, 3749 .type = CLUSTER_LAYER, 3750 .win_sel_port_offset = 0, 3751 .layer_sel_win_id = 0, 3752 .reg_offset = 0, 3753 .max_upscale_factor = 4, 3754 .max_downscale_factor = 4, 3755 }, 3756 3757 { 3758 .name = "Cluster1", 3759 .phys_id = ROCKCHIP_VOP2_CLUSTER1, 3760 .type = CLUSTER_LAYER, 3761 .win_sel_port_offset = 1, 3762 .layer_sel_win_id = 1, 3763 .reg_offset = 0x200, 3764 .max_upscale_factor = 4, 3765 .max_downscale_factor = 4, 3766 }, 3767 3768 { 3769 .name = "Esmart0", 3770 .phys_id = ROCKCHIP_VOP2_ESMART0, 3771 .type = ESMART_LAYER, 3772 .win_sel_port_offset = 4, 3773 .layer_sel_win_id = 2, 3774 .reg_offset = 0, 3775 .max_upscale_factor = 8, 3776 .max_downscale_factor = 8, 3777 }, 3778 3779 { 3780 .name = "Esmart1", 3781 .phys_id = ROCKCHIP_VOP2_ESMART1, 3782 .type = ESMART_LAYER, 3783 .win_sel_port_offset = 5, 3784 .layer_sel_win_id = 6, 3785 .reg_offset = 0x200, 3786 .max_upscale_factor = 8, 3787 .max_downscale_factor = 8, 3788 }, 3789 3790 { 3791 .name = "Smart0", 3792 .phys_id = ROCKCHIP_VOP2_SMART0, 3793 .type = SMART_LAYER, 3794 .win_sel_port_offset = 6, 3795 .layer_sel_win_id = 3, 3796 .reg_offset = 0x400, 3797 .max_upscale_factor = 8, 3798 .max_downscale_factor = 8, 3799 }, 3800 3801 { 3802 .name = "Smart1", 3803 .phys_id = ROCKCHIP_VOP2_SMART1, 3804 .type = SMART_LAYER, 3805 .win_sel_port_offset = 7, 3806 .layer_sel_win_id = 7, 3807 .reg_offset = 0x600, 3808 .max_upscale_factor = 8, 3809 .max_downscale_factor = 8, 3810 }, 3811 }; 3812 3813 static struct vop2_vp_data rk3568_vp_data[3] = { 3814 { 3815 .feature = VOP_FEATURE_OUTPUT_10BIT, 3816 .pre_scan_max_dly = 42, 3817 .max_output = {4096, 2304}, 3818 }, 3819 { 3820 .feature = 0, 3821 .pre_scan_max_dly = 40, 3822 .max_output = {2048, 1536}, 3823 }, 3824 { 3825 .feature = 0, 3826 .pre_scan_max_dly = 40, 3827 .max_output = {1920, 1080}, 3828 }, 3829 }; 3830 3831 const struct vop2_data rk3568_vop = { 3832 .version = VOP_VERSION_RK3568, 3833 .nr_vps = 3, 3834 .vp_data = rk3568_vp_data, 3835 .win_data = rk3568_win_data, 3836 .plane_mask = rk356x_vp_plane_mask[0], 3837 .plane_table = rk356x_plane_table, 3838 .nr_layers = 6, 3839 .nr_mixers = 5, 3840 .nr_gammas = 1, 3841 }; 3842 3843 static struct vop2_plane_table rk3588_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = { 3844 {ROCKCHIP_VOP2_CLUSTER0, CLUSTER_LAYER}, 3845 {ROCKCHIP_VOP2_CLUSTER1, CLUSTER_LAYER}, 3846 {ROCKCHIP_VOP2_CLUSTER2, CLUSTER_LAYER}, 3847 {ROCKCHIP_VOP2_CLUSTER3, CLUSTER_LAYER}, 3848 {ROCKCHIP_VOP2_ESMART0, ESMART_LAYER}, 3849 {ROCKCHIP_VOP2_ESMART1, ESMART_LAYER}, 3850 {ROCKCHIP_VOP2_ESMART2, ESMART_LAYER}, 3851 {ROCKCHIP_VOP2_ESMART3, ESMART_LAYER}, 3852 }; 3853 3854 static struct vop2_vp_plane_mask rk3588_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = { 3855 { /* one display policy */ 3856 {/* main display */ 3857 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0, 3858 .attached_layers_nr = 8, 3859 .attached_layers = { 3860 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART2, 3861 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_ESMART3, 3862 ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_CLUSTER3 3863 }, 3864 }, 3865 {/* second display */}, 3866 {/* third display */}, 3867 {/* fourth display */}, 3868 }, 3869 3870 { /* two display policy */ 3871 {/* main display */ 3872 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0, 3873 .attached_layers_nr = 4, 3874 .attached_layers = { 3875 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, 3876 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1 3877 }, 3878 }, 3879 3880 {/* second display */ 3881 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER2, 3882 .attached_layers_nr = 4, 3883 .attached_layers = { 3884 ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2, 3885 ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART3 3886 }, 3887 }, 3888 {/* third display */}, 3889 {/* fourth display */}, 3890 }, 3891 3892 { /* three display policy */ 3893 {/* main display */ 3894 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0, 3895 .attached_layers_nr = 3, 3896 .attached_layers = { 3897 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART0 3898 }, 3899 }, 3900 3901 {/* second display */ 3902 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER2, 3903 .attached_layers_nr = 3, 3904 .attached_layers = { 3905 ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART1 3906 }, 3907 }, 3908 3909 {/* third display */ 3910 .primary_plane_id = ROCKCHIP_VOP2_ESMART2, 3911 .attached_layers_nr = 2, 3912 .attached_layers = { ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3 }, 3913 }, 3914 3915 {/* fourth display */}, 3916 }, 3917 3918 { /* four display policy */ 3919 {/* main display */ 3920 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0, 3921 .attached_layers_nr = 2, 3922 .attached_layers = { ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0 }, 3923 }, 3924 3925 {/* second display */ 3926 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER1, 3927 .attached_layers_nr = 2, 3928 .attached_layers = { ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1 }, 3929 }, 3930 3931 {/* third display */ 3932 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER2, 3933 .attached_layers_nr = 2, 3934 .attached_layers = { ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2 }, 3935 }, 3936 3937 {/* fourth display */ 3938 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER3, 3939 .attached_layers_nr = 2, 3940 .attached_layers = { ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART3 }, 3941 }, 3942 }, 3943 3944 }; 3945 3946 static struct vop2_win_data rk3588_win_data[8] = { 3947 { 3948 .name = "Cluster0", 3949 .phys_id = ROCKCHIP_VOP2_CLUSTER0, 3950 .splice_win_id = ROCKCHIP_VOP2_CLUSTER1, 3951 .type = CLUSTER_LAYER, 3952 .win_sel_port_offset = 0, 3953 .layer_sel_win_id = 0, 3954 .reg_offset = 0, 3955 .axi_id = 0, 3956 .axi_yrgb_id = 2, 3957 .axi_uv_id = 3, 3958 .pd_id = VOP2_PD_CLUSTER0, 3959 .max_upscale_factor = 4, 3960 .max_downscale_factor = 4, 3961 }, 3962 3963 { 3964 .name = "Cluster1", 3965 .phys_id = ROCKCHIP_VOP2_CLUSTER1, 3966 .type = CLUSTER_LAYER, 3967 .win_sel_port_offset = 1, 3968 .layer_sel_win_id = 1, 3969 .reg_offset = 0x200, 3970 .axi_id = 0, 3971 .axi_yrgb_id = 6, 3972 .axi_uv_id = 7, 3973 .pd_id = VOP2_PD_CLUSTER1, 3974 .max_upscale_factor = 4, 3975 .max_downscale_factor = 4, 3976 }, 3977 3978 { 3979 .name = "Cluster2", 3980 .phys_id = ROCKCHIP_VOP2_CLUSTER2, 3981 .splice_win_id = ROCKCHIP_VOP2_CLUSTER3, 3982 .type = CLUSTER_LAYER, 3983 .win_sel_port_offset = 2, 3984 .layer_sel_win_id = 4, 3985 .reg_offset = 0x400, 3986 .axi_id = 1, 3987 .axi_yrgb_id = 2, 3988 .axi_uv_id = 3, 3989 .pd_id = VOP2_PD_CLUSTER2, 3990 .max_upscale_factor = 4, 3991 .max_downscale_factor = 4, 3992 }, 3993 3994 { 3995 .name = "Cluster3", 3996 .phys_id = ROCKCHIP_VOP2_CLUSTER3, 3997 .type = CLUSTER_LAYER, 3998 .win_sel_port_offset = 3, 3999 .layer_sel_win_id = 5, 4000 .reg_offset = 0x600, 4001 .axi_id = 1, 4002 .axi_yrgb_id = 6, 4003 .axi_uv_id = 7, 4004 .pd_id = VOP2_PD_CLUSTER3, 4005 .max_upscale_factor = 4, 4006 .max_downscale_factor = 4, 4007 }, 4008 4009 { 4010 .name = "Esmart0", 4011 .phys_id = ROCKCHIP_VOP2_ESMART0, 4012 .splice_win_id = ROCKCHIP_VOP2_ESMART1, 4013 .type = ESMART_LAYER, 4014 .win_sel_port_offset = 4, 4015 .layer_sel_win_id = 2, 4016 .reg_offset = 0, 4017 .axi_id = 0, 4018 .axi_yrgb_id = 0x0a, 4019 .axi_uv_id = 0x0b, 4020 .max_upscale_factor = 8, 4021 .max_downscale_factor = 8, 4022 }, 4023 4024 { 4025 .name = "Esmart1", 4026 .phys_id = ROCKCHIP_VOP2_ESMART1, 4027 .type = ESMART_LAYER, 4028 .win_sel_port_offset = 5, 4029 .layer_sel_win_id = 3, 4030 .reg_offset = 0x200, 4031 .axi_id = 0, 4032 .axi_yrgb_id = 0x0c, 4033 .axi_uv_id = 0x0d, 4034 .pd_id = VOP2_PD_ESMART, 4035 .max_upscale_factor = 8, 4036 .max_downscale_factor = 8, 4037 }, 4038 4039 { 4040 .name = "Esmart2", 4041 .phys_id = ROCKCHIP_VOP2_ESMART2, 4042 .splice_win_id = ROCKCHIP_VOP2_ESMART3, 4043 .type = ESMART_LAYER, 4044 .win_sel_port_offset = 6, 4045 .layer_sel_win_id = 6, 4046 .reg_offset = 0x400, 4047 .axi_id = 1, 4048 .axi_yrgb_id = 0x0a, 4049 .axi_uv_id = 0x0b, 4050 .pd_id = VOP2_PD_ESMART, 4051 .max_upscale_factor = 8, 4052 .max_downscale_factor = 8, 4053 }, 4054 4055 { 4056 .name = "Esmart3", 4057 .phys_id = ROCKCHIP_VOP2_ESMART3, 4058 .type = ESMART_LAYER, 4059 .win_sel_port_offset = 7, 4060 .layer_sel_win_id = 7, 4061 .reg_offset = 0x600, 4062 .axi_id = 1, 4063 .axi_yrgb_id = 0x0c, 4064 .axi_uv_id = 0x0d, 4065 .pd_id = VOP2_PD_ESMART, 4066 .max_upscale_factor = 8, 4067 .max_downscale_factor = 8, 4068 }, 4069 }; 4070 4071 static struct dsc_error_info dsc_ecw[] = { 4072 {0x00000000, "no error detected by DSC encoder"}, 4073 {0x0030ffff, "bits per component error"}, 4074 {0x0040ffff, "multiple mode error"}, 4075 {0x0050ffff, "line buffer depth error"}, 4076 {0x0060ffff, "minor version error"}, 4077 {0x0070ffff, "picture height error"}, 4078 {0x0080ffff, "picture width error"}, 4079 {0x0090ffff, "number of slices error"}, 4080 {0x00c0ffff, "slice height Error "}, 4081 {0x00d0ffff, "slice width error"}, 4082 {0x00e0ffff, "second line BPG offset error"}, 4083 {0x00f0ffff, "non second line BPG offset error"}, 4084 {0x0100ffff, "PPS ID error"}, 4085 {0x0110ffff, "bits per pixel (BPP) Error"}, 4086 {0x0120ffff, "buffer flow error"}, /* dsc_buffer_flow */ 4087 4088 {0x01510001, "slice 0 RC buffer model overflow error"}, 4089 {0x01510002, "slice 1 RC buffer model overflow error"}, 4090 {0x01510004, "slice 2 RC buffer model overflow error"}, 4091 {0x01510008, "slice 3 RC buffer model overflow error"}, 4092 {0x01510010, "slice 4 RC buffer model overflow error"}, 4093 {0x01510020, "slice 5 RC buffer model overflow error"}, 4094 {0x01510040, "slice 6 RC buffer model overflow error"}, 4095 {0x01510080, "slice 7 RC buffer model overflow error"}, 4096 4097 {0x01610001, "slice 0 RC buffer model underflow error"}, 4098 {0x01610002, "slice 1 RC buffer model underflow error"}, 4099 {0x01610004, "slice 2 RC buffer model underflow error"}, 4100 {0x01610008, "slice 3 RC buffer model underflow error"}, 4101 {0x01610010, "slice 4 RC buffer model underflow error"}, 4102 {0x01610020, "slice 5 RC buffer model underflow error"}, 4103 {0x01610040, "slice 6 RC buffer model underflow error"}, 4104 {0x01610080, "slice 7 RC buffer model underflow error"}, 4105 4106 {0xffffffff, "unsuccessful RESET cycle status"}, 4107 {0x00a0ffff, "ICH full error precision settings error"}, 4108 {0x0020ffff, "native mode"}, 4109 }; 4110 4111 static struct dsc_error_info dsc_buffer_flow[] = { 4112 {0x00000000, "rate buffer status"}, 4113 {0x00000001, "line buffer status"}, 4114 {0x00000002, "decoder model status"}, 4115 {0x00000003, "pixel buffer status"}, 4116 {0x00000004, "balance fifo buffer status"}, 4117 {0x00000005, "syntax element fifo status"}, 4118 }; 4119 4120 static struct vop2_dsc_data rk3588_dsc_data[] = { 4121 { 4122 .id = ROCKCHIP_VOP2_DSC_8K, 4123 .pd_id = VOP2_PD_DSC_8K, 4124 .max_slice_num = 8, 4125 .max_linebuf_depth = 11, 4126 .min_bits_per_pixel = 8, 4127 .dsc_txp_clk_src_name = "dsc_8k_txp_clk_src", 4128 .dsc_txp_clk_name = "dsc_8k_txp_clk", 4129 .dsc_pxl_clk_name = "dsc_8k_pxl_clk", 4130 .dsc_cds_clk_name = "dsc_8k_cds_clk", 4131 }, 4132 4133 { 4134 .id = ROCKCHIP_VOP2_DSC_4K, 4135 .pd_id = VOP2_PD_DSC_4K, 4136 .max_slice_num = 2, 4137 .max_linebuf_depth = 11, 4138 .min_bits_per_pixel = 8, 4139 .dsc_txp_clk_src_name = "dsc_4k_txp_clk_src", 4140 .dsc_txp_clk_name = "dsc_4k_txp_clk", 4141 .dsc_pxl_clk_name = "dsc_4k_pxl_clk", 4142 .dsc_cds_clk_name = "dsc_4k_cds_clk", 4143 }, 4144 }; 4145 4146 static struct vop2_vp_data rk3588_vp_data[4] = { 4147 { 4148 .splice_vp_id = 1, 4149 .feature = VOP_FEATURE_OUTPUT_10BIT, 4150 .pre_scan_max_dly = 54, 4151 .max_dclk = 600000, 4152 .max_output = {7680, 4320}, 4153 }, 4154 { 4155 .feature = VOP_FEATURE_OUTPUT_10BIT, 4156 .pre_scan_max_dly = 54, 4157 .max_dclk = 600000, 4158 .max_output = {4096, 2304}, 4159 }, 4160 { 4161 .feature = VOP_FEATURE_OUTPUT_10BIT, 4162 .pre_scan_max_dly = 52, 4163 .max_dclk = 600000, 4164 .max_output = {4096, 2304}, 4165 }, 4166 { 4167 .feature = 0, 4168 .pre_scan_max_dly = 52, 4169 .max_dclk = 200000, 4170 .max_output = {1920, 1080}, 4171 }, 4172 }; 4173 4174 static struct vop2_power_domain_data rk3588_vop_pd_data[] = { 4175 { 4176 .id = VOP2_PD_CLUSTER0, 4177 .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER0), 4178 }, 4179 { 4180 .id = VOP2_PD_CLUSTER1, 4181 .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER1), 4182 .parent_id = VOP2_PD_CLUSTER0, 4183 }, 4184 { 4185 .id = VOP2_PD_CLUSTER2, 4186 .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER2), 4187 .parent_id = VOP2_PD_CLUSTER0, 4188 }, 4189 { 4190 .id = VOP2_PD_CLUSTER3, 4191 .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER3), 4192 .parent_id = VOP2_PD_CLUSTER0, 4193 }, 4194 { 4195 .id = VOP2_PD_ESMART, 4196 .module_id_mask = BIT(ROCKCHIP_VOP2_ESMART1) | 4197 BIT(ROCKCHIP_VOP2_ESMART2) | 4198 BIT(ROCKCHIP_VOP2_ESMART3), 4199 }, 4200 { 4201 .id = VOP2_PD_DSC_8K, 4202 .module_id_mask = BIT(ROCKCHIP_VOP2_DSC_8K), 4203 }, 4204 { 4205 .id = VOP2_PD_DSC_4K, 4206 .module_id_mask = BIT(ROCKCHIP_VOP2_DSC_4K), 4207 }, 4208 }; 4209 4210 const struct vop2_data rk3588_vop = { 4211 .version = VOP_VERSION_RK3588, 4212 .nr_vps = 4, 4213 .vp_data = rk3588_vp_data, 4214 .win_data = rk3588_win_data, 4215 .plane_mask = rk3588_vp_plane_mask[0], 4216 .plane_table = rk3588_plane_table, 4217 .pd = rk3588_vop_pd_data, 4218 .dsc = rk3588_dsc_data, 4219 .dsc_error_ecw = dsc_ecw, 4220 .dsc_error_buffer_flow = dsc_buffer_flow, 4221 .nr_layers = 8, 4222 .nr_mixers = 7, 4223 .nr_gammas = 4, 4224 .nr_pd = ARRAY_SIZE(rk3588_vop_pd_data), 4225 .nr_dscs = 2, 4226 .nr_dsc_ecw = ARRAY_SIZE(dsc_ecw), 4227 .nr_dsc_buffer_flow = ARRAY_SIZE(dsc_buffer_flow), 4228 }; 4229 4230 const struct rockchip_crtc_funcs rockchip_vop2_funcs = { 4231 .preinit = rockchip_vop2_preinit, 4232 .prepare = rockchip_vop2_prepare, 4233 .init = rockchip_vop2_init, 4234 .set_plane = rockchip_vop2_set_plane, 4235 .enable = rockchip_vop2_enable, 4236 .disable = rockchip_vop2_disable, 4237 .fixup_dts = rockchip_vop2_fixup_dts, 4238 .check = rockchip_vop2_check, 4239 .mode_valid = rockchip_vop2_mode_valid, 4240 .plane_check = rockchip_vop2_plane_check, 4241 }; 4242