1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <asm/arch/cpu.h> 14 #include <asm/unaligned.h> 15 #include <asm/io.h> 16 #include <linux/list.h> 17 #include <linux/media-bus-format.h> 18 #include <clk.h> 19 #include <asm/arch/clock.h> 20 #include <linux/err.h> 21 #include <linux/ioport.h> 22 #include <dm/device.h> 23 #include <dm/read.h> 24 #include <fixp-arith.h> 25 #include <syscon.h> 26 27 #include "rockchip_display.h" 28 #include "rockchip_crtc.h" 29 #include "rockchip_connector.h" 30 31 /* System registers definition */ 32 #define RK3568_REG_CFG_DONE 0x000 33 #define CFG_DONE_EN BIT(15) 34 35 #define RK3568_VERSION_INFO 0x004 36 #define EN_MASK 1 37 38 #define RK3568_AUTO_GATING_CTRL 0x008 39 40 #define RK3568_SYS_AXI_LUT_CTRL 0x024 41 #define LUT_DMA_EN_SHIFT 0 42 43 #define RK3568_DSP_IF_EN 0x028 44 #define RGB_EN_SHIFT 0 45 #define HDMI0_EN_SHIFT 1 46 #define EDP0_EN_SHIFT 3 47 #define MIPI0_EN_SHIFT 4 48 #define MIPI1_EN_SHIFT 20 49 #define LVDS0_EN_SHIFT 5 50 #define LVDS1_EN_SHIFT 24 51 #define BT1120_EN_SHIFT 6 52 #define BT656_EN_SHIFT 7 53 #define IF_MUX_MASK 3 54 #define RGB_MUX_SHIFT 8 55 #define HDMI0_MUX_SHIFT 10 56 #define EDP0_MUX_SHIFT 14 57 #define MIPI0_MUX_SHIFT 16 58 #define MIPI1_MUX_SHIFT 21 59 #define LVDS0_MUX_SHIFT 18 60 #define LVDS1_MUX_SHIFT 25 61 62 #define RK3568_DSP_IF_CTRL 0x02c 63 #define LVDS_DUAL_EN_SHIFT 0 64 #define LVDS_DUAL_LEFT_RIGHT_EN_SHIFT 1 65 #define LVDS_DUAL_SWAP_EN_SHIFT 2 66 #define RK3568_DSP_IF_POL 0x030 67 #define IF_CTRL_REG_DONE_IMD_MASK 1 68 #define IF_CTRL_REG_DONE_IMD_SHIFT 28 69 #define IF_CRTL_MIPI_DCLK_POL_SHIT 19 70 #define IF_CRTL_EDP_DCLK_POL_SHIT 15 71 #define IF_CRTL_HDMI_DCLK_POL_SHIT 7 72 #define IF_CRTL_HDMI_PIN_POL_MASK 0x7 73 #define IF_CRTL_HDMI_PIN_POL_SHIT 4 74 #define IF_CRTL_RGB_LVDS_DCLK_POL_SHIT 3 75 #define RK3568_SYS_OTP_WIN_EN 0x50 76 #define OTP_WIN_EN_SHIFT 0 77 #define RK3568_SYS_LUT_PORT_SEL 0x58 78 #define GAMMA_PORT_SEL_MASK 0x3 79 #define GAMMA_PORT_SEL_SHIFT 0 80 81 #define RK3568_VP0_LINE_FLAG 0x70 82 #define RK3568_VP1_LINE_FLAG 0x74 83 #define RK3568_VP2_LINE_FLAG 0x78 84 #define RK3568_SYS0_INT_EN 0x80 85 #define RK3568_SYS0_INT_CLR 0x84 86 #define RK3568_SYS0_INT_STATUS 0x88 87 #define RK3568_SYS1_INT_EN 0x90 88 #define RK3568_SYS1_INT_CLR 0x94 89 #define RK3568_SYS1_INT_STATUS 0x98 90 #define RK3568_VP0_INT_EN 0xA0 91 #define RK3568_VP0_INT_CLR 0xA4 92 #define RK3568_VP0_INT_STATUS 0xA8 93 #define RK3568_VP1_INT_EN 0xB0 94 #define RK3568_VP1_INT_CLR 0xB4 95 #define RK3568_VP1_INT_STATUS 0xB8 96 #define RK3568_VP2_INT_EN 0xC0 97 #define RK3568_VP2_INT_CLR 0xC4 98 #define RK3568_VP2_INT_STATUS 0xC8 99 100 /* Overlay registers definition */ 101 #define RK3568_OVL_CTRL 0x600 102 #define OVL_PORT_MUX_REG_DONE_IMD_SHIFT 28 103 #define RK3568_OVL_LAYER_SEL 0x604 104 #define LAYER_SEL_MASK 0xf 105 106 #define RK3568_OVL_PORT_SEL 0x608 107 #define PORT_MUX_MASK 0xf 108 #define PORT_MUX_SHIFT 0 109 #define LAYER_SEL_PORT_MASK 0x3 110 #define LAYER_SEL_PORT_SHIFT 16 111 112 #define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610 113 #define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614 114 #define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618 115 #define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C 116 #define RK3568_MIX0_SRC_COLOR_CTRL 0x650 117 #define RK3568_MIX0_DST_COLOR_CTRL 0x654 118 #define RK3568_MIX0_SRC_ALPHA_CTRL 0x658 119 #define RK3568_MIX0_DST_ALPHA_CTRL 0x65C 120 #define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0 121 #define RK3568_HDR0_DST_COLOR_CTRL 0x6C4 122 #define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8 123 #define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC 124 #define RK3568_VP0_BG_MIX_CTRL 0x6E0 125 #define BG_MIX_CTRL_MASK 0xff 126 #define BG_MIX_CTRL_SHIFT 24 127 #define RK3568_VP1_BG_MIX_CTRL 0x6E4 128 #define RK3568_VP2_BG_MIX_CTRL 0x6E8 129 #define RK3568_CLUSTER_DLY_NUM 0x6F0 130 #define RK3568_SMART_DLY_NUM 0x6F8 131 132 /* Video Port registers definition */ 133 #define RK3568_VP0_DSP_CTRL 0xC00 134 #define OUT_MODE_MASK 0xf 135 #define OUT_MODE_SHIFT 0 136 #define DATA_SWAP_MASK 0x1f 137 #define DATA_SWAP_SHIFT 8 138 #define DSP_RB_SWAP 2 139 #define CORE_DCLK_DIV_EN_SHIFT 4 140 #define P2I_EN_SHIFT 5 141 #define DSP_FILED_POL 6 142 #define INTERLACE_EN_SHIFT 7 143 #define POST_DSP_OUT_R2Y_SHIFT 15 144 #define PRE_DITHER_DOWN_EN_SHIFT 16 145 #define DITHER_DOWN_EN_SHIFT 17 146 #define DSP_LUT_EN_SHIFT 28 147 148 #define STANDBY_EN_SHIFT 31 149 150 #define RK3568_VP0_MIPI_CTRL 0xC04 151 #define DCLK_DIV2_SHIFT 4 152 #define DCLK_DIV2_MASK 0x3 153 #define MIPI_DUAL_EN_SHIFT 20 154 #define MIPI_DUAL_SWAP_EN_SHIFT 21 155 156 #define RK3568_VP0_COLOR_BAR_CTRL 0xC08 157 #define RK3568_VP0_3D_LUT_CTRL 0xC10 158 #define VP0_3D_LUT_EN_SHIFT 0 159 #define VP0_3D_LUT_UPDATE_SHIFT 2 160 161 #define RK3568_VP0_3D_LUT_MST 0xC20 162 163 #define RK3568_VP0_DSP_BG 0xC2C 164 #define RK3568_VP0_PRE_SCAN_HTIMING 0xC30 165 #define RK3568_VP0_POST_DSP_HACT_INFO 0xC34 166 #define RK3568_VP0_POST_DSP_VACT_INFO 0xC38 167 #define RK3568_VP0_POST_SCL_FACTOR_YRGB 0xC3C 168 #define RK3568_VP0_POST_SCL_CTRL 0xC40 169 #define RK3568_VP0_POST_DSP_VACT_INFO_F1 0xC44 170 #define RK3568_VP0_DSP_HTOTAL_HS_END 0xC48 171 #define RK3568_VP0_DSP_HACT_ST_END 0xC4C 172 #define RK3568_VP0_DSP_VTOTAL_VS_END 0xC50 173 #define RK3568_VP0_DSP_VACT_ST_END 0xC54 174 #define RK3568_VP0_DSP_VS_ST_END_F1 0xC58 175 #define RK3568_VP0_DSP_VACT_ST_END_F1 0xC5C 176 177 #define RK3568_VP0_BCSH_CTRL 0xC60 178 #define BCSH_CTRL_Y2R_SHIFT 0 179 #define BCSH_CTRL_Y2R_MASK 0x1 180 #define BCSH_CTRL_Y2R_CSC_MODE_SHIFT 2 181 #define BCSH_CTRL_Y2R_CSC_MODE_MASK 0x3 182 #define BCSH_CTRL_R2Y_SHIFT 4 183 #define BCSH_CTRL_R2Y_MASK 0x1 184 #define BCSH_CTRL_R2Y_CSC_MODE_SHIFT 6 185 #define BCSH_CTRL_R2Y_CSC_MODE_MASK 0x3 186 187 #define RK3568_VP0_BCSH_BCS 0xC64 188 #define BCSH_BRIGHTNESS_SHIFT 0 189 #define BCSH_BRIGHTNESS_MASK 0xFF 190 #define BCSH_CONTRAST_SHIFT 8 191 #define BCSH_CONTRAST_MASK 0x1FF 192 #define BCSH_SATURATION_SHIFT 20 193 #define BCSH_SATURATION_MASK 0x3FF 194 #define BCSH_OUT_MODE_SHIFT 30 195 #define BCSH_OUT_MODE_MASK 0x3 196 197 #define RK3568_VP0_BCSH_H 0xC68 198 #define BCSH_SIN_HUE_SHIFT 0 199 #define BCSH_SIN_HUE_MASK 0x1FF 200 #define BCSH_COS_HUE_SHIFT 16 201 #define BCSH_COS_HUE_MASK 0x1FF 202 203 #define RK3568_VP0_BCSH_COLOR 0xC6C 204 #define BCSH_EN_SHIFT 31 205 #define BCSH_EN_MASK 1 206 207 #define RK3568_VP1_DSP_CTRL 0xD00 208 #define RK3568_VP1_MIPI_CTRL 0xD04 209 #define RK3568_VP1_COLOR_BAR_CTRL 0xD08 210 #define RK3568_VP1_PRE_SCAN_HTIMING 0xD30 211 #define RK3568_VP1_POST_DSP_HACT_INFO 0xD34 212 #define RK3568_VP1_POST_DSP_VACT_INFO 0xD38 213 #define RK3568_VP1_POST_SCL_FACTOR_YRGB 0xD3C 214 #define RK3568_VP1_POST_SCL_CTRL 0xD40 215 #define RK3568_VP1_DSP_HACT_INFO 0xD34 216 #define RK3568_VP1_DSP_VACT_INFO 0xD38 217 #define RK3568_VP1_POST_DSP_VACT_INFO_F1 0xD44 218 #define RK3568_VP1_DSP_HTOTAL_HS_END 0xD48 219 #define RK3568_VP1_DSP_HACT_ST_END 0xD4C 220 #define RK3568_VP1_DSP_VTOTAL_VS_END 0xD50 221 #define RK3568_VP1_DSP_VACT_ST_END 0xD54 222 #define RK3568_VP1_DSP_VS_ST_END_F1 0xD58 223 #define RK3568_VP1_DSP_VACT_ST_END_F1 0xD5C 224 225 #define RK3568_VP2_DSP_CTRL 0xE00 226 #define RK3568_VP2_MIPI_CTRL 0xE04 227 #define RK3568_VP2_COLOR_BAR_CTRL 0xE08 228 #define RK3568_VP2_PRE_SCAN_HTIMING 0xE30 229 #define RK3568_VP2_POST_DSP_HACT_INFO 0xE34 230 #define RK3568_VP2_POST_DSP_VACT_INFO 0xE38 231 #define RK3568_VP2_POST_SCL_FACTOR_YRGB 0xE3C 232 #define RK3568_VP2_POST_SCL_CTRL 0xE40 233 #define RK3568_VP2_DSP_HACT_INFO 0xE34 234 #define RK3568_VP2_DSP_VACT_INFO 0xE38 235 #define RK3568_VP2_POST_DSP_VACT_INFO_F1 0xE44 236 #define RK3568_VP2_DSP_HTOTAL_HS_END 0xE48 237 #define RK3568_VP2_DSP_HACT_ST_END 0xE4C 238 #define RK3568_VP2_DSP_VTOTAL_VS_END 0xE50 239 #define RK3568_VP2_DSP_VACT_ST_END 0xE54 240 #define RK3568_VP2_DSP_VS_ST_END_F1 0xE58 241 #define RK3568_VP2_DSP_VACT_ST_END_F1 0xE5C 242 243 /* Cluster0 register definition */ 244 #define RK3568_CLUSTER0_WIN0_CTRL0 0x1000 245 #define RK3568_CLUSTER0_WIN0_CTRL1 0x1004 246 #define RK3568_CLUSTER0_WIN0_YRGB_MST 0x1010 247 #define RK3568_CLUSTER0_WIN0_CBR_MST 0x1014 248 #define RK3568_CLUSTER0_WIN0_VIR 0x1018 249 #define RK3568_CLUSTER0_WIN0_ACT_INFO 0x1020 250 #define RK3568_CLUSTER0_WIN0_DSP_INFO 0x1024 251 #define RK3568_CLUSTER0_WIN0_DSP_ST 0x1028 252 #define RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB 0x1030 253 #define RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE 0x1054 254 #define RK3568_CLUSTER0_WIN0_AFBCD_HDR_PTR 0x1058 255 #define RK3568_CLUSTER0_WIN0_AFBCD_VIR_WIDTH 0x105C 256 #define RK3568_CLUSTER0_WIN0_AFBCD_PIC_SIZE 0x1060 257 #define RK3568_CLUSTER0_WIN0_AFBCD_PIC_OFFSET 0x1064 258 #define RK3568_CLUSTER0_WIN0_AFBCD_DSP_OFFSET 0x1068 259 #define RK3568_CLUSTER0_WIN0_AFBCD_CTRL 0x106C 260 261 #define RK3568_CLUSTER0_WIN1_CTRL0 0x1080 262 #define RK3568_CLUSTER0_WIN1_CTRL1 0x1084 263 #define RK3568_CLUSTER0_WIN1_YRGB_MST 0x1090 264 #define RK3568_CLUSTER0_WIN1_CBR_MST 0x1094 265 #define RK3568_CLUSTER0_WIN1_VIR 0x1098 266 #define RK3568_CLUSTER0_WIN1_ACT_INFO 0x10A0 267 #define RK3568_CLUSTER0_WIN1_DSP_INFO 0x10A4 268 #define RK3568_CLUSTER0_WIN1_DSP_ST 0x10A8 269 #define RK3568_CLUSTER0_WIN1_SCL_FACTOR_YRGB 0x10B0 270 #define RK3568_CLUSTER0_WIN1_AFBCD_ROTATE_MODE 0x10D4 271 #define RK3568_CLUSTER0_WIN1_AFBCD_HDR_PTR 0x10D8 272 #define RK3568_CLUSTER0_WIN1_AFBCD_VIR_WIDTH 0x10DC 273 #define RK3568_CLUSTER0_WIN1_AFBCD_PIC_SIZE 0x10E0 274 #define RK3568_CLUSTER0_WIN1_AFBCD_PIC_OFFSET 0x10E4 275 #define RK3568_CLUSTER0_WIN1_AFBCD_DSP_OFFSET 0x10E8 276 #define RK3568_CLUSTER0_WIN1_AFBCD_CTRL 0x10EC 277 278 #define RK3568_CLUSTER0_CTRL 0x1100 279 280 #define RK3568_CLUSTER1_WIN0_CTRL0 0x1200 281 #define RK3568_CLUSTER1_WIN0_CTRL1 0x1204 282 #define RK3568_CLUSTER1_WIN0_YRGB_MST 0x1210 283 #define RK3568_CLUSTER1_WIN0_CBR_MST 0x1214 284 #define RK3568_CLUSTER1_WIN0_VIR 0x1218 285 #define RK3568_CLUSTER1_WIN0_ACT_INFO 0x1220 286 #define RK3568_CLUSTER1_WIN0_DSP_INFO 0x1224 287 #define RK3568_CLUSTER1_WIN0_DSP_ST 0x1228 288 #define RK3568_CLUSTER1_WIN0_SCL_FACTOR_YRGB 0x1230 289 #define RK3568_CLUSTER1_WIN0_AFBCD_ROTATE_MODE 0x1254 290 #define RK3568_CLUSTER1_WIN0_AFBCD_HDR_PTR 0x1258 291 #define RK3568_CLUSTER1_WIN0_AFBCD_VIR_WIDTH 0x125C 292 #define RK3568_CLUSTER1_WIN0_AFBCD_PIC_SIZE 0x1260 293 #define RK3568_CLUSTER1_WIN0_AFBCD_PIC_OFFSET 0x1264 294 #define RK3568_CLUSTER1_WIN0_AFBCD_DSP_OFFSET 0x1268 295 #define RK3568_CLUSTER1_WIN0_AFBCD_CTRL 0x126C 296 297 #define RK3568_CLUSTER1_WIN1_CTRL0 0x1280 298 #define RK3568_CLUSTER1_WIN1_CTRL1 0x1284 299 #define RK3568_CLUSTER1_WIN1_YRGB_MST 0x1290 300 #define RK3568_CLUSTER1_WIN1_CBR_MST 0x1294 301 #define RK3568_CLUSTER1_WIN1_VIR 0x1298 302 #define RK3568_CLUSTER1_WIN1_ACT_INFO 0x12A0 303 #define RK3568_CLUSTER1_WIN1_DSP_INFO 0x12A4 304 #define RK3568_CLUSTER1_WIN1_DSP_ST 0x12A8 305 #define RK3568_CLUSTER1_WIN1_SCL_FACTOR_YRGB 0x12B0 306 #define RK3568_CLUSTER1_WIN1_AFBCD_ROTATE_MODE 0x12D4 307 #define RK3568_CLUSTER1_WIN1_AFBCD_HDR_PTR 0x12D8 308 #define RK3568_CLUSTER1_WIN1_AFBCD_VIR_WIDTH 0x12DC 309 #define RK3568_CLUSTER1_WIN1_AFBCD_PIC_SIZE 0x12E0 310 #define RK3568_CLUSTER1_WIN1_AFBCD_PIC_OFFSET 0x12E4 311 #define RK3568_CLUSTER1_WIN1_AFBCD_DSP_OFFSET 0x12E8 312 #define RK3568_CLUSTER1_WIN1_AFBCD_CTRL 0x12EC 313 314 #define RK3568_CLUSTER1_CTRL 0x1300 315 316 /* Esmart register definition */ 317 #define RK3568_ESMART0_CTRL0 0x1800 318 #define RGB2YUV_EN_SHIFT 1 319 #define CSC_MODE_SHIFT 2 320 #define CSC_MODE_MASK 0x3 321 322 #define RK3568_ESMART0_CTRL1 0x1804 323 #define YMIRROR_EN_SHIFT 31 324 #define RK3568_ESMART0_REGION0_CTRL 0x1810 325 #define REGION0_RB_SWAP_SHIFT 14 326 #define WIN_EN_SHIFT 0 327 #define WIN_FORMAT_MASK 0x1f 328 #define WIN_FORMAT_SHIFT 1 329 330 #define RK3568_ESMART0_REGION0_YRGB_MST 0x1814 331 #define RK3568_ESMART0_REGION0_CBR_MST 0x1818 332 #define RK3568_ESMART0_REGION0_VIR 0x181C 333 #define RK3568_ESMART0_REGION0_ACT_INFO 0x1820 334 #define RK3568_ESMART0_REGION0_DSP_INFO 0x1824 335 #define RK3568_ESMART0_REGION0_DSP_ST 0x1828 336 #define RK3568_ESMART0_REGION0_SCL_CTRL 0x1830 337 #define YRGB_XSCL_MODE_MASK 0x3 338 #define YRGB_XSCL_MODE_SHIFT 0 339 #define YRGB_XSCL_FILTER_MODE_MASK 0x3 340 #define YRGB_XSCL_FILTER_MODE_SHIFT 2 341 #define YRGB_YSCL_MODE_MASK 0x3 342 #define YRGB_YSCL_MODE_SHIFT 4 343 #define YRGB_YSCL_FILTER_MODE_MASK 0x3 344 #define YRGB_YSCL_FILTER_MODE_SHIFT 6 345 346 #define RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB 0x1834 347 #define RK3568_ESMART0_REGION0_SCL_FACTOR_CBR 0x1838 348 #define RK3568_ESMART0_REGION0_SCL_OFFSET 0x183C 349 #define RK3568_ESMART0_REGION1_CTRL 0x1840 350 #define YRGB_GT2_MASK 0x1 351 #define YRGB_GT2_SHIFT 8 352 #define YRGB_GT4_MASK 0x1 353 #define YRGB_GT4_SHIFT 9 354 355 #define RK3568_ESMART0_REGION1_YRGB_MST 0x1844 356 #define RK3568_ESMART0_REGION1_CBR_MST 0x1848 357 #define RK3568_ESMART0_REGION1_VIR 0x184C 358 #define RK3568_ESMART0_REGION1_ACT_INFO 0x1850 359 #define RK3568_ESMART0_REGION1_DSP_INFO 0x1854 360 #define RK3568_ESMART0_REGION1_DSP_ST 0x1858 361 #define RK3568_ESMART0_REGION1_SCL_CTRL 0x1860 362 #define RK3568_ESMART0_REGION1_SCL_FACTOR_YRGB 0x1864 363 #define RK3568_ESMART0_REGION1_SCL_FACTOR_CBR 0x1868 364 #define RK3568_ESMART0_REGION1_SCL_OFFSET 0x186C 365 #define RK3568_ESMART0_REGION2_CTRL 0x1870 366 #define RK3568_ESMART0_REGION2_YRGB_MST 0x1874 367 #define RK3568_ESMART0_REGION2_CBR_MST 0x1878 368 #define RK3568_ESMART0_REGION2_VIR 0x187C 369 #define RK3568_ESMART0_REGION2_ACT_INFO 0x1880 370 #define RK3568_ESMART0_REGION2_DSP_INFO 0x1884 371 #define RK3568_ESMART0_REGION2_DSP_ST 0x1888 372 #define RK3568_ESMART0_REGION2_SCL_CTRL 0x1890 373 #define RK3568_ESMART0_REGION2_SCL_FACTOR_YRGB 0x1894 374 #define RK3568_ESMART0_REGION2_SCL_FACTOR_CBR 0x1898 375 #define RK3568_ESMART0_REGION2_SCL_OFFSET 0x189C 376 #define RK3568_ESMART0_REGION3_CTRL 0x18A0 377 #define RK3568_ESMART0_REGION3_YRGB_MST 0x18A4 378 #define RK3568_ESMART0_REGION3_CBR_MST 0x18A8 379 #define RK3568_ESMART0_REGION3_VIR 0x18AC 380 #define RK3568_ESMART0_REGION3_ACT_INFO 0x18B0 381 #define RK3568_ESMART0_REGION3_DSP_INFO 0x18B4 382 #define RK3568_ESMART0_REGION3_DSP_ST 0x18B8 383 #define RK3568_ESMART0_REGION3_SCL_CTRL 0x18C0 384 #define RK3568_ESMART0_REGION3_SCL_FACTOR_YRGB 0x18C4 385 #define RK3568_ESMART0_REGION3_SCL_FACTOR_CBR 0x18C8 386 #define RK3568_ESMART0_REGION3_SCL_OFFSET 0x18CC 387 388 #define RK3568_ESMART1_CTRL0 0x1A00 389 #define RK3568_ESMART1_CTRL1 0x1A04 390 #define RK3568_ESMART1_REGION0_CTRL 0x1A10 391 #define RK3568_ESMART1_REGION0_YRGB_MST 0x1A14 392 #define RK3568_ESMART1_REGION0_CBR_MST 0x1A18 393 #define RK3568_ESMART1_REGION0_VIR 0x1A1C 394 #define RK3568_ESMART1_REGION0_ACT_INFO 0x1A20 395 #define RK3568_ESMART1_REGION0_DSP_INFO 0x1A24 396 #define RK3568_ESMART1_REGION0_DSP_ST 0x1A28 397 #define RK3568_ESMART1_REGION0_SCL_CTRL 0x1A30 398 #define RK3568_ESMART1_REGION0_SCL_FACTOR_YRGB 0x1A34 399 #define RK3568_ESMART1_REGION0_SCL_FACTOR_CBR 0x1A38 400 #define RK3568_ESMART1_REGION0_SCL_OFFSET 0x1A3C 401 #define RK3568_ESMART1_REGION1_CTRL 0x1A40 402 #define RK3568_ESMART1_REGION1_YRGB_MST 0x1A44 403 #define RK3568_ESMART1_REGION1_CBR_MST 0x1A48 404 #define RK3568_ESMART1_REGION1_VIR 0x1A4C 405 #define RK3568_ESMART1_REGION1_ACT_INFO 0x1A50 406 #define RK3568_ESMART1_REGION1_DSP_INFO 0x1A54 407 #define RK3568_ESMART1_REGION1_DSP_ST 0x1A58 408 #define RK3568_ESMART1_REGION1_SCL_CTRL 0x1A60 409 #define RK3568_ESMART1_REGION1_SCL_FACTOR_YRGB 0x1A64 410 #define RK3568_ESMART1_REGION1_SCL_FACTOR_CBR 0x1A68 411 #define RK3568_ESMART1_REGION1_SCL_OFFSET 0x1A6C 412 #define RK3568_ESMART1_REGION2_CTRL 0x1A70 413 #define RK3568_ESMART1_REGION2_YRGB_MST 0x1A74 414 #define RK3568_ESMART1_REGION2_CBR_MST 0x1A78 415 #define RK3568_ESMART1_REGION2_VIR 0x1A7C 416 #define RK3568_ESMART1_REGION2_ACT_INFO 0x1A80 417 #define RK3568_ESMART1_REGION2_DSP_INFO 0x1A84 418 #define RK3568_ESMART1_REGION2_DSP_ST 0x1A88 419 #define RK3568_ESMART1_REGION2_SCL_CTRL 0x1A90 420 #define RK3568_ESMART1_REGION2_SCL_FACTOR_YRGB 0x1A94 421 #define RK3568_ESMART1_REGION2_SCL_FACTOR_CBR 0x1A98 422 #define RK3568_ESMART1_REGION2_SCL_OFFSET 0x1A9C 423 #define RK3568_ESMART1_REGION3_CTRL 0x1AA0 424 #define RK3568_ESMART1_REGION3_YRGB_MST 0x1AA4 425 #define RK3568_ESMART1_REGION3_CBR_MST 0x1AA8 426 #define RK3568_ESMART1_REGION3_VIR 0x1AAC 427 #define RK3568_ESMART1_REGION3_ACT_INFO 0x1AB0 428 #define RK3568_ESMART1_REGION3_DSP_INFO 0x1AB4 429 #define RK3568_ESMART1_REGION3_DSP_ST 0x1AB8 430 #define RK3568_ESMART1_REGION3_SCL_CTRL 0x1AC0 431 #define RK3568_ESMART1_REGION3_SCL_FACTOR_YRGB 0x1AC4 432 #define RK3568_ESMART1_REGION3_SCL_FACTOR_CBR 0x1AC8 433 #define RK3568_ESMART1_REGION3_SCL_OFFSET 0x1ACC 434 435 #define RK3568_SMART0_CTRL0 0x1C00 436 #define RK3568_SMART0_CTRL1 0x1C04 437 #define RK3568_SMART0_REGION0_CTRL 0x1C10 438 #define RK3568_SMART0_REGION0_YRGB_MST 0x1C14 439 #define RK3568_SMART0_REGION0_CBR_MST 0x1C18 440 #define RK3568_SMART0_REGION0_VIR 0x1C1C 441 #define RK3568_SMART0_REGION0_ACT_INFO 0x1C20 442 #define RK3568_SMART0_REGION0_DSP_INFO 0x1C24 443 #define RK3568_SMART0_REGION0_DSP_ST 0x1C28 444 #define RK3568_SMART0_REGION0_SCL_CTRL 0x1C30 445 #define RK3568_SMART0_REGION0_SCL_FACTOR_YRGB 0x1C34 446 #define RK3568_SMART0_REGION0_SCL_FACTOR_CBR 0x1C38 447 #define RK3568_SMART0_REGION0_SCL_OFFSET 0x1C3C 448 #define RK3568_SMART0_REGION1_CTRL 0x1C40 449 #define RK3568_SMART0_REGION1_YRGB_MST 0x1C44 450 #define RK3568_SMART0_REGION1_CBR_MST 0x1C48 451 #define RK3568_SMART0_REGION1_VIR 0x1C4C 452 #define RK3568_SMART0_REGION1_ACT_INFO 0x1C50 453 #define RK3568_SMART0_REGION1_DSP_INFO 0x1C54 454 #define RK3568_SMART0_REGION1_DSP_ST 0x1C58 455 #define RK3568_SMART0_REGION1_SCL_CTRL 0x1C60 456 #define RK3568_SMART0_REGION1_SCL_FACTOR_YRGB 0x1C64 457 #define RK3568_SMART0_REGION1_SCL_FACTOR_CBR 0x1C68 458 #define RK3568_SMART0_REGION1_SCL_OFFSET 0x1C6C 459 #define RK3568_SMART0_REGION2_CTRL 0x1C70 460 #define RK3568_SMART0_REGION2_YRGB_MST 0x1C74 461 #define RK3568_SMART0_REGION2_CBR_MST 0x1C78 462 #define RK3568_SMART0_REGION2_VIR 0x1C7C 463 #define RK3568_SMART0_REGION2_ACT_INFO 0x1C80 464 #define RK3568_SMART0_REGION2_DSP_INFO 0x1C84 465 #define RK3568_SMART0_REGION2_DSP_ST 0x1C88 466 #define RK3568_SMART0_REGION2_SCL_CTRL 0x1C90 467 #define RK3568_SMART0_REGION2_SCL_FACTOR_YRGB 0x1C94 468 #define RK3568_SMART0_REGION2_SCL_FACTOR_CBR 0x1C98 469 #define RK3568_SMART0_REGION2_SCL_OFFSET 0x1C9C 470 #define RK3568_SMART0_REGION3_CTRL 0x1CA0 471 #define RK3568_SMART0_REGION3_YRGB_MST 0x1CA4 472 #define RK3568_SMART0_REGION3_CBR_MST 0x1CA8 473 #define RK3568_SMART0_REGION3_VIR 0x1CAC 474 #define RK3568_SMART0_REGION3_ACT_INFO 0x1CB0 475 #define RK3568_SMART0_REGION3_DSP_INFO 0x1CB4 476 #define RK3568_SMART0_REGION3_DSP_ST 0x1CB8 477 #define RK3568_SMART0_REGION3_SCL_CTRL 0x1CC0 478 #define RK3568_SMART0_REGION3_SCL_FACTOR_YRGB 0x1CC4 479 #define RK3568_SMART0_REGION3_SCL_FACTOR_CBR 0x1CC8 480 #define RK3568_SMART0_REGION3_SCL_OFFSET 0x1CCC 481 482 #define RK3568_SMART1_CTRL0 0x1E00 483 #define RK3568_SMART1_CTRL1 0x1E04 484 #define RK3568_SMART1_REGION0_CTRL 0x1E10 485 #define RK3568_SMART1_REGION0_YRGB_MST 0x1E14 486 #define RK3568_SMART1_REGION0_CBR_MST 0x1E18 487 #define RK3568_SMART1_REGION0_VIR 0x1E1C 488 #define RK3568_SMART1_REGION0_ACT_INFO 0x1E20 489 #define RK3568_SMART1_REGION0_DSP_INFO 0x1E24 490 #define RK3568_SMART1_REGION0_DSP_ST 0x1E28 491 #define RK3568_SMART1_REGION0_SCL_CTRL 0x1E30 492 #define RK3568_SMART1_REGION0_SCL_FACTOR_YRGB 0x1E34 493 #define RK3568_SMART1_REGION0_SCL_FACTOR_CBR 0x1E38 494 #define RK3568_SMART1_REGION0_SCL_OFFSET 0x1E3C 495 #define RK3568_SMART1_REGION1_CTRL 0x1E40 496 #define RK3568_SMART1_REGION1_YRGB_MST 0x1E44 497 #define RK3568_SMART1_REGION1_CBR_MST 0x1E48 498 #define RK3568_SMART1_REGION1_VIR 0x1E4C 499 #define RK3568_SMART1_REGION1_ACT_INFO 0x1E50 500 #define RK3568_SMART1_REGION1_DSP_INFO 0x1E54 501 #define RK3568_SMART1_REGION1_DSP_ST 0x1E58 502 #define RK3568_SMART1_REGION1_SCL_CTRL 0x1E60 503 #define RK3568_SMART1_REGION1_SCL_FACTOR_YRGB 0x1E64 504 #define RK3568_SMART1_REGION1_SCL_FACTOR_CBR 0x1E68 505 #define RK3568_SMART1_REGION1_SCL_OFFSET 0x1E6C 506 #define RK3568_SMART1_REGION2_CTRL 0x1E70 507 #define RK3568_SMART1_REGION2_YRGB_MST 0x1E74 508 #define RK3568_SMART1_REGION2_CBR_MST 0x1E78 509 #define RK3568_SMART1_REGION2_VIR 0x1E7C 510 #define RK3568_SMART1_REGION2_ACT_INFO 0x1E80 511 #define RK3568_SMART1_REGION2_DSP_INFO 0x1E84 512 #define RK3568_SMART1_REGION2_DSP_ST 0x1E88 513 #define RK3568_SMART1_REGION2_SCL_CTRL 0x1E90 514 #define RK3568_SMART1_REGION2_SCL_FACTOR_YRGB 0x1E94 515 #define RK3568_SMART1_REGION2_SCL_FACTOR_CBR 0x1E98 516 #define RK3568_SMART1_REGION2_SCL_OFFSET 0x1E9C 517 #define RK3568_SMART1_REGION3_CTRL 0x1EA0 518 #define RK3568_SMART1_REGION3_YRGB_MST 0x1EA4 519 #define RK3568_SMART1_REGION3_CBR_MST 0x1EA8 520 #define RK3568_SMART1_REGION3_VIR 0x1EAC 521 #define RK3568_SMART1_REGION3_ACT_INFO 0x1EB0 522 #define RK3568_SMART1_REGION3_DSP_INFO 0x1EB4 523 #define RK3568_SMART1_REGION3_DSP_ST 0x1EB8 524 #define RK3568_SMART1_REGION3_SCL_CTRL 0x1EC0 525 #define RK3568_SMART1_REGION3_SCL_FACTOR_YRGB 0x1EC4 526 #define RK3568_SMART1_REGION3_SCL_FACTOR_CBR 0x1EC8 527 #define RK3568_SMART1_REGION3_SCL_OFFSET 0x1ECC 528 529 #define RK3568_MAX_REG 0x1ED0 530 531 #define RK3568_GRF_VO_CON1 0x0364 532 #define GRF_BT656_CLK_INV_SHIFT 1 533 #define GRF_BT1120_CLK_INV_SHIFT 2 534 #define GRF_RGB_DCLK_INV_SHIFT 3 535 536 #define VOP2_LAYER_MAX 8 537 538 #define VOP_FEATURE_OUTPUT_10BIT BIT(0) 539 540 enum vop2_csc_format { 541 CSC_BT601L, 542 CSC_BT709L, 543 CSC_BT601F, 544 CSC_BT2020, 545 }; 546 547 enum vop2_pol { 548 HSYNC_POSITIVE = 0, 549 VSYNC_POSITIVE = 1, 550 DEN_NEGATIVE = 2, 551 DCLK_INVERT = 3 552 }; 553 554 enum vop2_bcsh_out_mode { 555 BCSH_OUT_MODE_BLACK, 556 BCSH_OUT_MODE_BLUE, 557 BCSH_OUT_MODE_COLOR_BAR, 558 BCSH_OUT_MODE_NORMAL_VIDEO, 559 }; 560 561 #define _VOP_REG(off, _mask, _shift, _write_mask) \ 562 { \ 563 .offset = off, \ 564 .mask = _mask, \ 565 .shift = _shift, \ 566 .write_mask = _write_mask, \ 567 } 568 569 #define VOP_REG(off, _mask, _shift) \ 570 _VOP_REG(off, _mask, _shift, false) 571 enum dither_down_mode { 572 RGB888_TO_RGB565 = 0x0, 573 RGB888_TO_RGB666 = 0x1 574 }; 575 576 enum vop2_video_ports_id { 577 VOP2_VP0, 578 VOP2_VP1, 579 VOP2_VP2, 580 VOP2_VP3, 581 VOP2_VP_MAX, 582 }; 583 584 /* This define must same with kernel win phy id */ 585 enum vop2_layer_phy_id { 586 ROCKCHIP_VOP2_CLUSTER0 = 0, 587 ROCKCHIP_VOP2_CLUSTER1, 588 ROCKCHIP_VOP2_ESMART0, 589 ROCKCHIP_VOP2_ESMART1, 590 ROCKCHIP_VOP2_SMART0, 591 ROCKCHIP_VOP2_SMART1, 592 ROCKCHIP_VOP2_CLUSTER2, 593 ROCKCHIP_VOP2_CLUSTER3, 594 ROCKCHIP_VOP2_ESMART2, 595 ROCKCHIP_VOP2_ESMART3, 596 }; 597 598 enum vop2_scale_up_mode { 599 VOP2_SCALE_UP_NRST_NBOR, 600 VOP2_SCALE_UP_BIL, 601 VOP2_SCALE_UP_BIC, 602 }; 603 604 enum vop2_scale_down_mode { 605 VOP2_SCALE_DOWN_NRST_NBOR, 606 VOP2_SCALE_DOWN_BIL, 607 VOP2_SCALE_DOWN_AVG, 608 }; 609 610 enum scale_mode { 611 SCALE_NONE = 0x0, 612 SCALE_UP = 0x1, 613 SCALE_DOWN = 0x2 614 }; 615 616 struct vop2_layer { 617 u8 id; 618 /** 619 * @win_phys_id: window id of the layer selected. 620 * Every layer must make sure to select different 621 * windows of others. 622 */ 623 u8 win_phys_id; 624 }; 625 626 struct vop2_win_data { 627 char *name; 628 u8 phys_id; 629 u8 win_sel_port_offset; 630 u8 layer_sel_win_id; 631 u32 reg_offset; 632 }; 633 634 struct vop2_vp_data { 635 u32 feature; 636 u8 pre_scan_max_dly; 637 struct vop_rect max_output; 638 }; 639 640 struct vop2_vp_plane_mask { 641 u8 primary_plane_id; /* use this win to show logo */ 642 u8 attached_layers_nr; /* number layers attach to this vp */ 643 u8 attached_layers[VOP2_LAYER_MAX]; /* the layers attached to this vp */ 644 u32 plane_mask; 645 }; 646 647 struct vop2_data { 648 u32 version; 649 struct vop2_vp_data *vp_data; 650 struct vop2_win_data *win_data; 651 struct vop2_vp_plane_mask *plane_mask; 652 u8 nr_vps; 653 u8 nr_layers; 654 u8 nr_mixers; 655 u8 nr_gammas; 656 }; 657 658 struct vop2 { 659 u32 *regsbak; 660 void *regs; 661 void *grf; 662 u32 reg_len; 663 u32 version; 664 bool global_init; 665 const struct vop2_data *data; 666 struct vop2_vp_plane_mask vp_plane_mask[VOP2_VP_MAX]; 667 }; 668 669 static struct vop2 *rockchip_vop2; 670 /* 671 * bli_sd_factor = (src - 1) / (dst - 1) << 12; 672 * avg_sd_factor: 673 * bli_su_factor: 674 * bic_su_factor: 675 * = (src - 1) / (dst - 1) << 16; 676 * 677 * gt2 enable: dst get one line from two line of the src 678 * gt4 enable: dst get one line from four line of the src. 679 * 680 */ 681 #define VOP2_BILI_SCL_DN(src, dst) (((src - 1) << 12) / (dst - 1)) 682 #define VOP2_COMMON_SCL(src, dst) (((src - 1) << 16) / (dst - 1)) 683 684 #define VOP2_BILI_SCL_FAC_CHECK(src, dst, fac) \ 685 (fac * (dst - 1) >> 12 < (src - 1)) 686 #define VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac) \ 687 (fac * (dst - 1) >> 16 < (src - 1)) 688 689 static uint16_t vop2_scale_factor(enum scale_mode mode, 690 int32_t filter_mode, 691 uint32_t src, uint32_t dst) 692 { 693 uint32_t fac = 0; 694 int i = 0; 695 696 if (mode == SCALE_NONE) 697 return 0; 698 699 /* 700 * A workaround to avoid zero div. 701 */ 702 if ((dst == 1) || (src == 1)) { 703 dst = dst + 1; 704 src = src + 1; 705 } 706 707 if ((mode == SCALE_DOWN) && (filter_mode == VOP2_SCALE_DOWN_BIL)) { 708 fac = VOP2_BILI_SCL_DN(src, dst); 709 for (i = 0; i < 100; i++) { 710 if (VOP2_BILI_SCL_FAC_CHECK(src, dst, fac)) 711 break; 712 fac -= 1; 713 printf("down fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac); 714 } 715 } else { 716 fac = VOP2_COMMON_SCL(src, dst); 717 for (i = 0; i < 100; i++) { 718 if (VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac)) 719 break; 720 fac -= 1; 721 printf("up fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac); 722 } 723 } 724 725 return fac; 726 } 727 728 static inline enum scale_mode scl_get_scl_mode(int src, int dst) 729 { 730 if (src < dst) 731 return SCALE_UP; 732 else if (src > dst) 733 return SCALE_DOWN; 734 735 return SCALE_NONE; 736 } 737 738 static u8 vop2_vp_primary_plane_order[VOP2_VP_MAX] = { 739 ROCKCHIP_VOP2_SMART0, 740 ROCKCHIP_VOP2_SMART1, 741 ROCKCHIP_VOP2_ESMART1, 742 }; 743 744 static inline int interpolate(int x1, int y1, int x2, int y2, int x) 745 { 746 return y1 + (y2 - y1) * (x - x1) / (x2 - x1); 747 } 748 749 static int vop2_get_primary_plane(struct vop2 *vop2, u32 plane_mask) 750 { 751 int i = 0; 752 753 for (i = 0; i < vop2->data->nr_vps; i++) { 754 if (plane_mask & BIT(vop2_vp_primary_plane_order[i])) 755 return vop2_vp_primary_plane_order[i]; 756 } 757 758 return ROCKCHIP_VOP2_SMART0; 759 } 760 761 static inline u16 scl_cal_scale(int src, int dst, int shift) 762 { 763 return ((src * 2 - 3) << (shift - 1)) / (dst - 1); 764 } 765 766 static inline u16 scl_cal_scale2(int src, int dst) 767 { 768 return ((src - 1) << 12) / (dst - 1); 769 } 770 771 static inline void vop2_writel(struct vop2 *vop2, u32 offset, u32 v) 772 { 773 writel(v, vop2->regs + offset); 774 vop2->regsbak[offset >> 2] = v; 775 } 776 777 static inline u32 vop2_readl(struct vop2 *vop2, u32 offset) 778 { 779 return readl(vop2->regs + offset); 780 } 781 782 static inline void vop2_mask_write(struct vop2 *vop2, u32 offset, 783 u32 mask, u32 shift, u32 v, 784 bool write_mask) 785 { 786 if (!mask) 787 return; 788 789 if (write_mask) { 790 v = ((v & mask) << shift) | (mask << (shift + 16)); 791 } else { 792 u32 cached_val = vop2->regsbak[offset >> 2]; 793 794 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 795 vop2->regsbak[offset >> 2] = v; 796 } 797 798 writel(v, vop2->regs + offset); 799 } 800 801 static inline void vop2_grf_writel(struct vop2 *vop, u32 offset, 802 u32 mask, u32 shift, u32 v) 803 { 804 u32 val = 0; 805 806 val = (v << shift) | (mask << (shift + 16)); 807 writel(val, vop->grf + offset); 808 } 809 810 static inline int us_to_vertical_line(struct drm_display_mode *mode, int us) 811 { 812 return us * mode->clock / mode->htotal / 1000; 813 } 814 815 static char* get_output_if_name(u32 output_if, char *name) 816 { 817 if (output_if & VOP_OUTPUT_IF_RGB) 818 strcat(name, " RGB"); 819 if (output_if & VOP_OUTPUT_IF_BT1120) 820 strcat(name, " BT1120"); 821 if (output_if & VOP_OUTPUT_IF_BT656) 822 strcat(name, " BT656"); 823 if (output_if & VOP_OUTPUT_IF_LVDS0) 824 strcat(name, " LVDS0"); 825 if (output_if & VOP_OUTPUT_IF_LVDS1) 826 strcat(name, " LVDS1"); 827 if (output_if & VOP_OUTPUT_IF_MIPI0) 828 strcat(name, " MIPI0"); 829 if (output_if & VOP_OUTPUT_IF_MIPI1) 830 strcat(name, " MIPI1"); 831 if (output_if & VOP_OUTPUT_IF_eDP0) 832 strcat(name, " eDP0"); 833 if (output_if & VOP_OUTPUT_IF_eDP1) 834 strcat(name, " eDP1"); 835 if (output_if & VOP_OUTPUT_IF_DP0) 836 strcat(name, " DP0"); 837 if (output_if & VOP_OUTPUT_IF_DP1) 838 strcat(name, " DP1"); 839 if (output_if & VOP_OUTPUT_IF_HDMI0) 840 strcat(name, " HDMI0"); 841 if (output_if & VOP_OUTPUT_IF_HDMI1) 842 strcat(name, " HDMI1"); 843 844 return name; 845 } 846 847 static char *get_plane_name(int plane_id, char *name) 848 { 849 switch (plane_id) { 850 case ROCKCHIP_VOP2_CLUSTER0: 851 strcat(name, "Cluster0"); 852 break; 853 case ROCKCHIP_VOP2_CLUSTER1: 854 strcat(name, "Cluster1"); 855 break; 856 case ROCKCHIP_VOP2_ESMART0: 857 strcat(name, "Esmart0"); 858 break; 859 case ROCKCHIP_VOP2_ESMART1: 860 strcat(name, "Esmart1"); 861 break; 862 case ROCKCHIP_VOP2_SMART0: 863 strcat(name, "Smart0"); 864 break; 865 case ROCKCHIP_VOP2_SMART1: 866 strcat(name, "Smart1"); 867 break; 868 case ROCKCHIP_VOP2_CLUSTER2: 869 strcat(name, "Cluster2"); 870 break; 871 case ROCKCHIP_VOP2_CLUSTER3: 872 strcat(name, "Cluster3"); 873 break; 874 case ROCKCHIP_VOP2_ESMART2: 875 strcat(name, "Esmart2"); 876 break; 877 case ROCKCHIP_VOP2_ESMART3: 878 strcat(name, "Esmart3"); 879 break; 880 } 881 882 return name; 883 } 884 885 static bool is_yuv_output(u32 bus_format) 886 { 887 switch (bus_format) { 888 case MEDIA_BUS_FMT_YUV8_1X24: 889 case MEDIA_BUS_FMT_YUV10_1X30: 890 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 891 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 892 return true; 893 default: 894 return false; 895 } 896 } 897 898 static int vop2_convert_csc_mode(int csc_mode) 899 { 900 switch (csc_mode) { 901 case V4L2_COLORSPACE_SMPTE170M: 902 case V4L2_COLORSPACE_470_SYSTEM_M: 903 case V4L2_COLORSPACE_470_SYSTEM_BG: 904 return CSC_BT601L; 905 case V4L2_COLORSPACE_REC709: 906 case V4L2_COLORSPACE_SMPTE240M: 907 case V4L2_COLORSPACE_DEFAULT: 908 return CSC_BT709L; 909 case V4L2_COLORSPACE_JPEG: 910 return CSC_BT601F; 911 case V4L2_COLORSPACE_BT2020: 912 return CSC_BT2020; 913 default: 914 return CSC_BT709L; 915 } 916 } 917 918 static bool is_uv_swap(u32 bus_format, u32 output_mode) 919 { 920 /* 921 * FIXME: 922 * 923 * There is no media type for YUV444 output, 924 * so when out_mode is AAAA or P888, assume output is YUV444 on 925 * yuv format. 926 * 927 * From H/W testing, YUV444 mode need a rb swap. 928 */ 929 if ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 930 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 931 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 932 output_mode == ROCKCHIP_OUT_MODE_P888)) 933 return true; 934 else 935 return false; 936 } 937 938 static inline bool is_hot_plug_devices(int output_type) 939 { 940 switch (output_type) { 941 case DRM_MODE_CONNECTOR_HDMIA: 942 case DRM_MODE_CONNECTOR_HDMIB: 943 case DRM_MODE_CONNECTOR_TV: 944 case DRM_MODE_CONNECTOR_DisplayPort: 945 case DRM_MODE_CONNECTOR_VGA: 946 case DRM_MODE_CONNECTOR_Unknown: 947 return true; 948 default: 949 return false; 950 } 951 } 952 953 static int rockchip_vop2_gamma_lut_init(struct vop2 *vop2, 954 struct display_state *state) 955 { 956 struct connector_state *conn_state = &state->conn_state; 957 struct crtc_state *cstate = &state->crtc_state; 958 struct resource gamma_res; 959 fdt_size_t lut_size; 960 int i, lut_len, ret = 0; 961 u32 *lut_regs; 962 u32 *lut_val; 963 u32 r, g, b; 964 u32 vp_offset = cstate->crtc_id * 0x100; 965 struct base2_disp_info *disp_info = conn_state->disp_info; 966 static int gamma_lut_en_num = 1; 967 968 if (gamma_lut_en_num > vop2->data->nr_gammas) { 969 printf("warn: only %d vp support gamma\n", vop2->data->nr_gammas); 970 return 0; 971 } 972 973 if (!disp_info) 974 return 0; 975 976 if (!disp_info->gamma_lut_data.size) 977 return 0; 978 979 ret = ofnode_read_resource_byname(cstate->node, "gamma_lut", &gamma_res); 980 if (ret) 981 printf("failed to get gamma lut res\n"); 982 lut_regs = (u32 *)gamma_res.start; 983 lut_size = gamma_res.end - gamma_res.start + 1; 984 if (lut_regs == (u32 *)FDT_ADDR_T_NONE) { 985 printf("failed to get gamma lut register\n"); 986 return 0; 987 } 988 lut_len = lut_size / 4; 989 if (lut_len != 256 && lut_len != 1024) { 990 printf("Warning: unsupport gamma lut table[%d]\n", lut_len); 991 return 0; 992 } 993 lut_val = (u32 *)calloc(1, lut_size); 994 for (i = 0; i < lut_len; i++) { 995 r = disp_info->gamma_lut_data.lred[i] * (lut_len - 1) / 0xffff; 996 g = disp_info->gamma_lut_data.lgreen[i] * (lut_len - 1) / 0xffff; 997 b = disp_info->gamma_lut_data.lblue[i] * (lut_len - 1) / 0xffff; 998 999 lut_val[i] = b * lut_len * lut_len + g * lut_len + r; 1000 } 1001 1002 for (i = 0; i < lut_len; i++) 1003 writel(lut_val[i], lut_regs + i); 1004 1005 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, 1006 GAMMA_PORT_SEL_MASK, GAMMA_PORT_SEL_SHIFT, 1007 cstate->crtc_id , false); 1008 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 1009 EN_MASK, DSP_LUT_EN_SHIFT, 1, false); 1010 gamma_lut_en_num++; 1011 1012 return 0; 1013 } 1014 1015 static int rockchip_vop2_cubic_lut_init(struct vop2 *vop2, 1016 struct display_state *state) 1017 { 1018 struct connector_state *conn_state = &state->conn_state; 1019 struct crtc_state *cstate = &state->crtc_state; 1020 int i, cubic_lut_len; 1021 u32 vp_offset = cstate->crtc_id * 0x100; 1022 struct base2_disp_info *disp_info = conn_state->disp_info; 1023 struct base2_cubic_lut_data *lut = &conn_state->disp_info->cubic_lut_data; 1024 u32 *cubic_lut_addr; 1025 1026 if (!disp_info || CONFIG_ROCKCHIP_CUBIC_LUT_SIZE == 0) 1027 return 0; 1028 1029 if (!disp_info->cubic_lut_data.size) 1030 return 0; 1031 1032 cubic_lut_addr = (u32 *)get_cubic_lut_buffer(cstate->crtc_id); 1033 cubic_lut_len = disp_info->cubic_lut_data.size; 1034 1035 for (i = 0; i < cubic_lut_len / 2; i++) { 1036 *cubic_lut_addr++ = ((lut->lred[2 * i]) & 0xfff) + 1037 ((lut->lgreen[2 * i] & 0xfff) << 12) + 1038 ((lut->lblue[2 * i] & 0xff) << 24); 1039 *cubic_lut_addr++ = ((lut->lblue[2 * i] & 0xf00) >> 8) + 1040 ((lut->lred[2 * i + 1] & 0xfff) << 4) + 1041 ((lut->lgreen[2 * i + 1] & 0xfff) << 16) + 1042 ((lut->lblue[2 * i + 1] & 0xf) << 28); 1043 *cubic_lut_addr++ = (lut->lblue[2 * i + 1] & 0xff0) >> 4; 1044 *cubic_lut_addr++ = 0; 1045 } 1046 1047 if (cubic_lut_len % 2) { 1048 *cubic_lut_addr++ = (lut->lred[2 * i] & 0xfff) + 1049 ((lut->lgreen[2 * i] & 0xfff) << 12) + 1050 ((lut->lblue[2 * i] & 0xff) << 24); 1051 *cubic_lut_addr++ = (lut->lblue[2 * i] & 0xf00) >> 8; 1052 *cubic_lut_addr++ = 0; 1053 *cubic_lut_addr = 0; 1054 } 1055 1056 vop2_writel(vop2, RK3568_VP0_3D_LUT_MST + vp_offset, 1057 get_cubic_lut_buffer(cstate->crtc_id)); 1058 vop2_mask_write(vop2, RK3568_SYS_AXI_LUT_CTRL, 1059 EN_MASK, LUT_DMA_EN_SHIFT, 1, false); 1060 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, 1061 EN_MASK, VP0_3D_LUT_EN_SHIFT, 1, false); 1062 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, 1063 EN_MASK, VP0_3D_LUT_UPDATE_SHIFT, 1, false); 1064 1065 return 0; 1066 } 1067 1068 static void vop2_tv_config_update(struct display_state *state, struct vop2 *vop2) 1069 { 1070 struct connector_state *conn_state = &state->conn_state; 1071 struct base_bcsh_info *bcsh_info; 1072 struct crtc_state *cstate = &state->crtc_state; 1073 int brightness, contrast, saturation, hue, sin_hue, cos_hue; 1074 bool bcsh_en = false, post_r2y_en = false, post_y2r_en = false; 1075 u32 vp_offset = (cstate->crtc_id * 0x100); 1076 int post_csc_mode; 1077 1078 if (!conn_state->disp_info) 1079 return; 1080 bcsh_info = &conn_state->disp_info->bcsh_info; 1081 if (!bcsh_info) 1082 return; 1083 1084 if (bcsh_info->brightness != 50 || 1085 bcsh_info->contrast != 50 || 1086 bcsh_info->saturation != 50 || bcsh_info->hue != 50) 1087 bcsh_en = true; 1088 1089 if (bcsh_en) { 1090 if (!cstate->yuv_overlay) 1091 post_r2y_en = 1; 1092 if (!is_yuv_output(conn_state->bus_format)) 1093 post_y2r_en = 1; 1094 } else { 1095 if (!cstate->yuv_overlay && is_yuv_output(conn_state->bus_format)) 1096 post_r2y_en = 1; 1097 if (cstate->yuv_overlay && !is_yuv_output(conn_state->bus_format)) 1098 post_y2r_en = 1; 1099 } 1100 1101 post_csc_mode = vop2_convert_csc_mode(conn_state->color_space); 1102 1103 1104 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_MASK, 1105 BCSH_CTRL_R2Y_SHIFT, post_r2y_en, false); 1106 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_MASK, 1107 BCSH_CTRL_Y2R_SHIFT, post_y2r_en, false); 1108 1109 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_CSC_MODE_MASK, 1110 BCSH_CTRL_R2Y_CSC_MODE_SHIFT, post_csc_mode, false); 1111 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_CSC_MODE_MASK, 1112 BCSH_CTRL_Y2R_CSC_MODE_SHIFT, post_csc_mode, false); 1113 if (!bcsh_en) { 1114 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, 1115 BCSH_EN_MASK, BCSH_EN_SHIFT, 0, false); 1116 return; 1117 } 1118 1119 if (cstate->feature & VOP_FEATURE_OUTPUT_10BIT) 1120 brightness = interpolate(0, -128, 100, 127, 1121 bcsh_info->brightness); 1122 else 1123 brightness = interpolate(0, -32, 100, 31, 1124 bcsh_info->brightness); 1125 contrast = interpolate(0, 0, 100, 511, bcsh_info->contrast); 1126 saturation = interpolate(0, 0, 100, 511, bcsh_info->saturation); 1127 hue = interpolate(0, -30, 100, 30, bcsh_info->hue); 1128 1129 1130 /* 1131 * a:[-30~0): 1132 * sin_hue = 0x100 - sin(a)*256; 1133 * cos_hue = cos(a)*256; 1134 * a:[0~30] 1135 * sin_hue = sin(a)*256; 1136 * cos_hue = cos(a)*256; 1137 */ 1138 sin_hue = fixp_sin32(hue) >> 23; 1139 cos_hue = fixp_cos32(hue) >> 23; 1140 1141 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1142 BCSH_BRIGHTNESS_MASK, BCSH_BRIGHTNESS_SHIFT, 1143 brightness, false); 1144 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1145 BCSH_CONTRAST_MASK, BCSH_CONTRAST_SHIFT, contrast, false); 1146 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1147 BCSH_SATURATION_MASK, BCSH_SATURATION_SHIFT, 1148 saturation * contrast / 0x100, false); 1149 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, 1150 BCSH_SIN_HUE_MASK, BCSH_SIN_HUE_SHIFT, sin_hue, false); 1151 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, 1152 BCSH_COS_HUE_MASK, BCSH_COS_HUE_SHIFT, cos_hue, false); 1153 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1154 BCSH_OUT_MODE_MASK, BCSH_OUT_MODE_SHIFT, 1155 BCSH_OUT_MODE_NORMAL_VIDEO, false); 1156 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, 1157 BCSH_EN_MASK, BCSH_EN_SHIFT, 1, false); 1158 } 1159 1160 static void vop2_post_config(struct display_state *state, struct vop2 *vop2) 1161 { 1162 struct connector_state *conn_state = &state->conn_state; 1163 struct drm_display_mode *mode = &conn_state->mode; 1164 struct crtc_state *cstate = &state->crtc_state; 1165 u32 vp_offset = (cstate->crtc_id * 0x100); 1166 u16 vtotal = mode->crtc_vtotal; 1167 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 1168 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 1169 u16 hdisplay = mode->crtc_hdisplay; 1170 u16 vdisplay = mode->crtc_vdisplay; 1171 u16 hsize = 1172 hdisplay * (conn_state->overscan.left_margin + 1173 conn_state->overscan.right_margin) / 200; 1174 u16 vsize = 1175 vdisplay * (conn_state->overscan.top_margin + 1176 conn_state->overscan.bottom_margin) / 200; 1177 u16 hact_end, vact_end; 1178 u32 val; 1179 u32 bg_ovl_dly, bg_dly, pre_scan_dly; 1180 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 1181 1182 hsize = round_down(hsize, 2); 1183 vsize = round_down(vsize, 2); 1184 1185 hact_st += hdisplay * (100 - conn_state->overscan.left_margin) / 200; 1186 hact_end = hact_st + hsize; 1187 val = hact_st << 16; 1188 val |= hact_end; 1189 1190 vop2_writel(vop2, RK3568_VP0_POST_DSP_HACT_INFO + vp_offset, val); 1191 vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200; 1192 vact_end = vact_st + vsize; 1193 val = vact_st << 16; 1194 val |= vact_end; 1195 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO + vp_offset, val); 1196 val = scl_cal_scale2(vdisplay, vsize) << 16; 1197 val |= scl_cal_scale2(hdisplay, hsize); 1198 vop2_writel(vop2, RK3568_VP0_POST_SCL_FACTOR_YRGB + vp_offset, val); 1199 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0) 1200 #define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1) 1201 vop2_writel(vop2, RK3568_VP0_POST_SCL_CTRL + vp_offset, 1202 POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) | 1203 POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize)); 1204 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1205 u16 vact_st_f1 = vtotal + vact_st + 1; 1206 u16 vact_end_f1 = vact_st_f1 + vsize; 1207 1208 val = vact_st_f1 << 16 | vact_end_f1; 1209 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO_F1 + vp_offset, val); 1210 } 1211 1212 bg_ovl_dly = cstate->crtc->vps[cstate->crtc_id].bg_ovl_dly; 1213 bg_dly = vop2->data->vp_data[cstate->crtc_id].pre_scan_max_dly; 1214 bg_dly -= bg_ovl_dly; 1215 pre_scan_dly = bg_dly + (hdisplay >> 1) - 1; 1216 pre_scan_dly = (pre_scan_dly << 16) | hsync_len; 1217 vop2_mask_write(vop2, RK3568_VP0_BG_MIX_CTRL + cstate->crtc_id * 4, 1218 BG_MIX_CTRL_MASK, BG_MIX_CTRL_SHIFT, bg_dly, false); 1219 vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + vp_offset, pre_scan_dly); 1220 } 1221 1222 static void vop2_global_initial(struct vop2 *vop2, struct display_state *state) 1223 { 1224 struct crtc_state *cstate = &state->crtc_state; 1225 int i, j, port_mux = 0, total_used_layer = 0; 1226 u8 shift = 0; 1227 int layer_phy_id = 0; 1228 u32 layer_nr = 0; 1229 struct vop2_win_data *win_data; 1230 struct vop2_vp_plane_mask *plane_mask; 1231 1232 if (vop2->global_init) 1233 return; 1234 1235 /* OTP must enable at the first time, otherwise mirror layer register is error */ 1236 if (soc_is_rk3566()) 1237 vop2_mask_write(vop2, RK3568_SYS_OTP_WIN_EN, EN_MASK, 1238 OTP_WIN_EN_SHIFT, 1, false); 1239 1240 memcpy(vop2->regsbak, vop2->regs, vop2->reg_len); 1241 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, 1242 OVL_PORT_MUX_REG_DONE_IMD_SHIFT, 1, false); 1243 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1244 IF_CTRL_REG_DONE_IMD_SHIFT, 1, false); 1245 1246 if (cstate->crtc->assign_plane) {/* dts assign plane */ 1247 u32 plane_mask; 1248 int primary_plane_id; 1249 1250 for (i = 0; i < vop2->data->nr_vps; i++) { 1251 plane_mask = cstate->crtc->vps[i].plane_mask; 1252 vop2->vp_plane_mask[i].plane_mask = plane_mask; 1253 layer_nr = hweight32(plane_mask); /* use bitmap to store plane mask */ 1254 vop2->vp_plane_mask[i].attached_layers_nr = layer_nr; 1255 primary_plane_id = vop2_get_primary_plane(vop2, plane_mask); 1256 vop2->vp_plane_mask[i].primary_plane_id = primary_plane_id; 1257 vop2->vp_plane_mask[i].plane_mask = plane_mask; 1258 1259 /* plane mask[bitmap] convert into layer phy id[enum vop2_layer_phy_id]*/ 1260 for (j = 0; j < layer_nr; j++) { 1261 vop2->vp_plane_mask[i].attached_layers[j] = ffs(plane_mask) - 1; 1262 plane_mask &= ~BIT(vop2->vp_plane_mask[i].attached_layers[j]); 1263 } 1264 } 1265 } else {/* need soft assign plane mask */ 1266 /* find the first unplug devices and set it as main display */ 1267 int main_vp_index = -1; 1268 int active_vp_num = 0; 1269 1270 for (i = 0; i < vop2->data->nr_vps; i++) { 1271 if (cstate->crtc->vps[i].enable) 1272 active_vp_num++; 1273 } 1274 printf("VOP have %d active VP\n", active_vp_num); 1275 1276 if (soc_is_rk3566() && active_vp_num > 2) 1277 printf("ERROR: rk3566 only support 2 display output!!\n"); 1278 plane_mask = vop2->data->plane_mask; 1279 plane_mask += (active_vp_num - 1) * VOP2_VP_MAX; 1280 1281 for (i = 0; i < vop2->data->nr_vps; i++) { 1282 if (!is_hot_plug_devices(cstate->crtc->vps[i].output_type)) { 1283 vop2->vp_plane_mask[i] = plane_mask[0]; /* the first store main display plane mask*/ 1284 main_vp_index = i; 1285 break; 1286 } 1287 } 1288 1289 /* if no find unplug devices, use vp0 as main display */ 1290 if (main_vp_index < 0) { 1291 main_vp_index = 0; 1292 vop2->vp_plane_mask[0] = plane_mask[0]; 1293 } 1294 1295 j = 1; /* plane_mask[0] store main display, so we from plane_mask[1] */ 1296 1297 /* init other display except main display */ 1298 for (i = 0; i < vop2->data->nr_vps; i++) { 1299 if (i == main_vp_index || !cstate->crtc->vps[i].enable) /* main display or no connect devices */ 1300 continue; 1301 vop2->vp_plane_mask[i] = plane_mask[j++]; 1302 } 1303 1304 /* store plane mask for vop2_fixup_dts */ 1305 for (i = 0; i < vop2->data->nr_vps; i++) { 1306 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1307 /* rk3566 only support 3+3 policy */ 1308 if (soc_is_rk3566() && active_vp_num == 1) { 1309 if (cstate->crtc->vps[i].enable) { 1310 for (j = 0; j < 3; j++) { 1311 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1312 vop2->vp_plane_mask[i].plane_mask |= BIT(layer_phy_id); 1313 } 1314 } 1315 } else { 1316 for (j = 0; j < layer_nr; j++) { 1317 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1318 vop2->vp_plane_mask[i].plane_mask |= BIT(layer_phy_id); 1319 } 1320 } 1321 } 1322 } 1323 1324 for (i = 0; i < vop2->data->nr_vps; i++) { 1325 printf("vp%d have layer nr:%d[", i, vop2->vp_plane_mask[i].attached_layers_nr); 1326 for (j = 0; j < vop2->vp_plane_mask[i].attached_layers_nr; j++) 1327 printf("%d ", vop2->vp_plane_mask[i].attached_layers[j]); 1328 printf("], primary plane: %d\n", vop2->vp_plane_mask[i].primary_plane_id); 1329 } 1330 1331 shift = 0; 1332 /* layer sel win id */ 1333 for (i = 0; i < vop2->data->nr_vps; i++) { 1334 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1335 for (j = 0; j < layer_nr; j++) { 1336 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1337 win_data = &vop2->data->win_data[layer_phy_id]; 1338 vop2_mask_write(vop2, RK3568_OVL_LAYER_SEL, LAYER_SEL_MASK, 1339 shift, win_data->layer_sel_win_id, false); 1340 shift += 4; 1341 } 1342 } 1343 1344 /* win sel port */ 1345 for (i = 0; i < vop2->data->nr_vps; i++) { 1346 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1347 for (j = 0; j < layer_nr; j++) { 1348 if (!cstate->crtc->vps[i].enable) 1349 continue; 1350 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1351 win_data = &vop2->data->win_data[layer_phy_id]; 1352 shift = win_data->win_sel_port_offset * 2; 1353 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, LAYER_SEL_PORT_MASK, 1354 LAYER_SEL_PORT_SHIFT + shift, i, false); 1355 } 1356 } 1357 1358 /** 1359 * port mux config 1360 */ 1361 for (i = 0; i < vop2->data->nr_vps; i++) { 1362 shift = i * 4; 1363 if (cstate->crtc->vps[i].enable) { 1364 total_used_layer += vop2->vp_plane_mask[i].attached_layers_nr; 1365 port_mux = total_used_layer - 1; 1366 } else { 1367 port_mux = 8; 1368 } 1369 1370 if (i == vop2->data->nr_vps - 1) 1371 port_mux = vop2->data->nr_mixers; 1372 1373 cstate->crtc->vps[i].bg_ovl_dly = (vop2->data->nr_mixers - port_mux) << 1; 1374 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, PORT_MUX_MASK, 1375 PORT_MUX_SHIFT + shift, port_mux, false); 1376 } 1377 1378 vop2_writel(vop2, RK3568_AUTO_GATING_CTRL, 0); 1379 1380 vop2->global_init = true; 1381 } 1382 1383 static int vop2_initial(struct vop2 *vop2, struct display_state *state) 1384 { 1385 struct crtc_state *cstate = &state->crtc_state; 1386 struct connector_state *conn_state = &state->conn_state; 1387 struct drm_display_mode *mode = &conn_state->mode; 1388 char dclk_name[9]; 1389 struct clk dclk; 1390 int ret; 1391 1392 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1393 ret = clk_set_defaults(cstate->dev); 1394 if (ret) 1395 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1396 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", cstate->crtc_id); 1397 ret = clk_get_by_name(cstate->dev, dclk_name, &dclk); 1398 if (!ret) 1399 ret = clk_set_rate(&dclk, mode->clock * 1000); 1400 if (IS_ERR_VALUE(ret)) { 1401 printf("%s: Failed to set vp%d dclk[%d khz]: ret=%d\n", 1402 __func__, cstate->crtc_id, mode->clock, ret); 1403 return ret; 1404 } 1405 1406 vop2_global_initial(vop2, state); 1407 rockchip_vop2_gamma_lut_init(vop2, state); 1408 rockchip_vop2_cubic_lut_init(vop2, state); 1409 1410 return 0; 1411 } 1412 1413 /* 1414 * VOP2 have multi video ports. 1415 * video port ------- crtc 1416 */ 1417 static int rockchip_vop2_preinit(struct display_state *state) 1418 { 1419 struct crtc_state *cstate = &state->crtc_state; 1420 const struct vop2_data *vop2_data = cstate->crtc->data; 1421 1422 if (!rockchip_vop2) { 1423 rockchip_vop2 = calloc(1, sizeof(struct vop2)); 1424 if (!rockchip_vop2) 1425 return -ENOMEM; 1426 rockchip_vop2->regs = dev_read_addr_ptr(cstate->dev); 1427 rockchip_vop2->regsbak = malloc(RK3568_MAX_REG); 1428 rockchip_vop2->reg_len = RK3568_MAX_REG; 1429 rockchip_vop2->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1430 if (rockchip_vop2->grf <= 0) 1431 printf("%s: Get syscon grf failed (ret=%p)\n", __func__, rockchip_vop2->grf); 1432 1433 rockchip_vop2->version = vop2_data->version; 1434 rockchip_vop2->data = vop2_data; 1435 } 1436 1437 cstate->private = rockchip_vop2; 1438 cstate->max_output = vop2_data->vp_data[cstate->crtc_id].max_output; 1439 cstate->feature = vop2_data->vp_data[cstate->crtc_id].feature; 1440 1441 return 0; 1442 } 1443 1444 static int rockchip_vop2_init(struct display_state *state) 1445 { 1446 struct crtc_state *cstate = &state->crtc_state; 1447 struct connector_state *conn_state = &state->conn_state; 1448 struct drm_display_mode *mode = &conn_state->mode; 1449 struct vop2 *vop2 = cstate->private; 1450 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 1451 u16 hdisplay = mode->crtc_hdisplay; 1452 u16 htotal = mode->crtc_htotal; 1453 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 1454 u16 hact_end = hact_st + hdisplay; 1455 u16 vdisplay = mode->crtc_vdisplay; 1456 u16 vtotal = mode->crtc_vtotal; 1457 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 1458 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 1459 u16 vact_end = vact_st + vdisplay; 1460 bool yuv_overlay = false; 1461 u32 vp_offset = (cstate->crtc_id * 0x100); 1462 u32 val; 1463 bool dclk_inv; 1464 u8 dither_down_en = 0; 1465 u8 pre_dither_down_en = 0; 1466 char output_type_name[30] = {0}; 1467 1468 printf("VOP update mode to: %dx%d%s%d, type:%s for VP%d\n", 1469 mode->hdisplay, mode->vdisplay, 1470 mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p", 1471 mode->vscan, 1472 get_output_if_name(conn_state->output_if, output_type_name), 1473 cstate->crtc_id); 1474 1475 vop2_initial(vop2, state); 1476 dclk_inv = (mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1; 1477 val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE); 1478 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE); 1479 1480 if (conn_state->output_if & VOP_OUTPUT_IF_RGB) { 1481 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, 1482 1, false); 1483 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1484 RGB_MUX_SHIFT, cstate->crtc_id, false); 1485 vop2_grf_writel(vop2, RK3568_GRF_VO_CON1, EN_MASK, 1486 GRF_RGB_DCLK_INV_SHIFT, dclk_inv); 1487 } 1488 1489 if (conn_state->output_if & VOP_OUTPUT_IF_BT1120) { 1490 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, 1491 1, false); 1492 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, 1493 BT1120_EN_SHIFT, 1, false); 1494 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1495 RGB_MUX_SHIFT, cstate->crtc_id, false); 1496 vop2_grf_writel(vop2, RK3568_GRF_VO_CON1, EN_MASK, 1497 GRF_BT1120_CLK_INV_SHIFT, !dclk_inv); 1498 } 1499 1500 if (conn_state->output_if & VOP_OUTPUT_IF_BT656) { 1501 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT, 1502 1, false); 1503 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1504 RGB_MUX_SHIFT, cstate->crtc_id, false); 1505 vop2_grf_writel(vop2, RK3568_GRF_VO_CON1, EN_MASK, 1506 GRF_BT656_CLK_INV_SHIFT, !dclk_inv); 1507 } 1508 1509 if (conn_state->output_if & VOP_OUTPUT_IF_LVDS0) { 1510 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT, 1511 1, false); 1512 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1513 LVDS0_MUX_SHIFT, cstate->crtc_id, false); 1514 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1515 IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false); 1516 } 1517 1518 if (conn_state->output_if & VOP_OUTPUT_IF_LVDS1) { 1519 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS1_EN_SHIFT, 1520 1, false); 1521 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1522 LVDS1_MUX_SHIFT, cstate->crtc_id, false); 1523 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1524 IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false); 1525 } 1526 1527 if (conn_state->output_flags & 1528 (ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE | 1529 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)) { 1530 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 1531 LVDS_DUAL_EN_SHIFT, 1, false); 1532 if (conn_state->output_flags & 1533 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 1534 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 1535 LVDS_DUAL_LEFT_RIGHT_EN_SHIFT, 1, 1536 false); 1537 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) 1538 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 1539 LVDS_DUAL_SWAP_EN_SHIFT, 1, false); 1540 } 1541 1542 if (conn_state->output_if & VOP_OUTPUT_IF_MIPI0) { 1543 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT, 1544 1, false); 1545 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1546 MIPI0_MUX_SHIFT, cstate->crtc_id, false); 1547 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1548 IF_CRTL_MIPI_DCLK_POL_SHIT, dclk_inv, false); 1549 } 1550 1551 if (conn_state->output_if & VOP_OUTPUT_IF_MIPI1) { 1552 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI1_EN_SHIFT, 1553 1, false); 1554 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1555 MIPI1_MUX_SHIFT, cstate->crtc_id, false); 1556 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1557 IF_CRTL_MIPI_DCLK_POL_SHIT, dclk_inv, false); 1558 } 1559 1560 if (conn_state->output_flags & 1561 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { 1562 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, 1563 MIPI_DUAL_EN_SHIFT, 1, false); 1564 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) 1565 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 1566 EN_MASK, MIPI_DUAL_SWAP_EN_SHIFT, 1, 1567 false); 1568 } 1569 1570 if (conn_state->output_if & VOP_OUTPUT_IF_eDP0) { 1571 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, EDP0_EN_SHIFT, 1572 1, false); 1573 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1574 EDP0_MUX_SHIFT, cstate->crtc_id, false); 1575 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1576 IF_CRTL_EDP_DCLK_POL_SHIT, dclk_inv, false); 1577 } 1578 1579 if (conn_state->output_if & VOP_OUTPUT_IF_HDMI0) { 1580 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT, 1581 1, false); 1582 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 1583 HDMI0_MUX_SHIFT, cstate->crtc_id, false); 1584 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1585 IF_CRTL_HDMI_DCLK_POL_SHIT, 1, false); 1586 vop2_mask_write(vop2, RK3568_DSP_IF_POL, 1587 IF_CRTL_HDMI_PIN_POL_MASK, 1588 IF_CRTL_HDMI_PIN_POL_SHIT, val, false); 1589 } 1590 1591 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA && 1592 !(cstate->feature & VOP_FEATURE_OUTPUT_10BIT)) 1593 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 1594 1595 if (is_uv_swap(conn_state->bus_format, conn_state->output_mode)) 1596 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 1597 DATA_SWAP_MASK, DATA_SWAP_SHIFT, DSP_RB_SWAP, 1598 false); 1599 else 1600 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 1601 DATA_SWAP_MASK, DATA_SWAP_SHIFT, 0, 1602 false); 1603 1604 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, OUT_MODE_MASK, 1605 OUT_MODE_SHIFT, conn_state->output_mode, false); 1606 1607 switch (conn_state->bus_format) { 1608 case MEDIA_BUS_FMT_RGB565_1X16: 1609 dither_down_en = 1; 1610 break; 1611 case MEDIA_BUS_FMT_RGB666_1X18: 1612 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 1613 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 1614 case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA: 1615 dither_down_en = 1; 1616 break; 1617 case MEDIA_BUS_FMT_YUV8_1X24: 1618 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1619 dither_down_en = 0; 1620 pre_dither_down_en = 1; 1621 break; 1622 case MEDIA_BUS_FMT_YUV10_1X30: 1623 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1624 case MEDIA_BUS_FMT_RGB888_1X24: 1625 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 1626 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 1627 default: 1628 dither_down_en = 0; 1629 pre_dither_down_en = 0; 1630 break; 1631 } 1632 1633 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA) 1634 pre_dither_down_en = 0; 1635 else 1636 pre_dither_down_en = 1; 1637 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1638 DITHER_DOWN_EN_SHIFT, dither_down_en, false); 1639 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1640 PRE_DITHER_DOWN_EN_SHIFT, pre_dither_down_en, false); 1641 1642 yuv_overlay = is_yuv_output(conn_state->bus_format) ? 1 : 0; 1643 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, cstate->crtc_id, 1644 yuv_overlay, false); 1645 1646 cstate->yuv_overlay = yuv_overlay; 1647 1648 vop2_writel(vop2, RK3568_VP0_DSP_HTOTAL_HS_END + vp_offset, 1649 (htotal << 16) | hsync_len); 1650 val = hact_st << 16; 1651 val |= hact_end; 1652 vop2_writel(vop2, RK3568_VP0_DSP_HACT_ST_END + vp_offset, val); 1653 val = vact_st << 16; 1654 val |= vact_end; 1655 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END + vp_offset, val); 1656 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1657 u16 vact_st_f1 = vtotal + vact_st + 1; 1658 u16 vact_end_f1 = vact_st_f1 + vdisplay; 1659 1660 val = vact_st_f1 << 16 | vact_end_f1; 1661 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END_F1 + vp_offset, 1662 val); 1663 1664 val = vtotal << 16 | (vtotal + vsync_len); 1665 vop2_writel(vop2, RK3568_VP0_DSP_VS_ST_END_F1 + vp_offset, val); 1666 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1667 INTERLACE_EN_SHIFT, 1, false); 1668 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1669 DSP_FILED_POL, 1, false); 1670 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1671 P2I_EN_SHIFT, 1, false); 1672 vtotal += vtotal + 1; 1673 } else { 1674 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1675 INTERLACE_EN_SHIFT, 0, false); 1676 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1677 P2I_EN_SHIFT, 0, false); 1678 } 1679 vop2_writel(vop2, RK3568_VP0_DSP_VTOTAL_VS_END + vp_offset, 1680 (vtotal << 16) | vsync_len); 1681 val = !!(mode->flags & DRM_MODE_FLAG_DBLCLK); 1682 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1683 CORE_DCLK_DIV_EN_SHIFT, val, false); 1684 1685 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420) 1686 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 1687 DCLK_DIV2_MASK, DCLK_DIV2_SHIFT, 0x3, false); 1688 else 1689 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 1690 DCLK_DIV2_MASK, DCLK_DIV2_SHIFT, 0, false); 1691 1692 if (yuv_overlay) 1693 val = 0x20010200; 1694 else 1695 val = 0; 1696 vop2_writel(vop2, RK3568_VP0_DSP_BG + vp_offset, val); 1697 1698 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1699 POST_DSP_OUT_R2Y_SHIFT, yuv_overlay, false); 1700 1701 vop2_tv_config_update(state, vop2); 1702 vop2_post_config(state, vop2); 1703 1704 return 0; 1705 } 1706 1707 static void vop2_setup_scale(struct vop2 *vop2, uint32_t win_offset, 1708 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 1709 uint32_t dst_h) 1710 { 1711 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 1712 uint16_t hscl_filter_mode, vscl_filter_mode; 1713 uint8_t gt2 = 0, gt4 = 0; 1714 uint32_t xfac = 0, yfac = 0; 1715 uint16_t hsu_filter_mode = VOP2_SCALE_UP_BIC; 1716 uint16_t hsd_filter_mode = VOP2_SCALE_DOWN_BIL; 1717 uint16_t vsu_filter_mode = VOP2_SCALE_UP_BIL; 1718 uint16_t vsd_filter_mode = VOP2_SCALE_DOWN_BIL; 1719 1720 if (src_h >= (4 * dst_h)) 1721 gt4 = 1; 1722 else if (src_h >= (2 * dst_h)) 1723 gt2 = 1; 1724 1725 if (gt4) 1726 src_h >>= 2; 1727 else if (gt2) 1728 src_h >>= 1; 1729 1730 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 1731 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 1732 1733 if (yrgb_hor_scl_mode == SCALE_UP) 1734 hscl_filter_mode = hsu_filter_mode; 1735 else 1736 hscl_filter_mode = hsd_filter_mode; 1737 1738 if (yrgb_ver_scl_mode == SCALE_UP) 1739 vscl_filter_mode = vsu_filter_mode; 1740 else 1741 vscl_filter_mode = vsd_filter_mode; 1742 1743 /* 1744 * RK3568 VOP Esmart/Smart dsp_w should be even pixel 1745 * at scale down mode 1746 */ 1747 if ((yrgb_hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) { 1748 printf("win dst_w[%d] should align as 2 pixel\n", dst_w); 1749 dst_w += 1; 1750 } 1751 1752 xfac = vop2_scale_factor(yrgb_hor_scl_mode, hscl_filter_mode, src_w, dst_w); 1753 yfac = vop2_scale_factor(yrgb_ver_scl_mode, vscl_filter_mode, src_h, dst_h); 1754 vop2_writel(vop2, RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB + win_offset, 1755 yfac << 16 | xfac); 1756 1757 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, 1758 YRGB_GT2_MASK, YRGB_GT2_SHIFT, gt2, false); 1759 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, 1760 YRGB_GT4_MASK, YRGB_GT4_SHIFT, gt4, false); 1761 1762 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 1763 YRGB_XSCL_MODE_MASK, YRGB_XSCL_MODE_SHIFT, yrgb_hor_scl_mode, false); 1764 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 1765 YRGB_YSCL_MODE_MASK, YRGB_YSCL_MODE_SHIFT, yrgb_ver_scl_mode, false); 1766 1767 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 1768 YRGB_XSCL_FILTER_MODE_MASK, YRGB_XSCL_FILTER_MODE_SHIFT, 1769 hscl_filter_mode, false); 1770 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 1771 YRGB_YSCL_FILTER_MODE_MASK, YRGB_YSCL_FILTER_MODE_SHIFT, 1772 vscl_filter_mode, false); 1773 } 1774 1775 static int rockchip_vop2_set_plane(struct display_state *state) 1776 { 1777 struct crtc_state *cstate = &state->crtc_state; 1778 struct connector_state *conn_state = &state->conn_state; 1779 struct drm_display_mode *mode = &conn_state->mode; 1780 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 1781 struct vop2 *vop2 = cstate->private; 1782 int src_w = cstate->src_w; 1783 int src_h = cstate->src_h; 1784 int crtc_x = cstate->crtc_x; 1785 int crtc_y = cstate->crtc_y; 1786 int crtc_w = cstate->crtc_w; 1787 int crtc_h = cstate->crtc_h; 1788 int xvir = cstate->xvir; 1789 int y_mirror = 0; 1790 int csc_mode; 1791 u32 win_offset; 1792 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id); 1793 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; 1794 char plane_name[10] = {0}; 1795 1796 win_offset = vop2->data->win_data[primary_plane_id].reg_offset; 1797 if (crtc_w > cstate->max_output.width) { 1798 printf("ERROR: output w[%d] exceeded max width[%d]\n", 1799 crtc_w, cstate->max_output.width); 1800 return -EINVAL; 1801 } 1802 1803 /* 1804 * This is workaround solution for IC design: 1805 * esmart can't support scale down when actual_w % 16 == 1. 1806 */ 1807 if (src_w > crtc_w && (src_w & 0xf) == 1) { 1808 printf("WARN: vp%d unsupported act_w[%d] mode 16 = 1 when scale down\n", cstate->crtc_id, src_w); 1809 src_w -= 1; 1810 } 1811 1812 act_info = (src_h - 1) << 16; 1813 act_info |= (src_w - 1) & 0xffff; 1814 1815 dsp_info = (crtc_h - 1) << 16; 1816 dsp_info |= (crtc_w - 1) & 0xffff; 1817 1818 dsp_stx = crtc_x; 1819 dsp_sty = crtc_y; 1820 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 1821 1822 if (mode->flags & DRM_MODE_FLAG_YMIRROR) 1823 y_mirror = 1; 1824 else 1825 y_mirror = 0; 1826 1827 vop2_setup_scale(vop2, win_offset, src_w, src_h, crtc_w, crtc_h); 1828 1829 if (y_mirror) 1830 cstate->dma_addr += (src_h - 1) * xvir * 4; 1831 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, EN_MASK, 1832 YMIRROR_EN_SHIFT, y_mirror, false); 1833 1834 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, 1835 WIN_FORMAT_MASK, WIN_FORMAT_SHIFT, cstate->format, 1836 false); 1837 vop2_writel(vop2, RK3568_ESMART0_REGION0_VIR + win_offset, xvir); 1838 vop2_writel(vop2, RK3568_ESMART0_REGION0_YRGB_MST + win_offset, 1839 cstate->dma_addr); 1840 1841 vop2_writel(vop2, RK3568_ESMART0_REGION0_ACT_INFO + win_offset, 1842 act_info); 1843 vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_INFO + win_offset, 1844 dsp_info); 1845 vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_ST + win_offset, dsp_st); 1846 1847 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK, 1848 WIN_EN_SHIFT, 1, false); 1849 1850 csc_mode = vop2_convert_csc_mode(conn_state->color_space); 1851 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, EN_MASK, 1852 RGB2YUV_EN_SHIFT, 1853 is_yuv_output(conn_state->bus_format), false); 1854 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, CSC_MODE_MASK, 1855 CSC_MODE_SHIFT, csc_mode, false); 1856 1857 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 1858 1859 printf("VOP VP%d enable %s[%dx%d->%dx%d@%dx%d] fmt[%d] addr[0x%x]\n", 1860 cstate->crtc_id, get_plane_name(primary_plane_id, plane_name), 1861 src_w, src_h, crtc_w, crtc_h, crtc_x, crtc_y, cstate->format, 1862 cstate->dma_addr); 1863 1864 return 0; 1865 } 1866 1867 static int rockchip_vop2_prepare(struct display_state *state) 1868 { 1869 return 0; 1870 } 1871 1872 static int rockchip_vop2_enable(struct display_state *state) 1873 { 1874 struct crtc_state *cstate = &state->crtc_state; 1875 struct vop2 *vop2 = cstate->private; 1876 u32 vp_offset = (cstate->crtc_id * 0x100); 1877 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id); 1878 1879 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1880 STANDBY_EN_SHIFT, 0, false); 1881 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 1882 1883 return 0; 1884 } 1885 1886 static int rockchip_vop2_disable(struct display_state *state) 1887 { 1888 struct crtc_state *cstate = &state->crtc_state; 1889 struct vop2 *vop2 = cstate->private; 1890 u32 vp_offset = (cstate->crtc_id * 0x100); 1891 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id); 1892 1893 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 1894 STANDBY_EN_SHIFT, 1, false); 1895 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 1896 1897 return 0; 1898 } 1899 1900 static int rockchip_vop2_fixup_dts(struct display_state *state, void *blob) 1901 { 1902 struct crtc_state *cstate = &state->crtc_state; 1903 struct vop2 *vop2 = cstate->private; 1904 ofnode vp_node; 1905 struct device_node *port_parent_node = cstate->ports_node; 1906 static bool vop_fix_dts; 1907 const char *path; 1908 u32 plane_mask = 0; 1909 int vp_id = 0; 1910 1911 if (vop_fix_dts) 1912 return 0; 1913 1914 ofnode_for_each_subnode(vp_node, np_to_ofnode(port_parent_node)) { 1915 path = vp_node.np->full_name; 1916 plane_mask = vop2->vp_plane_mask[vp_id].plane_mask; 1917 1918 if (cstate->crtc->assign_plane) 1919 continue; 1920 printf("vp%d, plane_mask:0x%x, primary-id:%d\n", 1921 vp_id, plane_mask, 1922 vop2->vp_plane_mask[vp_id].primary_plane_id); 1923 1924 do_fixup_by_path_u32(blob, path, "rockchip,plane-mask", 1925 plane_mask, 1); 1926 do_fixup_by_path_u32(blob, path, "rockchip,primary-plane", 1927 vop2->vp_plane_mask[vp_id].primary_plane_id, 1); 1928 vp_id++; 1929 } 1930 1931 vop_fix_dts = true; 1932 1933 return 0; 1934 } 1935 1936 static struct vop2_vp_plane_mask rk356x_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = { 1937 { /* one display policy */ 1938 {/* main display */ 1939 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 1940 .attached_layers_nr = 6, 1941 .attached_layers = { 1942 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0, 1943 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_SMART1 1944 }, 1945 }, 1946 {/* second display */}, 1947 {/* third display */}, 1948 {/* fourth display */}, 1949 }, 1950 1951 { /* two display policy */ 1952 {/* main display */ 1953 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 1954 .attached_layers_nr = 3, 1955 .attached_layers = { 1956 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0 1957 }, 1958 }, 1959 1960 {/* second display */ 1961 .primary_plane_id = ROCKCHIP_VOP2_SMART1, 1962 .attached_layers_nr = 3, 1963 .attached_layers = { 1964 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_SMART1 1965 }, 1966 }, 1967 {/* third display */}, 1968 {/* fourth display */}, 1969 }, 1970 1971 { /* three display policy */ 1972 {/* main display */ 1973 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 1974 .attached_layers_nr = 3, 1975 .attached_layers = { 1976 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0 1977 }, 1978 }, 1979 1980 {/* second display */ 1981 .primary_plane_id = ROCKCHIP_VOP2_SMART1, 1982 .attached_layers_nr = 2, 1983 .attached_layers = { 1984 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_SMART1 1985 }, 1986 }, 1987 1988 {/* third display */ 1989 .primary_plane_id = ROCKCHIP_VOP2_ESMART1, 1990 .attached_layers_nr = 1, 1991 .attached_layers = { ROCKCHIP_VOP2_ESMART1 }, 1992 }, 1993 1994 {/* fourth display */}, 1995 }, 1996 1997 {/* reserved for four display policy */}, 1998 }; 1999 2000 static struct vop2_win_data rk3568_win_data[6] = { 2001 { 2002 .name = "Cluster0", 2003 .phys_id = ROCKCHIP_VOP2_CLUSTER0, 2004 .win_sel_port_offset = 0, 2005 .layer_sel_win_id = 0, 2006 .reg_offset = 0, 2007 }, 2008 2009 { 2010 .name = "Cluster1", 2011 .phys_id = ROCKCHIP_VOP2_CLUSTER1, 2012 .win_sel_port_offset = 1, 2013 .layer_sel_win_id = 1, 2014 .reg_offset = 0x200, 2015 }, 2016 2017 { 2018 .name = "Esmart0", 2019 .phys_id = ROCKCHIP_VOP2_ESMART0, 2020 .win_sel_port_offset = 4, 2021 .layer_sel_win_id = 2, 2022 .reg_offset = 0, 2023 }, 2024 2025 { 2026 .name = "Esmart1", 2027 .phys_id = ROCKCHIP_VOP2_ESMART1, 2028 .win_sel_port_offset = 5, 2029 .layer_sel_win_id = 6, 2030 .reg_offset = 0x200, 2031 }, 2032 2033 { 2034 .name = "Smart0", 2035 .phys_id = ROCKCHIP_VOP2_SMART0, 2036 .win_sel_port_offset = 6, 2037 .layer_sel_win_id = 3, 2038 .reg_offset = 0x400, 2039 }, 2040 2041 { 2042 .name = "Smart1", 2043 .phys_id = ROCKCHIP_VOP2_SMART1, 2044 .win_sel_port_offset = 7, 2045 .layer_sel_win_id = 7, 2046 .reg_offset = 0x600, 2047 }, 2048 }; 2049 2050 static struct vop2_vp_data rk3568_vp_data[3] = { 2051 { 2052 .feature = VOP_FEATURE_OUTPUT_10BIT, 2053 .pre_scan_max_dly = 42, 2054 .max_output = {4096, 2304}, 2055 }, 2056 { 2057 .feature = 0, 2058 .pre_scan_max_dly = 40, 2059 .max_output = {2048, 1536}, 2060 }, 2061 { 2062 .feature = 0, 2063 .pre_scan_max_dly = 40, 2064 .max_output = {1920, 1080}, 2065 }, 2066 }; 2067 2068 const struct vop2_data rk3568_vop = { 2069 .nr_vps = 3, 2070 .vp_data = rk3568_vp_data, 2071 .win_data = rk3568_win_data, 2072 .plane_mask = rk356x_vp_plane_mask[0], 2073 .nr_layers = 6, 2074 .nr_mixers = 5, 2075 .nr_gammas = 1, 2076 }; 2077 2078 const struct rockchip_crtc_funcs rockchip_vop2_funcs = { 2079 .preinit = rockchip_vop2_preinit, 2080 .prepare = rockchip_vop2_prepare, 2081 .init = rockchip_vop2_init, 2082 .set_plane = rockchip_vop2_set_plane, 2083 .enable = rockchip_vop2_enable, 2084 .disable = rockchip_vop2_disable, 2085 .fixup_dts = rockchip_vop2_fixup_dts, 2086 }; 2087