1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <regmap.h> 14 #include <asm/arch/cpu.h> 15 #include <asm/unaligned.h> 16 #include <asm/io.h> 17 #include <linux/list.h> 18 #include <linux/log2.h> 19 #include <linux/media-bus-format.h> 20 #include <clk.h> 21 #include <asm/arch/clock.h> 22 #include <linux/err.h> 23 #include <linux/ioport.h> 24 #include <dm/device.h> 25 #include <dm/read.h> 26 #include <fixp-arith.h> 27 #include <syscon.h> 28 #include <linux/iopoll.h> 29 #include <dm/uclass-internal.h> 30 31 #include "rockchip_display.h" 32 #include "rockchip_crtc.h" 33 #include "rockchip_connector.h" 34 35 /* System registers definition */ 36 #define RK3568_REG_CFG_DONE 0x000 37 #define CFG_DONE_EN BIT(15) 38 39 #define RK3568_VERSION_INFO 0x004 40 #define EN_MASK 1 41 42 #define RK3568_AUTO_GATING_CTRL 0x008 43 44 #define RK3568_SYS_AXI_LUT_CTRL 0x024 45 #define LUT_DMA_EN_SHIFT 0 46 47 #define RK3568_DSP_IF_EN 0x028 48 #define RGB_EN_SHIFT 0 49 #define RK3588_DP0_EN_SHIFT 0 50 #define RK3588_DP1_EN_SHIFT 1 51 #define RK3588_RGB_EN_SHIFT 8 52 #define HDMI0_EN_SHIFT 1 53 #define EDP0_EN_SHIFT 3 54 #define RK3588_EDP0_EN_SHIFT 2 55 #define RK3588_HDMI0_EN_SHIFT 3 56 #define MIPI0_EN_SHIFT 4 57 #define RK3588_EDP1_EN_SHIFT 4 58 #define RK3588_HDMI1_EN_SHIFT 5 59 #define RK3588_MIPI0_EN_SHIFT 6 60 #define MIPI1_EN_SHIFT 20 61 #define RK3588_MIPI1_EN_SHIFT 7 62 #define LVDS0_EN_SHIFT 5 63 #define LVDS1_EN_SHIFT 24 64 #define BT1120_EN_SHIFT 6 65 #define BT656_EN_SHIFT 7 66 #define IF_MUX_MASK 3 67 #define RGB_MUX_SHIFT 8 68 #define HDMI0_MUX_SHIFT 10 69 #define RK3588_DP0_MUX_SHIFT 12 70 #define RK3588_DP1_MUX_SHIFT 14 71 #define EDP0_MUX_SHIFT 14 72 #define RK3588_HDMI_EDP0_MUX_SHIFT 16 73 #define RK3588_HDMI_EDP1_MUX_SHIFT 18 74 #define MIPI0_MUX_SHIFT 16 75 #define RK3588_MIPI0_MUX_SHIFT 20 76 #define MIPI1_MUX_SHIFT 21 77 #define LVDS0_MUX_SHIFT 18 78 #define LVDS1_MUX_SHIFT 25 79 80 #define RK3568_DSP_IF_CTRL 0x02c 81 #define LVDS_DUAL_EN_SHIFT 0 82 #define LVDS_DUAL_LEFT_RIGHT_EN_SHIFT 1 83 #define LVDS_DUAL_SWAP_EN_SHIFT 2 84 #define RK3588_HDMI_DUAL_EN_SHIFT 8 85 #define RK3588_EDP_DUAL_EN_SHIFT 8 86 #define RK3588_DP_DUAL_EN_SHIFT 9 87 #define RK3568_MIPI_DUAL_EN_SHIFT 10 88 #define RK3588_MIPI_DSI0_MODE_SEL_SHIFT 11 89 #define RK3588_MIPI_DSI1_MODE_SEL_SHIFT 12 90 91 #define RK3568_DSP_IF_POL 0x030 92 #define IF_CTRL_REG_DONE_IMD_MASK 1 93 #define IF_CTRL_REG_DONE_IMD_SHIFT 28 94 #define IF_CRTL_MIPI_DCLK_POL_SHIT 19 95 #define IF_CRTL_EDP_DCLK_POL_SHIT 15 96 #define IF_CRTL_HDMI_DCLK_POL_SHIT 7 97 #define IF_CRTL_HDMI_PIN_POL_MASK 0x7 98 #define IF_CRTL_HDMI_PIN_POL_SHIT 4 99 100 #define RK3588_DP0_PIN_POL_SHIFT 8 101 #define RK3588_DP1_PIN_POL_SHIFT 12 102 #define RK3588_IF_PIN_POL_MASK 0x7 103 104 #define IF_CRTL_RGB_LVDS_DCLK_POL_SHIT 3 105 106 #define HDMI_EDP0_DCLK_DIV_SHIFT 16 107 #define HDMI_EDP0_PIXCLK_DIV_SHIFT 18 108 #define HDMI_EDP1_DCLK_DIV_SHIFT 20 109 #define HDMI_EDP1_PIXCLK_DIV_SHIFT 22 110 #define MIPI0_PIXCLK_DIV_SHIFT 24 111 #define MIPI1_PIXCLK_DIV_SHIFT 26 112 113 #define RK3568_SYS_OTP_WIN_EN 0x50 114 #define OTP_WIN_EN_SHIFT 0 115 #define RK3568_SYS_LUT_PORT_SEL 0x58 116 #define GAMMA_PORT_SEL_MASK 0x3 117 #define GAMMA_PORT_SEL_SHIFT 0 118 #define PORT_MERGE_EN_SHIFT 16 119 120 #define RK3568_SYS_PD_CTRL 0x034 121 #define RK3568_VP0_LINE_FLAG 0x70 122 #define RK3568_VP1_LINE_FLAG 0x74 123 #define RK3568_VP2_LINE_FLAG 0x78 124 #define RK3568_SYS0_INT_EN 0x80 125 #define RK3568_SYS0_INT_CLR 0x84 126 #define RK3568_SYS0_INT_STATUS 0x88 127 #define RK3568_SYS1_INT_EN 0x90 128 #define RK3568_SYS1_INT_CLR 0x94 129 #define RK3568_SYS1_INT_STATUS 0x98 130 #define RK3568_VP0_INT_EN 0xA0 131 #define RK3568_VP0_INT_CLR 0xA4 132 #define RK3568_VP0_INT_STATUS 0xA8 133 #define RK3568_VP1_INT_EN 0xB0 134 #define RK3568_VP1_INT_CLR 0xB4 135 #define RK3568_VP1_INT_STATUS 0xB8 136 #define RK3568_VP2_INT_EN 0xC0 137 #define RK3568_VP2_INT_CLR 0xC4 138 #define RK3568_VP2_INT_STATUS 0xC8 139 #define RK3588_CLUSTER0_PD_EN_SHIFT 0 140 #define RK3588_CLUSTER1_PD_EN_SHIFT 1 141 #define RK3588_CLUSTER2_PD_EN_SHIFT 2 142 #define RK3588_CLUSTER3_PD_EN_SHIFT 3 143 #define RK3588_DSC_8K_PD_EN_SHIFT 5 144 #define RK3588_DSC_4K_PD_EN_SHIFT 6 145 #define RK3588_ESMART_PD_EN_SHIFT 7 146 147 #define RK3568_SYS_STATUS0 0x60 148 #define RK3588_CLUSTER0_PD_STATUS_SHIFT 8 149 #define RK3588_CLUSTER1_PD_STATUS_SHIFT 9 150 #define RK3588_CLUSTER2_PD_STATUS_SHIFT 10 151 #define RK3588_CLUSTER3_PD_STATUS_SHIFT 11 152 #define RK3588_DSC_8K_PD_STATUS_SHIFT 13 153 #define RK3588_DSC_4K_PD_STATUS_SHIFT 14 154 #define RK3588_ESMART_PD_STATUS_SHIFT 15 155 156 #define RK3568_SYS_CTRL_LINE_FLAG0 0x70 157 #define LINE_FLAG_NUM_MASK 0x1fff 158 #define RK3568_DSP_LINE_FLAG_NUM0_SHIFT 0 159 #define RK3568_DSP_LINE_FLAG_NUM1_SHIFT 16 160 161 /* DSC CTRL registers definition */ 162 #define RK3588_DSC_8K_SYS_CTRL 0x200 163 #define DSC_PORT_SEL_MASK 0x3 164 #define DSC_PORT_SEL_SHIFT 0 165 #define DSC_MAN_MODE_MASK 0x1 166 #define DSC_MAN_MODE_SHIFT 2 167 #define DSC_INTERFACE_MODE_MASK 0x3 168 #define DSC_INTERFACE_MODE_SHIFT 4 169 #define DSC_PIXEL_NUM_MASK 0x3 170 #define DSC_PIXEL_NUM_SHIFT 6 171 #define DSC_PXL_CLK_DIV_MASK 0x1 172 #define DSC_PXL_CLK_DIV_SHIFT 8 173 #define DSC_CDS_CLK_DIV_MASK 0x3 174 #define DSC_CDS_CLK_DIV_SHIFT 12 175 #define DSC_TXP_CLK_DIV_MASK 0x3 176 #define DSC_TXP_CLK_DIV_SHIFT 14 177 #define DSC_INIT_DLY_MODE_MASK 0x1 178 #define DSC_INIT_DLY_MODE_SHIFT 16 179 #define DSC_SCAN_EN_SHIFT 17 180 #define DSC_HALT_EN_SHIFT 18 181 182 #define RK3588_DSC_8K_RST 0x204 183 #define RST_DEASSERT_MASK 0x1 184 #define RST_DEASSERT_SHIFT 0 185 186 #define RK3588_DSC_8K_CFG_DONE 0x208 187 #define DSC_CFG_DONE_SHIFT 0 188 189 #define RK3588_DSC_8K_INIT_DLY 0x20C 190 #define DSC_INIT_DLY_NUM_MASK 0xffff 191 #define DSC_INIT_DLY_NUM_SHIFT 0 192 #define SCAN_TIMING_PARA_IMD_EN_SHIFT 16 193 194 #define RK3588_DSC_8K_HTOTAL_HS_END 0x210 195 #define DSC_HTOTAL_PW_MASK 0xffffffff 196 #define DSC_HTOTAL_PW_SHIFT 0 197 198 #define RK3588_DSC_8K_HACT_ST_END 0x214 199 #define DSC_HACT_ST_END_MASK 0xffffffff 200 #define DSC_HACT_ST_END_SHIFT 0 201 202 #define RK3588_DSC_8K_VTOTAL_VS_END 0x218 203 #define DSC_VTOTAL_PW_MASK 0xffffffff 204 #define DSC_VTOTAL_PW_SHIFT 0 205 206 #define RK3588_DSC_8K_VACT_ST_END 0x21C 207 #define DSC_VACT_ST_END_MASK 0xffffffff 208 #define DSC_VACT_ST_END_SHIFT 0 209 210 #define RK3588_DSC_8K_STATUS 0x220 211 212 /* Overlay registers definition */ 213 #define RK3568_OVL_CTRL 0x600 214 #define OVL_MODE_SEL_MASK 0x1 215 #define OVL_MODE_SEL_SHIFT 0 216 #define OVL_PORT_MUX_REG_DONE_IMD_SHIFT 28 217 #define RK3568_OVL_LAYER_SEL 0x604 218 #define LAYER_SEL_MASK 0xf 219 220 #define RK3568_OVL_PORT_SEL 0x608 221 #define PORT_MUX_MASK 0xf 222 #define PORT_MUX_SHIFT 0 223 #define LAYER_SEL_PORT_MASK 0x3 224 #define LAYER_SEL_PORT_SHIFT 16 225 226 #define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610 227 #define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614 228 #define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618 229 #define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C 230 #define RK3568_MIX0_SRC_COLOR_CTRL 0x650 231 #define RK3568_MIX0_DST_COLOR_CTRL 0x654 232 #define RK3568_MIX0_SRC_ALPHA_CTRL 0x658 233 #define RK3568_MIX0_DST_ALPHA_CTRL 0x65C 234 #define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0 235 #define RK3568_HDR0_DST_COLOR_CTRL 0x6C4 236 #define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8 237 #define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC 238 #define RK3568_VP0_BG_MIX_CTRL 0x6E0 239 #define BG_MIX_CTRL_MASK 0xff 240 #define BG_MIX_CTRL_SHIFT 24 241 #define RK3568_VP1_BG_MIX_CTRL 0x6E4 242 #define RK3568_VP2_BG_MIX_CTRL 0x6E8 243 #define RK3568_CLUSTER_DLY_NUM 0x6F0 244 #define RK3568_SMART_DLY_NUM 0x6F8 245 246 /* Video Port registers definition */ 247 #define RK3568_VP0_DSP_CTRL 0xC00 248 #define OUT_MODE_MASK 0xf 249 #define OUT_MODE_SHIFT 0 250 #define DATA_SWAP_MASK 0x1f 251 #define DATA_SWAP_SHIFT 8 252 #define DSP_BG_SWAP 0x1 253 #define DSP_RB_SWAP 0x2 254 #define DSP_RG_SWAP 0x4 255 #define DSP_DELTA_SWAP 0x8 256 #define CORE_DCLK_DIV_EN_SHIFT 4 257 #define P2I_EN_SHIFT 5 258 #define DSP_FILED_POL 6 259 #define INTERLACE_EN_SHIFT 7 260 #define POST_DSP_OUT_R2Y_SHIFT 15 261 #define PRE_DITHER_DOWN_EN_SHIFT 16 262 #define DITHER_DOWN_EN_SHIFT 17 263 #define DSP_LUT_EN_SHIFT 28 264 265 #define STANDBY_EN_SHIFT 31 266 267 #define RK3568_VP0_MIPI_CTRL 0xC04 268 #define DCLK_DIV2_SHIFT 4 269 #define DCLK_DIV2_MASK 0x3 270 #define MIPI_DUAL_EN_SHIFT 20 271 #define MIPI_DUAL_SWAP_EN_SHIFT 21 272 #define EDPI_TE_EN 28 273 #define EDPI_WMS_HOLD_EN 30 274 #define EDPI_WMS_FS 31 275 276 277 #define RK3568_VP0_COLOR_BAR_CTRL 0xC08 278 #define RK3568_VP0_3D_LUT_CTRL 0xC10 279 #define VP0_3D_LUT_EN_SHIFT 0 280 #define VP0_3D_LUT_UPDATE_SHIFT 2 281 282 #define RK3588_VP0_CLK_CTRL 0xC0C 283 #define DCLK_CORE_DIV_SHIFT 0 284 #define DCLK_OUT_DIV_SHIFT 2 285 286 #define RK3568_VP0_3D_LUT_MST 0xC20 287 288 #define RK3568_VP0_DSP_BG 0xC2C 289 #define RK3568_VP0_PRE_SCAN_HTIMING 0xC30 290 #define RK3568_VP0_POST_DSP_HACT_INFO 0xC34 291 #define RK3568_VP0_POST_DSP_VACT_INFO 0xC38 292 #define RK3568_VP0_POST_SCL_FACTOR_YRGB 0xC3C 293 #define RK3568_VP0_POST_SCL_CTRL 0xC40 294 #define RK3568_VP0_POST_DSP_VACT_INFO_F1 0xC44 295 #define RK3568_VP0_DSP_HTOTAL_HS_END 0xC48 296 #define RK3568_VP0_DSP_HACT_ST_END 0xC4C 297 #define RK3568_VP0_DSP_VTOTAL_VS_END 0xC50 298 #define RK3568_VP0_DSP_VACT_ST_END 0xC54 299 #define RK3568_VP0_DSP_VS_ST_END_F1 0xC58 300 #define RK3568_VP0_DSP_VACT_ST_END_F1 0xC5C 301 302 #define RK3568_VP0_BCSH_CTRL 0xC60 303 #define BCSH_CTRL_Y2R_SHIFT 0 304 #define BCSH_CTRL_Y2R_MASK 0x1 305 #define BCSH_CTRL_Y2R_CSC_MODE_SHIFT 2 306 #define BCSH_CTRL_Y2R_CSC_MODE_MASK 0x3 307 #define BCSH_CTRL_R2Y_SHIFT 4 308 #define BCSH_CTRL_R2Y_MASK 0x1 309 #define BCSH_CTRL_R2Y_CSC_MODE_SHIFT 6 310 #define BCSH_CTRL_R2Y_CSC_MODE_MASK 0x3 311 312 #define RK3568_VP0_BCSH_BCS 0xC64 313 #define BCSH_BRIGHTNESS_SHIFT 0 314 #define BCSH_BRIGHTNESS_MASK 0xFF 315 #define BCSH_CONTRAST_SHIFT 8 316 #define BCSH_CONTRAST_MASK 0x1FF 317 #define BCSH_SATURATION_SHIFT 20 318 #define BCSH_SATURATION_MASK 0x3FF 319 #define BCSH_OUT_MODE_SHIFT 30 320 #define BCSH_OUT_MODE_MASK 0x3 321 322 #define RK3568_VP0_BCSH_H 0xC68 323 #define BCSH_SIN_HUE_SHIFT 0 324 #define BCSH_SIN_HUE_MASK 0x1FF 325 #define BCSH_COS_HUE_SHIFT 16 326 #define BCSH_COS_HUE_MASK 0x1FF 327 328 #define RK3568_VP0_BCSH_COLOR 0xC6C 329 #define BCSH_EN_SHIFT 31 330 #define BCSH_EN_MASK 1 331 332 #define RK3568_VP1_DSP_CTRL 0xD00 333 #define RK3568_VP1_MIPI_CTRL 0xD04 334 #define RK3568_VP1_COLOR_BAR_CTRL 0xD08 335 #define RK3568_VP1_PRE_SCAN_HTIMING 0xD30 336 #define RK3568_VP1_POST_DSP_HACT_INFO 0xD34 337 #define RK3568_VP1_POST_DSP_VACT_INFO 0xD38 338 #define RK3568_VP1_POST_SCL_FACTOR_YRGB 0xD3C 339 #define RK3568_VP1_POST_SCL_CTRL 0xD40 340 #define RK3568_VP1_DSP_HACT_INFO 0xD34 341 #define RK3568_VP1_DSP_VACT_INFO 0xD38 342 #define RK3568_VP1_POST_DSP_VACT_INFO_F1 0xD44 343 #define RK3568_VP1_DSP_HTOTAL_HS_END 0xD48 344 #define RK3568_VP1_DSP_HACT_ST_END 0xD4C 345 #define RK3568_VP1_DSP_VTOTAL_VS_END 0xD50 346 #define RK3568_VP1_DSP_VACT_ST_END 0xD54 347 #define RK3568_VP1_DSP_VS_ST_END_F1 0xD58 348 #define RK3568_VP1_DSP_VACT_ST_END_F1 0xD5C 349 350 #define RK3568_VP2_DSP_CTRL 0xE00 351 #define RK3568_VP2_MIPI_CTRL 0xE04 352 #define RK3568_VP2_COLOR_BAR_CTRL 0xE08 353 #define RK3568_VP2_PRE_SCAN_HTIMING 0xE30 354 #define RK3568_VP2_POST_DSP_HACT_INFO 0xE34 355 #define RK3568_VP2_POST_DSP_VACT_INFO 0xE38 356 #define RK3568_VP2_POST_SCL_FACTOR_YRGB 0xE3C 357 #define RK3568_VP2_POST_SCL_CTRL 0xE40 358 #define RK3568_VP2_DSP_HACT_INFO 0xE34 359 #define RK3568_VP2_DSP_VACT_INFO 0xE38 360 #define RK3568_VP2_POST_DSP_VACT_INFO_F1 0xE44 361 #define RK3568_VP2_DSP_HTOTAL_HS_END 0xE48 362 #define RK3568_VP2_DSP_HACT_ST_END 0xE4C 363 #define RK3568_VP2_DSP_VTOTAL_VS_END 0xE50 364 #define RK3568_VP2_DSP_VACT_ST_END 0xE54 365 #define RK3568_VP2_DSP_VS_ST_END_F1 0xE58 366 #define RK3568_VP2_DSP_VACT_ST_END_F1 0xE5C 367 368 /* Cluster0 register definition */ 369 #define RK3568_CLUSTER0_WIN0_CTRL0 0x1000 370 #define CLUSTER_YUV2RGB_EN_SHIFT 8 371 #define CLUSTER_RGB2YUV_EN_SHIFT 9 372 #define CLUSTER_CSC_MODE_SHIFT 10 373 #define CLUSTER_YRGB_XSCL_MODE_SHIFT 12 374 #define CLUSTER_YRGB_YSCL_MODE_SHIFT 14 375 #define RK3568_CLUSTER0_WIN0_CTRL1 0x1004 376 #define CLUSTER_YRGB_GT2_SHIFT 28 377 #define CLUSTER_YRGB_GT4_SHIFT 29 378 #define RK3568_CLUSTER0_WIN0_CTRL2 0x1008 379 #define CLUSTER_AXI_YRGB_ID_MASK 0x1f 380 #define CLUSTER_AXI_YRGB_ID_SHIFT 0 381 #define CLUSTER_AXI_UV_ID_MASK 0x1f 382 #define CLUSTER_AXI_UV_ID_SHIFT 5 383 384 #define RK3568_CLUSTER0_WIN0_YRGB_MST 0x1010 385 #define RK3568_CLUSTER0_WIN0_CBR_MST 0x1014 386 #define RK3568_CLUSTER0_WIN0_VIR 0x1018 387 #define RK3568_CLUSTER0_WIN0_ACT_INFO 0x1020 388 #define RK3568_CLUSTER0_WIN0_DSP_INFO 0x1024 389 #define RK3568_CLUSTER0_WIN0_DSP_ST 0x1028 390 #define RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB 0x1030 391 #define RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE 0x1054 392 #define RK3568_CLUSTER0_WIN0_AFBCD_HDR_PTR 0x1058 393 #define RK3568_CLUSTER0_WIN0_AFBCD_VIR_WIDTH 0x105C 394 #define RK3568_CLUSTER0_WIN0_AFBCD_PIC_SIZE 0x1060 395 #define RK3568_CLUSTER0_WIN0_AFBCD_PIC_OFFSET 0x1064 396 #define RK3568_CLUSTER0_WIN0_AFBCD_DSP_OFFSET 0x1068 397 #define RK3568_CLUSTER0_WIN0_AFBCD_CTRL 0x106C 398 399 #define RK3568_CLUSTER0_WIN1_CTRL0 0x1080 400 #define RK3568_CLUSTER0_WIN1_CTRL1 0x1084 401 #define RK3568_CLUSTER0_WIN1_YRGB_MST 0x1090 402 #define RK3568_CLUSTER0_WIN1_CBR_MST 0x1094 403 #define RK3568_CLUSTER0_WIN1_VIR 0x1098 404 #define RK3568_CLUSTER0_WIN1_ACT_INFO 0x10A0 405 #define RK3568_CLUSTER0_WIN1_DSP_INFO 0x10A4 406 #define RK3568_CLUSTER0_WIN1_DSP_ST 0x10A8 407 #define RK3568_CLUSTER0_WIN1_SCL_FACTOR_YRGB 0x10B0 408 #define RK3568_CLUSTER0_WIN1_AFBCD_ROTATE_MODE 0x10D4 409 #define RK3568_CLUSTER0_WIN1_AFBCD_HDR_PTR 0x10D8 410 #define RK3568_CLUSTER0_WIN1_AFBCD_VIR_WIDTH 0x10DC 411 #define RK3568_CLUSTER0_WIN1_AFBCD_PIC_SIZE 0x10E0 412 #define RK3568_CLUSTER0_WIN1_AFBCD_PIC_OFFSET 0x10E4 413 #define RK3568_CLUSTER0_WIN1_AFBCD_DSP_OFFSET 0x10E8 414 #define RK3568_CLUSTER0_WIN1_AFBCD_CTRL 0x10EC 415 416 #define RK3568_CLUSTER0_CTRL 0x1100 417 #define CLUSTER_EN_SHIFT 0 418 #define CLUSTER_AXI_ID_MASK 0x1 419 #define CLUSTER_AXI_ID_SHIFT 13 420 421 #define RK3568_CLUSTER1_WIN0_CTRL0 0x1200 422 #define RK3568_CLUSTER1_WIN0_CTRL1 0x1204 423 #define RK3568_CLUSTER1_WIN0_YRGB_MST 0x1210 424 #define RK3568_CLUSTER1_WIN0_CBR_MST 0x1214 425 #define RK3568_CLUSTER1_WIN0_VIR 0x1218 426 #define RK3568_CLUSTER1_WIN0_ACT_INFO 0x1220 427 #define RK3568_CLUSTER1_WIN0_DSP_INFO 0x1224 428 #define RK3568_CLUSTER1_WIN0_DSP_ST 0x1228 429 #define RK3568_CLUSTER1_WIN0_SCL_FACTOR_YRGB 0x1230 430 #define RK3568_CLUSTER1_WIN0_AFBCD_ROTATE_MODE 0x1254 431 #define RK3568_CLUSTER1_WIN0_AFBCD_HDR_PTR 0x1258 432 #define RK3568_CLUSTER1_WIN0_AFBCD_VIR_WIDTH 0x125C 433 #define RK3568_CLUSTER1_WIN0_AFBCD_PIC_SIZE 0x1260 434 #define RK3568_CLUSTER1_WIN0_AFBCD_PIC_OFFSET 0x1264 435 #define RK3568_CLUSTER1_WIN0_AFBCD_DSP_OFFSET 0x1268 436 #define RK3568_CLUSTER1_WIN0_AFBCD_CTRL 0x126C 437 438 #define RK3568_CLUSTER1_WIN1_CTRL0 0x1280 439 #define RK3568_CLUSTER1_WIN1_CTRL1 0x1284 440 #define RK3568_CLUSTER1_WIN1_YRGB_MST 0x1290 441 #define RK3568_CLUSTER1_WIN1_CBR_MST 0x1294 442 #define RK3568_CLUSTER1_WIN1_VIR 0x1298 443 #define RK3568_CLUSTER1_WIN1_ACT_INFO 0x12A0 444 #define RK3568_CLUSTER1_WIN1_DSP_INFO 0x12A4 445 #define RK3568_CLUSTER1_WIN1_DSP_ST 0x12A8 446 #define RK3568_CLUSTER1_WIN1_SCL_FACTOR_YRGB 0x12B0 447 #define RK3568_CLUSTER1_WIN1_AFBCD_ROTATE_MODE 0x12D4 448 #define RK3568_CLUSTER1_WIN1_AFBCD_HDR_PTR 0x12D8 449 #define RK3568_CLUSTER1_WIN1_AFBCD_VIR_WIDTH 0x12DC 450 #define RK3568_CLUSTER1_WIN1_AFBCD_PIC_SIZE 0x12E0 451 #define RK3568_CLUSTER1_WIN1_AFBCD_PIC_OFFSET 0x12E4 452 #define RK3568_CLUSTER1_WIN1_AFBCD_DSP_OFFSET 0x12E8 453 #define RK3568_CLUSTER1_WIN1_AFBCD_CTRL 0x12EC 454 455 #define RK3568_CLUSTER1_CTRL 0x1300 456 457 /* Esmart register definition */ 458 #define RK3568_ESMART0_CTRL0 0x1800 459 #define RGB2YUV_EN_SHIFT 1 460 #define CSC_MODE_SHIFT 2 461 #define CSC_MODE_MASK 0x3 462 463 #define RK3568_ESMART0_CTRL1 0x1804 464 #define ESMART_AXI_YRGB_ID_MASK 0x1f 465 #define ESMART_AXI_YRGB_ID_SHIFT 4 466 #define ESMART_AXI_UV_ID_MASK 0x1f 467 #define ESMART_AXI_UV_ID_SHIFT 12 468 #define YMIRROR_EN_SHIFT 31 469 470 #define RK3568_ESMART0_AXI_CTRL 0x1808 471 #define ESMART_AXI_ID_MASK 0x1 472 #define ESMART_AXI_ID_SHIFT 1 473 474 #define RK3568_ESMART0_REGION0_CTRL 0x1810 475 #define REGION0_RB_SWAP_SHIFT 14 476 #define WIN_EN_SHIFT 0 477 #define WIN_FORMAT_MASK 0x1f 478 #define WIN_FORMAT_SHIFT 1 479 480 #define RK3568_ESMART0_REGION0_YRGB_MST 0x1814 481 #define RK3568_ESMART0_REGION0_CBR_MST 0x1818 482 #define RK3568_ESMART0_REGION0_VIR 0x181C 483 #define RK3568_ESMART0_REGION0_ACT_INFO 0x1820 484 #define RK3568_ESMART0_REGION0_DSP_INFO 0x1824 485 #define RK3568_ESMART0_REGION0_DSP_ST 0x1828 486 #define RK3568_ESMART0_REGION0_SCL_CTRL 0x1830 487 #define YRGB_XSCL_MODE_MASK 0x3 488 #define YRGB_XSCL_MODE_SHIFT 0 489 #define YRGB_XSCL_FILTER_MODE_MASK 0x3 490 #define YRGB_XSCL_FILTER_MODE_SHIFT 2 491 #define YRGB_YSCL_MODE_MASK 0x3 492 #define YRGB_YSCL_MODE_SHIFT 4 493 #define YRGB_YSCL_FILTER_MODE_MASK 0x3 494 #define YRGB_YSCL_FILTER_MODE_SHIFT 6 495 496 #define RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB 0x1834 497 #define RK3568_ESMART0_REGION0_SCL_FACTOR_CBR 0x1838 498 #define RK3568_ESMART0_REGION0_SCL_OFFSET 0x183C 499 #define RK3568_ESMART0_REGION1_CTRL 0x1840 500 #define YRGB_GT2_MASK 0x1 501 #define YRGB_GT2_SHIFT 8 502 #define YRGB_GT4_MASK 0x1 503 #define YRGB_GT4_SHIFT 9 504 505 #define RK3568_ESMART0_REGION1_YRGB_MST 0x1844 506 #define RK3568_ESMART0_REGION1_CBR_MST 0x1848 507 #define RK3568_ESMART0_REGION1_VIR 0x184C 508 #define RK3568_ESMART0_REGION1_ACT_INFO 0x1850 509 #define RK3568_ESMART0_REGION1_DSP_INFO 0x1854 510 #define RK3568_ESMART0_REGION1_DSP_ST 0x1858 511 #define RK3568_ESMART0_REGION1_SCL_CTRL 0x1860 512 #define RK3568_ESMART0_REGION1_SCL_FACTOR_YRGB 0x1864 513 #define RK3568_ESMART0_REGION1_SCL_FACTOR_CBR 0x1868 514 #define RK3568_ESMART0_REGION1_SCL_OFFSET 0x186C 515 #define RK3568_ESMART0_REGION2_CTRL 0x1870 516 #define RK3568_ESMART0_REGION2_YRGB_MST 0x1874 517 #define RK3568_ESMART0_REGION2_CBR_MST 0x1878 518 #define RK3568_ESMART0_REGION2_VIR 0x187C 519 #define RK3568_ESMART0_REGION2_ACT_INFO 0x1880 520 #define RK3568_ESMART0_REGION2_DSP_INFO 0x1884 521 #define RK3568_ESMART0_REGION2_DSP_ST 0x1888 522 #define RK3568_ESMART0_REGION2_SCL_CTRL 0x1890 523 #define RK3568_ESMART0_REGION2_SCL_FACTOR_YRGB 0x1894 524 #define RK3568_ESMART0_REGION2_SCL_FACTOR_CBR 0x1898 525 #define RK3568_ESMART0_REGION2_SCL_OFFSET 0x189C 526 #define RK3568_ESMART0_REGION3_CTRL 0x18A0 527 #define RK3568_ESMART0_REGION3_YRGB_MST 0x18A4 528 #define RK3568_ESMART0_REGION3_CBR_MST 0x18A8 529 #define RK3568_ESMART0_REGION3_VIR 0x18AC 530 #define RK3568_ESMART0_REGION3_ACT_INFO 0x18B0 531 #define RK3568_ESMART0_REGION3_DSP_INFO 0x18B4 532 #define RK3568_ESMART0_REGION3_DSP_ST 0x18B8 533 #define RK3568_ESMART0_REGION3_SCL_CTRL 0x18C0 534 #define RK3568_ESMART0_REGION3_SCL_FACTOR_YRGB 0x18C4 535 #define RK3568_ESMART0_REGION3_SCL_FACTOR_CBR 0x18C8 536 #define RK3568_ESMART0_REGION3_SCL_OFFSET 0x18CC 537 538 #define RK3568_ESMART1_CTRL0 0x1A00 539 #define RK3568_ESMART1_CTRL1 0x1A04 540 #define RK3568_ESMART1_REGION0_CTRL 0x1A10 541 #define RK3568_ESMART1_REGION0_YRGB_MST 0x1A14 542 #define RK3568_ESMART1_REGION0_CBR_MST 0x1A18 543 #define RK3568_ESMART1_REGION0_VIR 0x1A1C 544 #define RK3568_ESMART1_REGION0_ACT_INFO 0x1A20 545 #define RK3568_ESMART1_REGION0_DSP_INFO 0x1A24 546 #define RK3568_ESMART1_REGION0_DSP_ST 0x1A28 547 #define RK3568_ESMART1_REGION0_SCL_CTRL 0x1A30 548 #define RK3568_ESMART1_REGION0_SCL_FACTOR_YRGB 0x1A34 549 #define RK3568_ESMART1_REGION0_SCL_FACTOR_CBR 0x1A38 550 #define RK3568_ESMART1_REGION0_SCL_OFFSET 0x1A3C 551 #define RK3568_ESMART1_REGION1_CTRL 0x1A40 552 #define RK3568_ESMART1_REGION1_YRGB_MST 0x1A44 553 #define RK3568_ESMART1_REGION1_CBR_MST 0x1A48 554 #define RK3568_ESMART1_REGION1_VIR 0x1A4C 555 #define RK3568_ESMART1_REGION1_ACT_INFO 0x1A50 556 #define RK3568_ESMART1_REGION1_DSP_INFO 0x1A54 557 #define RK3568_ESMART1_REGION1_DSP_ST 0x1A58 558 #define RK3568_ESMART1_REGION1_SCL_CTRL 0x1A60 559 #define RK3568_ESMART1_REGION1_SCL_FACTOR_YRGB 0x1A64 560 #define RK3568_ESMART1_REGION1_SCL_FACTOR_CBR 0x1A68 561 #define RK3568_ESMART1_REGION1_SCL_OFFSET 0x1A6C 562 #define RK3568_ESMART1_REGION2_CTRL 0x1A70 563 #define RK3568_ESMART1_REGION2_YRGB_MST 0x1A74 564 #define RK3568_ESMART1_REGION2_CBR_MST 0x1A78 565 #define RK3568_ESMART1_REGION2_VIR 0x1A7C 566 #define RK3568_ESMART1_REGION2_ACT_INFO 0x1A80 567 #define RK3568_ESMART1_REGION2_DSP_INFO 0x1A84 568 #define RK3568_ESMART1_REGION2_DSP_ST 0x1A88 569 #define RK3568_ESMART1_REGION2_SCL_CTRL 0x1A90 570 #define RK3568_ESMART1_REGION2_SCL_FACTOR_YRGB 0x1A94 571 #define RK3568_ESMART1_REGION2_SCL_FACTOR_CBR 0x1A98 572 #define RK3568_ESMART1_REGION2_SCL_OFFSET 0x1A9C 573 #define RK3568_ESMART1_REGION3_CTRL 0x1AA0 574 #define RK3568_ESMART1_REGION3_YRGB_MST 0x1AA4 575 #define RK3568_ESMART1_REGION3_CBR_MST 0x1AA8 576 #define RK3568_ESMART1_REGION3_VIR 0x1AAC 577 #define RK3568_ESMART1_REGION3_ACT_INFO 0x1AB0 578 #define RK3568_ESMART1_REGION3_DSP_INFO 0x1AB4 579 #define RK3568_ESMART1_REGION3_DSP_ST 0x1AB8 580 #define RK3568_ESMART1_REGION3_SCL_CTRL 0x1AC0 581 #define RK3568_ESMART1_REGION3_SCL_FACTOR_YRGB 0x1AC4 582 #define RK3568_ESMART1_REGION3_SCL_FACTOR_CBR 0x1AC8 583 #define RK3568_ESMART1_REGION3_SCL_OFFSET 0x1ACC 584 585 #define RK3568_SMART0_CTRL0 0x1C00 586 #define RK3568_SMART0_CTRL1 0x1C04 587 #define RK3568_SMART0_REGION0_CTRL 0x1C10 588 #define RK3568_SMART0_REGION0_YRGB_MST 0x1C14 589 #define RK3568_SMART0_REGION0_CBR_MST 0x1C18 590 #define RK3568_SMART0_REGION0_VIR 0x1C1C 591 #define RK3568_SMART0_REGION0_ACT_INFO 0x1C20 592 #define RK3568_SMART0_REGION0_DSP_INFO 0x1C24 593 #define RK3568_SMART0_REGION0_DSP_ST 0x1C28 594 #define RK3568_SMART0_REGION0_SCL_CTRL 0x1C30 595 #define RK3568_SMART0_REGION0_SCL_FACTOR_YRGB 0x1C34 596 #define RK3568_SMART0_REGION0_SCL_FACTOR_CBR 0x1C38 597 #define RK3568_SMART0_REGION0_SCL_OFFSET 0x1C3C 598 #define RK3568_SMART0_REGION1_CTRL 0x1C40 599 #define RK3568_SMART0_REGION1_YRGB_MST 0x1C44 600 #define RK3568_SMART0_REGION1_CBR_MST 0x1C48 601 #define RK3568_SMART0_REGION1_VIR 0x1C4C 602 #define RK3568_SMART0_REGION1_ACT_INFO 0x1C50 603 #define RK3568_SMART0_REGION1_DSP_INFO 0x1C54 604 #define RK3568_SMART0_REGION1_DSP_ST 0x1C58 605 #define RK3568_SMART0_REGION1_SCL_CTRL 0x1C60 606 #define RK3568_SMART0_REGION1_SCL_FACTOR_YRGB 0x1C64 607 #define RK3568_SMART0_REGION1_SCL_FACTOR_CBR 0x1C68 608 #define RK3568_SMART0_REGION1_SCL_OFFSET 0x1C6C 609 #define RK3568_SMART0_REGION2_CTRL 0x1C70 610 #define RK3568_SMART0_REGION2_YRGB_MST 0x1C74 611 #define RK3568_SMART0_REGION2_CBR_MST 0x1C78 612 #define RK3568_SMART0_REGION2_VIR 0x1C7C 613 #define RK3568_SMART0_REGION2_ACT_INFO 0x1C80 614 #define RK3568_SMART0_REGION2_DSP_INFO 0x1C84 615 #define RK3568_SMART0_REGION2_DSP_ST 0x1C88 616 #define RK3568_SMART0_REGION2_SCL_CTRL 0x1C90 617 #define RK3568_SMART0_REGION2_SCL_FACTOR_YRGB 0x1C94 618 #define RK3568_SMART0_REGION2_SCL_FACTOR_CBR 0x1C98 619 #define RK3568_SMART0_REGION2_SCL_OFFSET 0x1C9C 620 #define RK3568_SMART0_REGION3_CTRL 0x1CA0 621 #define RK3568_SMART0_REGION3_YRGB_MST 0x1CA4 622 #define RK3568_SMART0_REGION3_CBR_MST 0x1CA8 623 #define RK3568_SMART0_REGION3_VIR 0x1CAC 624 #define RK3568_SMART0_REGION3_ACT_INFO 0x1CB0 625 #define RK3568_SMART0_REGION3_DSP_INFO 0x1CB4 626 #define RK3568_SMART0_REGION3_DSP_ST 0x1CB8 627 #define RK3568_SMART0_REGION3_SCL_CTRL 0x1CC0 628 #define RK3568_SMART0_REGION3_SCL_FACTOR_YRGB 0x1CC4 629 #define RK3568_SMART0_REGION3_SCL_FACTOR_CBR 0x1CC8 630 #define RK3568_SMART0_REGION3_SCL_OFFSET 0x1CCC 631 632 #define RK3568_SMART1_CTRL0 0x1E00 633 #define RK3568_SMART1_CTRL1 0x1E04 634 #define RK3568_SMART1_REGION0_CTRL 0x1E10 635 #define RK3568_SMART1_REGION0_YRGB_MST 0x1E14 636 #define RK3568_SMART1_REGION0_CBR_MST 0x1E18 637 #define RK3568_SMART1_REGION0_VIR 0x1E1C 638 #define RK3568_SMART1_REGION0_ACT_INFO 0x1E20 639 #define RK3568_SMART1_REGION0_DSP_INFO 0x1E24 640 #define RK3568_SMART1_REGION0_DSP_ST 0x1E28 641 #define RK3568_SMART1_REGION0_SCL_CTRL 0x1E30 642 #define RK3568_SMART1_REGION0_SCL_FACTOR_YRGB 0x1E34 643 #define RK3568_SMART1_REGION0_SCL_FACTOR_CBR 0x1E38 644 #define RK3568_SMART1_REGION0_SCL_OFFSET 0x1E3C 645 #define RK3568_SMART1_REGION1_CTRL 0x1E40 646 #define RK3568_SMART1_REGION1_YRGB_MST 0x1E44 647 #define RK3568_SMART1_REGION1_CBR_MST 0x1E48 648 #define RK3568_SMART1_REGION1_VIR 0x1E4C 649 #define RK3568_SMART1_REGION1_ACT_INFO 0x1E50 650 #define RK3568_SMART1_REGION1_DSP_INFO 0x1E54 651 #define RK3568_SMART1_REGION1_DSP_ST 0x1E58 652 #define RK3568_SMART1_REGION1_SCL_CTRL 0x1E60 653 #define RK3568_SMART1_REGION1_SCL_FACTOR_YRGB 0x1E64 654 #define RK3568_SMART1_REGION1_SCL_FACTOR_CBR 0x1E68 655 #define RK3568_SMART1_REGION1_SCL_OFFSET 0x1E6C 656 #define RK3568_SMART1_REGION2_CTRL 0x1E70 657 #define RK3568_SMART1_REGION2_YRGB_MST 0x1E74 658 #define RK3568_SMART1_REGION2_CBR_MST 0x1E78 659 #define RK3568_SMART1_REGION2_VIR 0x1E7C 660 #define RK3568_SMART1_REGION2_ACT_INFO 0x1E80 661 #define RK3568_SMART1_REGION2_DSP_INFO 0x1E84 662 #define RK3568_SMART1_REGION2_DSP_ST 0x1E88 663 #define RK3568_SMART1_REGION2_SCL_CTRL 0x1E90 664 #define RK3568_SMART1_REGION2_SCL_FACTOR_YRGB 0x1E94 665 #define RK3568_SMART1_REGION2_SCL_FACTOR_CBR 0x1E98 666 #define RK3568_SMART1_REGION2_SCL_OFFSET 0x1E9C 667 #define RK3568_SMART1_REGION3_CTRL 0x1EA0 668 #define RK3568_SMART1_REGION3_YRGB_MST 0x1EA4 669 #define RK3568_SMART1_REGION3_CBR_MST 0x1EA8 670 #define RK3568_SMART1_REGION3_VIR 0x1EAC 671 #define RK3568_SMART1_REGION3_ACT_INFO 0x1EB0 672 #define RK3568_SMART1_REGION3_DSP_INFO 0x1EB4 673 #define RK3568_SMART1_REGION3_DSP_ST 0x1EB8 674 #define RK3568_SMART1_REGION3_SCL_CTRL 0x1EC0 675 #define RK3568_SMART1_REGION3_SCL_FACTOR_YRGB 0x1EC4 676 #define RK3568_SMART1_REGION3_SCL_FACTOR_CBR 0x1EC8 677 #define RK3568_SMART1_REGION3_SCL_OFFSET 0x1ECC 678 679 /* DSC 8K/4K register definition */ 680 #define RK3588_DSC_8K_PPS0_3 0x4000 681 #define RK3588_DSC_8K_CTRL0 0x40A0 682 #define DSC_EN_SHIFT 0 683 #define DSC_RBIT_SHIFT 2 684 #define DSC_RBYT_SHIFT 3 685 #define DSC_FLAL_SHIFT 4 686 #define DSC_MER_SHIFT 5 687 #define DSC_EPB_SHIFT 6 688 #define DSC_EPL_SHIFT 7 689 #define DSC_NSLC_SHIFT 16 690 #define DSC_SBO_SHIFT 28 691 #define DSC_IFEP_SHIFT 29 692 #define DSC_PPS_UPD_SHIFT 31 693 694 #define RK3588_DSC_8K_CTRL1 0x40A4 695 #define RK3588_DSC_8K_STS0 0x40A8 696 #define RK3588_DSC_8K_ERS 0x40C4 697 698 #define RK3588_DSC_4K_PPS0_3 0x4100 699 #define RK3588_DSC_4K_CTRL0 0x41A0 700 #define RK3588_DSC_4K_CTRL1 0x41A4 701 #define RK3588_DSC_4K_STS0 0x41A8 702 #define RK3588_DSC_4K_ERS 0x41C4 703 704 #define RK3568_MAX_REG 0x1ED0 705 706 #define RK3568_GRF_VO_CON1 0x0364 707 #define GRF_BT656_CLK_INV_SHIFT 1 708 #define GRF_BT1120_CLK_INV_SHIFT 2 709 #define GRF_RGB_DCLK_INV_SHIFT 3 710 711 #define RK3588_GRF_VOP_CON2 0x0008 712 #define RK3588_GRF_EDP0_ENABLE_SHIFT 0 713 #define RK3588_GRF_HDMITX0_ENABLE_SHIFT 1 714 #define RK3588_GRF_EDP1_ENABLE_SHIFT 3 715 #define RK3588_GRF_HDMITX1_ENABLE_SHIFT 4 716 717 #define RK3588_GRF_VO1_CON0 0x0000 718 #define HDMI_SYNC_POL_MASK 0x3 719 #define HDMI0_SYNC_POL_SHIFT 5 720 #define HDMI1_SYNC_POL_SHIFT 7 721 722 #define RK3588_PMU_BISR_CON3 0x20C 723 #define RK3588_PD_CLUSTER0_REPAIR_EN_SHIFT 9 724 #define RK3588_PD_CLUSTER1_REPAIR_EN_SHIFT 10 725 #define RK3588_PD_CLUSTER2_REPAIR_EN_SHIFT 11 726 #define RK3588_PD_CLUSTER3_REPAIR_EN_SHIFT 12 727 #define RK3588_PD_DSC_8K_REPAIR_EN_SHIFT 13 728 #define RK3588_PD_DSC_4K_REPAIR_EN_SHIFT 14 729 #define RK3588_PD_ESMART_REPAIR_EN_SHIFT 15 730 731 #define RK3588_PMU_BISR_STATUS5 0x294 732 #define RK3588_PD_CLUSTER0_PWR_STAT_SHIFI 9 733 #define RK3588_PD_CLUSTER1_PWR_STAT_SHIFI 10 734 #define RK3588_PD_CLUSTER2_PWR_STAT_SHIFI 11 735 #define RK3588_PD_CLUSTER3_PWR_STAT_SHIFI 12 736 #define RK3588_PD_DSC_8K_PWR_STAT_SHIFI 13 737 #define RK3588_PD_DSC_4K_PWR_STAT_SHIFI 14 738 #define RK3588_PD_ESMART_PWR_STAT_SHIFI 15 739 740 #define VOP2_LAYER_MAX 8 741 742 #define VOP2_MAX_VP_OUTPUT_WIDTH 4096 743 744 #define VOP_FEATURE_OUTPUT_10BIT BIT(0) 745 746 /* KHz */ 747 #define VOP2_MAX_DCLK_RATE 600000 748 749 /* 750 * vop2 dsc id 751 */ 752 #define ROCKCHIP_VOP2_DSC_8K 0 753 #define ROCKCHIP_VOP2_DSC_4K 1 754 755 /* 756 * vop2 internal power domain id, 757 * should be all none zero, 0 will be 758 * treat as invalid; 759 */ 760 #define VOP2_PD_CLUSTER0 BIT(0) 761 #define VOP2_PD_CLUSTER1 BIT(1) 762 #define VOP2_PD_CLUSTER2 BIT(2) 763 #define VOP2_PD_CLUSTER3 BIT(3) 764 #define VOP2_PD_DSC_8K BIT(5) 765 #define VOP2_PD_DSC_4K BIT(6) 766 #define VOP2_PD_ESMART BIT(7) 767 768 enum vop2_csc_format { 769 CSC_BT601L, 770 CSC_BT709L, 771 CSC_BT601F, 772 CSC_BT2020, 773 }; 774 775 enum vop2_pol { 776 HSYNC_POSITIVE = 0, 777 VSYNC_POSITIVE = 1, 778 DEN_NEGATIVE = 2, 779 DCLK_INVERT = 3 780 }; 781 782 enum vop2_bcsh_out_mode { 783 BCSH_OUT_MODE_BLACK, 784 BCSH_OUT_MODE_BLUE, 785 BCSH_OUT_MODE_COLOR_BAR, 786 BCSH_OUT_MODE_NORMAL_VIDEO, 787 }; 788 789 #define _VOP_REG(off, _mask, _shift, _write_mask) \ 790 { \ 791 .offset = off, \ 792 .mask = _mask, \ 793 .shift = _shift, \ 794 .write_mask = _write_mask, \ 795 } 796 797 #define VOP_REG(off, _mask, _shift) \ 798 _VOP_REG(off, _mask, _shift, false) 799 enum dither_down_mode { 800 RGB888_TO_RGB565 = 0x0, 801 RGB888_TO_RGB666 = 0x1 802 }; 803 804 enum vop2_video_ports_id { 805 VOP2_VP0, 806 VOP2_VP1, 807 VOP2_VP2, 808 VOP2_VP3, 809 VOP2_VP_MAX, 810 }; 811 812 enum vop2_layer_type { 813 CLUSTER_LAYER = 0, 814 ESMART_LAYER = 1, 815 SMART_LAYER = 2, 816 }; 817 818 /* This define must same with kernel win phy id */ 819 enum vop2_layer_phy_id { 820 ROCKCHIP_VOP2_CLUSTER0 = 0, 821 ROCKCHIP_VOP2_CLUSTER1, 822 ROCKCHIP_VOP2_ESMART0, 823 ROCKCHIP_VOP2_ESMART1, 824 ROCKCHIP_VOP2_SMART0, 825 ROCKCHIP_VOP2_SMART1, 826 ROCKCHIP_VOP2_CLUSTER2, 827 ROCKCHIP_VOP2_CLUSTER3, 828 ROCKCHIP_VOP2_ESMART2, 829 ROCKCHIP_VOP2_ESMART3, 830 ROCKCHIP_VOP2_LAYER_MAX, 831 }; 832 833 enum vop2_scale_up_mode { 834 VOP2_SCALE_UP_NRST_NBOR, 835 VOP2_SCALE_UP_BIL, 836 VOP2_SCALE_UP_BIC, 837 }; 838 839 enum vop2_scale_down_mode { 840 VOP2_SCALE_DOWN_NRST_NBOR, 841 VOP2_SCALE_DOWN_BIL, 842 VOP2_SCALE_DOWN_AVG, 843 }; 844 845 enum scale_mode { 846 SCALE_NONE = 0x0, 847 SCALE_UP = 0x1, 848 SCALE_DOWN = 0x2 849 }; 850 851 enum vop_dsc_interface_mode { 852 VOP_DSC_IF_DISABLE = 0, 853 VOP_DSC_IF_HDMI = 1, 854 VOP_DSC_IF_MIPI_DS_MODE = 2, 855 VOP_DSC_IF_MIPI_VIDEO_MODE = 3, 856 }; 857 858 struct vop2_layer { 859 u8 id; 860 /** 861 * @win_phys_id: window id of the layer selected. 862 * Every layer must make sure to select different 863 * windows of others. 864 */ 865 u8 win_phys_id; 866 }; 867 868 struct vop2_power_domain_data { 869 u8 id; 870 u8 parent_id; 871 /* 872 * @module_id_mask: module id of which module this power domain is belongs to. 873 * PD_CLUSTER0,1,2,3 only belongs to CLUSTER0/1/2/3, PD_Esmart0 shared by Esmart1/2/3 874 */ 875 u32 module_id_mask; 876 }; 877 878 struct vop2_win_data { 879 char *name; 880 u8 phys_id; 881 enum vop2_layer_type type; 882 u8 win_sel_port_offset; 883 u8 layer_sel_win_id; 884 u8 axi_id; 885 u8 axi_uv_id; 886 u8 axi_yrgb_id; 887 u8 splice_win_id; 888 u8 pd_id; 889 u32 reg_offset; 890 bool splice_mode_right; 891 }; 892 893 struct vop2_vp_data { 894 u32 feature; 895 u8 pre_scan_max_dly; 896 u8 splice_vp_id; 897 struct vop_rect max_output; 898 u32 max_dclk; 899 }; 900 901 struct vop2_plane_table { 902 enum vop2_layer_phy_id plane_id; 903 enum vop2_layer_type plane_type; 904 }; 905 906 struct vop2_vp_plane_mask { 907 u8 primary_plane_id; /* use this win to show logo */ 908 u8 attached_layers_nr; /* number layers attach to this vp */ 909 u8 attached_layers[VOP2_LAYER_MAX]; /* the layers attached to this vp */ 910 u32 plane_mask; 911 int cursor_plane_id; 912 }; 913 914 struct vop2_dsc_data { 915 u8 id; 916 u8 pd_id; 917 u8 max_slice_num; 918 u8 max_linebuf_depth; /* used to generate the bitstream */ 919 u8 min_bits_per_pixel; /* bit num after encoder compress */ 920 const char *dsc_txp_clk_src_name; 921 const char *dsc_txp_clk_name; 922 const char *dsc_pxl_clk_name; 923 const char *dsc_cds_clk_name; 924 }; 925 926 struct dsc_error_info { 927 u32 dsc_error_val; 928 char dsc_error_info[50]; 929 }; 930 931 struct vop2_data { 932 u32 version; 933 struct vop2_vp_data *vp_data; 934 struct vop2_win_data *win_data; 935 struct vop2_vp_plane_mask *plane_mask; 936 struct vop2_plane_table *plane_table; 937 struct vop2_power_domain_data *pd; 938 struct vop2_dsc_data *dsc; 939 struct dsc_error_info *dsc_error_ecw; 940 struct dsc_error_info *dsc_error_buffer_flow; 941 u8 nr_vps; 942 u8 nr_layers; 943 u8 nr_mixers; 944 u8 nr_gammas; 945 u8 nr_pd; 946 u8 nr_dscs; 947 u8 nr_dsc_ecw; 948 u8 nr_dsc_buffer_flow; 949 u32 reg_len; 950 }; 951 952 struct vop2 { 953 u32 *regsbak; 954 void *regs; 955 void *grf; 956 void *vop_grf; 957 void *vo1_grf; 958 void *sys_pmu; 959 u32 reg_len; 960 u32 version; 961 bool global_init; 962 const struct vop2_data *data; 963 struct vop2_vp_plane_mask vp_plane_mask[VOP2_VP_MAX]; 964 }; 965 966 static struct vop2 *rockchip_vop2; 967 /* 968 * bli_sd_factor = (src - 1) / (dst - 1) << 12; 969 * avg_sd_factor: 970 * bli_su_factor: 971 * bic_su_factor: 972 * = (src - 1) / (dst - 1) << 16; 973 * 974 * gt2 enable: dst get one line from two line of the src 975 * gt4 enable: dst get one line from four line of the src. 976 * 977 */ 978 #define VOP2_BILI_SCL_DN(src, dst) (((src - 1) << 12) / (dst - 1)) 979 #define VOP2_COMMON_SCL(src, dst) (((src - 1) << 16) / (dst - 1)) 980 981 #define VOP2_BILI_SCL_FAC_CHECK(src, dst, fac) \ 982 (fac * (dst - 1) >> 12 < (src - 1)) 983 #define VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac) \ 984 (fac * (dst - 1) >> 16 < (src - 1)) 985 986 static uint16_t vop2_scale_factor(enum scale_mode mode, 987 int32_t filter_mode, 988 uint32_t src, uint32_t dst) 989 { 990 uint32_t fac = 0; 991 int i = 0; 992 993 if (mode == SCALE_NONE) 994 return 0; 995 996 /* 997 * A workaround to avoid zero div. 998 */ 999 if ((dst == 1) || (src == 1)) { 1000 dst = dst + 1; 1001 src = src + 1; 1002 } 1003 1004 if ((mode == SCALE_DOWN) && (filter_mode == VOP2_SCALE_DOWN_BIL)) { 1005 fac = VOP2_BILI_SCL_DN(src, dst); 1006 for (i = 0; i < 100; i++) { 1007 if (VOP2_BILI_SCL_FAC_CHECK(src, dst, fac)) 1008 break; 1009 fac -= 1; 1010 printf("down fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac); 1011 } 1012 } else { 1013 fac = VOP2_COMMON_SCL(src, dst); 1014 for (i = 0; i < 100; i++) { 1015 if (VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac)) 1016 break; 1017 fac -= 1; 1018 printf("up fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac); 1019 } 1020 } 1021 1022 return fac; 1023 } 1024 1025 static inline enum scale_mode scl_get_scl_mode(int src, int dst) 1026 { 1027 if (src < dst) 1028 return SCALE_UP; 1029 else if (src > dst) 1030 return SCALE_DOWN; 1031 1032 return SCALE_NONE; 1033 } 1034 1035 static u8 rk3588_vop2_vp_primary_plane_order[VOP2_VP_MAX] = { 1036 ROCKCHIP_VOP2_ESMART0, 1037 ROCKCHIP_VOP2_ESMART1, 1038 ROCKCHIP_VOP2_ESMART2, 1039 ROCKCHIP_VOP2_ESMART3, 1040 }; 1041 1042 static u8 rk3568_vop2_vp_primary_plane_order[VOP2_VP_MAX] = { 1043 ROCKCHIP_VOP2_SMART0, 1044 ROCKCHIP_VOP2_SMART1, 1045 ROCKCHIP_VOP2_ESMART1, 1046 }; 1047 1048 static inline int interpolate(int x1, int y1, int x2, int y2, int x) 1049 { 1050 return y1 + (y2 - y1) * (x - x1) / (x2 - x1); 1051 } 1052 1053 static int vop2_get_primary_plane(struct vop2 *vop2, u32 plane_mask) 1054 { 1055 int i = 0; 1056 u8 *vop2_vp_primary_plane_order; 1057 u8 default_primary_plane; 1058 1059 if (vop2->version == VOP_VERSION_RK3588) { 1060 vop2_vp_primary_plane_order = rk3588_vop2_vp_primary_plane_order; 1061 default_primary_plane = ROCKCHIP_VOP2_ESMART0; 1062 } else { 1063 vop2_vp_primary_plane_order = rk3568_vop2_vp_primary_plane_order; 1064 default_primary_plane = ROCKCHIP_VOP2_SMART0; 1065 } 1066 1067 for (i = 0; i < vop2->data->nr_vps; i++) { 1068 if (plane_mask & BIT(vop2_vp_primary_plane_order[i])) 1069 return vop2_vp_primary_plane_order[i]; 1070 } 1071 1072 return default_primary_plane; 1073 } 1074 1075 static inline u16 scl_cal_scale(int src, int dst, int shift) 1076 { 1077 return ((src * 2 - 3) << (shift - 1)) / (dst - 1); 1078 } 1079 1080 static inline u16 scl_cal_scale2(int src, int dst) 1081 { 1082 return ((src - 1) << 12) / (dst - 1); 1083 } 1084 1085 static inline void vop2_writel(struct vop2 *vop2, u32 offset, u32 v) 1086 { 1087 writel(v, vop2->regs + offset); 1088 vop2->regsbak[offset >> 2] = v; 1089 } 1090 1091 static inline u32 vop2_readl(struct vop2 *vop2, u32 offset) 1092 { 1093 return readl(vop2->regs + offset); 1094 } 1095 1096 static inline void vop2_mask_write(struct vop2 *vop2, u32 offset, 1097 u32 mask, u32 shift, u32 v, 1098 bool write_mask) 1099 { 1100 if (!mask) 1101 return; 1102 1103 if (write_mask) { 1104 v = ((v & mask) << shift) | (mask << (shift + 16)); 1105 } else { 1106 u32 cached_val = vop2->regsbak[offset >> 2]; 1107 1108 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 1109 vop2->regsbak[offset >> 2] = v; 1110 } 1111 1112 writel(v, vop2->regs + offset); 1113 } 1114 1115 static inline void vop2_grf_writel(struct vop2 *vop, void *grf_base, u32 offset, 1116 u32 mask, u32 shift, u32 v) 1117 { 1118 u32 val = 0; 1119 1120 val = (v << shift) | (mask << (shift + 16)); 1121 writel(val, grf_base + offset); 1122 } 1123 1124 static inline u32 vop2_grf_readl(struct vop2 *vop, void *grf_base, u32 offset, 1125 u32 mask, u32 shift) 1126 { 1127 return (readl(grf_base + offset) >> shift) & mask; 1128 } 1129 1130 static char* get_output_if_name(u32 output_if, char *name) 1131 { 1132 if (output_if & VOP_OUTPUT_IF_RGB) 1133 strcat(name, " RGB"); 1134 if (output_if & VOP_OUTPUT_IF_BT1120) 1135 strcat(name, " BT1120"); 1136 if (output_if & VOP_OUTPUT_IF_BT656) 1137 strcat(name, " BT656"); 1138 if (output_if & VOP_OUTPUT_IF_LVDS0) 1139 strcat(name, " LVDS0"); 1140 if (output_if & VOP_OUTPUT_IF_LVDS1) 1141 strcat(name, " LVDS1"); 1142 if (output_if & VOP_OUTPUT_IF_MIPI0) 1143 strcat(name, " MIPI0"); 1144 if (output_if & VOP_OUTPUT_IF_MIPI1) 1145 strcat(name, " MIPI1"); 1146 if (output_if & VOP_OUTPUT_IF_eDP0) 1147 strcat(name, " eDP0"); 1148 if (output_if & VOP_OUTPUT_IF_eDP1) 1149 strcat(name, " eDP1"); 1150 if (output_if & VOP_OUTPUT_IF_DP0) 1151 strcat(name, " DP0"); 1152 if (output_if & VOP_OUTPUT_IF_DP1) 1153 strcat(name, " DP1"); 1154 if (output_if & VOP_OUTPUT_IF_HDMI0) 1155 strcat(name, " HDMI0"); 1156 if (output_if & VOP_OUTPUT_IF_HDMI1) 1157 strcat(name, " HDMI1"); 1158 1159 return name; 1160 } 1161 1162 static char *get_plane_name(int plane_id, char *name) 1163 { 1164 switch (plane_id) { 1165 case ROCKCHIP_VOP2_CLUSTER0: 1166 strcat(name, "Cluster0"); 1167 break; 1168 case ROCKCHIP_VOP2_CLUSTER1: 1169 strcat(name, "Cluster1"); 1170 break; 1171 case ROCKCHIP_VOP2_ESMART0: 1172 strcat(name, "Esmart0"); 1173 break; 1174 case ROCKCHIP_VOP2_ESMART1: 1175 strcat(name, "Esmart1"); 1176 break; 1177 case ROCKCHIP_VOP2_SMART0: 1178 strcat(name, "Smart0"); 1179 break; 1180 case ROCKCHIP_VOP2_SMART1: 1181 strcat(name, "Smart1"); 1182 break; 1183 case ROCKCHIP_VOP2_CLUSTER2: 1184 strcat(name, "Cluster2"); 1185 break; 1186 case ROCKCHIP_VOP2_CLUSTER3: 1187 strcat(name, "Cluster3"); 1188 break; 1189 case ROCKCHIP_VOP2_ESMART2: 1190 strcat(name, "Esmart2"); 1191 break; 1192 case ROCKCHIP_VOP2_ESMART3: 1193 strcat(name, "Esmart3"); 1194 break; 1195 } 1196 1197 return name; 1198 } 1199 1200 static bool is_yuv_output(u32 bus_format) 1201 { 1202 switch (bus_format) { 1203 case MEDIA_BUS_FMT_YUV8_1X24: 1204 case MEDIA_BUS_FMT_YUV10_1X30: 1205 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1206 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1207 case MEDIA_BUS_FMT_YUYV8_2X8: 1208 case MEDIA_BUS_FMT_YVYU8_2X8: 1209 case MEDIA_BUS_FMT_UYVY8_2X8: 1210 case MEDIA_BUS_FMT_VYUY8_2X8: 1211 case MEDIA_BUS_FMT_YUYV8_1X16: 1212 case MEDIA_BUS_FMT_YVYU8_1X16: 1213 case MEDIA_BUS_FMT_UYVY8_1X16: 1214 case MEDIA_BUS_FMT_VYUY8_1X16: 1215 return true; 1216 default: 1217 return false; 1218 } 1219 } 1220 1221 static int vop2_convert_csc_mode(int csc_mode) 1222 { 1223 switch (csc_mode) { 1224 case V4L2_COLORSPACE_SMPTE170M: 1225 case V4L2_COLORSPACE_470_SYSTEM_M: 1226 case V4L2_COLORSPACE_470_SYSTEM_BG: 1227 return CSC_BT601L; 1228 case V4L2_COLORSPACE_REC709: 1229 case V4L2_COLORSPACE_SMPTE240M: 1230 case V4L2_COLORSPACE_DEFAULT: 1231 return CSC_BT709L; 1232 case V4L2_COLORSPACE_JPEG: 1233 return CSC_BT601F; 1234 case V4L2_COLORSPACE_BT2020: 1235 return CSC_BT2020; 1236 default: 1237 return CSC_BT709L; 1238 } 1239 } 1240 1241 static bool is_uv_swap(u32 bus_format, u32 output_mode) 1242 { 1243 /* 1244 * FIXME: 1245 * 1246 * There is no media type for YUV444 output, 1247 * so when out_mode is AAAA or P888, assume output is YUV444 on 1248 * yuv format. 1249 * 1250 * From H/W testing, YUV444 mode need a rb swap. 1251 */ 1252 if (bus_format == MEDIA_BUS_FMT_YVYU8_1X16 || 1253 bus_format == MEDIA_BUS_FMT_VYUY8_1X16 || 1254 bus_format == MEDIA_BUS_FMT_YVYU8_2X8 || 1255 bus_format == MEDIA_BUS_FMT_VYUY8_2X8 || 1256 ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 1257 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 1258 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 1259 output_mode == ROCKCHIP_OUT_MODE_P888))) 1260 return true; 1261 else 1262 return false; 1263 } 1264 1265 static inline bool is_hot_plug_devices(int output_type) 1266 { 1267 switch (output_type) { 1268 case DRM_MODE_CONNECTOR_HDMIA: 1269 case DRM_MODE_CONNECTOR_HDMIB: 1270 case DRM_MODE_CONNECTOR_TV: 1271 case DRM_MODE_CONNECTOR_DisplayPort: 1272 case DRM_MODE_CONNECTOR_VGA: 1273 case DRM_MODE_CONNECTOR_Unknown: 1274 return true; 1275 default: 1276 return false; 1277 } 1278 } 1279 1280 static struct vop2_win_data *vop2_find_win_by_phys_id(struct vop2 *vop2, int phys_id) 1281 { 1282 int i = 0; 1283 1284 for (i = 0; i < vop2->data->nr_layers; i++) { 1285 if (vop2->data->win_data[i].phys_id == phys_id) 1286 return &vop2->data->win_data[i]; 1287 } 1288 1289 return NULL; 1290 } 1291 1292 static struct vop2_power_domain_data *vop2_find_pd_data_by_id(struct vop2 *vop2, int pd_id) 1293 { 1294 int i = 0; 1295 1296 for (i = 0; i < vop2->data->nr_pd; i++) { 1297 if (vop2->data->pd[i].id == pd_id) 1298 return &vop2->data->pd[i]; 1299 } 1300 1301 return NULL; 1302 } 1303 1304 static int rockchip_vop2_gamma_lut_init(struct vop2 *vop2, 1305 struct display_state *state) 1306 { 1307 struct connector_state *conn_state = &state->conn_state; 1308 struct crtc_state *cstate = &state->crtc_state; 1309 struct resource gamma_res; 1310 fdt_size_t lut_size; 1311 int i, lut_len, ret = 0; 1312 u32 *lut_regs; 1313 u32 *lut_val; 1314 u32 r, g, b; 1315 u32 vp_offset = cstate->crtc_id * 0x100; 1316 struct base2_disp_info *disp_info = conn_state->disp_info; 1317 static int gamma_lut_en_num = 1; 1318 1319 if (gamma_lut_en_num > vop2->data->nr_gammas) { 1320 printf("warn: only %d vp support gamma\n", vop2->data->nr_gammas); 1321 return 0; 1322 } 1323 1324 if (!disp_info) 1325 return 0; 1326 1327 if (!disp_info->gamma_lut_data.size) 1328 return 0; 1329 1330 ret = ofnode_read_resource_byname(cstate->node, "gamma_lut", &gamma_res); 1331 if (ret) 1332 printf("failed to get gamma lut res\n"); 1333 lut_regs = (u32 *)gamma_res.start; 1334 lut_size = gamma_res.end - gamma_res.start + 1; 1335 if (lut_regs == (u32 *)FDT_ADDR_T_NONE) { 1336 printf("failed to get gamma lut register\n"); 1337 return 0; 1338 } 1339 lut_len = lut_size / 4; 1340 if (lut_len != 256 && lut_len != 1024) { 1341 printf("Warning: unsupport gamma lut table[%d]\n", lut_len); 1342 return 0; 1343 } 1344 lut_val = (u32 *)calloc(1, lut_size); 1345 for (i = 0; i < lut_len; i++) { 1346 r = disp_info->gamma_lut_data.lred[i] * (lut_len - 1) / 0xffff; 1347 g = disp_info->gamma_lut_data.lgreen[i] * (lut_len - 1) / 0xffff; 1348 b = disp_info->gamma_lut_data.lblue[i] * (lut_len - 1) / 0xffff; 1349 1350 lut_val[i] = b * lut_len * lut_len + g * lut_len + r; 1351 } 1352 1353 for (i = 0; i < lut_len; i++) 1354 writel(lut_val[i], lut_regs + i); 1355 1356 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, 1357 GAMMA_PORT_SEL_MASK, GAMMA_PORT_SEL_SHIFT, 1358 cstate->crtc_id , false); 1359 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 1360 EN_MASK, DSP_LUT_EN_SHIFT, 1, false); 1361 gamma_lut_en_num++; 1362 1363 return 0; 1364 } 1365 1366 static int rockchip_vop2_cubic_lut_init(struct vop2 *vop2, 1367 struct display_state *state) 1368 { 1369 struct connector_state *conn_state = &state->conn_state; 1370 struct crtc_state *cstate = &state->crtc_state; 1371 int i, cubic_lut_len; 1372 u32 vp_offset = cstate->crtc_id * 0x100; 1373 struct base2_disp_info *disp_info = conn_state->disp_info; 1374 struct base2_cubic_lut_data *lut = &conn_state->disp_info->cubic_lut_data; 1375 u32 *cubic_lut_addr; 1376 1377 if (!disp_info || CONFIG_ROCKCHIP_CUBIC_LUT_SIZE == 0) 1378 return 0; 1379 1380 if (!disp_info->cubic_lut_data.size) 1381 return 0; 1382 1383 cubic_lut_addr = (u32 *)get_cubic_lut_buffer(cstate->crtc_id); 1384 cubic_lut_len = disp_info->cubic_lut_data.size; 1385 1386 for (i = 0; i < cubic_lut_len / 2; i++) { 1387 *cubic_lut_addr++ = ((lut->lred[2 * i]) & 0xfff) + 1388 ((lut->lgreen[2 * i] & 0xfff) << 12) + 1389 ((lut->lblue[2 * i] & 0xff) << 24); 1390 *cubic_lut_addr++ = ((lut->lblue[2 * i] & 0xf00) >> 8) + 1391 ((lut->lred[2 * i + 1] & 0xfff) << 4) + 1392 ((lut->lgreen[2 * i + 1] & 0xfff) << 16) + 1393 ((lut->lblue[2 * i + 1] & 0xf) << 28); 1394 *cubic_lut_addr++ = (lut->lblue[2 * i + 1] & 0xff0) >> 4; 1395 *cubic_lut_addr++ = 0; 1396 } 1397 1398 if (cubic_lut_len % 2) { 1399 *cubic_lut_addr++ = (lut->lred[2 * i] & 0xfff) + 1400 ((lut->lgreen[2 * i] & 0xfff) << 12) + 1401 ((lut->lblue[2 * i] & 0xff) << 24); 1402 *cubic_lut_addr++ = (lut->lblue[2 * i] & 0xf00) >> 8; 1403 *cubic_lut_addr++ = 0; 1404 *cubic_lut_addr = 0; 1405 } 1406 1407 vop2_writel(vop2, RK3568_VP0_3D_LUT_MST + vp_offset, 1408 get_cubic_lut_buffer(cstate->crtc_id)); 1409 vop2_mask_write(vop2, RK3568_SYS_AXI_LUT_CTRL, 1410 EN_MASK, LUT_DMA_EN_SHIFT, 1, false); 1411 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, 1412 EN_MASK, VP0_3D_LUT_EN_SHIFT, 1, false); 1413 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, 1414 EN_MASK, VP0_3D_LUT_UPDATE_SHIFT, 1, false); 1415 1416 return 0; 1417 } 1418 1419 static void vop2_bcsh_reg_update(struct display_state *state, struct vop2 *vop2, 1420 struct bcsh_state *bcsh_state, int crtc_id) 1421 { 1422 struct crtc_state *cstate = &state->crtc_state; 1423 u32 vp_offset = crtc_id * 0x100; 1424 1425 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_MASK, 1426 BCSH_CTRL_R2Y_SHIFT, cstate->post_r2y_en, false); 1427 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_MASK, 1428 BCSH_CTRL_Y2R_SHIFT, cstate->post_y2r_en, false); 1429 1430 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_CSC_MODE_MASK, 1431 BCSH_CTRL_R2Y_CSC_MODE_SHIFT, cstate->post_csc_mode, false); 1432 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_CSC_MODE_MASK, 1433 BCSH_CTRL_Y2R_CSC_MODE_SHIFT, cstate->post_csc_mode, false); 1434 1435 if (!cstate->bcsh_en) { 1436 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, 1437 BCSH_EN_MASK, BCSH_EN_SHIFT, 0, false); 1438 return; 1439 } 1440 1441 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1442 BCSH_BRIGHTNESS_MASK, BCSH_BRIGHTNESS_SHIFT, 1443 bcsh_state->brightness, false); 1444 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1445 BCSH_CONTRAST_MASK, BCSH_CONTRAST_SHIFT, bcsh_state->contrast, false); 1446 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1447 BCSH_SATURATION_MASK, BCSH_SATURATION_SHIFT, 1448 bcsh_state->saturation * bcsh_state->contrast / 0x100, false); 1449 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, 1450 BCSH_SIN_HUE_MASK, BCSH_SIN_HUE_SHIFT, bcsh_state->sin_hue, false); 1451 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, 1452 BCSH_COS_HUE_MASK, BCSH_COS_HUE_SHIFT, bcsh_state->cos_hue, false); 1453 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1454 BCSH_OUT_MODE_MASK, BCSH_OUT_MODE_SHIFT, 1455 BCSH_OUT_MODE_NORMAL_VIDEO, false); 1456 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, 1457 BCSH_EN_MASK, BCSH_EN_SHIFT, 1, false); 1458 } 1459 1460 static void vop2_tv_config_update(struct display_state *state, struct vop2 *vop2) 1461 { 1462 struct connector_state *conn_state = &state->conn_state; 1463 struct base_bcsh_info *bcsh_info; 1464 struct crtc_state *cstate = &state->crtc_state; 1465 struct bcsh_state bcsh_state; 1466 int brightness, contrast, saturation, hue, sin_hue, cos_hue; 1467 1468 if (!conn_state->disp_info) 1469 return; 1470 bcsh_info = &conn_state->disp_info->bcsh_info; 1471 if (!bcsh_info) 1472 return; 1473 1474 if (bcsh_info->brightness != 50 || 1475 bcsh_info->contrast != 50 || 1476 bcsh_info->saturation != 50 || bcsh_info->hue != 50) 1477 cstate->bcsh_en = true; 1478 1479 if (cstate->bcsh_en) { 1480 if (!cstate->yuv_overlay) 1481 cstate->post_r2y_en = 1; 1482 if (!is_yuv_output(conn_state->bus_format)) 1483 cstate->post_y2r_en = 1; 1484 } else { 1485 if (!cstate->yuv_overlay && is_yuv_output(conn_state->bus_format)) 1486 cstate->post_r2y_en = 1; 1487 if (cstate->yuv_overlay && !is_yuv_output(conn_state->bus_format)) 1488 cstate->post_y2r_en = 1; 1489 } 1490 1491 cstate->post_csc_mode = vop2_convert_csc_mode(conn_state->color_space); 1492 1493 if (cstate->feature & VOP_FEATURE_OUTPUT_10BIT) 1494 brightness = interpolate(0, -128, 100, 127, 1495 bcsh_info->brightness); 1496 else 1497 brightness = interpolate(0, -32, 100, 31, 1498 bcsh_info->brightness); 1499 contrast = interpolate(0, 0, 100, 511, bcsh_info->contrast); 1500 saturation = interpolate(0, 0, 100, 511, bcsh_info->saturation); 1501 hue = interpolate(0, -30, 100, 30, bcsh_info->hue); 1502 1503 1504 /* 1505 * a:[-30~0): 1506 * sin_hue = 0x100 - sin(a)*256; 1507 * cos_hue = cos(a)*256; 1508 * a:[0~30] 1509 * sin_hue = sin(a)*256; 1510 * cos_hue = cos(a)*256; 1511 */ 1512 sin_hue = fixp_sin32(hue) >> 23; 1513 cos_hue = fixp_cos32(hue) >> 23; 1514 1515 bcsh_state.brightness = brightness; 1516 bcsh_state.contrast = contrast; 1517 bcsh_state.saturation = saturation; 1518 bcsh_state.sin_hue = sin_hue; 1519 bcsh_state.cos_hue = cos_hue; 1520 1521 vop2_bcsh_reg_update(state, vop2, &bcsh_state, cstate->crtc_id); 1522 if (cstate->splice_mode) 1523 vop2_bcsh_reg_update(state, vop2, &bcsh_state, cstate->splice_crtc_id); 1524 } 1525 1526 static void vop2_setup_dly_for_vp(struct display_state *state, struct vop2 *vop2, int crtc_id) 1527 { 1528 struct connector_state *conn_state = &state->conn_state; 1529 struct drm_display_mode *mode = &conn_state->mode; 1530 struct crtc_state *cstate = &state->crtc_state; 1531 u32 bg_ovl_dly, bg_dly, pre_scan_dly; 1532 u16 hdisplay = mode->crtc_hdisplay; 1533 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 1534 1535 bg_ovl_dly = cstate->crtc->vps[crtc_id].bg_ovl_dly; 1536 bg_dly = vop2->data->vp_data[crtc_id].pre_scan_max_dly; 1537 bg_dly -= bg_ovl_dly; 1538 1539 if (cstate->splice_mode) 1540 pre_scan_dly = bg_dly + (hdisplay >> 2) - 1; 1541 else 1542 pre_scan_dly = bg_dly + (hdisplay >> 1) - 1; 1543 1544 if (vop2->version == VOP_VERSION_RK3588 && hsync_len < 8) 1545 hsync_len = 8; 1546 pre_scan_dly = (pre_scan_dly << 16) | hsync_len; 1547 vop2_mask_write(vop2, RK3568_VP0_BG_MIX_CTRL + crtc_id * 4, 1548 BG_MIX_CTRL_MASK, BG_MIX_CTRL_SHIFT, bg_dly, false); 1549 vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly); 1550 } 1551 1552 static void vop2_post_config(struct display_state *state, struct vop2 *vop2) 1553 { 1554 struct connector_state *conn_state = &state->conn_state; 1555 struct drm_display_mode *mode = &conn_state->mode; 1556 struct crtc_state *cstate = &state->crtc_state; 1557 u32 vp_offset = (cstate->crtc_id * 0x100); 1558 u16 vtotal = mode->crtc_vtotal; 1559 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 1560 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 1561 u16 hdisplay = mode->crtc_hdisplay; 1562 u16 vdisplay = mode->crtc_vdisplay; 1563 u16 hsize = 1564 hdisplay * (conn_state->overscan.left_margin + 1565 conn_state->overscan.right_margin) / 200; 1566 u16 vsize = 1567 vdisplay * (conn_state->overscan.top_margin + 1568 conn_state->overscan.bottom_margin) / 200; 1569 u16 hact_end, vact_end; 1570 u32 val; 1571 1572 hsize = round_down(hsize, 2); 1573 vsize = round_down(vsize, 2); 1574 1575 hact_st += hdisplay * (100 - conn_state->overscan.left_margin) / 200; 1576 hact_end = hact_st + hsize; 1577 val = hact_st << 16; 1578 val |= hact_end; 1579 1580 vop2_writel(vop2, RK3568_VP0_POST_DSP_HACT_INFO + vp_offset, val); 1581 vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200; 1582 vact_end = vact_st + vsize; 1583 val = vact_st << 16; 1584 val |= vact_end; 1585 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO + vp_offset, val); 1586 val = scl_cal_scale2(vdisplay, vsize) << 16; 1587 val |= scl_cal_scale2(hdisplay, hsize); 1588 vop2_writel(vop2, RK3568_VP0_POST_SCL_FACTOR_YRGB + vp_offset, val); 1589 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0) 1590 #define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1) 1591 vop2_writel(vop2, RK3568_VP0_POST_SCL_CTRL + vp_offset, 1592 POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) | 1593 POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize)); 1594 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1595 u16 vact_st_f1 = vtotal + vact_st + 1; 1596 u16 vact_end_f1 = vact_st_f1 + vsize; 1597 1598 val = vact_st_f1 << 16 | vact_end_f1; 1599 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO_F1 + vp_offset, val); 1600 } 1601 1602 vop2_setup_dly_for_vp(state, vop2, cstate->crtc_id); 1603 if (cstate->splice_mode) 1604 vop2_setup_dly_for_vp(state, vop2, cstate->splice_crtc_id); 1605 } 1606 1607 /* 1608 * Read VOP internal power domain on/off status. 1609 * We should query BISR_STS register in PMU for 1610 * power up/down status when memory repair is enabled. 1611 * Return value: 1 for power on, 0 for power off; 1612 */ 1613 static int vop2_wait_power_domain_on(struct vop2 *vop2, struct vop2_power_domain_data *pd_data) 1614 { 1615 int val = 0; 1616 int shift = 0; 1617 int shift_factor = 0; 1618 bool is_bisr_en = false; 1619 1620 /* 1621 * The order of pd status bits in BISR_STS register 1622 * is different from that in VOP SYS_STS register. 1623 */ 1624 if (pd_data->id == VOP2_PD_DSC_8K || 1625 pd_data->id == VOP2_PD_DSC_4K || 1626 pd_data->id == VOP2_PD_ESMART) 1627 shift_factor = 1; 1628 1629 shift = RK3588_PD_CLUSTER0_REPAIR_EN_SHIFT + generic_ffs(pd_data->id) - 1 - shift_factor; 1630 is_bisr_en = vop2_grf_readl(vop2, vop2->sys_pmu, RK3588_PMU_BISR_CON3, EN_MASK, shift); 1631 if (is_bisr_en) { 1632 shift = RK3588_PD_CLUSTER0_PWR_STAT_SHIFI + generic_ffs(pd_data->id) - 1 - shift_factor; 1633 1634 return readl_poll_timeout(vop2->sys_pmu + RK3588_PMU_BISR_STATUS5, val, 1635 ((val >> shift) & 0x1), 50 * 1000); 1636 } else { 1637 shift = RK3588_CLUSTER0_PD_STATUS_SHIFT + generic_ffs(pd_data->id) - 1; 1638 1639 return readl_poll_timeout(vop2->regs + RK3568_SYS_STATUS0, val, 1640 !((val >> shift) & 0x1), 50 * 1000); 1641 } 1642 } 1643 1644 static int vop2_power_domain_on(struct vop2 *vop2, int pd_id) 1645 { 1646 struct vop2_power_domain_data *pd_data; 1647 int ret = 0; 1648 1649 if (!pd_id) 1650 return 0; 1651 1652 pd_data = vop2_find_pd_data_by_id(vop2, pd_id); 1653 if (!pd_data) { 1654 printf("can't find pd_data by id\n"); 1655 return -EINVAL; 1656 } 1657 1658 if (pd_data->parent_id) { 1659 ret = vop2_power_domain_on(vop2, pd_data->parent_id); 1660 if (ret) { 1661 printf("can't open parent power domain\n"); 1662 return -EINVAL; 1663 } 1664 } 1665 1666 vop2_mask_write(vop2, RK3568_SYS_PD_CTRL, EN_MASK, 1667 RK3588_CLUSTER0_PD_EN_SHIFT + generic_ffs(pd_id) - 1, 0, false); 1668 ret = vop2_wait_power_domain_on(vop2, pd_data); 1669 if (ret) { 1670 printf("wait vop2 power domain timeout\n"); 1671 return ret; 1672 } 1673 1674 return 0; 1675 } 1676 1677 static void rk3588_vop2_regsbak(struct vop2 *vop2) 1678 { 1679 u32 *base = vop2->regs; 1680 int i = 0; 1681 1682 /* 1683 * No need to backup HDR/DSC/GAMMA_LUT/BPP_LUT/MMU 1684 */ 1685 for (i = 0; i < (vop2->reg_len >> 2); i++) 1686 vop2->regsbak[i] = base[i]; 1687 } 1688 1689 static void vop2_global_initial(struct vop2 *vop2, struct display_state *state) 1690 { 1691 struct crtc_state *cstate = &state->crtc_state; 1692 int i, j, port_mux = 0, total_used_layer = 0; 1693 u8 shift = 0; 1694 int layer_phy_id = 0; 1695 u32 layer_nr = 0; 1696 struct vop2_win_data *win_data; 1697 struct vop2_vp_plane_mask *plane_mask; 1698 1699 if (vop2->global_init) 1700 return; 1701 1702 /* OTP must enable at the first time, otherwise mirror layer register is error */ 1703 if (soc_is_rk3566()) 1704 vop2_mask_write(vop2, RK3568_SYS_OTP_WIN_EN, EN_MASK, 1705 OTP_WIN_EN_SHIFT, 1, false); 1706 1707 if (cstate->crtc->assign_plane) {/* dts assign plane */ 1708 u32 plane_mask; 1709 int primary_plane_id; 1710 1711 for (i = 0; i < vop2->data->nr_vps; i++) { 1712 plane_mask = cstate->crtc->vps[i].plane_mask; 1713 vop2->vp_plane_mask[i].plane_mask = plane_mask; 1714 layer_nr = hweight32(plane_mask); /* use bitmap to store plane mask */ 1715 vop2->vp_plane_mask[i].attached_layers_nr = layer_nr; 1716 primary_plane_id = cstate->crtc->vps[i].primary_plane_id; 1717 if (primary_plane_id < 0) 1718 primary_plane_id = vop2_get_primary_plane(vop2, plane_mask); 1719 vop2->vp_plane_mask[i].primary_plane_id = primary_plane_id; 1720 vop2->vp_plane_mask[i].plane_mask = plane_mask; 1721 1722 /* plane mask[bitmap] convert into layer phy id[enum vop2_layer_phy_id]*/ 1723 for (j = 0; j < layer_nr; j++) { 1724 vop2->vp_plane_mask[i].attached_layers[j] = ffs(plane_mask) - 1; 1725 plane_mask &= ~BIT(vop2->vp_plane_mask[i].attached_layers[j]); 1726 } 1727 } 1728 } else {/* need soft assign plane mask */ 1729 /* find the first unplug devices and set it as main display */ 1730 int main_vp_index = -1; 1731 int active_vp_num = 0; 1732 1733 for (i = 0; i < vop2->data->nr_vps; i++) { 1734 if (cstate->crtc->vps[i].enable) 1735 active_vp_num++; 1736 } 1737 printf("VOP have %d active VP\n", active_vp_num); 1738 1739 if (soc_is_rk3566() && active_vp_num > 2) 1740 printf("ERROR: rk3566 only support 2 display output!!\n"); 1741 plane_mask = vop2->data->plane_mask; 1742 plane_mask += (active_vp_num - 1) * VOP2_VP_MAX; 1743 1744 for (i = 0; i < vop2->data->nr_vps; i++) { 1745 if (!is_hot_plug_devices(cstate->crtc->vps[i].output_type)) { 1746 vop2->vp_plane_mask[i] = plane_mask[0]; /* the first store main display plane mask*/ 1747 main_vp_index = i; 1748 break; 1749 } 1750 } 1751 1752 /* if no find unplug devices, use vp0 as main display */ 1753 if (main_vp_index < 0) { 1754 main_vp_index = 0; 1755 vop2->vp_plane_mask[0] = plane_mask[0]; 1756 } 1757 1758 j = 1; /* plane_mask[0] store main display, so we from plane_mask[1] */ 1759 1760 /* init other display except main display */ 1761 for (i = 0; i < vop2->data->nr_vps; i++) { 1762 if (i == main_vp_index || !cstate->crtc->vps[i].enable) /* main display or no connect devices */ 1763 continue; 1764 vop2->vp_plane_mask[i] = plane_mask[j++]; 1765 } 1766 1767 /* store plane mask for vop2_fixup_dts */ 1768 for (i = 0; i < vop2->data->nr_vps; i++) { 1769 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1770 for (j = 0; j < layer_nr; j++) { 1771 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1772 vop2->vp_plane_mask[i].plane_mask |= BIT(layer_phy_id); 1773 } 1774 } 1775 } 1776 1777 if (vop2->version == VOP_VERSION_RK3588) 1778 rk3588_vop2_regsbak(vop2); 1779 else 1780 memcpy(vop2->regsbak, vop2->regs, vop2->reg_len); 1781 1782 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, 1783 OVL_PORT_MUX_REG_DONE_IMD_SHIFT, 1, false); 1784 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1785 IF_CTRL_REG_DONE_IMD_SHIFT, 1, false); 1786 1787 for (i = 0; i < vop2->data->nr_vps; i++) { 1788 printf("vp%d have layer nr:%d[", i, vop2->vp_plane_mask[i].attached_layers_nr); 1789 for (j = 0; j < vop2->vp_plane_mask[i].attached_layers_nr; j++) 1790 printf("%d ", vop2->vp_plane_mask[i].attached_layers[j]); 1791 printf("], primary plane: %d\n", vop2->vp_plane_mask[i].primary_plane_id); 1792 } 1793 1794 shift = 0; 1795 /* layer sel win id */ 1796 for (i = 0; i < vop2->data->nr_vps; i++) { 1797 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1798 for (j = 0; j < layer_nr; j++) { 1799 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1800 win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id); 1801 vop2_mask_write(vop2, RK3568_OVL_LAYER_SEL, LAYER_SEL_MASK, 1802 shift, win_data->layer_sel_win_id, false); 1803 shift += 4; 1804 } 1805 } 1806 1807 /* win sel port */ 1808 for (i = 0; i < vop2->data->nr_vps; i++) { 1809 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1810 for (j = 0; j < layer_nr; j++) { 1811 if (!vop2->vp_plane_mask[i].attached_layers[j]) 1812 continue; 1813 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1814 win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id); 1815 shift = win_data->win_sel_port_offset * 2; 1816 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, LAYER_SEL_PORT_MASK, 1817 LAYER_SEL_PORT_SHIFT + shift, i, false); 1818 } 1819 } 1820 1821 /** 1822 * port mux config 1823 */ 1824 for (i = 0; i < vop2->data->nr_vps; i++) { 1825 shift = i * 4; 1826 if (vop2->vp_plane_mask[i].attached_layers_nr) { 1827 total_used_layer += vop2->vp_plane_mask[i].attached_layers_nr; 1828 port_mux = total_used_layer - 1; 1829 } else { 1830 port_mux = 8; 1831 } 1832 1833 if (i == vop2->data->nr_vps - 1) 1834 port_mux = vop2->data->nr_mixers; 1835 1836 cstate->crtc->vps[i].bg_ovl_dly = (vop2->data->nr_mixers - port_mux) << 1; 1837 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, PORT_MUX_MASK, 1838 PORT_MUX_SHIFT + shift, port_mux, false); 1839 } 1840 1841 if (vop2->version == VOP_VERSION_RK3568) 1842 vop2_writel(vop2, RK3568_AUTO_GATING_CTRL, 0); 1843 1844 vop2->global_init = true; 1845 } 1846 1847 static int vop2_initial(struct vop2 *vop2, struct display_state *state) 1848 { 1849 struct crtc_state *cstate = &state->crtc_state; 1850 int ret; 1851 1852 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1853 ret = clk_set_defaults(cstate->dev); 1854 if (ret) 1855 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1856 1857 rockchip_vop2_gamma_lut_init(vop2, state); 1858 rockchip_vop2_cubic_lut_init(vop2, state); 1859 1860 return 0; 1861 } 1862 1863 /* 1864 * VOP2 have multi video ports. 1865 * video port ------- crtc 1866 */ 1867 static int rockchip_vop2_preinit(struct display_state *state) 1868 { 1869 struct crtc_state *cstate = &state->crtc_state; 1870 const struct vop2_data *vop2_data = cstate->crtc->data; 1871 1872 if (!rockchip_vop2) { 1873 rockchip_vop2 = calloc(1, sizeof(struct vop2)); 1874 if (!rockchip_vop2) 1875 return -ENOMEM; 1876 rockchip_vop2->regs = dev_read_addr_ptr(cstate->dev); 1877 rockchip_vop2->regsbak = malloc(RK3568_MAX_REG); 1878 rockchip_vop2->reg_len = RK3568_MAX_REG; 1879 rockchip_vop2->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1880 if (rockchip_vop2->grf <= 0) 1881 printf("%s: Get syscon grf failed (ret=%p)\n", __func__, rockchip_vop2->grf); 1882 rockchip_vop2->version = vop2_data->version; 1883 rockchip_vop2->data = vop2_data; 1884 if (rockchip_vop2->version == VOP_VERSION_RK3588) { 1885 struct regmap *map; 1886 1887 rockchip_vop2->vop_grf = syscon_get_first_range(ROCKCHIP_SYSCON_VOP_GRF); 1888 if (rockchip_vop2->vop_grf <= 0) 1889 printf("%s: Get syscon vop_grf failed (ret=%p)\n", __func__, rockchip_vop2->vop_grf); 1890 map = syscon_regmap_lookup_by_phandle(cstate->dev, "rockchip,vo1-grf"); 1891 rockchip_vop2->vo1_grf = regmap_get_range(map, 0); 1892 if (rockchip_vop2->vo1_grf <= 0) 1893 printf("%s: Get syscon vo1_grf failed (ret=%p)\n", __func__, rockchip_vop2->vo1_grf); 1894 rockchip_vop2->sys_pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); 1895 if (rockchip_vop2->sys_pmu <= 0) 1896 printf("%s: Get syscon sys_pmu failed (ret=%p)\n", __func__, rockchip_vop2->sys_pmu); 1897 } 1898 } 1899 1900 cstate->private = rockchip_vop2; 1901 cstate->max_output = vop2_data->vp_data[cstate->crtc_id].max_output; 1902 cstate->feature = vop2_data->vp_data[cstate->crtc_id].feature; 1903 1904 vop2_global_initial(rockchip_vop2, state); 1905 1906 return 0; 1907 } 1908 1909 /* 1910 * calc the dclk on rk3588 1911 * the available div of dclk is 1, 2, 4 1912 * 1913 */ 1914 static unsigned long vop2_calc_dclk(unsigned long child_clk, unsigned long max_dclk) 1915 { 1916 if (child_clk * 4 <= max_dclk) 1917 return child_clk * 4; 1918 else if (child_clk * 2 <= max_dclk) 1919 return child_clk * 2; 1920 else if (child_clk <= max_dclk) 1921 return child_clk; 1922 else 1923 return 0; 1924 } 1925 1926 /* 1927 * 4 pixclk/cycle on rk3588 1928 * RGB/eDP/HDMI: if_pixclk >= dclk_core 1929 * DP: dp_pixclk = dclk_out <= dclk_core 1930 * DSI: mipi_pixclk <= dclk_out <= dclk_core 1931 */ 1932 static unsigned long vop2_calc_cru_cfg(struct display_state *state, 1933 int *dclk_core_div, int *dclk_out_div, 1934 int *if_pixclk_div, int *if_dclk_div) 1935 { 1936 struct crtc_state *cstate = &state->crtc_state; 1937 struct connector_state *conn_state = &state->conn_state; 1938 struct drm_display_mode *mode = &conn_state->mode; 1939 struct vop2 *vop2 = cstate->private; 1940 unsigned long v_pixclk = mode->crtc_clock; 1941 unsigned long dclk_core_rate = v_pixclk >> 2; 1942 unsigned long dclk_rate = v_pixclk; 1943 unsigned long dclk_out_rate; 1944 u64 if_dclk_rate; 1945 u64 if_pixclk_rate; 1946 int output_type = conn_state->type; 1947 int output_mode = conn_state->output_mode; 1948 int K = 1; 1949 1950 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE && 1951 output_mode == ROCKCHIP_OUT_MODE_YUV420) { 1952 printf("Dual channel and YUV420 can't work together\n"); 1953 return -EINVAL; 1954 } 1955 1956 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE || 1957 output_mode == ROCKCHIP_OUT_MODE_YUV420) 1958 K = 2; 1959 1960 if (output_type == DRM_MODE_CONNECTOR_HDMIA) { 1961 /* 1962 * K = 2: dclk_core = if_pixclk_rate > if_dclk_rate 1963 * K = 1: dclk_core = hdmie_edp_dclk > if_pixclk_rate 1964 */ 1965 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE || 1966 output_mode == ROCKCHIP_OUT_MODE_YUV420) { 1967 dclk_rate = dclk_rate >> 1; 1968 K = 2; 1969 } 1970 if (cstate->dsc_enable) { 1971 if_pixclk_rate = cstate->dsc_cds_clk_rate << 1; 1972 if_dclk_rate = cstate->dsc_cds_clk_rate; 1973 } else { 1974 if_pixclk_rate = (dclk_core_rate << 1) / K; 1975 if_dclk_rate = dclk_core_rate / K; 1976 } 1977 1978 if (v_pixclk > VOP2_MAX_DCLK_RATE) 1979 dclk_rate = vop2_calc_dclk(dclk_core_rate, vop2->data->vp_data->max_dclk); 1980 1981 if (!dclk_rate) { 1982 printf("DP if_pixclk_rate out of range(max_dclk: %d KHZ, dclk_core: %lld KHZ)\n", 1983 vop2->data->vp_data->max_dclk, if_pixclk_rate); 1984 return -EINVAL; 1985 } 1986 *if_pixclk_div = dclk_rate / if_pixclk_rate; 1987 *if_dclk_div = dclk_rate / if_dclk_rate; 1988 *dclk_core_div = dclk_rate / dclk_core_rate; 1989 printf("dclk:%lu,if_pixclk_div;%d,if_dclk_div:%d\n", 1990 dclk_rate, *if_pixclk_div, *if_dclk_div); 1991 } else if (output_type == DRM_MODE_CONNECTOR_eDP) { 1992 /* edp_pixclk = edp_dclk > dclk_core */ 1993 if_pixclk_rate = v_pixclk / K; 1994 if_dclk_rate = v_pixclk / K; 1995 dclk_rate = if_pixclk_rate * K; 1996 *dclk_core_div = dclk_rate / dclk_core_rate; 1997 *if_pixclk_div = dclk_rate / if_pixclk_rate; 1998 *if_dclk_div = *if_pixclk_div; 1999 } else if (output_type == DRM_MODE_CONNECTOR_DisplayPort) { 2000 dclk_out_rate = v_pixclk >> 2; 2001 dclk_out_rate = dclk_out_rate / K; 2002 2003 dclk_rate = vop2_calc_dclk(dclk_out_rate, vop2->data->vp_data->max_dclk); 2004 if (!dclk_rate) { 2005 printf("DP dclk_core out of range(max_dclk: %d KHZ, dclk_core: %ld KHZ)\n", 2006 vop2->data->vp_data->max_dclk, dclk_core_rate); 2007 return -EINVAL; 2008 } 2009 *dclk_out_div = dclk_rate / dclk_out_rate; 2010 *dclk_core_div = dclk_rate / dclk_core_rate; 2011 } else if (output_type == DRM_MODE_CONNECTOR_DSI) { 2012 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2013 K = 2; 2014 if (cstate->dsc_enable) 2015 /* dsc output is 96bit, dsi input is 192 bit */ 2016 if_pixclk_rate = cstate->dsc_cds_clk_rate >> 1; 2017 else 2018 if_pixclk_rate = dclk_core_rate / K; 2019 /* dclk_core = dclk_out * K = if_pixclk * K = v_pixclk / 4 */ 2020 dclk_out_rate = dclk_core_rate / K; 2021 /* dclk_rate = N * dclk_core_rate N = (1,2,4 ), we get a little factor here */ 2022 dclk_rate = vop2_calc_dclk(dclk_out_rate, vop2->data->vp_data->max_dclk); 2023 if (!dclk_rate) { 2024 printf("MIPI dclk out of range(max_dclk: %d KHZ, dclk_rate: %ld KHZ)\n", 2025 vop2->data->vp_data->max_dclk, dclk_rate); 2026 return -EINVAL; 2027 } 2028 2029 if (cstate->dsc_enable) 2030 dclk_rate = dclk_rate >> 1; 2031 2032 *dclk_out_div = dclk_rate / dclk_out_rate; 2033 *dclk_core_div = dclk_rate / dclk_core_rate; 2034 *if_pixclk_div = 1; /*mipi pixclk == dclk_out*/ 2035 if (cstate->dsc_enable) 2036 *if_pixclk_div = dclk_out_rate / if_pixclk_rate; 2037 2038 } else if (output_type == DRM_MODE_CONNECTOR_DPI) { 2039 dclk_rate = v_pixclk; 2040 *dclk_core_div = dclk_rate / dclk_core_rate; 2041 } 2042 2043 *if_pixclk_div = ilog2(*if_pixclk_div); 2044 *if_dclk_div = ilog2(*if_dclk_div); 2045 *dclk_core_div = ilog2(*dclk_core_div); 2046 *dclk_out_div = ilog2(*dclk_out_div); 2047 2048 return dclk_rate; 2049 } 2050 2051 static int vop2_calc_dsc_clk(struct display_state *state) 2052 { 2053 struct connector_state *conn_state = &state->conn_state; 2054 struct drm_display_mode *mode = &conn_state->mode; 2055 struct crtc_state *cstate = &state->crtc_state; 2056 u64 v_pixclk = mode->clock; /* video timing pixclk */ 2057 u8 k = 1; 2058 2059 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2060 k = 2; 2061 2062 cstate->dsc_txp_clk_rate = v_pixclk; 2063 do_div(cstate->dsc_txp_clk_rate, (cstate->dsc_pixel_num * k)); 2064 2065 cstate->dsc_pxl_clk_rate = v_pixclk; 2066 do_div(cstate->dsc_pxl_clk_rate, (cstate->dsc_slice_num * k)); 2067 2068 /* dsc_cds = crtc_clock / (cds_dat_width / bits_per_pixel) 2069 * cds_dat_width = 96; 2070 * bits_per_pixel = [8-12]; 2071 * As cds clk is div from txp clk and only support 1/2/4 div, 2072 * so when txp_clk is equal to v_pixclk, we set dsc_cds = crtc_clock / 4, 2073 * otherwise dsc_cds = crtc_clock / 8; 2074 */ 2075 cstate->dsc_cds_clk_rate = v_pixclk / (cstate->dsc_txp_clk_rate == v_pixclk ? 4 : 8); 2076 2077 return 0; 2078 } 2079 2080 static unsigned long rk3588_vop2_if_cfg(struct display_state *state) 2081 { 2082 struct crtc_state *cstate = &state->crtc_state; 2083 struct connector_state *conn_state = &state->conn_state; 2084 struct drm_display_mode *mode = &conn_state->mode; 2085 struct rockchip_dsc_sink_cap *dsc_sink_cap = &cstate->dsc_sink_cap; 2086 struct vop2 *vop2 = cstate->private; 2087 u32 vp_offset = (cstate->crtc_id * 0x100); 2088 u16 hdisplay = mode->crtc_hdisplay; 2089 int output_if = conn_state->output_if; 2090 int if_pixclk_div = 0; 2091 int if_dclk_div = 0; 2092 unsigned long dclk_rate; 2093 u32 val; 2094 2095 if (output_if & (VOP_OUTPUT_IF_HDMI0 | VOP_OUTPUT_IF_HDMI1)) { 2096 val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? BIT(HSYNC_POSITIVE) : 0; 2097 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? BIT(VSYNC_POSITIVE) : 0; 2098 } else { 2099 val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE); 2100 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE); 2101 } 2102 2103 if (cstate->dsc_enable) { 2104 int k = 1; 2105 2106 if (!vop2->data->nr_dscs) { 2107 printf("Unsupported DSC\n"); 2108 return 0; 2109 } 2110 2111 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2112 k = 2; 2113 2114 cstate->dsc_id = output_if & (VOP_OUTPUT_IF_MIPI0 | VOP_OUTPUT_IF_HDMI0) ? 0 : 1; 2115 cstate->dsc_slice_num = hdisplay / dsc_sink_cap->slice_width / k; 2116 cstate->dsc_pixel_num = cstate->dsc_slice_num > 4 ? 4 : cstate->dsc_slice_num; 2117 2118 vop2_calc_dsc_clk(state); 2119 printf("Enable DSC%d slice:%dx%d, slice num:%d\n", 2120 cstate->dsc_id, dsc_sink_cap->slice_width, 2121 dsc_sink_cap->slice_height, cstate->dsc_slice_num); 2122 } 2123 2124 dclk_rate = vop2_calc_cru_cfg(state, &cstate->dclk_core_div, &cstate->dclk_out_div, &if_pixclk_div, &if_dclk_div); 2125 2126 if (output_if & VOP_OUTPUT_IF_RGB) { 2127 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, 2128 4, false); 2129 } 2130 2131 if (output_if & VOP_OUTPUT_IF_BT1120) { 2132 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, 2133 3, false); 2134 } 2135 2136 if (output_if & VOP_OUTPUT_IF_BT656) { 2137 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, 2138 2, false); 2139 } 2140 2141 if (output_if & VOP_OUTPUT_IF_MIPI0) { 2142 if (cstate->crtc_id == 2) 2143 val = 0; 2144 else 2145 val = 1; 2146 2147 if (conn_state->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE) 2148 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2149 RK3588_MIPI_DSI0_MODE_SEL_SHIFT, 1, false); 2150 2151 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_MIPI0_EN_SHIFT, 2152 1, false); 2153 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 1, RK3588_MIPI0_MUX_SHIFT, val, false); 2154 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, MIPI0_PIXCLK_DIV_SHIFT, 2155 if_pixclk_div, false); 2156 2157 if (conn_state->hold_mode) { 2158 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2159 EN_MASK, EDPI_TE_EN, 1, false); 2160 2161 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2162 EN_MASK, EDPI_WMS_HOLD_EN, 1, false); 2163 } 2164 } 2165 2166 if (output_if & VOP_OUTPUT_IF_MIPI1) { 2167 if (cstate->crtc_id == 2) 2168 val = 0; 2169 else if (cstate->crtc_id == 3) 2170 val = 1; 2171 else 2172 val = 3; /*VP1*/ 2173 if (conn_state->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE) 2174 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2175 RK3588_MIPI_DSI1_MODE_SEL_SHIFT, 1, false); 2176 2177 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_MIPI1_EN_SHIFT, 2178 1, false); 2179 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, MIPI1_MUX_SHIFT, 2180 val, false); 2181 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, MIPI1_PIXCLK_DIV_SHIFT, 2182 if_pixclk_div, false); 2183 2184 if (conn_state->hold_mode) { 2185 /* UNDO: RK3588 VP1->DSC1->DSI1 only can support soft TE mode */ 2186 if (vop2->version == VOP_VERSION_RK3588 && val == 3) 2187 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2188 EN_MASK, EDPI_TE_EN, 0, false); 2189 else 2190 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2191 EN_MASK, EDPI_TE_EN, 1, false); 2192 2193 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2194 EN_MASK, EDPI_WMS_HOLD_EN, 1, false); 2195 } 2196 } 2197 2198 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { 2199 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, 2200 MIPI_DUAL_EN_SHIFT, 1, false); 2201 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) 2202 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2203 EN_MASK, MIPI_DUAL_SWAP_EN_SHIFT, 1, 2204 false); 2205 switch (conn_state->type) { 2206 case DRM_MODE_CONNECTOR_DisplayPort: 2207 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2208 RK3588_DP_DUAL_EN_SHIFT, 1, false); 2209 break; 2210 case DRM_MODE_CONNECTOR_eDP: 2211 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2212 RK3588_EDP_DUAL_EN_SHIFT, 1, false); 2213 break; 2214 case DRM_MODE_CONNECTOR_HDMIA: 2215 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2216 RK3588_HDMI_DUAL_EN_SHIFT, 1, false); 2217 break; 2218 case DRM_MODE_CONNECTOR_DSI: 2219 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2220 RK3568_MIPI_DUAL_EN_SHIFT, 1, false); 2221 break; 2222 default: 2223 break; 2224 } 2225 } 2226 2227 if (output_if & VOP_OUTPUT_IF_eDP0) { 2228 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_EDP0_EN_SHIFT, 2229 1, false); 2230 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP0_MUX_SHIFT, 2231 cstate->crtc_id, false); 2232 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_DCLK_DIV_SHIFT, 2233 if_dclk_div, false); 2234 2235 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_PIXCLK_DIV_SHIFT, 2236 if_pixclk_div, false); 2237 2238 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, 2239 RK3588_GRF_EDP0_ENABLE_SHIFT, 1); 2240 } 2241 2242 if (output_if & VOP_OUTPUT_IF_eDP1) { 2243 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_EDP1_EN_SHIFT, 2244 1, false); 2245 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP1_MUX_SHIFT, 2246 cstate->crtc_id, false); 2247 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_DCLK_DIV_SHIFT, 2248 if_dclk_div, false); 2249 2250 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_PIXCLK_DIV_SHIFT, 2251 if_pixclk_div, false); 2252 2253 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, 2254 RK3588_GRF_EDP1_ENABLE_SHIFT, 1); 2255 } 2256 2257 if (output_if & VOP_OUTPUT_IF_HDMI0) { 2258 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_HDMI0_EN_SHIFT, 2259 1, false); 2260 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP0_MUX_SHIFT, 2261 cstate->crtc_id, false); 2262 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_DCLK_DIV_SHIFT, 2263 if_dclk_div, false); 2264 2265 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_PIXCLK_DIV_SHIFT, 2266 if_pixclk_div, false); 2267 2268 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, 2269 RK3588_GRF_HDMITX0_ENABLE_SHIFT, 1); 2270 vop2_grf_writel(vop2, vop2->vo1_grf, RK3588_GRF_VO1_CON0, 2271 HDMI_SYNC_POL_MASK, 2272 HDMI0_SYNC_POL_SHIFT, val); 2273 } 2274 2275 if (output_if & VOP_OUTPUT_IF_HDMI1) { 2276 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_HDMI1_EN_SHIFT, 2277 1, false); 2278 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP1_MUX_SHIFT, 2279 cstate->crtc_id, false); 2280 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_DCLK_DIV_SHIFT, 2281 if_dclk_div, false); 2282 2283 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_PIXCLK_DIV_SHIFT, 2284 if_pixclk_div, false); 2285 2286 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, 2287 RK3588_GRF_HDMITX1_ENABLE_SHIFT, 1); 2288 vop2_grf_writel(vop2, vop2->vo1_grf, RK3588_GRF_VO1_CON0, 2289 HDMI_SYNC_POL_MASK, 2290 HDMI1_SYNC_POL_SHIFT, val); 2291 } 2292 2293 if (output_if & VOP_OUTPUT_IF_DP0) { 2294 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP0_EN_SHIFT, 2295 1, false); 2296 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_DP0_MUX_SHIFT, 2297 cstate->crtc_id, false); 2298 vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3588_IF_PIN_POL_MASK, 2299 RK3588_DP0_PIN_POL_SHIFT, val, false); 2300 } 2301 2302 if (output_if & VOP_OUTPUT_IF_DP1) { 2303 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP1_EN_SHIFT, 2304 1, false); 2305 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_DP1_MUX_SHIFT, 2306 cstate->crtc_id, false); 2307 vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3588_IF_PIN_POL_MASK, 2308 RK3588_DP1_PIN_POL_SHIFT, val, false); 2309 } 2310 2311 vop2_mask_write(vop2, RK3588_VP0_CLK_CTRL + vp_offset, 0x3, 2312 DCLK_CORE_DIV_SHIFT, cstate->dclk_core_div, false); 2313 vop2_mask_write(vop2, RK3588_VP0_CLK_CTRL + vp_offset, 0x3, 2314 DCLK_OUT_DIV_SHIFT, cstate->dclk_out_div, false); 2315 2316 return dclk_rate; 2317 } 2318 2319 static unsigned long rk3568_vop2_if_cfg(struct display_state *state) 2320 { 2321 struct crtc_state *cstate = &state->crtc_state; 2322 struct connector_state *conn_state = &state->conn_state; 2323 struct drm_display_mode *mode = &conn_state->mode; 2324 struct vop2 *vop2 = cstate->private; 2325 u32 vp_offset = (cstate->crtc_id * 0x100); 2326 bool dclk_inv; 2327 u32 val; 2328 2329 dclk_inv = (mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1; 2330 val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE); 2331 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE); 2332 2333 if (conn_state->output_if & VOP_OUTPUT_IF_RGB) { 2334 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, 2335 1, false); 2336 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2337 RGB_MUX_SHIFT, cstate->crtc_id, false); 2338 vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK, 2339 GRF_RGB_DCLK_INV_SHIFT, dclk_inv); 2340 } 2341 2342 if (conn_state->output_if & VOP_OUTPUT_IF_BT1120) { 2343 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, 2344 1, false); 2345 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, 2346 BT1120_EN_SHIFT, 1, false); 2347 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2348 RGB_MUX_SHIFT, cstate->crtc_id, false); 2349 vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK, 2350 GRF_BT1120_CLK_INV_SHIFT, !dclk_inv); 2351 } 2352 2353 if (conn_state->output_if & VOP_OUTPUT_IF_BT656) { 2354 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT, 2355 1, false); 2356 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2357 RGB_MUX_SHIFT, cstate->crtc_id, false); 2358 vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK, 2359 GRF_BT656_CLK_INV_SHIFT, !dclk_inv); 2360 } 2361 2362 if (conn_state->output_if & VOP_OUTPUT_IF_LVDS0) { 2363 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT, 2364 1, false); 2365 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2366 LVDS0_MUX_SHIFT, cstate->crtc_id, false); 2367 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2368 IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false); 2369 } 2370 2371 if (conn_state->output_if & VOP_OUTPUT_IF_LVDS1) { 2372 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS1_EN_SHIFT, 2373 1, false); 2374 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2375 LVDS1_MUX_SHIFT, cstate->crtc_id, false); 2376 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2377 IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false); 2378 } 2379 2380 if (conn_state->output_flags & 2381 (ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE | 2382 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)) { 2383 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2384 LVDS_DUAL_EN_SHIFT, 1, false); 2385 if (conn_state->output_flags & 2386 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2387 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2388 LVDS_DUAL_LEFT_RIGHT_EN_SHIFT, 1, 2389 false); 2390 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) 2391 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2392 LVDS_DUAL_SWAP_EN_SHIFT, 1, false); 2393 } 2394 2395 if (conn_state->output_if & VOP_OUTPUT_IF_MIPI0) { 2396 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT, 2397 1, false); 2398 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2399 MIPI0_MUX_SHIFT, cstate->crtc_id, false); 2400 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2401 IF_CRTL_MIPI_DCLK_POL_SHIT, dclk_inv, false); 2402 } 2403 2404 if (conn_state->output_if & VOP_OUTPUT_IF_MIPI1) { 2405 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI1_EN_SHIFT, 2406 1, false); 2407 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2408 MIPI1_MUX_SHIFT, cstate->crtc_id, false); 2409 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2410 IF_CRTL_MIPI_DCLK_POL_SHIT, dclk_inv, false); 2411 } 2412 2413 if (conn_state->output_flags & 2414 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { 2415 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, 2416 MIPI_DUAL_EN_SHIFT, 1, false); 2417 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) 2418 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2419 EN_MASK, MIPI_DUAL_SWAP_EN_SHIFT, 1, 2420 false); 2421 } 2422 2423 if (conn_state->output_if & VOP_OUTPUT_IF_eDP0) { 2424 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, EDP0_EN_SHIFT, 2425 1, false); 2426 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2427 EDP0_MUX_SHIFT, cstate->crtc_id, false); 2428 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2429 IF_CRTL_EDP_DCLK_POL_SHIT, dclk_inv, false); 2430 } 2431 2432 if (conn_state->output_if & VOP_OUTPUT_IF_HDMI0) { 2433 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT, 2434 1, false); 2435 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2436 HDMI0_MUX_SHIFT, cstate->crtc_id, false); 2437 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2438 IF_CRTL_HDMI_DCLK_POL_SHIT, 1, false); 2439 vop2_mask_write(vop2, RK3568_DSP_IF_POL, 2440 IF_CRTL_HDMI_PIN_POL_MASK, 2441 IF_CRTL_HDMI_PIN_POL_SHIT, val, false); 2442 } 2443 2444 return mode->clock; 2445 } 2446 2447 static void vop2_post_color_swap(struct display_state *state) 2448 { 2449 struct crtc_state *cstate = &state->crtc_state; 2450 struct connector_state *conn_state = &state->conn_state; 2451 struct vop2 *vop2 = cstate->private; 2452 u32 vp_offset = (cstate->crtc_id * 0x100); 2453 u32 output_type = conn_state->type; 2454 u32 data_swap = 0; 2455 2456 if (is_uv_swap(conn_state->bus_format, conn_state->output_mode)) 2457 data_swap = DSP_RB_SWAP; 2458 2459 if (vop2->version == VOP_VERSION_RK3588 && 2460 (output_type == DRM_MODE_CONNECTOR_HDMIA || 2461 output_type == DRM_MODE_CONNECTOR_eDP) && 2462 (conn_state->bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 2463 conn_state->bus_format == MEDIA_BUS_FMT_YUV10_1X30)) 2464 data_swap |= DSP_RG_SWAP; 2465 2466 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 2467 DATA_SWAP_MASK, DATA_SWAP_SHIFT, data_swap, false); 2468 } 2469 2470 static void vop2_clk_set_parent(struct clk *clk, struct clk *parent) 2471 { 2472 int ret = 0; 2473 2474 if (parent->dev) 2475 ret = clk_set_parent(clk, parent); 2476 if (ret < 0) 2477 debug("failed to set %s as parent for %s\n", 2478 parent->dev->name, clk->dev->name); 2479 } 2480 2481 static ulong vop2_clk_set_rate(struct clk *clk, ulong rate) 2482 { 2483 int ret = 0; 2484 2485 if (clk->dev) 2486 ret = clk_set_rate(clk, rate); 2487 if (ret < 0) 2488 debug("failed to set %s rate %lu \n", clk->dev->name, rate); 2489 2490 return ret; 2491 } 2492 2493 static void vop2_calc_dsc_cru_cfg(struct display_state *state, 2494 int *dsc_txp_clk_div, int *dsc_pxl_clk_div, 2495 int *dsc_cds_clk_div, u64 dclk_rate) 2496 { 2497 struct crtc_state *cstate = &state->crtc_state; 2498 2499 *dsc_txp_clk_div = dclk_rate / cstate->dsc_txp_clk_rate; 2500 *dsc_pxl_clk_div = dclk_rate / cstate->dsc_pxl_clk_rate; 2501 *dsc_cds_clk_div = dclk_rate / cstate->dsc_cds_clk_rate; 2502 2503 *dsc_txp_clk_div = ilog2(*dsc_txp_clk_div); 2504 *dsc_pxl_clk_div = ilog2(*dsc_pxl_clk_div); 2505 *dsc_cds_clk_div = ilog2(*dsc_cds_clk_div); 2506 } 2507 2508 static void vop2_load_pps(struct display_state *state, struct vop2 *vop2, u8 dsc_id) 2509 { 2510 struct crtc_state *cstate = &state->crtc_state; 2511 struct drm_dsc_picture_parameter_set *pps = &cstate->pps; 2512 struct drm_dsc_picture_parameter_set config_pps; 2513 const struct vop2_data *vop2_data = vop2->data; 2514 const struct vop2_dsc_data *dsc_data = &vop2_data->dsc[dsc_id]; 2515 u32 *pps_val = (u32 *)&config_pps; 2516 u32 decoder_regs_offset = (dsc_id * 0x100); 2517 int i = 0; 2518 2519 memcpy(&config_pps, pps, sizeof(config_pps)); 2520 2521 if ((config_pps.pps_3 & 0xf) > dsc_data->max_linebuf_depth) { 2522 config_pps.pps_3 &= 0xf0; 2523 config_pps.pps_3 |= dsc_data->max_linebuf_depth; 2524 printf("DSC%d max_linebuf_depth is: %d, current set value is: %d\n", 2525 dsc_id, dsc_data->max_linebuf_depth, config_pps.pps_3 & 0xf); 2526 } 2527 2528 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 2529 config_pps.rc_range_parameters[i] = 2530 (pps->rc_range_parameters[i] >> 3 & 0x1f) | 2531 ((pps->rc_range_parameters[i] >> 14 & 0x3) << 5) | 2532 ((pps->rc_range_parameters[i] >> 0 & 0x7) << 7) | 2533 ((pps->rc_range_parameters[i] >> 8 & 0x3f) << 10); 2534 } 2535 2536 for (i = 0; i < ROCKCHIP_DSC_PPS_SIZE_BYTE / 4; i++) 2537 vop2_writel(vop2, RK3588_DSC_8K_PPS0_3 + decoder_regs_offset + i * 4, *pps_val++); 2538 } 2539 2540 static void vop2_dsc_enable(struct display_state *state, struct vop2 *vop2, u8 dsc_id, u64 dclk_rate) 2541 { 2542 struct connector_state *conn_state = &state->conn_state; 2543 struct drm_display_mode *mode = &conn_state->mode; 2544 struct crtc_state *cstate = &state->crtc_state; 2545 struct rockchip_dsc_sink_cap *dsc_sink_cap = &cstate->dsc_sink_cap; 2546 const struct vop2_data *vop2_data = vop2->data; 2547 const struct vop2_dsc_data *dsc_data = &vop2_data->dsc[dsc_id]; 2548 bool mipi_ds_mode = false; 2549 u8 dsc_interface_mode = 0; 2550 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 2551 u16 hdisplay = mode->crtc_hdisplay; 2552 u16 htotal = mode->crtc_htotal; 2553 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 2554 u16 vdisplay = mode->crtc_vdisplay; 2555 u16 vtotal = mode->crtc_vtotal; 2556 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 2557 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 2558 u16 vact_end = vact_st + vdisplay; 2559 u32 ctrl_regs_offset = (dsc_id * 0x30); 2560 u32 decoder_regs_offset = (dsc_id * 0x100); 2561 u32 backup_regs_offset = 0; 2562 int dsc_txp_clk_div = 0; 2563 int dsc_pxl_clk_div = 0; 2564 int dsc_cds_clk_div = 0; 2565 2566 if (!vop2->data->nr_dscs) { 2567 printf("Unsupported DSC\n"); 2568 return; 2569 } 2570 2571 if (cstate->dsc_slice_num > dsc_data->max_slice_num) 2572 printf("DSC%d supported max slice is: %d, current is: %d\n", 2573 dsc_data->id, dsc_data->max_slice_num, cstate->dsc_slice_num); 2574 2575 if (dsc_data->pd_id) { 2576 if (vop2_power_domain_on(vop2, dsc_data->pd_id)) 2577 printf("open dsc%d pd fail\n", dsc_id); 2578 } 2579 2580 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, EN_MASK, 2581 SCAN_TIMING_PARA_IMD_EN_SHIFT, 1, false); 2582 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PORT_SEL_MASK, 2583 DSC_PORT_SEL_SHIFT, cstate->crtc_id, false); 2584 if (conn_state->output_if & (VOP_OUTPUT_IF_HDMI0 | VOP_OUTPUT_IF_HDMI1)) { 2585 dsc_interface_mode = VOP_DSC_IF_HDMI; 2586 } else { 2587 mipi_ds_mode = !!(conn_state->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE); 2588 if (mipi_ds_mode) 2589 dsc_interface_mode = VOP_DSC_IF_MIPI_DS_MODE; 2590 else 2591 dsc_interface_mode = VOP_DSC_IF_MIPI_VIDEO_MODE; 2592 } 2593 2594 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2595 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_MAN_MODE_MASK, 2596 DSC_MAN_MODE_SHIFT, 0, false); 2597 else 2598 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_MAN_MODE_MASK, 2599 DSC_MAN_MODE_SHIFT, 1, false); 2600 2601 vop2_calc_dsc_cru_cfg(state, &dsc_txp_clk_div, &dsc_pxl_clk_div, &dsc_cds_clk_div, dclk_rate); 2602 2603 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_INTERFACE_MODE_MASK, 2604 DSC_INTERFACE_MODE_SHIFT, dsc_interface_mode, false); 2605 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PIXEL_NUM_MASK, 2606 DSC_PIXEL_NUM_SHIFT, cstate->dsc_pixel_num >> 1, false); 2607 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_TXP_CLK_DIV_MASK, 2608 DSC_TXP_CLK_DIV_SHIFT, dsc_txp_clk_div, false); 2609 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PXL_CLK_DIV_MASK, 2610 DSC_PXL_CLK_DIV_SHIFT, dsc_pxl_clk_div, false); 2611 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_CDS_CLK_DIV_MASK, 2612 DSC_CDS_CLK_DIV_SHIFT, dsc_cds_clk_div, false); 2613 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, EN_MASK, 2614 DSC_SCAN_EN_SHIFT, !mipi_ds_mode, false); 2615 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_CDS_CLK_DIV_MASK, 2616 DSC_HALT_EN_SHIFT, mipi_ds_mode, false); 2617 2618 if (!mipi_ds_mode) { 2619 u16 dsc_hsync, dsc_htotal, dsc_hact_st, dsc_hact_end; 2620 u32 target_bpp = dsc_sink_cap->target_bits_per_pixel_x16; 2621 u64 dsc_cds_rate = cstate->dsc_cds_clk_rate; 2622 u32 v_pixclk_mhz = mode->crtc_clock / 1000; /* video timing pixclk */ 2623 u32 dly_num, dsc_cds_rate_mhz, val = 0; 2624 int k = 1; 2625 2626 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2627 k = 2; 2628 2629 if (target_bpp >> 4 < dsc_data->min_bits_per_pixel) 2630 printf("Unsupported bpp less than: %d\n", dsc_data->min_bits_per_pixel); 2631 2632 /* 2633 * dly_num = delay_line_num * T(one-line) / T (dsc_cds) 2634 * T (one-line) = 1/v_pixclk_mhz * htotal = htotal/v_pixclk_mhz 2635 * T (dsc_cds) = 1 / dsc_cds_rate_mhz 2636 * delay_line_num: according the pps initial_xmit_delay to adjust vop dsc delay 2637 * delay_line_num = 4 - BPP / 8 2638 * = (64 - target_bpp / 8) / 16 2639 * 2640 * dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16; 2641 */ 2642 do_div(dsc_cds_rate, 1000000); /* hz to Mhz */ 2643 dsc_cds_rate_mhz = dsc_cds_rate; 2644 dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16; 2645 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, DSC_INIT_DLY_MODE_MASK, 2646 DSC_INIT_DLY_MODE_SHIFT, 0, false); 2647 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, DSC_INIT_DLY_NUM_MASK, 2648 DSC_INIT_DLY_NUM_SHIFT, dly_num, false); 2649 2650 dsc_hsync = hsync_len / 2; 2651 /* 2652 * htotal / dclk_core = dsc_htotal /cds_clk 2653 * 2654 * dclk_core = DCLK / (1 << dclk_core->div_val) 2655 * cds_clk = txp_clk / (1 << dsc_cds_clk->div_val) 2656 * txp_clk = DCLK / (1 << dsc_txp_clk->div_val) 2657 * 2658 * dsc_htotal = htotal * (1 << dclk_core->div_val) / 2659 * ((1 << dsc_txp_clk->div_val) * (1 << dsc_cds_clk->div_val)) 2660 */ 2661 dsc_htotal = htotal * (1 << cstate->dclk_core_div) / 2662 ((1 << dsc_txp_clk_div) * (1 << dsc_cds_clk_div)); 2663 val = dsc_htotal << 16 | dsc_hsync; 2664 vop2_mask_write(vop2, RK3588_DSC_8K_HTOTAL_HS_END + ctrl_regs_offset, DSC_HTOTAL_PW_MASK, 2665 DSC_HTOTAL_PW_SHIFT, val, false); 2666 2667 dsc_hact_st = hact_st / 2; 2668 dsc_hact_end = (hdisplay / k * target_bpp >> 4) / 24 + dsc_hact_st; 2669 val = dsc_hact_end << 16 | dsc_hact_st; 2670 vop2_mask_write(vop2, RK3588_DSC_8K_HACT_ST_END + ctrl_regs_offset, DSC_HACT_ST_END_MASK, 2671 DSC_HACT_ST_END_SHIFT, val, false); 2672 2673 vop2_mask_write(vop2, RK3588_DSC_8K_VTOTAL_VS_END + ctrl_regs_offset, DSC_VTOTAL_PW_MASK, 2674 DSC_VTOTAL_PW_SHIFT, vtotal << 16 | vsync_len, false); 2675 vop2_mask_write(vop2, RK3588_DSC_8K_VACT_ST_END + ctrl_regs_offset, DSC_VACT_ST_END_MASK, 2676 DSC_VACT_ST_END_SHIFT, vact_end << 16 | vact_st, false); 2677 } 2678 2679 vop2_mask_write(vop2, RK3588_DSC_8K_RST + ctrl_regs_offset, RST_DEASSERT_MASK, 2680 RST_DEASSERT_SHIFT, 1, false); 2681 udelay(10); 2682 /* read current dsc core register and backup to regsbak */ 2683 backup_regs_offset = RK3588_DSC_8K_CTRL0; 2684 vop2->regsbak[backup_regs_offset >> 2] = vop2_readl(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset); 2685 2686 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2687 DSC_EN_SHIFT, 1, false); 2688 vop2_load_pps(state, vop2, dsc_id); 2689 2690 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2691 DSC_RBIT_SHIFT, 1, false); 2692 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2693 DSC_RBYT_SHIFT, 0, false); 2694 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2695 DSC_FLAL_SHIFT, 1, false); 2696 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2697 DSC_MER_SHIFT, 1, false); 2698 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2699 DSC_EPB_SHIFT, 0, false); 2700 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2701 DSC_EPL_SHIFT, 1, false); 2702 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2703 DSC_NSLC_SHIFT, ilog2(cstate->dsc_slice_num), false); 2704 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2705 DSC_SBO_SHIFT, 1, false); 2706 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2707 DSC_IFEP_SHIFT, dsc_sink_cap->version_minor == 2 ? 1 : 0, false); 2708 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2709 DSC_PPS_UPD_SHIFT, 1, false); 2710 2711 printf("DSC%d: txp:%lld div:%d, pxl:%lld div:%d, dsc:%lld div:%d\n", 2712 dsc_id, 2713 cstate->dsc_txp_clk_rate, dsc_txp_clk_div, 2714 cstate->dsc_pxl_clk_rate, dsc_pxl_clk_div, 2715 cstate->dsc_cds_clk_rate, dsc_cds_clk_div); 2716 } 2717 2718 static bool is_extend_pll(struct display_state *state, struct udevice **clk_dev) 2719 { 2720 struct crtc_state *cstate = &state->crtc_state; 2721 struct vop2 *vop2 = cstate->private; 2722 struct udevice *vp_dev, *dev; 2723 struct ofnode_phandle_args args; 2724 char vp_name[10]; 2725 int ret; 2726 2727 if (vop2->version != VOP_VERSION_RK3588) 2728 return false; 2729 2730 sprintf(vp_name, "port@%d", cstate->crtc_id); 2731 if (uclass_find_device_by_name(UCLASS_VIDEO_CRTC, vp_name, &vp_dev)) { 2732 debug("warn: can't get vp device\n"); 2733 return false; 2734 } 2735 2736 ret = dev_read_phandle_with_args(vp_dev, "assigned-clock-parents", "#clock-cells", 0, 2737 0, &args); 2738 if (ret) { 2739 debug("assigned-clock-parents's node not define\n"); 2740 return false; 2741 } 2742 2743 if (uclass_find_device_by_ofnode(UCLASS_CLK, args.node, &dev)) { 2744 debug("warn: can't get clk device\n"); 2745 return false; 2746 } 2747 2748 if (!strcmp(dev->name, "hdmiphypll_clk0") || !strcmp(dev->name, "hdmiphypll_clk1")) { 2749 printf("%s: clk dev :%s: vp port:%s\n", __func__, dev->name, vp_dev->name); 2750 if (clk_dev) 2751 *clk_dev = dev; 2752 return true; 2753 } 2754 2755 return false; 2756 } 2757 2758 static int rockchip_vop2_init(struct display_state *state) 2759 { 2760 struct crtc_state *cstate = &state->crtc_state; 2761 struct connector_state *conn_state = &state->conn_state; 2762 struct drm_display_mode *mode = &conn_state->mode; 2763 struct vop2 *vop2 = cstate->private; 2764 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 2765 u16 hdisplay = mode->crtc_hdisplay; 2766 u16 htotal = mode->crtc_htotal; 2767 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 2768 u16 hact_end = hact_st + hdisplay; 2769 u16 vdisplay = mode->crtc_vdisplay; 2770 u16 vtotal = mode->crtc_vtotal; 2771 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 2772 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 2773 u16 vact_end = vact_st + vdisplay; 2774 bool yuv_overlay = false; 2775 u32 vp_offset = (cstate->crtc_id * 0x100); 2776 u32 line_flag_offset = (cstate->crtc_id * 4); 2777 u32 val, act_end; 2778 u8 dither_down_en = 0; 2779 u8 pre_dither_down_en = 0; 2780 u8 dclk_div_factor = 0; 2781 char output_type_name[30] = {0}; 2782 char dclk_name[9]; 2783 struct clk dclk; 2784 struct clk hdmi0_phy_pll; 2785 struct clk hdmi1_phy_pll; 2786 struct clk hdmi_phy_pll; 2787 struct udevice *disp_dev; 2788 unsigned long dclk_rate; 2789 int ret; 2790 2791 printf("VOP update mode to: %dx%d%s%d, type:%s for VP%d\n", 2792 mode->crtc_hdisplay, mode->crtc_vdisplay, 2793 mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p", 2794 mode->vrefresh, 2795 get_output_if_name(conn_state->output_if, output_type_name), 2796 cstate->crtc_id); 2797 2798 if (mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) { 2799 cstate->splice_mode = true; 2800 cstate->splice_crtc_id = vop2->data->vp_data[cstate->crtc_id].splice_vp_id; 2801 if (!cstate->splice_crtc_id) { 2802 printf("%s: Splice mode is unsupported by vp%d\n", 2803 __func__, cstate->crtc_id); 2804 return -EINVAL; 2805 } 2806 2807 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, EN_MASK, 2808 PORT_MERGE_EN_SHIFT, 1, false); 2809 } 2810 2811 vop2_initial(vop2, state); 2812 if (vop2->version == VOP_VERSION_RK3588) 2813 dclk_rate = rk3588_vop2_if_cfg(state); 2814 else 2815 dclk_rate = rk3568_vop2_if_cfg(state); 2816 2817 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA && 2818 !(cstate->feature & VOP_FEATURE_OUTPUT_10BIT)) 2819 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 2820 2821 vop2_post_color_swap(state); 2822 2823 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, OUT_MODE_MASK, 2824 OUT_MODE_SHIFT, conn_state->output_mode, false); 2825 2826 switch (conn_state->bus_format) { 2827 case MEDIA_BUS_FMT_RGB565_1X16: 2828 dither_down_en = 1; 2829 break; 2830 case MEDIA_BUS_FMT_RGB666_1X18: 2831 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 2832 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 2833 case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA: 2834 dither_down_en = 1; 2835 break; 2836 case MEDIA_BUS_FMT_YUV8_1X24: 2837 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 2838 dither_down_en = 0; 2839 pre_dither_down_en = 1; 2840 break; 2841 case MEDIA_BUS_FMT_YUV10_1X30: 2842 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 2843 case MEDIA_BUS_FMT_RGB888_1X24: 2844 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 2845 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 2846 default: 2847 dither_down_en = 0; 2848 pre_dither_down_en = 0; 2849 break; 2850 } 2851 2852 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA) 2853 pre_dither_down_en = 0; 2854 else 2855 pre_dither_down_en = 1; 2856 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2857 DITHER_DOWN_EN_SHIFT, dither_down_en, false); 2858 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2859 PRE_DITHER_DOWN_EN_SHIFT, pre_dither_down_en, false); 2860 2861 yuv_overlay = is_yuv_output(conn_state->bus_format) ? 1 : 0; 2862 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, cstate->crtc_id, 2863 yuv_overlay, false); 2864 2865 cstate->yuv_overlay = yuv_overlay; 2866 2867 vop2_writel(vop2, RK3568_VP0_DSP_HTOTAL_HS_END + vp_offset, 2868 (htotal << 16) | hsync_len); 2869 val = hact_st << 16; 2870 val |= hact_end; 2871 vop2_writel(vop2, RK3568_VP0_DSP_HACT_ST_END + vp_offset, val); 2872 val = vact_st << 16; 2873 val |= vact_end; 2874 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END + vp_offset, val); 2875 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 2876 u16 vact_st_f1 = vtotal + vact_st + 1; 2877 u16 vact_end_f1 = vact_st_f1 + vdisplay; 2878 2879 val = vact_st_f1 << 16 | vact_end_f1; 2880 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END_F1 + vp_offset, 2881 val); 2882 2883 val = vtotal << 16 | (vtotal + vsync_len); 2884 vop2_writel(vop2, RK3568_VP0_DSP_VS_ST_END_F1 + vp_offset, val); 2885 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2886 INTERLACE_EN_SHIFT, 1, false); 2887 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2888 DSP_FILED_POL, 1, false); 2889 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2890 P2I_EN_SHIFT, 1, false); 2891 vtotal += vtotal + 1; 2892 act_end = vact_end_f1; 2893 } else { 2894 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2895 INTERLACE_EN_SHIFT, 0, false); 2896 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2897 P2I_EN_SHIFT, 0, false); 2898 act_end = vact_end; 2899 } 2900 vop2_writel(vop2, RK3568_VP0_DSP_VTOTAL_VS_END + vp_offset, 2901 (vtotal << 16) | vsync_len); 2902 2903 if (vop2->version == VOP_VERSION_RK3568) { 2904 if (mode->flags & DRM_MODE_FLAG_DBLCLK || 2905 conn_state->output_if & VOP_OUTPUT_IF_BT656) 2906 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2907 CORE_DCLK_DIV_EN_SHIFT, 1, false); 2908 else 2909 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2910 CORE_DCLK_DIV_EN_SHIFT, 0, false); 2911 } 2912 2913 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420) 2914 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2915 DCLK_DIV2_MASK, DCLK_DIV2_SHIFT, 0x3, false); 2916 else 2917 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2918 DCLK_DIV2_MASK, DCLK_DIV2_SHIFT, 0, false); 2919 2920 vop2_mask_write(vop2, RK3568_OVL_CTRL, OVL_MODE_SEL_MASK, 2921 OVL_MODE_SEL_SHIFT + cstate->crtc_id, yuv_overlay, false); 2922 2923 if (yuv_overlay) 2924 val = 0x20010200; 2925 else 2926 val = 0; 2927 vop2_writel(vop2, RK3568_VP0_DSP_BG + vp_offset, val); 2928 if (cstate->splice_mode) { 2929 vop2_mask_write(vop2, RK3568_OVL_CTRL, OVL_MODE_SEL_MASK, 2930 OVL_MODE_SEL_SHIFT + cstate->splice_crtc_id, 2931 yuv_overlay, false); 2932 vop2_writel(vop2, RK3568_VP0_DSP_BG + (cstate->splice_crtc_id * 0x100), val); 2933 } 2934 2935 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2936 POST_DSP_OUT_R2Y_SHIFT, yuv_overlay, false); 2937 2938 vop2_tv_config_update(state, vop2); 2939 vop2_post_config(state, vop2); 2940 2941 if (cstate->dsc_enable) { 2942 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { 2943 vop2_dsc_enable(state, vop2, 0, dclk_rate); 2944 vop2_dsc_enable(state, vop2, 1, dclk_rate); 2945 } else { 2946 vop2_dsc_enable(state, vop2, cstate->dsc_id, dclk_rate); 2947 } 2948 } 2949 2950 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", cstate->crtc_id); 2951 ret = clk_get_by_name(cstate->dev, dclk_name, &dclk); 2952 if (ret) { 2953 printf("%s: Failed to get dclk ret=%d\n", __func__, ret); 2954 return ret; 2955 } 2956 2957 ret = uclass_get_device_by_name(UCLASS_VIDEO, "display-subsystem", &disp_dev); 2958 if (!ret) { 2959 ret = clk_get_by_name(disp_dev, "hdmi0_phy_pll", &hdmi0_phy_pll); 2960 if (ret) 2961 debug("%s: hdmi0_phy_pll may not define\n", __func__); 2962 ret = clk_get_by_name(disp_dev, "hdmi1_phy_pll", &hdmi1_phy_pll); 2963 if (ret) 2964 debug("%s: hdmi1_phy_pll may not define\n", __func__); 2965 } else { 2966 hdmi0_phy_pll.dev = NULL; 2967 hdmi1_phy_pll.dev = NULL; 2968 debug("%s: Faile to find display-subsystem node\n", __func__); 2969 } 2970 2971 if (mode->crtc_clock < VOP2_MAX_DCLK_RATE) { 2972 if (conn_state->output_if & VOP_OUTPUT_IF_HDMI0) 2973 vop2_clk_set_parent(&dclk, &hdmi0_phy_pll); 2974 else if (conn_state->output_if & VOP_OUTPUT_IF_HDMI1) 2975 vop2_clk_set_parent(&dclk, &hdmi1_phy_pll); 2976 2977 /* 2978 * uboot clk driver won't set dclk parent's rate when use 2979 * hdmi phypll as dclk source. 2980 * So set dclk rate is meaningless. Set hdmi phypll rate 2981 * directly. 2982 */ 2983 if ((conn_state->output_if & VOP_OUTPUT_IF_HDMI0) && hdmi0_phy_pll.dev) { 2984 ret = vop2_clk_set_rate(&hdmi0_phy_pll, dclk_rate * 1000); 2985 } else if ((conn_state->output_if & VOP_OUTPUT_IF_HDMI1) && hdmi1_phy_pll.dev) { 2986 ret = vop2_clk_set_rate(&hdmi1_phy_pll, dclk_rate * 1000); 2987 } else { 2988 if (is_extend_pll(state, &hdmi_phy_pll.dev)) 2989 ret = vop2_clk_set_rate(&hdmi_phy_pll, dclk_rate * 1000); 2990 else 2991 ret = vop2_clk_set_rate(&dclk, dclk_rate * 1000); 2992 } 2993 } else { 2994 if (is_extend_pll(state, &hdmi_phy_pll.dev)) 2995 ret = vop2_clk_set_rate(&hdmi_phy_pll, dclk_rate * 1000); 2996 else 2997 ret = vop2_clk_set_rate(&dclk, dclk_rate * 1000); 2998 } 2999 3000 if (IS_ERR_VALUE(ret)) { 3001 printf("%s: Failed to set vp%d dclk[%ld KHZ] ret=%d\n", 3002 __func__, cstate->crtc_id, dclk_rate, ret); 3003 return ret; 3004 } else { 3005 dclk_div_factor = mode->clock / dclk_rate; 3006 mode->crtc_clock = ret * dclk_div_factor / 1000; 3007 printf("VP%d set crtc_clock to %dKHz\n", cstate->crtc_id, mode->crtc_clock); 3008 } 3009 3010 vop2_mask_write(vop2, RK3568_SYS_CTRL_LINE_FLAG0 + line_flag_offset, LINE_FLAG_NUM_MASK, 3011 RK3568_DSP_LINE_FLAG_NUM0_SHIFT, act_end, false); 3012 vop2_mask_write(vop2, RK3568_SYS_CTRL_LINE_FLAG0 + line_flag_offset, LINE_FLAG_NUM_MASK, 3013 RK3568_DSP_LINE_FLAG_NUM1_SHIFT, act_end, false); 3014 3015 return 0; 3016 } 3017 3018 static void vop2_setup_scale(struct vop2 *vop2, struct vop2_win_data *win, 3019 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 3020 uint32_t dst_h) 3021 { 3022 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 3023 uint16_t hscl_filter_mode, vscl_filter_mode; 3024 uint8_t gt2 = 0, gt4 = 0; 3025 uint32_t xfac = 0, yfac = 0; 3026 uint16_t hsu_filter_mode = VOP2_SCALE_UP_BIC; 3027 uint16_t hsd_filter_mode = VOP2_SCALE_DOWN_BIL; 3028 uint16_t vsu_filter_mode = VOP2_SCALE_UP_BIL; 3029 uint16_t vsd_filter_mode = VOP2_SCALE_DOWN_BIL; 3030 u32 win_offset = win->reg_offset; 3031 3032 if (src_h >= (4 * dst_h)) 3033 gt4 = 1; 3034 else if (src_h >= (2 * dst_h)) 3035 gt2 = 1; 3036 3037 if (gt4) 3038 src_h >>= 2; 3039 else if (gt2) 3040 src_h >>= 1; 3041 3042 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 3043 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 3044 3045 if (yrgb_hor_scl_mode == SCALE_UP) 3046 hscl_filter_mode = hsu_filter_mode; 3047 else 3048 hscl_filter_mode = hsd_filter_mode; 3049 3050 if (yrgb_ver_scl_mode == SCALE_UP) 3051 vscl_filter_mode = vsu_filter_mode; 3052 else 3053 vscl_filter_mode = vsd_filter_mode; 3054 3055 /* 3056 * RK3568 VOP Esmart/Smart dsp_w should be even pixel 3057 * at scale down mode 3058 */ 3059 if ((yrgb_hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) { 3060 printf("win dst_w[%d] should align as 2 pixel\n", dst_w); 3061 dst_w += 1; 3062 } 3063 3064 xfac = vop2_scale_factor(yrgb_hor_scl_mode, hscl_filter_mode, src_w, dst_w); 3065 yfac = vop2_scale_factor(yrgb_ver_scl_mode, vscl_filter_mode, src_h, dst_h); 3066 3067 if (win->type == CLUSTER_LAYER) { 3068 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB + win_offset, 3069 yfac << 16 | xfac); 3070 3071 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, 3072 YRGB_GT2_MASK, CLUSTER_YRGB_GT2_SHIFT, gt2, false); 3073 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, 3074 YRGB_GT4_MASK, CLUSTER_YRGB_GT4_SHIFT, gt4, false); 3075 3076 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, 3077 YRGB_XSCL_MODE_MASK, CLUSTER_YRGB_XSCL_MODE_SHIFT, yrgb_hor_scl_mode, false); 3078 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, 3079 YRGB_YSCL_MODE_MASK, CLUSTER_YRGB_YSCL_MODE_SHIFT, yrgb_ver_scl_mode, false); 3080 3081 } else { 3082 vop2_writel(vop2, RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB + win_offset, 3083 yfac << 16 | xfac); 3084 3085 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, 3086 YRGB_GT2_MASK, YRGB_GT2_SHIFT, gt2, false); 3087 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, 3088 YRGB_GT4_MASK, YRGB_GT4_SHIFT, gt4, false); 3089 3090 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 3091 YRGB_XSCL_MODE_MASK, YRGB_XSCL_MODE_SHIFT, yrgb_hor_scl_mode, false); 3092 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 3093 YRGB_YSCL_MODE_MASK, YRGB_YSCL_MODE_SHIFT, yrgb_ver_scl_mode, false); 3094 3095 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 3096 YRGB_XSCL_FILTER_MODE_MASK, YRGB_XSCL_FILTER_MODE_SHIFT, 3097 hscl_filter_mode, false); 3098 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 3099 YRGB_YSCL_FILTER_MODE_MASK, YRGB_YSCL_FILTER_MODE_SHIFT, 3100 vscl_filter_mode, false); 3101 } 3102 } 3103 3104 static void vop2_axi_config(struct vop2 *vop2, struct vop2_win_data *win) 3105 { 3106 u32 win_offset = win->reg_offset; 3107 3108 if (win->type == CLUSTER_LAYER) { 3109 vop2_mask_write(vop2, RK3568_CLUSTER0_CTRL + win_offset, CLUSTER_AXI_ID_MASK, 3110 CLUSTER_AXI_ID_SHIFT, win->axi_id, false); 3111 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL2 + win_offset, CLUSTER_AXI_YRGB_ID_MASK, 3112 CLUSTER_AXI_YRGB_ID_SHIFT, win->axi_yrgb_id, false); 3113 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL2 + win_offset, CLUSTER_AXI_UV_ID_MASK, 3114 CLUSTER_AXI_UV_ID_SHIFT, win->axi_uv_id, false); 3115 } else { 3116 vop2_mask_write(vop2, RK3568_ESMART0_AXI_CTRL + win_offset, ESMART_AXI_ID_MASK, 3117 ESMART_AXI_ID_SHIFT, win->axi_id, false); 3118 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, ESMART_AXI_YRGB_ID_MASK, 3119 ESMART_AXI_YRGB_ID_SHIFT, win->axi_yrgb_id, false); 3120 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, ESMART_AXI_UV_ID_MASK, 3121 ESMART_AXI_UV_ID_SHIFT, win->axi_uv_id, false); 3122 } 3123 } 3124 3125 static void vop2_set_cluster_win(struct display_state *state, struct vop2_win_data *win) 3126 { 3127 struct crtc_state *cstate = &state->crtc_state; 3128 struct connector_state *conn_state = &state->conn_state; 3129 struct drm_display_mode *mode = &conn_state->mode; 3130 struct vop2 *vop2 = cstate->private; 3131 int src_w = cstate->src_rect.w; 3132 int src_h = cstate->src_rect.h; 3133 int crtc_x = cstate->crtc_rect.x; 3134 int crtc_y = cstate->crtc_rect.y; 3135 int crtc_w = cstate->crtc_rect.w; 3136 int crtc_h = cstate->crtc_rect.h; 3137 int xvir = cstate->xvir; 3138 int y_mirror = 0; 3139 int csc_mode; 3140 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 3141 /* offset of the right window in splice mode */ 3142 u32 splice_pixel_offset = 0; 3143 u32 splice_yrgb_offset = 0; 3144 u32 win_offset = win->reg_offset; 3145 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); 3146 3147 if (win->splice_mode_right) { 3148 src_w = cstate->right_src_rect.w; 3149 src_h = cstate->right_src_rect.h; 3150 crtc_x = cstate->right_crtc_rect.x; 3151 crtc_y = cstate->right_crtc_rect.y; 3152 crtc_w = cstate->right_crtc_rect.w; 3153 crtc_h = cstate->right_crtc_rect.h; 3154 splice_pixel_offset = cstate->right_src_rect.x - cstate->src_rect.x; 3155 splice_yrgb_offset = splice_pixel_offset * (state->logo.bpp >> 3); 3156 cfg_done = CFG_DONE_EN | BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); 3157 } 3158 3159 act_info = (src_h - 1) << 16; 3160 act_info |= (src_w - 1) & 0xffff; 3161 3162 dsp_info = (crtc_h - 1) << 16; 3163 dsp_info |= (crtc_w - 1) & 0xffff; 3164 3165 dsp_stx = crtc_x; 3166 dsp_sty = crtc_y; 3167 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 3168 3169 if (mode->flags & DRM_MODE_FLAG_YMIRROR) 3170 y_mirror = 1; 3171 else 3172 y_mirror = 0; 3173 3174 vop2_setup_scale(vop2, win, src_w, src_h, crtc_w, crtc_h); 3175 3176 if (vop2->version == VOP_VERSION_RK3588) 3177 vop2_axi_config(vop2, win); 3178 3179 if (y_mirror) 3180 printf("WARN: y mirror is unsupported by cluster window\n"); 3181 3182 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, 3183 WIN_FORMAT_MASK, WIN_FORMAT_SHIFT, cstate->format, 3184 false); 3185 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_VIR + win_offset, xvir); 3186 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_YRGB_MST + win_offset, 3187 cstate->dma_addr + splice_yrgb_offset); 3188 3189 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_ACT_INFO + win_offset, act_info); 3190 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_DSP_INFO + win_offset, dsp_info); 3191 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_DSP_ST + win_offset, dsp_st); 3192 3193 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, WIN_EN_SHIFT, 1, false); 3194 3195 csc_mode = vop2_convert_csc_mode(conn_state->color_space); 3196 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, 3197 CLUSTER_RGB2YUV_EN_SHIFT, 3198 is_yuv_output(conn_state->bus_format), false); 3199 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, CSC_MODE_MASK, 3200 CLUSTER_CSC_MODE_SHIFT, csc_mode, false); 3201 vop2_mask_write(vop2, RK3568_CLUSTER0_CTRL + win_offset, EN_MASK, CLUSTER_EN_SHIFT, 1, false); 3202 3203 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 3204 } 3205 3206 static void vop2_set_smart_win(struct display_state *state, struct vop2_win_data *win) 3207 { 3208 struct crtc_state *cstate = &state->crtc_state; 3209 struct connector_state *conn_state = &state->conn_state; 3210 struct drm_display_mode *mode = &conn_state->mode; 3211 struct vop2 *vop2 = cstate->private; 3212 int src_w = cstate->src_rect.w; 3213 int src_h = cstate->src_rect.h; 3214 int crtc_x = cstate->crtc_rect.x; 3215 int crtc_y = cstate->crtc_rect.y; 3216 int crtc_w = cstate->crtc_rect.w; 3217 int crtc_h = cstate->crtc_rect.h; 3218 int xvir = cstate->xvir; 3219 int y_mirror = 0; 3220 int csc_mode; 3221 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 3222 /* offset of the right window in splice mode */ 3223 u32 splice_pixel_offset = 0; 3224 u32 splice_yrgb_offset = 0; 3225 u32 win_offset = win->reg_offset; 3226 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); 3227 3228 if (win->splice_mode_right) { 3229 src_w = cstate->right_src_rect.w; 3230 src_h = cstate->right_src_rect.h; 3231 crtc_x = cstate->right_crtc_rect.x; 3232 crtc_y = cstate->right_crtc_rect.y; 3233 crtc_w = cstate->right_crtc_rect.w; 3234 crtc_h = cstate->right_crtc_rect.h; 3235 splice_pixel_offset = cstate->right_src_rect.x - cstate->src_rect.x; 3236 splice_yrgb_offset = splice_pixel_offset * (state->logo.bpp >> 3); 3237 cfg_done = CFG_DONE_EN | BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); 3238 } 3239 3240 /* 3241 * This is workaround solution for IC design: 3242 * esmart can't support scale down when actual_w % 16 == 1. 3243 */ 3244 if (src_w > crtc_w && (src_w & 0xf) == 1) { 3245 printf("WARN: vp%d unsupported act_w[%d] mode 16 = 1 when scale down\n", cstate->crtc_id, src_w); 3246 src_w -= 1; 3247 } 3248 3249 act_info = (src_h - 1) << 16; 3250 act_info |= (src_w - 1) & 0xffff; 3251 3252 dsp_info = (crtc_h - 1) << 16; 3253 dsp_info |= (crtc_w - 1) & 0xffff; 3254 3255 dsp_stx = crtc_x; 3256 dsp_sty = crtc_y; 3257 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 3258 3259 if (mode->flags & DRM_MODE_FLAG_YMIRROR) 3260 y_mirror = 1; 3261 else 3262 y_mirror = 0; 3263 3264 vop2_setup_scale(vop2, win, src_w, src_h, crtc_w, crtc_h); 3265 3266 if (vop2->version == VOP_VERSION_RK3588) 3267 vop2_axi_config(vop2, win); 3268 3269 if (y_mirror) 3270 cstate->dma_addr += (src_h - 1) * xvir * 4; 3271 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, EN_MASK, 3272 YMIRROR_EN_SHIFT, y_mirror, false); 3273 3274 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, 3275 WIN_FORMAT_MASK, WIN_FORMAT_SHIFT, cstate->format, 3276 false); 3277 vop2_writel(vop2, RK3568_ESMART0_REGION0_VIR + win_offset, xvir); 3278 vop2_writel(vop2, RK3568_ESMART0_REGION0_YRGB_MST + win_offset, 3279 cstate->dma_addr + splice_yrgb_offset); 3280 3281 vop2_writel(vop2, RK3568_ESMART0_REGION0_ACT_INFO + win_offset, 3282 act_info); 3283 vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_INFO + win_offset, 3284 dsp_info); 3285 vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_ST + win_offset, dsp_st); 3286 3287 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK, 3288 WIN_EN_SHIFT, 1, false); 3289 3290 csc_mode = vop2_convert_csc_mode(conn_state->color_space); 3291 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, EN_MASK, 3292 RGB2YUV_EN_SHIFT, 3293 is_yuv_output(conn_state->bus_format), false); 3294 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, CSC_MODE_MASK, 3295 CSC_MODE_SHIFT, csc_mode, false); 3296 3297 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 3298 } 3299 3300 static void vop2_calc_display_rect_for_splice(struct display_state *state) 3301 { 3302 struct crtc_state *cstate = &state->crtc_state; 3303 struct connector_state *conn_state = &state->conn_state; 3304 struct drm_display_mode *mode = &conn_state->mode; 3305 struct display_rect *src_rect = &cstate->src_rect; 3306 struct display_rect *dst_rect = &cstate->crtc_rect; 3307 struct display_rect left_src, left_dst, right_src, right_dst; 3308 u16 half_hdisplay = mode->crtc_hdisplay >> 1; 3309 int left_src_w, left_dst_w, right_dst_w; 3310 3311 left_dst_w = min_t(u16, half_hdisplay, dst_rect->x + dst_rect->w) - dst_rect->x; 3312 if (left_dst_w < 0) 3313 left_dst_w = 0; 3314 right_dst_w = dst_rect->w - left_dst_w; 3315 3316 if (!right_dst_w) 3317 left_src_w = src_rect->w; 3318 else 3319 left_src_w = src_rect->x + src_rect->w - src_rect->w / 2; 3320 3321 left_src.x = src_rect->x; 3322 left_src.w = left_src_w; 3323 left_dst.x = dst_rect->x; 3324 left_dst.w = left_dst_w; 3325 right_src.x = left_src.x + left_src.w; 3326 right_src.w = src_rect->x + src_rect->w - left_src.x - left_src.w; 3327 right_dst.x = dst_rect->x + left_dst_w - half_hdisplay; 3328 right_dst.w = right_dst_w; 3329 3330 left_src.y = src_rect->y; 3331 left_src.h = src_rect->h; 3332 left_dst.y = dst_rect->y; 3333 left_dst.h = dst_rect->h; 3334 right_src.y = src_rect->y; 3335 right_src.h = src_rect->h; 3336 right_dst.y = dst_rect->y; 3337 right_dst.h = dst_rect->h; 3338 3339 memcpy(&cstate->src_rect, &left_src, sizeof(struct display_rect)); 3340 memcpy(&cstate->crtc_rect, &left_dst, sizeof(struct display_rect)); 3341 memcpy(&cstate->right_src_rect, &right_src, sizeof(struct display_rect)); 3342 memcpy(&cstate->right_crtc_rect, &right_dst, sizeof(struct display_rect)); 3343 } 3344 3345 static int rockchip_vop2_set_plane(struct display_state *state) 3346 { 3347 struct crtc_state *cstate = &state->crtc_state; 3348 struct vop2 *vop2 = cstate->private; 3349 struct vop2_win_data *win_data; 3350 struct vop2_win_data *splice_win_data; 3351 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; 3352 char plane_name[10] = {0}; 3353 3354 if (cstate->crtc_rect.w > cstate->max_output.width) { 3355 printf("ERROR: output w[%d] exceeded max width[%d]\n", 3356 cstate->crtc_rect.w, cstate->max_output.width); 3357 return -EINVAL; 3358 } 3359 3360 win_data = vop2_find_win_by_phys_id(vop2, primary_plane_id); 3361 if (!win_data) { 3362 printf("invalid win id %d\n", primary_plane_id); 3363 return -ENODEV; 3364 } 3365 3366 if (vop2->version == VOP_VERSION_RK3588) { 3367 if (vop2_power_domain_on(vop2, win_data->pd_id)) 3368 printf("open vp%d plane pd fail\n", cstate->crtc_id); 3369 } 3370 3371 if (cstate->splice_mode) { 3372 if (win_data->splice_win_id) { 3373 splice_win_data = vop2_find_win_by_phys_id(vop2, win_data->splice_win_id); 3374 splice_win_data->splice_mode_right = true; 3375 3376 if (vop2_power_domain_on(vop2, splice_win_data->pd_id)) 3377 printf("splice mode: open vp%d plane pd fail\n", cstate->splice_crtc_id); 3378 3379 vop2_calc_display_rect_for_splice(state); 3380 if (win_data->type == CLUSTER_LAYER) 3381 vop2_set_cluster_win(state, splice_win_data); 3382 else 3383 vop2_set_smart_win(state, splice_win_data); 3384 } else { 3385 printf("ERROR: splice mode is unsupported by plane %s\n", 3386 get_plane_name(primary_plane_id, plane_name)); 3387 return -EINVAL; 3388 } 3389 } 3390 3391 if (win_data->type == CLUSTER_LAYER) 3392 vop2_set_cluster_win(state, win_data); 3393 else 3394 vop2_set_smart_win(state, win_data); 3395 3396 printf("VOP VP%d enable %s[%dx%d->%dx%d@%dx%d] fmt[%d] addr[0x%x]\n", 3397 cstate->crtc_id, get_plane_name(primary_plane_id, plane_name), 3398 cstate->src_rect.w, cstate->src_rect.h, cstate->crtc_rect.w, cstate->crtc_rect.h, 3399 cstate->crtc_rect.x, cstate->crtc_rect.y, cstate->format, 3400 cstate->dma_addr); 3401 3402 return 0; 3403 } 3404 3405 static int rockchip_vop2_prepare(struct display_state *state) 3406 { 3407 return 0; 3408 } 3409 3410 static void vop2_dsc_cfg_done(struct display_state *state) 3411 { 3412 struct connector_state *conn_state = &state->conn_state; 3413 struct crtc_state *cstate = &state->crtc_state; 3414 struct vop2 *vop2 = cstate->private; 3415 u8 dsc_id = cstate->dsc_id; 3416 u32 ctrl_regs_offset = (dsc_id * 0x30); 3417 3418 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { 3419 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE, EN_MASK, 3420 DSC_CFG_DONE_SHIFT, 1, false); 3421 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE + 0x30, EN_MASK, 3422 DSC_CFG_DONE_SHIFT, 1, false); 3423 } else { 3424 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE + ctrl_regs_offset, EN_MASK, 3425 DSC_CFG_DONE_SHIFT, 1, false); 3426 } 3427 } 3428 3429 static int rockchip_vop2_enable(struct display_state *state) 3430 { 3431 struct crtc_state *cstate = &state->crtc_state; 3432 struct vop2 *vop2 = cstate->private; 3433 u32 vp_offset = (cstate->crtc_id * 0x100); 3434 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); 3435 3436 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 3437 STANDBY_EN_SHIFT, 0, false); 3438 3439 if (cstate->splice_mode) 3440 cfg_done |= BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); 3441 3442 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 3443 3444 if (cstate->dsc_enable) 3445 vop2_dsc_cfg_done(state); 3446 3447 return 0; 3448 } 3449 3450 static int rockchip_vop2_disable(struct display_state *state) 3451 { 3452 struct crtc_state *cstate = &state->crtc_state; 3453 struct vop2 *vop2 = cstate->private; 3454 u32 vp_offset = (cstate->crtc_id * 0x100); 3455 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); 3456 3457 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 3458 STANDBY_EN_SHIFT, 1, false); 3459 3460 if (cstate->splice_mode) 3461 cfg_done |= BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); 3462 3463 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 3464 3465 return 0; 3466 } 3467 3468 static int rockchip_vop2_get_cursor_plane(struct display_state *state, u32 plane_mask, int cursor_plane) 3469 { 3470 struct crtc_state *cstate = &state->crtc_state; 3471 struct vop2 *vop2 = cstate->private; 3472 int i = 0; 3473 int correct_cursor_plane = -1; 3474 int plane_type = -1; 3475 3476 if (cursor_plane < 0) 3477 return -1; 3478 3479 if (plane_mask & (1 << cursor_plane)) 3480 return cursor_plane; 3481 3482 /* Get current cursor plane type */ 3483 for (i = 0; i < vop2->data->nr_layers; i++) { 3484 if (vop2->data->plane_table[i].plane_id == cursor_plane) { 3485 plane_type = vop2->data->plane_table[i].plane_type; 3486 break; 3487 } 3488 } 3489 3490 /* Get the other same plane type plane id */ 3491 for (i = 0; i < vop2->data->nr_layers; i++) { 3492 if (vop2->data->plane_table[i].plane_type == plane_type && 3493 vop2->data->plane_table[i].plane_id != cursor_plane) { 3494 correct_cursor_plane = vop2->data->plane_table[i].plane_id; 3495 break; 3496 } 3497 } 3498 3499 /* To check whether the new correct_cursor_plane is attach to current vp */ 3500 if (correct_cursor_plane < 0 || !(plane_mask & (1 << correct_cursor_plane))) { 3501 printf("error: faild to find correct plane as cursor plane\n"); 3502 return -1; 3503 } 3504 3505 printf("vp%d adjust cursor plane from %d to %d\n", 3506 cstate->crtc_id, cursor_plane, correct_cursor_plane); 3507 3508 return correct_cursor_plane; 3509 } 3510 3511 static int rockchip_vop2_fixup_dts(struct display_state *state, void *blob) 3512 { 3513 struct crtc_state *cstate = &state->crtc_state; 3514 struct vop2 *vop2 = cstate->private; 3515 ofnode vp_node; 3516 struct device_node *port_parent_node = cstate->ports_node; 3517 static bool vop_fix_dts; 3518 const char *path; 3519 u32 plane_mask = 0; 3520 int vp_id = 0; 3521 int cursor_plane_id = -1; 3522 3523 if (vop_fix_dts) 3524 return 0; 3525 3526 ofnode_for_each_subnode(vp_node, np_to_ofnode(port_parent_node)) { 3527 path = vp_node.np->full_name; 3528 plane_mask = vop2->vp_plane_mask[vp_id].plane_mask; 3529 3530 if (cstate->crtc->assign_plane) 3531 continue; 3532 cursor_plane_id = rockchip_vop2_get_cursor_plane(state, plane_mask, 3533 cstate->crtc->vps[vp_id].cursor_plane); 3534 printf("vp%d, plane_mask:0x%x, primary-id:%d, curser-id:%d\n", 3535 vp_id, plane_mask, 3536 vop2->vp_plane_mask[vp_id].primary_plane_id, 3537 cursor_plane_id); 3538 3539 do_fixup_by_path_u32(blob, path, "rockchip,plane-mask", 3540 plane_mask, 1); 3541 do_fixup_by_path_u32(blob, path, "rockchip,primary-plane", 3542 vop2->vp_plane_mask[vp_id].primary_plane_id, 1); 3543 if (cursor_plane_id >= 0) 3544 do_fixup_by_path_u32(blob, path, "cursor-win-id", 3545 cursor_plane_id, 1); 3546 vp_id++; 3547 } 3548 3549 vop_fix_dts = true; 3550 3551 return 0; 3552 } 3553 3554 static struct vop2_plane_table rk356x_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = { 3555 {ROCKCHIP_VOP2_CLUSTER0, CLUSTER_LAYER}, 3556 {ROCKCHIP_VOP2_CLUSTER1, CLUSTER_LAYER}, 3557 {ROCKCHIP_VOP2_ESMART0, ESMART_LAYER}, 3558 {ROCKCHIP_VOP2_ESMART1, ESMART_LAYER}, 3559 {ROCKCHIP_VOP2_SMART0, SMART_LAYER}, 3560 {ROCKCHIP_VOP2_SMART0, SMART_LAYER}, 3561 }; 3562 3563 static struct vop2_vp_plane_mask rk356x_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = { 3564 { /* one display policy */ 3565 {/* main display */ 3566 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 3567 .attached_layers_nr = 6, 3568 .attached_layers = { 3569 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0, 3570 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_SMART1 3571 }, 3572 }, 3573 {/* second display */}, 3574 {/* third display */}, 3575 {/* fourth display */}, 3576 }, 3577 3578 { /* two display policy */ 3579 {/* main display */ 3580 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 3581 .attached_layers_nr = 3, 3582 .attached_layers = { 3583 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0 3584 }, 3585 }, 3586 3587 {/* second display */ 3588 .primary_plane_id = ROCKCHIP_VOP2_SMART1, 3589 .attached_layers_nr = 3, 3590 .attached_layers = { 3591 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_SMART1 3592 }, 3593 }, 3594 {/* third display */}, 3595 {/* fourth display */}, 3596 }, 3597 3598 { /* three display policy */ 3599 {/* main display */ 3600 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 3601 .attached_layers_nr = 3, 3602 .attached_layers = { 3603 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0 3604 }, 3605 }, 3606 3607 {/* second display */ 3608 .primary_plane_id = ROCKCHIP_VOP2_SMART1, 3609 .attached_layers_nr = 2, 3610 .attached_layers = { 3611 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_SMART1 3612 }, 3613 }, 3614 3615 {/* third display */ 3616 .primary_plane_id = ROCKCHIP_VOP2_ESMART1, 3617 .attached_layers_nr = 1, 3618 .attached_layers = { ROCKCHIP_VOP2_ESMART1 }, 3619 }, 3620 3621 {/* fourth display */}, 3622 }, 3623 3624 {/* reserved for four display policy */}, 3625 }; 3626 3627 static struct vop2_win_data rk3568_win_data[6] = { 3628 { 3629 .name = "Cluster0", 3630 .phys_id = ROCKCHIP_VOP2_CLUSTER0, 3631 .type = CLUSTER_LAYER, 3632 .win_sel_port_offset = 0, 3633 .layer_sel_win_id = 0, 3634 .reg_offset = 0, 3635 }, 3636 3637 { 3638 .name = "Cluster1", 3639 .phys_id = ROCKCHIP_VOP2_CLUSTER1, 3640 .type = CLUSTER_LAYER, 3641 .win_sel_port_offset = 1, 3642 .layer_sel_win_id = 1, 3643 .reg_offset = 0x200, 3644 }, 3645 3646 { 3647 .name = "Esmart0", 3648 .phys_id = ROCKCHIP_VOP2_ESMART0, 3649 .type = ESMART_LAYER, 3650 .win_sel_port_offset = 4, 3651 .layer_sel_win_id = 2, 3652 .reg_offset = 0, 3653 }, 3654 3655 { 3656 .name = "Esmart1", 3657 .phys_id = ROCKCHIP_VOP2_ESMART1, 3658 .type = ESMART_LAYER, 3659 .win_sel_port_offset = 5, 3660 .layer_sel_win_id = 6, 3661 .reg_offset = 0x200, 3662 }, 3663 3664 { 3665 .name = "Smart0", 3666 .phys_id = ROCKCHIP_VOP2_SMART0, 3667 .type = SMART_LAYER, 3668 .win_sel_port_offset = 6, 3669 .layer_sel_win_id = 3, 3670 .reg_offset = 0x400, 3671 }, 3672 3673 { 3674 .name = "Smart1", 3675 .phys_id = ROCKCHIP_VOP2_SMART1, 3676 .type = SMART_LAYER, 3677 .win_sel_port_offset = 7, 3678 .layer_sel_win_id = 7, 3679 .reg_offset = 0x600, 3680 }, 3681 }; 3682 3683 static struct vop2_vp_data rk3568_vp_data[3] = { 3684 { 3685 .feature = VOP_FEATURE_OUTPUT_10BIT, 3686 .pre_scan_max_dly = 42, 3687 .max_output = {4096, 2304}, 3688 }, 3689 { 3690 .feature = 0, 3691 .pre_scan_max_dly = 40, 3692 .max_output = {2048, 1536}, 3693 }, 3694 { 3695 .feature = 0, 3696 .pre_scan_max_dly = 40, 3697 .max_output = {1920, 1080}, 3698 }, 3699 }; 3700 3701 const struct vop2_data rk3568_vop = { 3702 .version = VOP_VERSION_RK3568, 3703 .nr_vps = 3, 3704 .vp_data = rk3568_vp_data, 3705 .win_data = rk3568_win_data, 3706 .plane_mask = rk356x_vp_plane_mask[0], 3707 .plane_table = rk356x_plane_table, 3708 .nr_layers = 6, 3709 .nr_mixers = 5, 3710 .nr_gammas = 1, 3711 }; 3712 3713 static struct vop2_plane_table rk3588_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = { 3714 {ROCKCHIP_VOP2_CLUSTER0, CLUSTER_LAYER}, 3715 {ROCKCHIP_VOP2_CLUSTER1, CLUSTER_LAYER}, 3716 {ROCKCHIP_VOP2_CLUSTER2, CLUSTER_LAYER}, 3717 {ROCKCHIP_VOP2_CLUSTER3, CLUSTER_LAYER}, 3718 {ROCKCHIP_VOP2_ESMART0, ESMART_LAYER}, 3719 {ROCKCHIP_VOP2_ESMART1, ESMART_LAYER}, 3720 {ROCKCHIP_VOP2_ESMART2, ESMART_LAYER}, 3721 {ROCKCHIP_VOP2_ESMART3, ESMART_LAYER}, 3722 }; 3723 3724 static struct vop2_vp_plane_mask rk3588_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = { 3725 { /* one display policy */ 3726 {/* main display */ 3727 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0, 3728 .attached_layers_nr = 8, 3729 .attached_layers = { 3730 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART2, 3731 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_ESMART3, 3732 ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_CLUSTER3 3733 }, 3734 }, 3735 {/* second display */}, 3736 {/* third display */}, 3737 {/* fourth display */}, 3738 }, 3739 3740 { /* two display policy */ 3741 {/* main display */ 3742 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0, 3743 .attached_layers_nr = 4, 3744 .attached_layers = { 3745 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, 3746 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1 3747 }, 3748 }, 3749 3750 {/* second display */ 3751 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER2, 3752 .attached_layers_nr = 4, 3753 .attached_layers = { 3754 ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2, 3755 ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART3 3756 }, 3757 }, 3758 {/* third display */}, 3759 {/* fourth display */}, 3760 }, 3761 3762 { /* three display policy */ 3763 {/* main display */ 3764 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0, 3765 .attached_layers_nr = 3, 3766 .attached_layers = { 3767 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART0 3768 }, 3769 }, 3770 3771 {/* second display */ 3772 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER2, 3773 .attached_layers_nr = 3, 3774 .attached_layers = { 3775 ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART1 3776 }, 3777 }, 3778 3779 {/* third display */ 3780 .primary_plane_id = ROCKCHIP_VOP2_ESMART2, 3781 .attached_layers_nr = 2, 3782 .attached_layers = { ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3 }, 3783 }, 3784 3785 {/* fourth display */}, 3786 }, 3787 3788 { /* four display policy */ 3789 {/* main display */ 3790 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0, 3791 .attached_layers_nr = 2, 3792 .attached_layers = { ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0 }, 3793 }, 3794 3795 {/* second display */ 3796 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER1, 3797 .attached_layers_nr = 2, 3798 .attached_layers = { ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1 }, 3799 }, 3800 3801 {/* third display */ 3802 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER2, 3803 .attached_layers_nr = 2, 3804 .attached_layers = { ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2 }, 3805 }, 3806 3807 {/* fourth display */ 3808 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER3, 3809 .attached_layers_nr = 2, 3810 .attached_layers = { ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART3 }, 3811 }, 3812 }, 3813 3814 }; 3815 3816 static struct vop2_win_data rk3588_win_data[8] = { 3817 { 3818 .name = "Cluster0", 3819 .phys_id = ROCKCHIP_VOP2_CLUSTER0, 3820 .splice_win_id = ROCKCHIP_VOP2_CLUSTER1, 3821 .type = CLUSTER_LAYER, 3822 .win_sel_port_offset = 0, 3823 .layer_sel_win_id = 0, 3824 .reg_offset = 0, 3825 .axi_id = 0, 3826 .axi_yrgb_id = 2, 3827 .axi_uv_id = 3, 3828 .pd_id = VOP2_PD_CLUSTER0, 3829 }, 3830 3831 { 3832 .name = "Cluster1", 3833 .phys_id = ROCKCHIP_VOP2_CLUSTER1, 3834 .type = CLUSTER_LAYER, 3835 .win_sel_port_offset = 1, 3836 .layer_sel_win_id = 1, 3837 .reg_offset = 0x200, 3838 .axi_id = 0, 3839 .axi_yrgb_id = 6, 3840 .axi_uv_id = 7, 3841 .pd_id = VOP2_PD_CLUSTER1, 3842 }, 3843 3844 { 3845 .name = "Cluster2", 3846 .phys_id = ROCKCHIP_VOP2_CLUSTER2, 3847 .splice_win_id = ROCKCHIP_VOP2_CLUSTER3, 3848 .type = CLUSTER_LAYER, 3849 .win_sel_port_offset = 2, 3850 .layer_sel_win_id = 4, 3851 .reg_offset = 0x400, 3852 .axi_id = 1, 3853 .axi_yrgb_id = 2, 3854 .axi_uv_id = 3, 3855 .pd_id = VOP2_PD_CLUSTER2, 3856 }, 3857 3858 { 3859 .name = "Cluster3", 3860 .phys_id = ROCKCHIP_VOP2_CLUSTER3, 3861 .type = CLUSTER_LAYER, 3862 .win_sel_port_offset = 3, 3863 .layer_sel_win_id = 5, 3864 .reg_offset = 0x600, 3865 .axi_id = 1, 3866 .axi_yrgb_id = 6, 3867 .axi_uv_id = 7, 3868 .pd_id = VOP2_PD_CLUSTER3, 3869 }, 3870 3871 { 3872 .name = "Esmart0", 3873 .phys_id = ROCKCHIP_VOP2_ESMART0, 3874 .splice_win_id = ROCKCHIP_VOP2_ESMART1, 3875 .type = ESMART_LAYER, 3876 .win_sel_port_offset = 4, 3877 .layer_sel_win_id = 2, 3878 .reg_offset = 0, 3879 .axi_id = 0, 3880 .axi_yrgb_id = 0x0a, 3881 .axi_uv_id = 0x0b, 3882 }, 3883 3884 { 3885 .name = "Esmart1", 3886 .phys_id = ROCKCHIP_VOP2_ESMART1, 3887 .type = ESMART_LAYER, 3888 .win_sel_port_offset = 5, 3889 .layer_sel_win_id = 3, 3890 .reg_offset = 0x200, 3891 .axi_id = 0, 3892 .axi_yrgb_id = 0x0c, 3893 .axi_uv_id = 0x0d, 3894 .pd_id = VOP2_PD_ESMART, 3895 }, 3896 3897 { 3898 .name = "Esmart2", 3899 .phys_id = ROCKCHIP_VOP2_ESMART2, 3900 .splice_win_id = ROCKCHIP_VOP2_ESMART3, 3901 .type = ESMART_LAYER, 3902 .win_sel_port_offset = 6, 3903 .layer_sel_win_id = 6, 3904 .reg_offset = 0x400, 3905 .axi_id = 1, 3906 .axi_yrgb_id = 0x0a, 3907 .axi_uv_id = 0x0b, 3908 .pd_id = VOP2_PD_ESMART, 3909 }, 3910 3911 { 3912 .name = "Esmart3", 3913 .phys_id = ROCKCHIP_VOP2_ESMART3, 3914 .type = ESMART_LAYER, 3915 .win_sel_port_offset = 7, 3916 .layer_sel_win_id = 7, 3917 .reg_offset = 0x600, 3918 .axi_id = 1, 3919 .axi_yrgb_id = 0x0c, 3920 .axi_uv_id = 0x0d, 3921 .pd_id = VOP2_PD_ESMART, 3922 }, 3923 }; 3924 3925 static struct dsc_error_info dsc_ecw[] = { 3926 {0x00000000, "no error detected by DSC encoder"}, 3927 {0x0030ffff, "bits per component error"}, 3928 {0x0040ffff, "multiple mode error"}, 3929 {0x0050ffff, "line buffer depth error"}, 3930 {0x0060ffff, "minor version error"}, 3931 {0x0070ffff, "picture height error"}, 3932 {0x0080ffff, "picture width error"}, 3933 {0x0090ffff, "number of slices error"}, 3934 {0x00c0ffff, "slice height Error "}, 3935 {0x00d0ffff, "slice width error"}, 3936 {0x00e0ffff, "second line BPG offset error"}, 3937 {0x00f0ffff, "non second line BPG offset error"}, 3938 {0x0100ffff, "PPS ID error"}, 3939 {0x0110ffff, "bits per pixel (BPP) Error"}, 3940 {0x0120ffff, "buffer flow error"}, /* dsc_buffer_flow */ 3941 3942 {0x01510001, "slice 0 RC buffer model overflow error"}, 3943 {0x01510002, "slice 1 RC buffer model overflow error"}, 3944 {0x01510004, "slice 2 RC buffer model overflow error"}, 3945 {0x01510008, "slice 3 RC buffer model overflow error"}, 3946 {0x01510010, "slice 4 RC buffer model overflow error"}, 3947 {0x01510020, "slice 5 RC buffer model overflow error"}, 3948 {0x01510040, "slice 6 RC buffer model overflow error"}, 3949 {0x01510080, "slice 7 RC buffer model overflow error"}, 3950 3951 {0x01610001, "slice 0 RC buffer model underflow error"}, 3952 {0x01610002, "slice 1 RC buffer model underflow error"}, 3953 {0x01610004, "slice 2 RC buffer model underflow error"}, 3954 {0x01610008, "slice 3 RC buffer model underflow error"}, 3955 {0x01610010, "slice 4 RC buffer model underflow error"}, 3956 {0x01610020, "slice 5 RC buffer model underflow error"}, 3957 {0x01610040, "slice 6 RC buffer model underflow error"}, 3958 {0x01610080, "slice 7 RC buffer model underflow error"}, 3959 3960 {0xffffffff, "unsuccessful RESET cycle status"}, 3961 {0x00a0ffff, "ICH full error precision settings error"}, 3962 {0x0020ffff, "native mode"}, 3963 }; 3964 3965 static struct dsc_error_info dsc_buffer_flow[] = { 3966 {0x00000000, "rate buffer status"}, 3967 {0x00000001, "line buffer status"}, 3968 {0x00000002, "decoder model status"}, 3969 {0x00000003, "pixel buffer status"}, 3970 {0x00000004, "balance fifo buffer status"}, 3971 {0x00000005, "syntax element fifo status"}, 3972 }; 3973 3974 static struct vop2_dsc_data rk3588_dsc_data[] = { 3975 { 3976 .id = ROCKCHIP_VOP2_DSC_8K, 3977 .pd_id = VOP2_PD_DSC_8K, 3978 .max_slice_num = 8, 3979 .max_linebuf_depth = 11, 3980 .min_bits_per_pixel = 8, 3981 .dsc_txp_clk_src_name = "dsc_8k_txp_clk_src", 3982 .dsc_txp_clk_name = "dsc_8k_txp_clk", 3983 .dsc_pxl_clk_name = "dsc_8k_pxl_clk", 3984 .dsc_cds_clk_name = "dsc_8k_cds_clk", 3985 }, 3986 3987 { 3988 .id = ROCKCHIP_VOP2_DSC_4K, 3989 .pd_id = VOP2_PD_DSC_4K, 3990 .max_slice_num = 2, 3991 .max_linebuf_depth = 11, 3992 .min_bits_per_pixel = 8, 3993 .dsc_txp_clk_src_name = "dsc_4k_txp_clk_src", 3994 .dsc_txp_clk_name = "dsc_4k_txp_clk", 3995 .dsc_pxl_clk_name = "dsc_4k_pxl_clk", 3996 .dsc_cds_clk_name = "dsc_4k_cds_clk", 3997 }, 3998 }; 3999 4000 static struct vop2_vp_data rk3588_vp_data[4] = { 4001 { 4002 .splice_vp_id = 1, 4003 .feature = VOP_FEATURE_OUTPUT_10BIT, 4004 .pre_scan_max_dly = 54, 4005 .max_dclk = 600000, 4006 .max_output = {7680, 4320}, 4007 }, 4008 { 4009 .feature = VOP_FEATURE_OUTPUT_10BIT, 4010 .pre_scan_max_dly = 54, 4011 .max_dclk = 600000, 4012 .max_output = {4096, 2304}, 4013 }, 4014 { 4015 .feature = VOP_FEATURE_OUTPUT_10BIT, 4016 .pre_scan_max_dly = 52, 4017 .max_dclk = 600000, 4018 .max_output = {4096, 2304}, 4019 }, 4020 { 4021 .feature = 0, 4022 .pre_scan_max_dly = 52, 4023 .max_dclk = 200000, 4024 .max_output = {1920, 1080}, 4025 }, 4026 }; 4027 4028 static struct vop2_power_domain_data rk3588_vop_pd_data[] = { 4029 { 4030 .id = VOP2_PD_CLUSTER0, 4031 .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER0), 4032 }, 4033 { 4034 .id = VOP2_PD_CLUSTER1, 4035 .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER1), 4036 .parent_id = VOP2_PD_CLUSTER0, 4037 }, 4038 { 4039 .id = VOP2_PD_CLUSTER2, 4040 .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER2), 4041 .parent_id = VOP2_PD_CLUSTER0, 4042 }, 4043 { 4044 .id = VOP2_PD_CLUSTER3, 4045 .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER3), 4046 .parent_id = VOP2_PD_CLUSTER0, 4047 }, 4048 { 4049 .id = VOP2_PD_ESMART, 4050 .module_id_mask = BIT(ROCKCHIP_VOP2_ESMART1) | 4051 BIT(ROCKCHIP_VOP2_ESMART2) | 4052 BIT(ROCKCHIP_VOP2_ESMART3), 4053 }, 4054 { 4055 .id = VOP2_PD_DSC_8K, 4056 .module_id_mask = BIT(ROCKCHIP_VOP2_DSC_8K), 4057 }, 4058 { 4059 .id = VOP2_PD_DSC_4K, 4060 .module_id_mask = BIT(ROCKCHIP_VOP2_DSC_4K), 4061 }, 4062 }; 4063 4064 const struct vop2_data rk3588_vop = { 4065 .version = VOP_VERSION_RK3588, 4066 .nr_vps = 4, 4067 .vp_data = rk3588_vp_data, 4068 .win_data = rk3588_win_data, 4069 .plane_mask = rk3588_vp_plane_mask[0], 4070 .plane_table = rk3588_plane_table, 4071 .pd = rk3588_vop_pd_data, 4072 .dsc = rk3588_dsc_data, 4073 .dsc_error_ecw = dsc_ecw, 4074 .dsc_error_buffer_flow = dsc_buffer_flow, 4075 .nr_layers = 8, 4076 .nr_mixers = 7, 4077 .nr_gammas = 4, 4078 .nr_pd = ARRAY_SIZE(rk3588_vop_pd_data), 4079 .nr_dscs = 2, 4080 .nr_dsc_ecw = ARRAY_SIZE(dsc_ecw), 4081 .nr_dsc_buffer_flow = ARRAY_SIZE(dsc_buffer_flow), 4082 }; 4083 4084 const struct rockchip_crtc_funcs rockchip_vop2_funcs = { 4085 .preinit = rockchip_vop2_preinit, 4086 .prepare = rockchip_vop2_prepare, 4087 .init = rockchip_vop2_init, 4088 .set_plane = rockchip_vop2_set_plane, 4089 .enable = rockchip_vop2_enable, 4090 .disable = rockchip_vop2_disable, 4091 .fixup_dts = rockchip_vop2_fixup_dts, 4092 }; 4093