1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ROCKCHIP_VOP_H_ 8 #define _ROCKCHIP_VOP_H_ 9 10 /* 11 * major: IP major vertion, used for IP structure 12 * minor: big feature change under same structure 13 */ 14 #define VOP_VERSION(major, minor) ((major) << 8 | (minor)) 15 #define VOP_MAJOR(version) ((version) >> 8) 16 #define VOP_MINOR(version) ((version) & 0xff) 17 18 #define VOP_REG_SUPPORT(vop, reg) \ 19 (!reg.major || (reg.major == VOP_MAJOR(vop->version) && \ 20 reg.begin_minor <= VOP_MINOR(vop->version) && \ 21 reg.end_minor >= VOP_MINOR(vop->version) && \ 22 reg.mask)) 23 24 #define VOP_WIN_SUPPORT(vop, win, name) \ 25 VOP_REG_SUPPORT(vop, win->name) 26 27 #define VOP_CTRL_SUPPORT(vop, name) \ 28 VOP_REG_SUPPORT(vop, vop->ctrl->name) 29 30 #define __REG_SET(x, off, mask, shift, v, write_mask) \ 31 vop_mask_write(x, off, mask, shift, v, write_mask) 32 33 #define _REG_SET(vop, name, off, reg, mask, v) \ 34 do { \ 35 if (VOP_REG_SUPPORT(vop, reg)) \ 36 __REG_SET(vop, off + reg.offset, mask, reg.shift, \ 37 v, reg.write_mask); \ 38 else \ 39 debug("Warning: not support "#name"\n"); \ 40 } while(0) 41 42 #define REG_SET(x, name, off, reg, v) \ 43 _REG_SET(x, name, off, reg, reg.mask, v) 44 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \ 45 _REG_SET(x, name, off, reg, reg.mask & mask, v) 46 47 #define VOP_WIN_SET(x, name, v) \ 48 REG_SET(x, name, x->win_offset, x->win->name, v) 49 #define VOP_WIN_SET_EXT(x, ext, name, v) \ 50 REG_SET(x, name, x->win_offset, x->win->ext->name, v) 51 #define VOP_SCL_SET(x, name, v) \ 52 REG_SET(x, name, x->win_offset, x->win->scl->name, v) 53 #define VOP_SCL_SET_EXT(x, name, v) \ 54 REG_SET(x, name, x->win_offset, x->win->scl->ext->name, v) 55 56 #define VOP_CTRL_SET(x, name, v) \ 57 REG_SET(x, name, 0, (x)->ctrl->name, v) 58 #define VOP_LINE_FLAG_SET(x, name, v) \ 59 REG_SET(x, name, 0, (x)->line_flag->name, v) 60 61 #define VOP_CTRL_GET(x, name) \ 62 vop_read_reg(x, 0, &vop->ctrl->name) 63 64 #define VOP_WIN_GET(x, name) \ 65 vop_read_reg(x, vop->win->offset, &vop->win->name) 66 67 #define CVBS_PAL_VDISPLAY 288 68 69 enum alpha_mode { 70 ALPHA_STRAIGHT, 71 ALPHA_INVERSE, 72 }; 73 74 enum global_blend_mode { 75 ALPHA_GLOBAL, 76 ALPHA_PER_PIX, 77 ALPHA_PER_PIX_GLOBAL, 78 }; 79 80 enum alpha_cal_mode { 81 ALPHA_SATURATION, 82 ALPHA_NO_SATURATION, 83 }; 84 85 enum color_mode { 86 ALPHA_SRC_PRE_MUL, 87 ALPHA_SRC_NO_PRE_MUL, 88 }; 89 90 enum factor_mode { 91 ALPHA_ZERO, 92 ALPHA_ONE, 93 ALPHA_SRC, 94 ALPHA_SRC_INVERSE, 95 ALPHA_SRC_GLOBAL, 96 }; 97 98 enum scale_mode { 99 SCALE_NONE = 0x0, 100 SCALE_UP = 0x1, 101 SCALE_DOWN = 0x2 102 }; 103 104 enum lb_mode { 105 LB_YUV_3840X5 = 0x0, 106 LB_YUV_2560X8 = 0x1, 107 LB_RGB_3840X2 = 0x2, 108 LB_RGB_2560X4 = 0x3, 109 LB_RGB_1920X5 = 0x4, 110 LB_RGB_1280X8 = 0x5 111 }; 112 113 enum sacle_up_mode { 114 SCALE_UP_BIL = 0x0, 115 SCALE_UP_BIC = 0x1 116 }; 117 118 enum scale_down_mode { 119 SCALE_DOWN_BIL = 0x0, 120 SCALE_DOWN_AVG = 0x1 121 }; 122 123 enum dither_down_mode { 124 RGB888_TO_RGB565 = 0x0, 125 RGB888_TO_RGB666 = 0x1 126 }; 127 128 enum dither_down_mode_sel { 129 DITHER_DOWN_ALLEGRO = 0x0, 130 DITHER_DOWN_FRC = 0x1 131 }; 132 133 enum vop_csc_format { 134 CSC_BT601L, 135 CSC_BT709L, 136 CSC_BT601F, 137 CSC_BT2020, 138 }; 139 140 #define DSP_BG_SWAP 0x1 141 #define DSP_RB_SWAP 0x2 142 #define DSP_RG_SWAP 0x4 143 #define DSP_DELTA_SWAP 0x8 144 145 #define PRE_DITHER_DOWN_EN(x) ((x) << 0) 146 #define DITHER_DOWN_EN(x) ((x) << 1) 147 #define DITHER_DOWN_MODE(x) ((x) << 2) 148 #define DITHER_DOWN_MODE_SEL(x) ((x) << 3) 149 150 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 151 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12 152 #define SCL_MAX_VSKIPLINES 4 153 #define MIN_SCL_FT_AFTER_VSKIP 1 154 155 static inline uint16_t scl_cal_scale(int src, int dst, int shift) 156 { 157 return ((src * 2 - 3) << (shift - 1)) / (dst - 1); 158 } 159 160 static inline uint16_t scl_cal_scale2(int src, int dst) 161 { 162 return ((src - 1) << 12) / (dst - 1); 163 } 164 165 #define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12) 166 #define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16) 167 #define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16) 168 169 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h, 170 int vskiplines) 171 { 172 int act_height; 173 174 act_height = (src_h + vskiplines - 1) / vskiplines; 175 176 return GET_SCL_FT_BILI_DN(act_height, dst_h); 177 } 178 179 static inline enum scale_mode scl_get_scl_mode(int src, int dst) 180 { 181 if (src < dst) 182 return SCALE_UP; 183 else if (src > dst) 184 return SCALE_DOWN; 185 186 return SCALE_NONE; 187 } 188 189 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth) 190 { 191 uint32_t vskiplines; 192 193 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2) 194 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP) 195 break; 196 197 return vskiplines; 198 } 199 200 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv) 201 { 202 int lb_mode; 203 204 if (width > 2560) 205 lb_mode = LB_RGB_3840X2; 206 else if (width > 1920) 207 lb_mode = LB_RGB_2560X4; 208 else if (!is_yuv) 209 lb_mode = LB_RGB_1920X5; 210 else if (width > 1280) 211 lb_mode = LB_YUV_3840X5; 212 else 213 lb_mode = LB_YUV_2560X8; 214 215 return lb_mode; 216 } 217 218 struct vop_reg_data { 219 uint32_t offset; 220 uint32_t value; 221 }; 222 223 struct vop_reg { 224 uint32_t mask; 225 uint32_t offset:12; 226 uint32_t shift:5; 227 uint32_t begin_minor:4; 228 uint32_t end_minor:4; 229 uint32_t major:3; 230 uint32_t write_mask:1; 231 }; 232 233 struct vop_ctrl { 234 struct vop_reg standby; 235 struct vop_reg axi_outstanding_max_num; 236 struct vop_reg axi_max_outstanding_en; 237 struct vop_reg htotal_pw; 238 struct vop_reg hact_st_end; 239 struct vop_reg vtotal_pw; 240 struct vop_reg vact_st_end; 241 struct vop_reg vact_st_end_f1; 242 struct vop_reg vs_st_end_f1; 243 struct vop_reg hpost_st_end; 244 struct vop_reg vpost_st_end; 245 struct vop_reg vpost_st_end_f1; 246 struct vop_reg post_scl_factor; 247 struct vop_reg post_scl_ctrl; 248 struct vop_reg dsp_interlace; 249 struct vop_reg global_regdone_en; 250 struct vop_reg auto_gate_en; 251 struct vop_reg post_lb_mode; 252 struct vop_reg dsp_layer_sel; 253 struct vop_reg overlay_mode; 254 struct vop_reg core_dclk_div; 255 struct vop_reg dclk_ddr; 256 struct vop_reg p2i_en; 257 struct vop_reg hdmi_dclk_out_en; 258 struct vop_reg rgb_en; 259 struct vop_reg lvds_en; 260 struct vop_reg edp_en; 261 struct vop_reg hdmi_en; 262 struct vop_reg mipi_en; 263 struct vop_reg data01_swap; 264 struct vop_reg mipi_dual_channel_en; 265 struct vop_reg dp_en; 266 struct vop_reg dclk_pol; 267 struct vop_reg pin_pol; 268 struct vop_reg rgb_dclk_pol; 269 struct vop_reg rgb_pin_pol; 270 struct vop_reg lvds_dclk_pol; 271 struct vop_reg lvds_pin_pol; 272 struct vop_reg hdmi_dclk_pol; 273 struct vop_reg hdmi_pin_pol; 274 struct vop_reg edp_dclk_pol; 275 struct vop_reg edp_pin_pol; 276 struct vop_reg mipi_dclk_pol; 277 struct vop_reg mipi_pin_pol; 278 struct vop_reg dp_dclk_pol; 279 struct vop_reg dp_pin_pol; 280 281 struct vop_reg dither_up; 282 struct vop_reg dither_down; 283 284 struct vop_reg sw_dac_sel; 285 struct vop_reg tve_sw_mode; 286 struct vop_reg tve_dclk_pol; 287 struct vop_reg tve_dclk_en; 288 struct vop_reg sw_genlock; 289 struct vop_reg sw_uv_offset_en; 290 291 struct vop_reg dsp_out_yuv; 292 struct vop_reg dsp_data_swap; 293 struct vop_reg dsp_ccir656_avg; 294 struct vop_reg dsp_black; 295 struct vop_reg dsp_blank; 296 struct vop_reg dsp_outzero; 297 struct vop_reg dsp_lut_en; 298 struct vop_reg update_gamma_lut; 299 300 struct vop_reg out_mode; 301 302 struct vop_reg xmirror; 303 struct vop_reg ymirror; 304 struct vop_reg dsp_background; 305 306 /* CABC */ 307 struct vop_reg cabc_total_num; 308 struct vop_reg cabc_config_mode; 309 struct vop_reg cabc_stage_up_mode; 310 struct vop_reg cabc_scale_cfg_value; 311 struct vop_reg cabc_scale_cfg_enable; 312 struct vop_reg cabc_global_dn_limit_en; 313 struct vop_reg cabc_lut_en; 314 struct vop_reg cabc_en; 315 struct vop_reg cabc_handle_en; 316 struct vop_reg cabc_stage_up; 317 struct vop_reg cabc_stage_down; 318 struct vop_reg cabc_global_dn; 319 struct vop_reg cabc_calc_pixel_num; 320 321 struct vop_reg win_gate[4]; 322 struct vop_reg win_channel[4]; 323 324 /* BCSH */ 325 struct vop_reg bcsh_brightness; 326 struct vop_reg bcsh_contrast; 327 struct vop_reg bcsh_sat_con; 328 struct vop_reg bcsh_sin_hue; 329 struct vop_reg bcsh_cos_hue; 330 struct vop_reg bcsh_r2y_csc_mode; 331 struct vop_reg bcsh_r2y_en; 332 struct vop_reg bcsh_y2r_csc_mode; 333 struct vop_reg bcsh_y2r_en; 334 struct vop_reg bcsh_color_bar; 335 struct vop_reg bcsh_out_mode; 336 struct vop_reg bcsh_en; 337 struct vop_reg reg_done_frm; 338 339 /* MCU OUTPUT */ 340 struct vop_reg mcu_pix_total; 341 struct vop_reg mcu_cs_pst; 342 struct vop_reg mcu_cs_pend; 343 struct vop_reg mcu_rw_pst; 344 struct vop_reg mcu_rw_pend; 345 struct vop_reg mcu_clk_sel; 346 struct vop_reg mcu_hold_mode; 347 struct vop_reg mcu_frame_st; 348 struct vop_reg mcu_rs; 349 struct vop_reg mcu_bypass; 350 struct vop_reg mcu_type; 351 struct vop_reg mcu_rw_bypass_port; 352 353 354 struct vop_reg cfg_done; 355 }; 356 357 struct vop_scl_extension { 358 struct vop_reg cbcr_vsd_mode; 359 struct vop_reg cbcr_vsu_mode; 360 struct vop_reg cbcr_hsd_mode; 361 struct vop_reg cbcr_ver_scl_mode; 362 struct vop_reg cbcr_hor_scl_mode; 363 struct vop_reg yrgb_vsd_mode; 364 struct vop_reg yrgb_vsu_mode; 365 struct vop_reg yrgb_hsd_mode; 366 struct vop_reg yrgb_ver_scl_mode; 367 struct vop_reg yrgb_hor_scl_mode; 368 struct vop_reg line_load_mode; 369 struct vop_reg cbcr_axi_gather_num; 370 struct vop_reg yrgb_axi_gather_num; 371 struct vop_reg vsd_cbcr_gt2; 372 struct vop_reg vsd_cbcr_gt4; 373 struct vop_reg vsd_yrgb_gt2; 374 struct vop_reg vsd_yrgb_gt4; 375 struct vop_reg bic_coe_sel; 376 struct vop_reg cbcr_axi_gather_en; 377 struct vop_reg yrgb_axi_gather_en; 378 struct vop_reg lb_mode; 379 }; 380 381 struct vop_scl_regs { 382 const struct vop_scl_extension *ext; 383 384 struct vop_reg scale_yrgb_x; 385 struct vop_reg scale_yrgb_y; 386 struct vop_reg scale_cbcr_x; 387 struct vop_reg scale_cbcr_y; 388 }; 389 390 struct vop_win { 391 const struct vop_scl_regs *scl; 392 393 struct vop_reg enable; 394 struct vop_reg format; 395 struct vop_reg ymirror; 396 struct vop_reg rb_swap; 397 struct vop_reg act_info; 398 struct vop_reg dsp_info; 399 struct vop_reg dsp_st; 400 struct vop_reg yrgb_mst; 401 struct vop_reg uv_mst; 402 struct vop_reg yrgb_vir; 403 struct vop_reg uv_vir; 404 struct vop_reg alpha_mode; 405 struct vop_reg alpha_en; 406 407 struct vop_reg dst_alpha_ctl; 408 struct vop_reg src_alpha_ctl; 409 }; 410 411 struct vop_line_flag { 412 struct vop_reg line_flag_num[2]; 413 }; 414 415 struct vop_rect { 416 int width; 417 int height; 418 }; 419 420 #define VOP_FEATURE_OUTPUT_10BIT BIT(0) 421 422 struct vop_data { 423 uint32_t version; 424 const struct vop_ctrl *ctrl; 425 const struct vop_win *win; 426 const struct vop_line_flag *line_flag; 427 int win_offset; 428 int reg_len; 429 u64 feature; 430 struct vop_rect max_output; 431 }; 432 433 struct vop { 434 u32 *regsbak; 435 void *regs; 436 437 uint32_t version; 438 const struct vop_ctrl *ctrl; 439 const struct vop_win *win; 440 const struct vop_line_flag *line_flag; 441 int win_offset; 442 struct vop_rect max_output; 443 }; 444 445 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 446 { 447 writel(v, vop->regs + offset); 448 vop->regsbak[offset >> 2] = v; 449 } 450 451 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 452 { 453 return readl(vop->regs + offset); 454 } 455 456 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 457 const struct vop_reg *reg) 458 { 459 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 460 } 461 462 static inline void vop_mask_write(struct vop *vop, uint32_t offset, 463 uint32_t mask, uint32_t shift, uint32_t v, 464 bool write_mask) 465 { 466 if (!mask) 467 return; 468 469 if (write_mask) { 470 v = ((v & mask) << shift) | (mask << (shift + 16)); 471 } else { 472 uint32_t cached_val = vop->regsbak[offset >> 2]; 473 474 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 475 vop->regsbak[offset >> 2] = v; 476 } 477 478 writel(v, vop->regs + offset); 479 } 480 481 static inline void vop_cfg_done(struct vop *vop) 482 { 483 VOP_CTRL_SET(vop, cfg_done, 1); 484 } 485 486 /** 487 * drm_format_horz_chroma_subsampling - get the horizontal chroma subsampling factor 488 * @format: pixel format (DRM_FORMAT_*) 489 * 490 * Returns: 491 * The horizontal chroma subsampling factor for the 492 * specified pixel format. 493 */ 494 static inline int drm_format_horz_chroma_subsampling(uint32_t format) 495 { 496 /* uboot only support RGB format */ 497 return 1; 498 } 499 500 /** 501 * drm_format_vert_chroma_subsampling - get the vertical chroma subsampling factor 502 * @format: pixel format (DRM_FORMAT_*) 503 * 504 * Returns: 505 * The vertical chroma subsampling factor for the 506 * specified pixel format. 507 */ 508 static inline int drm_format_vert_chroma_subsampling(uint32_t format) 509 { 510 /* uboot only support RGB format */ 511 return 1; 512 } 513 514 #endif 515