1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ROCKCHIP_VOP_H_ 8 #define _ROCKCHIP_VOP_H_ 9 #include "rockchip_display.h" 10 11 /* 12 * major: IP major vertion, used for IP structure 13 * minor: big feature change under same structure 14 */ 15 #define VOP_VERSION(major, minor) ((major) << 8 | (minor)) 16 #define VOP_MAJOR(version) ((version) >> 8) 17 #define VOP_MINOR(version) ((version) & 0xff) 18 19 #define VOP_REG_SUPPORT(vop, reg) \ 20 (reg.mask && \ 21 (!reg.major || \ 22 (reg.major == VOP_MAJOR(vop->version) && \ 23 reg.begin_minor <= VOP_MINOR(vop->version) && \ 24 reg.end_minor >= VOP_MINOR(vop->version)))) 25 26 #define VOP_WIN_SUPPORT(vop, win, name) \ 27 VOP_REG_SUPPORT(vop, win->name) 28 29 #define VOP_CTRL_SUPPORT(vop, name) \ 30 VOP_REG_SUPPORT(vop, vop->ctrl->name) 31 32 #define __REG_SET(x, off, mask, shift, v, write_mask) \ 33 vop_mask_write(x, off, mask, shift, v, write_mask) 34 35 #define _REG_SET(vop, name, off, reg, mask, v) \ 36 do { \ 37 if (VOP_REG_SUPPORT(vop, reg)) \ 38 __REG_SET(vop, off + reg.offset, mask, reg.shift, \ 39 v, reg.write_mask); \ 40 else \ 41 debug("Warning: not support "#name"\n"); \ 42 } while(0) 43 44 #define REG_SET(x, name, off, reg, v) \ 45 _REG_SET(x, name, off, reg, reg.mask, v) 46 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \ 47 _REG_SET(x, name, off, reg, reg.mask & mask, v) 48 49 #define VOP_WIN_SET(x, name, v) \ 50 REG_SET(x, name, x->win_offset, x->win->name, v) 51 #define VOP_WIN_SET_EXT(x, ext, name, v) \ 52 REG_SET(x, name, x->win_offset, x->win->ext->name, v) 53 #define VOP_SCL_SET(x, name, v) \ 54 REG_SET(x, name, x->win_offset, x->win->scl->name, v) 55 #define VOP_SCL_SET_EXT(x, name, v) \ 56 REG_SET(x, name, x->win_offset, x->win->scl->ext->name, v) 57 58 #define VOP_CTRL_SET(x, name, v) \ 59 REG_SET(x, name, 0, (x)->ctrl->name, v) 60 #define VOP_LINE_FLAG_SET(x, name, v) \ 61 REG_SET(x, name, 0, (x)->line_flag->name, v) 62 #define VOP_WIN_CSC_SET(x, name, v) \ 63 REG_SET(x, name, 0, (x)->win_csc->name, v) 64 65 #define VOP_CTRL_GET(x, name) \ 66 vop_read_reg(x, 0, &vop->ctrl->name) 67 68 #define VOP_WIN_GET(x, name) \ 69 vop_read_reg(x, vop->win->offset, &vop->win->name) 70 71 #define VOP_GRF_SET(vop, name, v) \ 72 do { \ 73 if (vop->grf_ctrl) { \ 74 vop_grf_writel(vop, vop->grf_ctrl->name, v); \ 75 } \ 76 } while (0) 77 78 #define CVBS_PAL_VDISPLAY 288 79 80 enum alpha_mode { 81 ALPHA_STRAIGHT, 82 ALPHA_INVERSE, 83 }; 84 85 enum global_blend_mode { 86 ALPHA_GLOBAL, 87 ALPHA_PER_PIX, 88 ALPHA_PER_PIX_GLOBAL, 89 }; 90 91 enum alpha_cal_mode { 92 ALPHA_SATURATION, 93 ALPHA_NO_SATURATION, 94 }; 95 96 enum color_mode { 97 ALPHA_SRC_PRE_MUL, 98 ALPHA_SRC_NO_PRE_MUL, 99 }; 100 101 enum factor_mode { 102 ALPHA_ZERO, 103 ALPHA_ONE, 104 ALPHA_SRC, 105 ALPHA_SRC_INVERSE, 106 ALPHA_SRC_GLOBAL, 107 }; 108 109 enum scale_mode { 110 SCALE_NONE = 0x0, 111 SCALE_UP = 0x1, 112 SCALE_DOWN = 0x2 113 }; 114 115 enum lb_mode { 116 LB_YUV_3840X5 = 0x0, 117 LB_YUV_2560X8 = 0x1, 118 LB_RGB_3840X2 = 0x2, 119 LB_RGB_2560X4 = 0x3, 120 LB_RGB_1920X5 = 0x4, 121 LB_RGB_1280X8 = 0x5 122 }; 123 124 enum sacle_up_mode { 125 SCALE_UP_BIL = 0x0, 126 SCALE_UP_BIC = 0x1 127 }; 128 129 enum scale_down_mode { 130 SCALE_DOWN_BIL = 0x0, 131 SCALE_DOWN_AVG = 0x1 132 }; 133 134 enum dither_down_mode { 135 RGB888_TO_RGB565 = 0x0, 136 RGB888_TO_RGB666 = 0x1 137 }; 138 139 enum dither_down_mode_sel { 140 DITHER_DOWN_ALLEGRO = 0x0, 141 DITHER_DOWN_FRC = 0x1 142 }; 143 144 enum vop_csc_format { 145 CSC_BT601L, 146 CSC_BT709L, 147 CSC_BT601F, 148 CSC_BT2020, 149 }; 150 151 #define DSP_BG_SWAP 0x1 152 #define DSP_RB_SWAP 0x2 153 #define DSP_RG_SWAP 0x4 154 #define DSP_DELTA_SWAP 0x8 155 156 #define PRE_DITHER_DOWN_EN(x) ((x) << 0) 157 #define DITHER_DOWN_EN(x) ((x) << 1) 158 #define DITHER_DOWN_MODE(x) ((x) << 2) 159 #define DITHER_DOWN_MODE_SEL(x) ((x) << 3) 160 161 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 162 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12 163 #define SCL_MAX_VSKIPLINES 4 164 #define MIN_SCL_FT_AFTER_VSKIP 1 165 166 static inline uint16_t scl_cal_scale(int src, int dst, int shift) 167 { 168 return ((src * 2 - 3) << (shift - 1)) / (dst - 1); 169 } 170 171 static inline uint16_t scl_cal_scale2(int src, int dst) 172 { 173 return ((src - 1) << 12) / (dst - 1); 174 } 175 176 #define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12) 177 #define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16) 178 #define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16) 179 180 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h, 181 int vskiplines) 182 { 183 int act_height; 184 185 act_height = (src_h + vskiplines - 1) / vskiplines; 186 187 return GET_SCL_FT_BILI_DN(act_height, dst_h); 188 } 189 190 static inline enum scale_mode scl_get_scl_mode(int src, int dst) 191 { 192 if (src < dst) 193 return SCALE_UP; 194 else if (src > dst) 195 return SCALE_DOWN; 196 197 return SCALE_NONE; 198 } 199 200 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth) 201 { 202 uint32_t vskiplines; 203 204 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2) 205 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP) 206 break; 207 208 return vskiplines; 209 } 210 211 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv) 212 { 213 int lb_mode; 214 215 if (width > 2560) 216 lb_mode = LB_RGB_3840X2; 217 else if (width > 1920) 218 lb_mode = LB_RGB_2560X4; 219 else if (!is_yuv) 220 lb_mode = LB_RGB_1920X5; 221 else if (width > 1280) 222 lb_mode = LB_YUV_3840X5; 223 else 224 lb_mode = LB_YUV_2560X8; 225 226 return lb_mode; 227 } 228 229 struct vop_reg_data { 230 uint32_t offset; 231 uint32_t value; 232 }; 233 234 struct vop_reg { 235 uint32_t mask; 236 uint32_t offset:12; 237 uint32_t shift:5; 238 uint32_t begin_minor:4; 239 uint32_t end_minor:4; 240 uint32_t major:3; 241 uint32_t write_mask:1; 242 }; 243 244 struct vop_ctrl { 245 struct vop_reg standby; 246 struct vop_reg axi_outstanding_max_num; 247 struct vop_reg axi_max_outstanding_en; 248 struct vop_reg htotal_pw; 249 struct vop_reg hact_st_end; 250 struct vop_reg vtotal_pw; 251 struct vop_reg vact_st_end; 252 struct vop_reg vact_st_end_f1; 253 struct vop_reg vs_st_end_f1; 254 struct vop_reg hpost_st_end; 255 struct vop_reg vpost_st_end; 256 struct vop_reg vpost_st_end_f1; 257 struct vop_reg post_scl_factor; 258 struct vop_reg post_scl_ctrl; 259 struct vop_reg dsp_interlace; 260 struct vop_reg global_regdone_en; 261 struct vop_reg auto_gate_en; 262 struct vop_reg post_lb_mode; 263 struct vop_reg dsp_layer_sel; 264 struct vop_reg overlay_mode; 265 struct vop_reg core_dclk_div; 266 struct vop_reg dclk_ddr; 267 struct vop_reg p2i_en; 268 struct vop_reg hdmi_dclk_out_en; 269 struct vop_reg rgb_en; 270 struct vop_reg lvds_en; 271 struct vop_reg edp_en; 272 struct vop_reg hdmi_en; 273 struct vop_reg mipi_en; 274 struct vop_reg data01_swap; 275 struct vop_reg mipi_dual_channel_en; 276 struct vop_reg dp_en; 277 struct vop_reg dclk_pol; 278 struct vop_reg pin_pol; 279 struct vop_reg rgb_dclk_pol; 280 struct vop_reg rgb_pin_pol; 281 struct vop_reg lvds_dclk_pol; 282 struct vop_reg lvds_pin_pol; 283 struct vop_reg hdmi_dclk_pol; 284 struct vop_reg hdmi_pin_pol; 285 struct vop_reg edp_dclk_pol; 286 struct vop_reg edp_pin_pol; 287 struct vop_reg mipi_dclk_pol; 288 struct vop_reg mipi_pin_pol; 289 struct vop_reg dp_dclk_pol; 290 struct vop_reg dp_pin_pol; 291 292 struct vop_reg dither_up; 293 struct vop_reg dither_down; 294 295 struct vop_reg sw_dac_sel; 296 struct vop_reg tve_sw_mode; 297 struct vop_reg tve_dclk_pol; 298 struct vop_reg tve_dclk_en; 299 struct vop_reg sw_genlock; 300 struct vop_reg sw_uv_offset_en; 301 302 struct vop_reg dsp_out_yuv; 303 struct vop_reg dsp_data_swap; 304 struct vop_reg dsp_ccir656_avg; 305 struct vop_reg dsp_black; 306 struct vop_reg dsp_blank; 307 struct vop_reg dsp_outzero; 308 struct vop_reg dsp_lut_en; 309 struct vop_reg update_gamma_lut; 310 311 struct vop_reg out_mode; 312 313 struct vop_reg xmirror; 314 struct vop_reg ymirror; 315 struct vop_reg dsp_background; 316 317 /* CABC */ 318 struct vop_reg cabc_total_num; 319 struct vop_reg cabc_config_mode; 320 struct vop_reg cabc_stage_up_mode; 321 struct vop_reg cabc_scale_cfg_value; 322 struct vop_reg cabc_scale_cfg_enable; 323 struct vop_reg cabc_global_dn_limit_en; 324 struct vop_reg cabc_lut_en; 325 struct vop_reg cabc_en; 326 struct vop_reg cabc_handle_en; 327 struct vop_reg cabc_stage_up; 328 struct vop_reg cabc_stage_down; 329 struct vop_reg cabc_global_dn; 330 struct vop_reg cabc_calc_pixel_num; 331 332 struct vop_reg win_gate[4]; 333 struct vop_reg win_channel[4]; 334 335 /* BCSH */ 336 struct vop_reg bcsh_brightness; 337 struct vop_reg bcsh_contrast; 338 struct vop_reg bcsh_sat_con; 339 struct vop_reg bcsh_sin_hue; 340 struct vop_reg bcsh_cos_hue; 341 struct vop_reg bcsh_r2y_csc_mode; 342 struct vop_reg bcsh_r2y_en; 343 struct vop_reg bcsh_y2r_csc_mode; 344 struct vop_reg bcsh_y2r_en; 345 struct vop_reg bcsh_color_bar; 346 struct vop_reg bcsh_out_mode; 347 struct vop_reg bcsh_en; 348 struct vop_reg reg_done_frm; 349 350 /* MCU OUTPUT */ 351 struct vop_reg mcu_pix_total; 352 struct vop_reg mcu_cs_pst; 353 struct vop_reg mcu_cs_pend; 354 struct vop_reg mcu_rw_pst; 355 struct vop_reg mcu_rw_pend; 356 struct vop_reg mcu_clk_sel; 357 struct vop_reg mcu_hold_mode; 358 struct vop_reg mcu_frame_st; 359 struct vop_reg mcu_rs; 360 struct vop_reg mcu_bypass; 361 struct vop_reg mcu_type; 362 struct vop_reg mcu_rw_bypass_port; 363 364 365 struct vop_reg cfg_done; 366 }; 367 368 struct vop_scl_extension { 369 struct vop_reg cbcr_vsd_mode; 370 struct vop_reg cbcr_vsu_mode; 371 struct vop_reg cbcr_hsd_mode; 372 struct vop_reg cbcr_ver_scl_mode; 373 struct vop_reg cbcr_hor_scl_mode; 374 struct vop_reg yrgb_vsd_mode; 375 struct vop_reg yrgb_vsu_mode; 376 struct vop_reg yrgb_hsd_mode; 377 struct vop_reg yrgb_ver_scl_mode; 378 struct vop_reg yrgb_hor_scl_mode; 379 struct vop_reg line_load_mode; 380 struct vop_reg cbcr_axi_gather_num; 381 struct vop_reg yrgb_axi_gather_num; 382 struct vop_reg vsd_cbcr_gt2; 383 struct vop_reg vsd_cbcr_gt4; 384 struct vop_reg vsd_yrgb_gt2; 385 struct vop_reg vsd_yrgb_gt4; 386 struct vop_reg bic_coe_sel; 387 struct vop_reg cbcr_axi_gather_en; 388 struct vop_reg yrgb_axi_gather_en; 389 struct vop_reg lb_mode; 390 }; 391 392 struct vop_scl_regs { 393 const struct vop_scl_extension *ext; 394 395 struct vop_reg scale_yrgb_x; 396 struct vop_reg scale_yrgb_y; 397 struct vop_reg scale_cbcr_x; 398 struct vop_reg scale_cbcr_y; 399 }; 400 401 struct vop_win { 402 const struct vop_scl_regs *scl; 403 404 struct vop_reg gate; 405 struct vop_reg enable; 406 struct vop_reg format; 407 struct vop_reg ymirror; 408 struct vop_reg rb_swap; 409 struct vop_reg act_info; 410 struct vop_reg dsp_info; 411 struct vop_reg dsp_st; 412 struct vop_reg yrgb_mst; 413 struct vop_reg uv_mst; 414 struct vop_reg yrgb_vir; 415 struct vop_reg uv_vir; 416 struct vop_reg alpha_mode; 417 struct vop_reg alpha_en; 418 419 struct vop_reg dst_alpha_ctl; 420 struct vop_reg src_alpha_ctl; 421 }; 422 423 struct vop_line_flag { 424 struct vop_reg line_flag_num[2]; 425 }; 426 427 struct vop_grf_ctrl { 428 struct vop_reg grf_dclk_inv; 429 }; 430 431 struct vop_csc_table { 432 const uint32_t *r2y_bt601; 433 const uint32_t *r2y_bt601_12_235; 434 const uint32_t *r2y_bt709; 435 const uint32_t *r2y_bt2020; 436 }; 437 438 struct vop_csc { 439 struct vop_reg y2r_en; 440 struct vop_reg r2r_en; 441 struct vop_reg r2y_en; 442 443 uint32_t y2r_offset; 444 uint32_t r2r_offset; 445 uint32_t r2y_offset; 446 }; 447 448 #define VOP_FEATURE_OUTPUT_10BIT BIT(0) 449 450 struct vop_data { 451 uint32_t version; 452 const struct vop_ctrl *ctrl; 453 const struct vop_win *win; 454 const struct vop_line_flag *line_flag; 455 const struct vop_grf_ctrl *grf_ctrl; 456 const struct vop_csc_table *csc_table; 457 const struct vop_csc *win_csc; 458 int win_offset; 459 int reg_len; 460 u64 feature; 461 struct vop_rect max_output; 462 }; 463 464 struct vop { 465 u32 *regsbak; 466 void *regs; 467 void *grf; 468 469 uint32_t version; 470 const struct vop_ctrl *ctrl; 471 const struct vop_win *win; 472 const struct vop_line_flag *line_flag; 473 const struct vop_grf_ctrl *grf_ctrl; 474 const struct vop_csc_table *csc_table; 475 const struct vop_csc *win_csc; 476 int win_offset; 477 }; 478 479 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 480 { 481 writel(v, vop->regs + offset); 482 vop->regsbak[offset >> 2] = v; 483 } 484 485 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 486 { 487 return readl(vop->regs + offset); 488 } 489 490 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 491 const struct vop_reg *reg) 492 { 493 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 494 } 495 496 static inline void vop_mask_write(struct vop *vop, uint32_t offset, 497 uint32_t mask, uint32_t shift, uint32_t v, 498 bool write_mask) 499 { 500 if (!mask) 501 return; 502 503 if (write_mask) { 504 v = ((v & mask) << shift) | (mask << (shift + 16)); 505 } else { 506 uint32_t cached_val = vop->regsbak[offset >> 2]; 507 508 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 509 vop->regsbak[offset >> 2] = v; 510 } 511 512 writel(v, vop->regs + offset); 513 } 514 515 static inline void vop_cfg_done(struct vop *vop) 516 { 517 VOP_CTRL_SET(vop, cfg_done, 1); 518 } 519 520 static inline void vop_grf_writel(struct vop *vop, struct vop_reg reg, u32 v) 521 { 522 u32 val = 0; 523 524 if (VOP_REG_SUPPORT(vop, reg)) { 525 val = (v << reg.shift) | (reg.mask << (reg.shift + 16)); 526 writel(val, vop->grf + reg.offset); 527 } 528 } 529 530 /** 531 * drm_format_horz_chroma_subsampling - get the horizontal chroma subsampling factor 532 * @format: pixel format (DRM_FORMAT_*) 533 * 534 * Returns: 535 * The horizontal chroma subsampling factor for the 536 * specified pixel format. 537 */ 538 static inline int drm_format_horz_chroma_subsampling(uint32_t format) 539 { 540 /* uboot only support RGB format */ 541 return 1; 542 } 543 544 /** 545 * drm_format_vert_chroma_subsampling - get the vertical chroma subsampling factor 546 * @format: pixel format (DRM_FORMAT_*) 547 * 548 * Returns: 549 * The vertical chroma subsampling factor for the 550 * specified pixel format. 551 */ 552 static inline int drm_format_vert_chroma_subsampling(uint32_t format) 553 { 554 /* uboot only support RGB format */ 555 return 1; 556 } 557 558 #endif 559