1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ROCKCHIP_VOP_H_ 8 #define _ROCKCHIP_VOP_H_ 9 10 /* 11 * major: IP major vertion, used for IP structure 12 * minor: big feature change under same structure 13 */ 14 #define VOP_VERSION(major, minor) ((major) << 8 | (minor)) 15 #define VOP_MAJOR(version) ((version) >> 8) 16 #define VOP_MINOR(version) ((version) & 0xff) 17 18 #define VOP_REG_SUPPORT(vop, reg) \ 19 (!reg.major || (reg.major == VOP_MAJOR(vop->version) && \ 20 reg.begin_minor <= VOP_MINOR(vop->version) && \ 21 reg.end_minor >= VOP_MINOR(vop->version) && \ 22 reg.mask)) 23 24 #define VOP_WIN_SUPPORT(vop, win, name) \ 25 VOP_REG_SUPPORT(vop, win->name) 26 27 #define VOP_CTRL_SUPPORT(vop, name) \ 28 VOP_REG_SUPPORT(vop, vop->ctrl->name) 29 30 #define __REG_SET(x, off, mask, shift, v, write_mask) \ 31 vop_mask_write(x, off, mask, shift, v, write_mask) 32 33 #define _REG_SET(vop, name, off, reg, mask, v) \ 34 do { \ 35 if (VOP_REG_SUPPORT(vop, reg)) \ 36 __REG_SET(vop, off + reg.offset, mask, reg.shift, \ 37 v, reg.write_mask); \ 38 else \ 39 debug("Warning: not support "#name"\n"); \ 40 } while(0) 41 42 #define REG_SET(x, name, off, reg, v) \ 43 _REG_SET(x, name, off, reg, reg.mask, v) 44 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \ 45 _REG_SET(x, name, off, reg, reg.mask & mask, v) 46 47 #define VOP_WIN_SET(x, name, v) \ 48 REG_SET(x, name, x->win_offset, x->win->name, v) 49 #define VOP_WIN_SET_EXT(x, ext, name, v) \ 50 REG_SET(x, name, x->win_offset, x->win->ext->name, v) 51 #define VOP_SCL_SET(x, name, v) \ 52 REG_SET(x, name, x->win_offset, x->win->scl->name, v) 53 #define VOP_SCL_SET_EXT(x, name, v) \ 54 REG_SET(x, name, x->win_offset, x->win->scl->ext->name, v) 55 56 #define VOP_CTRL_SET(x, name, v) \ 57 REG_SET(x, name, 0, (x)->ctrl->name, v) 58 #define VOP_LINE_FLAG_SET(x, name, v) \ 59 REG_SET(x, name, 0, (x)->line_flag->name, v) 60 61 #define VOP_CTRL_GET(x, name) \ 62 vop_read_reg(x, 0, &vop->ctrl->name) 63 64 #define VOP_WIN_GET(x, name) \ 65 vop_read_reg(x, vop->win->offset, &vop->win->name) 66 67 #define VOP_GRF_SET(vop, name, v) \ 68 do { \ 69 if (vop->grf_ctrl) { \ 70 vop_grf_writel(vop, vop->grf_ctrl->name, v); \ 71 } \ 72 } while (0) 73 74 #define CVBS_PAL_VDISPLAY 288 75 76 enum alpha_mode { 77 ALPHA_STRAIGHT, 78 ALPHA_INVERSE, 79 }; 80 81 enum global_blend_mode { 82 ALPHA_GLOBAL, 83 ALPHA_PER_PIX, 84 ALPHA_PER_PIX_GLOBAL, 85 }; 86 87 enum alpha_cal_mode { 88 ALPHA_SATURATION, 89 ALPHA_NO_SATURATION, 90 }; 91 92 enum color_mode { 93 ALPHA_SRC_PRE_MUL, 94 ALPHA_SRC_NO_PRE_MUL, 95 }; 96 97 enum factor_mode { 98 ALPHA_ZERO, 99 ALPHA_ONE, 100 ALPHA_SRC, 101 ALPHA_SRC_INVERSE, 102 ALPHA_SRC_GLOBAL, 103 }; 104 105 enum scale_mode { 106 SCALE_NONE = 0x0, 107 SCALE_UP = 0x1, 108 SCALE_DOWN = 0x2 109 }; 110 111 enum lb_mode { 112 LB_YUV_3840X5 = 0x0, 113 LB_YUV_2560X8 = 0x1, 114 LB_RGB_3840X2 = 0x2, 115 LB_RGB_2560X4 = 0x3, 116 LB_RGB_1920X5 = 0x4, 117 LB_RGB_1280X8 = 0x5 118 }; 119 120 enum sacle_up_mode { 121 SCALE_UP_BIL = 0x0, 122 SCALE_UP_BIC = 0x1 123 }; 124 125 enum scale_down_mode { 126 SCALE_DOWN_BIL = 0x0, 127 SCALE_DOWN_AVG = 0x1 128 }; 129 130 enum dither_down_mode { 131 RGB888_TO_RGB565 = 0x0, 132 RGB888_TO_RGB666 = 0x1 133 }; 134 135 enum dither_down_mode_sel { 136 DITHER_DOWN_ALLEGRO = 0x0, 137 DITHER_DOWN_FRC = 0x1 138 }; 139 140 enum vop_csc_format { 141 CSC_BT601L, 142 CSC_BT709L, 143 CSC_BT601F, 144 CSC_BT2020, 145 }; 146 147 #define DSP_BG_SWAP 0x1 148 #define DSP_RB_SWAP 0x2 149 #define DSP_RG_SWAP 0x4 150 #define DSP_DELTA_SWAP 0x8 151 152 #define PRE_DITHER_DOWN_EN(x) ((x) << 0) 153 #define DITHER_DOWN_EN(x) ((x) << 1) 154 #define DITHER_DOWN_MODE(x) ((x) << 2) 155 #define DITHER_DOWN_MODE_SEL(x) ((x) << 3) 156 157 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 158 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12 159 #define SCL_MAX_VSKIPLINES 4 160 #define MIN_SCL_FT_AFTER_VSKIP 1 161 162 static inline uint16_t scl_cal_scale(int src, int dst, int shift) 163 { 164 return ((src * 2 - 3) << (shift - 1)) / (dst - 1); 165 } 166 167 static inline uint16_t scl_cal_scale2(int src, int dst) 168 { 169 return ((src - 1) << 12) / (dst - 1); 170 } 171 172 #define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12) 173 #define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16) 174 #define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16) 175 176 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h, 177 int vskiplines) 178 { 179 int act_height; 180 181 act_height = (src_h + vskiplines - 1) / vskiplines; 182 183 return GET_SCL_FT_BILI_DN(act_height, dst_h); 184 } 185 186 static inline enum scale_mode scl_get_scl_mode(int src, int dst) 187 { 188 if (src < dst) 189 return SCALE_UP; 190 else if (src > dst) 191 return SCALE_DOWN; 192 193 return SCALE_NONE; 194 } 195 196 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth) 197 { 198 uint32_t vskiplines; 199 200 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2) 201 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP) 202 break; 203 204 return vskiplines; 205 } 206 207 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv) 208 { 209 int lb_mode; 210 211 if (width > 2560) 212 lb_mode = LB_RGB_3840X2; 213 else if (width > 1920) 214 lb_mode = LB_RGB_2560X4; 215 else if (!is_yuv) 216 lb_mode = LB_RGB_1920X5; 217 else if (width > 1280) 218 lb_mode = LB_YUV_3840X5; 219 else 220 lb_mode = LB_YUV_2560X8; 221 222 return lb_mode; 223 } 224 225 struct vop_reg_data { 226 uint32_t offset; 227 uint32_t value; 228 }; 229 230 struct vop_reg { 231 uint32_t mask; 232 uint32_t offset:12; 233 uint32_t shift:5; 234 uint32_t begin_minor:4; 235 uint32_t end_minor:4; 236 uint32_t major:3; 237 uint32_t write_mask:1; 238 }; 239 240 struct vop_ctrl { 241 struct vop_reg standby; 242 struct vop_reg axi_outstanding_max_num; 243 struct vop_reg axi_max_outstanding_en; 244 struct vop_reg htotal_pw; 245 struct vop_reg hact_st_end; 246 struct vop_reg vtotal_pw; 247 struct vop_reg vact_st_end; 248 struct vop_reg vact_st_end_f1; 249 struct vop_reg vs_st_end_f1; 250 struct vop_reg hpost_st_end; 251 struct vop_reg vpost_st_end; 252 struct vop_reg vpost_st_end_f1; 253 struct vop_reg post_scl_factor; 254 struct vop_reg post_scl_ctrl; 255 struct vop_reg dsp_interlace; 256 struct vop_reg global_regdone_en; 257 struct vop_reg auto_gate_en; 258 struct vop_reg post_lb_mode; 259 struct vop_reg dsp_layer_sel; 260 struct vop_reg overlay_mode; 261 struct vop_reg core_dclk_div; 262 struct vop_reg dclk_ddr; 263 struct vop_reg p2i_en; 264 struct vop_reg hdmi_dclk_out_en; 265 struct vop_reg rgb_en; 266 struct vop_reg lvds_en; 267 struct vop_reg edp_en; 268 struct vop_reg hdmi_en; 269 struct vop_reg mipi_en; 270 struct vop_reg data01_swap; 271 struct vop_reg mipi_dual_channel_en; 272 struct vop_reg dp_en; 273 struct vop_reg dclk_pol; 274 struct vop_reg pin_pol; 275 struct vop_reg rgb_dclk_pol; 276 struct vop_reg rgb_pin_pol; 277 struct vop_reg lvds_dclk_pol; 278 struct vop_reg lvds_pin_pol; 279 struct vop_reg hdmi_dclk_pol; 280 struct vop_reg hdmi_pin_pol; 281 struct vop_reg edp_dclk_pol; 282 struct vop_reg edp_pin_pol; 283 struct vop_reg mipi_dclk_pol; 284 struct vop_reg mipi_pin_pol; 285 struct vop_reg dp_dclk_pol; 286 struct vop_reg dp_pin_pol; 287 288 struct vop_reg dither_up; 289 struct vop_reg dither_down; 290 291 struct vop_reg sw_dac_sel; 292 struct vop_reg tve_sw_mode; 293 struct vop_reg tve_dclk_pol; 294 struct vop_reg tve_dclk_en; 295 struct vop_reg sw_genlock; 296 struct vop_reg sw_uv_offset_en; 297 298 struct vop_reg dsp_out_yuv; 299 struct vop_reg dsp_data_swap; 300 struct vop_reg dsp_ccir656_avg; 301 struct vop_reg dsp_black; 302 struct vop_reg dsp_blank; 303 struct vop_reg dsp_outzero; 304 struct vop_reg dsp_lut_en; 305 struct vop_reg update_gamma_lut; 306 307 struct vop_reg out_mode; 308 309 struct vop_reg xmirror; 310 struct vop_reg ymirror; 311 struct vop_reg dsp_background; 312 313 /* CABC */ 314 struct vop_reg cabc_total_num; 315 struct vop_reg cabc_config_mode; 316 struct vop_reg cabc_stage_up_mode; 317 struct vop_reg cabc_scale_cfg_value; 318 struct vop_reg cabc_scale_cfg_enable; 319 struct vop_reg cabc_global_dn_limit_en; 320 struct vop_reg cabc_lut_en; 321 struct vop_reg cabc_en; 322 struct vop_reg cabc_handle_en; 323 struct vop_reg cabc_stage_up; 324 struct vop_reg cabc_stage_down; 325 struct vop_reg cabc_global_dn; 326 struct vop_reg cabc_calc_pixel_num; 327 328 struct vop_reg win_gate[4]; 329 struct vop_reg win_channel[4]; 330 331 /* BCSH */ 332 struct vop_reg bcsh_brightness; 333 struct vop_reg bcsh_contrast; 334 struct vop_reg bcsh_sat_con; 335 struct vop_reg bcsh_sin_hue; 336 struct vop_reg bcsh_cos_hue; 337 struct vop_reg bcsh_r2y_csc_mode; 338 struct vop_reg bcsh_r2y_en; 339 struct vop_reg bcsh_y2r_csc_mode; 340 struct vop_reg bcsh_y2r_en; 341 struct vop_reg bcsh_color_bar; 342 struct vop_reg bcsh_out_mode; 343 struct vop_reg bcsh_en; 344 struct vop_reg reg_done_frm; 345 346 /* MCU OUTPUT */ 347 struct vop_reg mcu_pix_total; 348 struct vop_reg mcu_cs_pst; 349 struct vop_reg mcu_cs_pend; 350 struct vop_reg mcu_rw_pst; 351 struct vop_reg mcu_rw_pend; 352 struct vop_reg mcu_clk_sel; 353 struct vop_reg mcu_hold_mode; 354 struct vop_reg mcu_frame_st; 355 struct vop_reg mcu_rs; 356 struct vop_reg mcu_bypass; 357 struct vop_reg mcu_type; 358 struct vop_reg mcu_rw_bypass_port; 359 360 361 struct vop_reg cfg_done; 362 }; 363 364 struct vop_scl_extension { 365 struct vop_reg cbcr_vsd_mode; 366 struct vop_reg cbcr_vsu_mode; 367 struct vop_reg cbcr_hsd_mode; 368 struct vop_reg cbcr_ver_scl_mode; 369 struct vop_reg cbcr_hor_scl_mode; 370 struct vop_reg yrgb_vsd_mode; 371 struct vop_reg yrgb_vsu_mode; 372 struct vop_reg yrgb_hsd_mode; 373 struct vop_reg yrgb_ver_scl_mode; 374 struct vop_reg yrgb_hor_scl_mode; 375 struct vop_reg line_load_mode; 376 struct vop_reg cbcr_axi_gather_num; 377 struct vop_reg yrgb_axi_gather_num; 378 struct vop_reg vsd_cbcr_gt2; 379 struct vop_reg vsd_cbcr_gt4; 380 struct vop_reg vsd_yrgb_gt2; 381 struct vop_reg vsd_yrgb_gt4; 382 struct vop_reg bic_coe_sel; 383 struct vop_reg cbcr_axi_gather_en; 384 struct vop_reg yrgb_axi_gather_en; 385 struct vop_reg lb_mode; 386 }; 387 388 struct vop_scl_regs { 389 const struct vop_scl_extension *ext; 390 391 struct vop_reg scale_yrgb_x; 392 struct vop_reg scale_yrgb_y; 393 struct vop_reg scale_cbcr_x; 394 struct vop_reg scale_cbcr_y; 395 }; 396 397 struct vop_win { 398 const struct vop_scl_regs *scl; 399 400 struct vop_reg enable; 401 struct vop_reg format; 402 struct vop_reg ymirror; 403 struct vop_reg rb_swap; 404 struct vop_reg act_info; 405 struct vop_reg dsp_info; 406 struct vop_reg dsp_st; 407 struct vop_reg yrgb_mst; 408 struct vop_reg uv_mst; 409 struct vop_reg yrgb_vir; 410 struct vop_reg uv_vir; 411 struct vop_reg alpha_mode; 412 struct vop_reg alpha_en; 413 414 struct vop_reg dst_alpha_ctl; 415 struct vop_reg src_alpha_ctl; 416 }; 417 418 struct vop_line_flag { 419 struct vop_reg line_flag_num[2]; 420 }; 421 422 struct vop_grf_ctrl { 423 struct vop_reg grf_dclk_inv; 424 }; 425 426 struct vop_rect { 427 int width; 428 int height; 429 }; 430 431 #define VOP_FEATURE_OUTPUT_10BIT BIT(0) 432 433 struct vop_data { 434 uint32_t version; 435 const struct vop_ctrl *ctrl; 436 const struct vop_win *win; 437 const struct vop_line_flag *line_flag; 438 const struct vop_grf_ctrl *grf_ctrl; 439 int win_offset; 440 int reg_len; 441 u64 feature; 442 struct vop_rect max_output; 443 }; 444 445 struct vop { 446 u32 *regsbak; 447 void *regs; 448 void *grf; 449 450 uint32_t version; 451 const struct vop_ctrl *ctrl; 452 const struct vop_win *win; 453 const struct vop_line_flag *line_flag; 454 const struct vop_grf_ctrl *grf_ctrl; 455 int win_offset; 456 struct vop_rect max_output; 457 }; 458 459 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 460 { 461 writel(v, vop->regs + offset); 462 vop->regsbak[offset >> 2] = v; 463 } 464 465 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 466 { 467 return readl(vop->regs + offset); 468 } 469 470 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 471 const struct vop_reg *reg) 472 { 473 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 474 } 475 476 static inline void vop_mask_write(struct vop *vop, uint32_t offset, 477 uint32_t mask, uint32_t shift, uint32_t v, 478 bool write_mask) 479 { 480 if (!mask) 481 return; 482 483 if (write_mask) { 484 v = ((v & mask) << shift) | (mask << (shift + 16)); 485 } else { 486 uint32_t cached_val = vop->regsbak[offset >> 2]; 487 488 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 489 vop->regsbak[offset >> 2] = v; 490 } 491 492 writel(v, vop->regs + offset); 493 } 494 495 static inline void vop_cfg_done(struct vop *vop) 496 { 497 VOP_CTRL_SET(vop, cfg_done, 1); 498 } 499 500 static inline void vop_grf_writel(struct vop *vop, struct vop_reg reg, u32 v) 501 { 502 u32 val = 0; 503 504 if (VOP_REG_SUPPORT(vop, reg)) { 505 val = (v << reg.shift) | (reg.mask << (reg.shift + 16)); 506 writel(val, vop->grf + reg.offset); 507 } 508 } 509 510 /** 511 * drm_format_horz_chroma_subsampling - get the horizontal chroma subsampling factor 512 * @format: pixel format (DRM_FORMAT_*) 513 * 514 * Returns: 515 * The horizontal chroma subsampling factor for the 516 * specified pixel format. 517 */ 518 static inline int drm_format_horz_chroma_subsampling(uint32_t format) 519 { 520 /* uboot only support RGB format */ 521 return 1; 522 } 523 524 /** 525 * drm_format_vert_chroma_subsampling - get the vertical chroma subsampling factor 526 * @format: pixel format (DRM_FORMAT_*) 527 * 528 * Returns: 529 * The vertical chroma subsampling factor for the 530 * specified pixel format. 531 */ 532 static inline int drm_format_vert_chroma_subsampling(uint32_t format) 533 { 534 /* uboot only support RGB format */ 535 return 1; 536 } 537 538 #endif 539