xref: /rk3399_rockchip-uboot/drivers/video/drm/rockchip_vop.h (revision 7e044b9aeceaa3c07ba4dd8939761bd87f4c8300)
1 /*
2  * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef _ROCKCHIP_VOP_H_
8 #define _ROCKCHIP_VOP_H_
9 #include "rockchip_display.h"
10 #include <asm/gpio.h>
11 
12 
13 #define VOP_REG_SUPPORT(vop, reg) \
14 		(reg.mask && \
15 		 (!reg.major || \
16 		  (reg.major == VOP_MAJOR(vop->version) && \
17 		   reg.begin_minor <= VOP_MINOR(vop->version) && \
18 		   reg.end_minor >= VOP_MINOR(vop->version))))
19 
20 #define VOP_WIN_SUPPORT(vop, win, name) \
21 		VOP_REG_SUPPORT(vop, win->name)
22 
23 #define VOP_CTRL_SUPPORT(vop, name) \
24 		VOP_REG_SUPPORT(vop, vop->ctrl->name)
25 
26 #define __REG_SET(x, off, mask, shift, v, write_mask) \
27 		vop_mask_write(x, off, mask, shift, v, write_mask)
28 
29 #define _REG_SET(vop, name, off, reg, mask, v) \
30 	do { \
31 		if (VOP_REG_SUPPORT(vop, reg)) \
32 			__REG_SET(vop, off + reg.offset, mask, reg.shift, \
33 				  v, reg.write_mask); \
34 		else \
35 			debug("Warning: not support "#name"\n"); \
36 	} while(0)
37 
38 #define REG_SET(x, name, off, reg, v) \
39 		_REG_SET(x, name, off, reg, reg.mask, v)
40 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
41 		_REG_SET(x, name, off, reg, reg.mask & mask, v)
42 
43 #define VOP_WIN_SET(x, name, v) \
44 		REG_SET(x, name, x->win_offset, x->win->name, v)
45 #define VOP_WIN_SET_EXT(x, ext, name, v) \
46 		REG_SET(x, name, x->win_offset, x->win->ext->name, v)
47 #define VOP_SCL_SET(x, name, v) \
48 		REG_SET(x, name, x->win_offset, x->win->scl->name, v)
49 #define VOP_SCL_SET_EXT(x, name, v) \
50 		REG_SET(x, name, x->win_offset, x->win->scl->ext->name, v)
51 
52 #define VOP_CTRL_SET(x, name, v) \
53 		REG_SET(x, name, 0, (x)->ctrl->name, v)
54 #define VOP_LINE_FLAG_SET(x, name, v) \
55 		REG_SET(x, name, 0, (x)->line_flag->name, v)
56 #define VOP_WIN_CSC_SET(x, name, v) \
57 		REG_SET(x, name, 0, (x)->win_csc->name, v)
58 
59 #define VOP_CTRL_GET(x, name) \
60 		vop_read_reg(x, 0, &vop->ctrl->name)
61 
62 #define VOP_WIN_GET(x, name) \
63 		vop_read_reg(x, vop->win->offset, &vop->win->name)
64 
65 #define VOP_GRF_SET(vop, name, v) \
66 	do { \
67 		if (vop->grf_ctrl) { \
68 			vop_grf_writel(vop, vop->grf_ctrl->name, v); \
69 		} \
70 	} while (0)
71 
72 #define CVBS_PAL_VDISPLAY              288
73 
74 enum alpha_mode {
75 	ALPHA_STRAIGHT,
76 	ALPHA_INVERSE,
77 };
78 
79 enum global_blend_mode {
80 	ALPHA_GLOBAL,
81 	ALPHA_PER_PIX,
82 	ALPHA_PER_PIX_GLOBAL,
83 };
84 
85 enum alpha_cal_mode {
86 	ALPHA_SATURATION,
87 	ALPHA_NO_SATURATION,
88 };
89 
90 enum color_mode {
91 	ALPHA_SRC_PRE_MUL,
92 	ALPHA_SRC_NO_PRE_MUL,
93 };
94 
95 enum factor_mode {
96 	ALPHA_ZERO,
97 	ALPHA_ONE,
98 	ALPHA_SRC,
99 	ALPHA_SRC_INVERSE,
100 	ALPHA_SRC_GLOBAL,
101 };
102 
103 enum scale_mode {
104 	SCALE_NONE = 0x0,
105 	SCALE_UP   = 0x1,
106 	SCALE_DOWN = 0x2
107 };
108 
109 enum lb_mode {
110 	LB_YUV_3840X5 = 0x0,
111 	LB_YUV_2560X8 = 0x1,
112 	LB_RGB_3840X2 = 0x2,
113 	LB_RGB_2560X4 = 0x3,
114 	LB_RGB_1920X5 = 0x4,
115 	LB_RGB_1280X8 = 0x5
116 };
117 
118 enum sacle_up_mode {
119 	SCALE_UP_BIL = 0x0,
120 	SCALE_UP_BIC = 0x1
121 };
122 
123 enum scale_down_mode {
124 	SCALE_DOWN_BIL = 0x0,
125 	SCALE_DOWN_AVG = 0x1
126 };
127 
128 enum dither_down_mode {
129 	RGB888_TO_RGB565 = 0x0,
130 	RGB888_TO_RGB666 = 0x1
131 };
132 
133 enum dither_down_mode_sel {
134 	DITHER_DOWN_ALLEGRO = 0x0,
135 	DITHER_DOWN_FRC = 0x1
136 };
137 
138 enum vop_csc_format {
139 	CSC_BT601L,
140 	CSC_BT709L,
141 	CSC_BT601F,
142 	CSC_BT2020,
143 };
144 
145 #define DSP_BG_SWAP		0x1
146 #define DSP_RB_SWAP		0x2
147 #define DSP_RG_SWAP		0x4
148 #define DSP_DELTA_SWAP		0x8
149 
150 #define PRE_DITHER_DOWN_EN(x)	((x) << 0)
151 #define DITHER_DOWN_EN(x)	((x) << 1)
152 #define DITHER_DOWN_MODE(x)	((x) << 2)
153 #define DITHER_DOWN_MODE_SEL(x)	((x) << 3)
154 
155 #define FRAC_16_16(mult, div)    (((mult) << 16) / (div))
156 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT	12
157 #define SCL_MAX_VSKIPLINES		4
158 #define MIN_SCL_FT_AFTER_VSKIP		1
159 
160 static inline uint16_t scl_cal_scale(int src, int dst, int shift)
161 {
162 	return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
163 }
164 
165 static inline uint16_t scl_cal_scale2(int src, int dst)
166 {
167 	return ((src - 1) << 12) / (dst - 1);
168 }
169 
170 #define GET_SCL_FT_BILI_DN(src, dst)	scl_cal_scale(src, dst, 12)
171 #define GET_SCL_FT_BILI_UP(src, dst)	scl_cal_scale(src, dst, 16)
172 #define GET_SCL_FT_BIC(src, dst)	scl_cal_scale(src, dst, 16)
173 
174 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
175 					     int vskiplines)
176 {
177 	int act_height;
178 
179 	act_height = (src_h + vskiplines - 1) / vskiplines;
180 
181 	return GET_SCL_FT_BILI_DN(act_height, dst_h);
182 }
183 
184 static inline enum scale_mode scl_get_scl_mode(int src, int dst)
185 {
186 	if (src < dst)
187 		return SCALE_UP;
188 	else if (src > dst)
189 		return SCALE_DOWN;
190 
191 	return SCALE_NONE;
192 }
193 
194 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
195 {
196 	uint32_t vskiplines;
197 
198 	for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
199 		if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
200 			break;
201 
202 	return vskiplines;
203 }
204 
205 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
206 {
207 	int lb_mode;
208 
209 	if (width > 2560)
210 		lb_mode = LB_RGB_3840X2;
211 	else if (width > 1920)
212 		lb_mode = LB_RGB_2560X4;
213 	else if (!is_yuv)
214 		lb_mode = LB_RGB_1920X5;
215 	else if (width > 1280)
216 		lb_mode = LB_YUV_3840X5;
217 	else
218 		lb_mode = LB_YUV_2560X8;
219 
220 	return lb_mode;
221 }
222 
223 struct vop_reg_data {
224 	uint32_t offset;
225 	uint32_t value;
226 };
227 
228 struct vop_reg {
229 	uint32_t mask;
230 	uint32_t offset:17;
231 	uint32_t shift:5;
232 	uint32_t begin_minor:4;
233 	uint32_t end_minor:4;
234 	uint32_t reserved:2;
235 	uint32_t major:3;
236 	uint32_t write_mask:1;
237 };
238 
239 struct vop_ctrl {
240 	struct vop_reg standby;
241 	struct vop_reg axi_outstanding_max_num;
242 	struct vop_reg axi_max_outstanding_en;
243 	struct vop_reg htotal_pw;
244 	struct vop_reg hact_st_end;
245 	struct vop_reg vtotal_pw;
246 	struct vop_reg vact_st_end;
247 	struct vop_reg vact_st_end_f1;
248 	struct vop_reg vs_st_end_f1;
249 	struct vop_reg hpost_st_end;
250 	struct vop_reg vpost_st_end;
251 	struct vop_reg vpost_st_end_f1;
252 	struct vop_reg post_scl_factor;
253 	struct vop_reg post_scl_ctrl;
254 	struct vop_reg dsp_interlace;
255 	struct vop_reg global_regdone_en;
256 	struct vop_reg auto_gate_en;
257 	struct vop_reg post_lb_mode;
258 	struct vop_reg dsp_layer_sel;
259 	struct vop_reg overlay_mode;
260 	struct vop_reg core_dclk_div;
261 	struct vop_reg dclk_ddr;
262 	struct vop_reg p2i_en;
263 	struct vop_reg hdmi_dclk_out_en;
264 	struct vop_reg rgb_en;
265 	struct vop_reg lvds_en;
266 	struct vop_reg edp_en;
267 	struct vop_reg hdmi_en;
268 	struct vop_reg mipi_en;
269 	struct vop_reg data01_swap;
270 	struct vop_reg mipi_dual_channel_en;
271 	struct vop_reg dp_en;
272 	struct vop_reg dclk_pol;
273 	struct vop_reg pin_pol;
274 	struct vop_reg rgb_dclk_pol;
275 	struct vop_reg rgb_pin_pol;
276 	struct vop_reg lvds_dclk_pol;
277 	struct vop_reg lvds_pin_pol;
278 	struct vop_reg hdmi_dclk_pol;
279 	struct vop_reg hdmi_pin_pol;
280 	struct vop_reg edp_dclk_pol;
281 	struct vop_reg edp_pin_pol;
282 	struct vop_reg mipi_dclk_pol;
283 	struct vop_reg mipi_pin_pol;
284 	struct vop_reg dp_dclk_pol;
285 	struct vop_reg dp_pin_pol;
286 
287 	struct vop_reg dither_up;
288 	struct vop_reg dither_down;
289 
290 	struct vop_reg sw_dac_sel;
291 	struct vop_reg tve_sw_mode;
292 	struct vop_reg tve_dclk_pol;
293 	struct vop_reg tve_dclk_en;
294 	struct vop_reg sw_genlock;
295 	struct vop_reg sw_uv_offset_en;
296 
297 	struct vop_reg dsp_out_yuv;
298 	struct vop_reg dsp_data_swap;
299 	struct vop_reg dsp_ccir656_avg;
300 	struct vop_reg dsp_black;
301 	struct vop_reg dsp_blank;
302 	struct vop_reg dsp_outzero;
303 	struct vop_reg dsp_lut_en;
304 	struct vop_reg update_gamma_lut;
305 
306 	struct vop_reg out_mode;
307 
308 	struct vop_reg xmirror;
309 	struct vop_reg ymirror;
310 	struct vop_reg dsp_background;
311 
312 	/* CABC */
313 	struct vop_reg cabc_total_num;
314 	struct vop_reg cabc_config_mode;
315 	struct vop_reg cabc_stage_up_mode;
316 	struct vop_reg cabc_scale_cfg_value;
317 	struct vop_reg cabc_scale_cfg_enable;
318 	struct vop_reg cabc_global_dn_limit_en;
319 	struct vop_reg cabc_lut_en;
320 	struct vop_reg cabc_en;
321 	struct vop_reg cabc_handle_en;
322 	struct vop_reg cabc_stage_up;
323 	struct vop_reg cabc_stage_down;
324 	struct vop_reg cabc_global_dn;
325 	struct vop_reg cabc_calc_pixel_num;
326 
327 	struct vop_reg win_gate[4];
328 	struct vop_reg win_channel[4];
329 
330 	/* BCSH */
331 	struct vop_reg bcsh_brightness;
332 	struct vop_reg bcsh_contrast;
333 	struct vop_reg bcsh_sat_con;
334 	struct vop_reg bcsh_sin_hue;
335 	struct vop_reg bcsh_cos_hue;
336 	struct vop_reg bcsh_r2y_csc_mode;
337 	struct vop_reg bcsh_r2y_en;
338 	struct vop_reg bcsh_y2r_csc_mode;
339 	struct vop_reg bcsh_y2r_en;
340 	struct vop_reg bcsh_color_bar;
341 	struct vop_reg bcsh_out_mode;
342 	struct vop_reg bcsh_en;
343 	struct vop_reg reg_done_frm;
344 
345 	/* MCU OUTPUT */
346 	struct vop_reg mcu_pix_total;
347 	struct vop_reg mcu_cs_pst;
348 	struct vop_reg mcu_cs_pend;
349 	struct vop_reg mcu_rw_pst;
350 	struct vop_reg mcu_rw_pend;
351 	struct vop_reg mcu_clk_sel;
352 	struct vop_reg mcu_hold_mode;
353 	struct vop_reg mcu_frame_st;
354 	struct vop_reg mcu_rs;
355 	struct vop_reg mcu_bypass;
356 	struct vop_reg mcu_type;
357 	struct vop_reg mcu_rw_bypass_port;
358 
359 
360 	struct vop_reg cfg_done;
361 };
362 
363 struct vop_scl_extension {
364 	struct vop_reg cbcr_vsd_mode;
365 	struct vop_reg cbcr_vsu_mode;
366 	struct vop_reg cbcr_hsd_mode;
367 	struct vop_reg cbcr_ver_scl_mode;
368 	struct vop_reg cbcr_hor_scl_mode;
369 	struct vop_reg yrgb_vsd_mode;
370 	struct vop_reg yrgb_vsu_mode;
371 	struct vop_reg yrgb_hsd_mode;
372 	struct vop_reg yrgb_ver_scl_mode;
373 	struct vop_reg yrgb_hor_scl_mode;
374 	struct vop_reg line_load_mode;
375 	struct vop_reg cbcr_axi_gather_num;
376 	struct vop_reg yrgb_axi_gather_num;
377 	struct vop_reg vsd_cbcr_gt2;
378 	struct vop_reg vsd_cbcr_gt4;
379 	struct vop_reg vsd_yrgb_gt2;
380 	struct vop_reg vsd_yrgb_gt4;
381 	struct vop_reg bic_coe_sel;
382 	struct vop_reg cbcr_axi_gather_en;
383 	struct vop_reg yrgb_axi_gather_en;
384 	struct vop_reg lb_mode;
385 };
386 
387 struct vop_scl_regs {
388 	const struct vop_scl_extension *ext;
389 
390 	struct vop_reg scale_yrgb_x;
391 	struct vop_reg scale_yrgb_y;
392 	struct vop_reg scale_cbcr_x;
393 	struct vop_reg scale_cbcr_y;
394 };
395 
396 struct vop_win {
397 	const struct vop_scl_regs *scl;
398 
399 	struct vop_reg gate;
400 	struct vop_reg enable;
401 	struct vop_reg format;
402 	struct vop_reg ymirror;
403 	struct vop_reg rb_swap;
404 	struct vop_reg act_info;
405 	struct vop_reg dsp_info;
406 	struct vop_reg dsp_st;
407 	struct vop_reg yrgb_mst;
408 	struct vop_reg uv_mst;
409 	struct vop_reg yrgb_vir;
410 	struct vop_reg uv_vir;
411 	struct vop_reg alpha_mode;
412 	struct vop_reg alpha_en;
413 
414 	struct vop_reg dst_alpha_ctl;
415 	struct vop_reg src_alpha_ctl;
416 };
417 
418 struct vop_line_flag {
419 	struct vop_reg line_flag_num[2];
420 };
421 
422 struct vop_grf_ctrl {
423 	struct vop_reg grf_dclk_inv;
424 };
425 
426 struct vop_csc_table {
427 	const uint32_t *r2y_bt601;
428 	const uint32_t *r2y_bt601_12_235;
429 	const uint32_t *r2y_bt709;
430 	const uint32_t *r2y_bt2020;
431 };
432 
433 struct vop_csc {
434 	struct vop_reg y2r_en;
435 	struct vop_reg r2r_en;
436 	struct vop_reg r2y_en;
437 
438 	uint32_t y2r_offset;
439 	uint32_t r2r_offset;
440 	uint32_t r2y_offset;
441 };
442 
443 #define VOP_FEATURE_OUTPUT_10BIT	BIT(0)
444 
445 struct vop_data {
446 	uint32_t version;
447 	const struct vop_ctrl *ctrl;
448 	const struct vop_win *win;
449 	const struct vop_line_flag *line_flag;
450 	const struct vop_grf_ctrl *grf_ctrl;
451 	const struct vop_csc_table *csc_table;
452 	const struct vop_csc *win_csc;
453 	int win_offset;
454 	int reg_len;
455 	u64 feature;
456 	struct vop_rect max_output;
457 };
458 
459 struct vop {
460 	u32 *regsbak;
461 	void *regs;
462 	void *grf;
463 
464 	uint32_t version;
465 	const struct vop_ctrl *ctrl;
466 	const struct vop_win *win;
467 	const struct vop_line_flag *line_flag;
468 	const struct vop_grf_ctrl *grf_ctrl;
469 	const struct vop_csc_table *csc_table;
470 	const struct vop_csc *win_csc;
471 	int win_offset;
472 
473 	struct gpio_desc mcu_rs_gpio;
474 };
475 
476 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
477 {
478 	writel(v, vop->regs + offset);
479 	vop->regsbak[offset >> 2] = v;
480 }
481 
482 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
483 {
484 	return readl(vop->regs + offset);
485 }
486 
487 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
488 				    const struct vop_reg *reg)
489 {
490 	return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
491 }
492 
493 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
494 				  uint32_t mask, uint32_t shift, uint32_t v,
495 				  bool write_mask)
496 {
497 	if (!mask)
498 		return;
499 
500 	if (write_mask) {
501 		v = ((v & mask) << shift) | (mask << (shift + 16));
502 	} else {
503 		uint32_t cached_val = vop->regsbak[offset >> 2];
504 
505 		v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
506 		vop->regsbak[offset >> 2] = v;
507 	}
508 
509 	writel(v, vop->regs + offset);
510 }
511 
512 static inline void vop_cfg_done(struct vop *vop)
513 {
514 	VOP_CTRL_SET(vop, cfg_done, 1);
515 }
516 
517 static inline void vop_grf_writel(struct vop *vop, struct vop_reg reg, u32 v)
518 {
519 	u32 val = 0;
520 
521 	if (VOP_REG_SUPPORT(vop, reg)) {
522 		val = (v << reg.shift) | (reg.mask << (reg.shift + 16));
523 		writel(val, vop->grf + reg.offset);
524 	}
525 }
526 
527 /**
528  * drm_format_horz_chroma_subsampling - get the horizontal chroma subsampling factor
529  * @format: pixel format (DRM_FORMAT_*)
530  *
531  * Returns:
532  * The horizontal chroma subsampling factor for the
533  * specified pixel format.
534  */
535 static inline int drm_format_horz_chroma_subsampling(uint32_t format)
536 {
537 	/* uboot only support RGB format */
538 	return 1;
539 }
540 
541 /**
542  * drm_format_vert_chroma_subsampling - get the vertical chroma subsampling factor
543  * @format: pixel format (DRM_FORMAT_*)
544  *
545  * Returns:
546  * The vertical chroma subsampling factor for the
547  * specified pixel format.
548  */
549 static inline int drm_format_vert_chroma_subsampling(uint32_t format)
550 {
551 	/* uboot only support RGB format */
552 	return 1;
553 }
554 
555 #endif
556