1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ROCKCHIP_VOP_H_ 8 #define _ROCKCHIP_VOP_H_ 9 10 /* 11 * major: IP major vertion, used for IP structure 12 * minor: big feature change under same structure 13 */ 14 #define VOP_VERSION(major, minor) ((major) << 8 | (minor)) 15 #define VOP_MAJOR(version) ((version) >> 8) 16 #define VOP_MINOR(version) ((version) & 0xff) 17 18 #define VOP_REG_SUPPORT(vop, reg) \ 19 (!reg.major || (reg.major == VOP_MAJOR(vop->version) && \ 20 reg.begin_minor <= VOP_MINOR(vop->version) && \ 21 reg.end_minor >= VOP_MINOR(vop->version) && \ 22 reg.mask)) 23 24 #define VOP_WIN_SUPPORT(vop, win, name) \ 25 VOP_REG_SUPPORT(vop, win->phy->name) 26 27 #define VOP_CTRL_SUPPORT(vop, name) \ 28 VOP_REG_SUPPORT(vop, vop->ctrl->name) 29 30 #define __REG_SET(x, off, mask, shift, v, write_mask) \ 31 vop_mask_write(x, off, mask, shift, v, write_mask) 32 33 #define _REG_SET(vop, name, off, reg, mask, v) \ 34 do { \ 35 if (VOP_REG_SUPPORT(vop, reg)) \ 36 __REG_SET(vop, off + reg.offset, mask, reg.shift, \ 37 v, reg.write_mask); \ 38 else \ 39 debug("Warning: not support "#name"\n"); \ 40 } while(0) 41 42 #define REG_SET(x, name, off, reg, v) \ 43 _REG_SET(x, name, off, reg, reg.mask, v) 44 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \ 45 _REG_SET(x, name, off, reg, reg.mask & mask, v) 46 47 #define VOP_WIN_SET(x, name, v) \ 48 REG_SET(x, name, x->win_offset, x->win->name, v) 49 #define VOP_WIN_SET_EXT(x, ext, name, v) \ 50 REG_SET(x, name, x->win_offset, x->win->ext->name, v) 51 #define VOP_SCL_SET(x, name, v) \ 52 REG_SET(x, name, x->win_offset, x->win->scl->name, v) 53 #define VOP_SCL_SET_EXT(x, name, v) \ 54 REG_SET(x, name, x->win_offset, x->win->scl->ext->name, v) 55 56 #define VOP_CTRL_SET(x, name, v) \ 57 REG_SET(x, name, 0, (x)->ctrl->name, v) 58 #define VOP_LINE_FLAG_SET(x, name, v) \ 59 REG_SET(x, name, 0, (x)->line_flag->name, v) 60 61 #define VOP_CTRL_GET(x, name) \ 62 vop_read_reg(x, 0, &vop->ctrl->name) 63 64 #define VOP_WIN_GET(x, name) \ 65 vop_read_reg(x, vop->win->offset, &vop->win->name) 66 67 enum alpha_mode { 68 ALPHA_STRAIGHT, 69 ALPHA_INVERSE, 70 }; 71 72 enum global_blend_mode { 73 ALPHA_GLOBAL, 74 ALPHA_PER_PIX, 75 ALPHA_PER_PIX_GLOBAL, 76 }; 77 78 enum alpha_cal_mode { 79 ALPHA_SATURATION, 80 ALPHA_NO_SATURATION, 81 }; 82 83 enum color_mode { 84 ALPHA_SRC_PRE_MUL, 85 ALPHA_SRC_NO_PRE_MUL, 86 }; 87 88 enum factor_mode { 89 ALPHA_ZERO, 90 ALPHA_ONE, 91 ALPHA_SRC, 92 ALPHA_SRC_INVERSE, 93 ALPHA_SRC_GLOBAL, 94 }; 95 96 enum scale_mode { 97 SCALE_NONE = 0x0, 98 SCALE_UP = 0x1, 99 SCALE_DOWN = 0x2 100 }; 101 102 enum lb_mode { 103 LB_YUV_3840X5 = 0x0, 104 LB_YUV_2560X8 = 0x1, 105 LB_RGB_3840X2 = 0x2, 106 LB_RGB_2560X4 = 0x3, 107 LB_RGB_1920X5 = 0x4, 108 LB_RGB_1280X8 = 0x5 109 }; 110 111 enum sacle_up_mode { 112 SCALE_UP_BIL = 0x0, 113 SCALE_UP_BIC = 0x1 114 }; 115 116 enum scale_down_mode { 117 SCALE_DOWN_BIL = 0x0, 118 SCALE_DOWN_AVG = 0x1 119 }; 120 121 enum dither_down_mode { 122 RGB888_TO_RGB565 = 0x0, 123 RGB888_TO_RGB666 = 0x1 124 }; 125 126 enum dither_down_mode_sel { 127 DITHER_DOWN_ALLEGRO = 0x0, 128 DITHER_DOWN_FRC = 0x1 129 }; 130 131 #define PRE_DITHER_DOWN_EN(x) ((x) << 0) 132 #define DITHER_DOWN_EN(x) ((x) << 1) 133 #define DITHER_DOWN_MODE(x) ((x) << 2) 134 #define DITHER_DOWN_MODE_SEL(x) ((x) << 3) 135 136 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 137 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12 138 #define SCL_MAX_VSKIPLINES 4 139 #define MIN_SCL_FT_AFTER_VSKIP 1 140 141 static inline uint16_t scl_cal_scale(int src, int dst, int shift) 142 { 143 return ((src * 2 - 3) << (shift - 1)) / (dst - 1); 144 } 145 146 static inline uint16_t scl_cal_scale2(int src, int dst) 147 { 148 return ((src - 1) << 12) / (dst - 1); 149 } 150 151 #define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12) 152 #define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16) 153 #define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16) 154 155 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h, 156 int vskiplines) 157 { 158 int act_height; 159 160 act_height = (src_h + vskiplines - 1) / vskiplines; 161 162 return GET_SCL_FT_BILI_DN(act_height, dst_h); 163 } 164 165 static inline enum scale_mode scl_get_scl_mode(int src, int dst) 166 { 167 if (src < dst) 168 return SCALE_UP; 169 else if (src > dst) 170 return SCALE_DOWN; 171 172 return SCALE_NONE; 173 } 174 175 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth) 176 { 177 uint32_t vskiplines; 178 179 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2) 180 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP) 181 break; 182 183 return vskiplines; 184 } 185 186 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv) 187 { 188 int lb_mode; 189 190 if (width > 2560) 191 lb_mode = LB_RGB_3840X2; 192 else if (width > 1920) 193 lb_mode = LB_RGB_2560X4; 194 else if (!is_yuv) 195 lb_mode = LB_RGB_1920X5; 196 else if (width > 1280) 197 lb_mode = LB_YUV_3840X5; 198 else 199 lb_mode = LB_YUV_2560X8; 200 201 return lb_mode; 202 } 203 204 struct vop_reg_data { 205 uint32_t offset; 206 uint32_t value; 207 }; 208 209 struct vop_reg { 210 uint32_t mask; 211 uint32_t offset:12; 212 uint32_t shift:5; 213 uint32_t begin_minor:4; 214 uint32_t end_minor:4; 215 uint32_t major:3; 216 uint32_t write_mask:1; 217 }; 218 219 struct vop_ctrl { 220 struct vop_reg standby; 221 struct vop_reg htotal_pw; 222 struct vop_reg hact_st_end; 223 struct vop_reg vtotal_pw; 224 struct vop_reg vact_st_end; 225 struct vop_reg vact_st_end_f1; 226 struct vop_reg vs_st_end_f1; 227 struct vop_reg hpost_st_end; 228 struct vop_reg vpost_st_end; 229 struct vop_reg vpost_st_end_f1; 230 struct vop_reg post_scl_factor; 231 struct vop_reg post_scl_ctrl; 232 struct vop_reg dsp_interlace; 233 struct vop_reg global_regdone_en; 234 struct vop_reg auto_gate_en; 235 struct vop_reg post_lb_mode; 236 struct vop_reg dsp_layer_sel; 237 struct vop_reg overlay_mode; 238 struct vop_reg core_dclk_div; 239 struct vop_reg dclk_ddr; 240 struct vop_reg p2i_en; 241 struct vop_reg rgb_en; 242 struct vop_reg edp_en; 243 struct vop_reg hdmi_en; 244 struct vop_reg mipi_en; 245 struct vop_reg data01_swap; 246 struct vop_reg mipi_dual_channel_en; 247 struct vop_reg dp_en; 248 struct vop_reg pin_pol; 249 struct vop_reg rgb_pin_pol; 250 struct vop_reg hdmi_pin_pol; 251 struct vop_reg edp_pin_pol; 252 struct vop_reg mipi_pin_pol; 253 struct vop_reg dp_pin_pol; 254 255 struct vop_reg dither_up; 256 struct vop_reg dither_down; 257 258 struct vop_reg dsp_out_yuv; 259 struct vop_reg dsp_data_swap; 260 struct vop_reg dsp_ccir656_avg; 261 struct vop_reg dsp_black; 262 struct vop_reg dsp_blank; 263 struct vop_reg dsp_outzero; 264 struct vop_reg dsp_lut_en; 265 struct vop_reg update_gamma_lut; 266 267 struct vop_reg out_mode; 268 269 struct vop_reg xmirror; 270 struct vop_reg ymirror; 271 struct vop_reg dsp_background; 272 273 struct vop_reg win_gate[4]; 274 struct vop_reg cfg_done; 275 }; 276 277 struct vop_scl_extension { 278 struct vop_reg cbcr_vsd_mode; 279 struct vop_reg cbcr_vsu_mode; 280 struct vop_reg cbcr_hsd_mode; 281 struct vop_reg cbcr_ver_scl_mode; 282 struct vop_reg cbcr_hor_scl_mode; 283 struct vop_reg yrgb_vsd_mode; 284 struct vop_reg yrgb_vsu_mode; 285 struct vop_reg yrgb_hsd_mode; 286 struct vop_reg yrgb_ver_scl_mode; 287 struct vop_reg yrgb_hor_scl_mode; 288 struct vop_reg line_load_mode; 289 struct vop_reg cbcr_axi_gather_num; 290 struct vop_reg yrgb_axi_gather_num; 291 struct vop_reg vsd_cbcr_gt2; 292 struct vop_reg vsd_cbcr_gt4; 293 struct vop_reg vsd_yrgb_gt2; 294 struct vop_reg vsd_yrgb_gt4; 295 struct vop_reg bic_coe_sel; 296 struct vop_reg cbcr_axi_gather_en; 297 struct vop_reg yrgb_axi_gather_en; 298 struct vop_reg lb_mode; 299 }; 300 301 struct vop_scl_regs { 302 const struct vop_scl_extension *ext; 303 304 struct vop_reg scale_yrgb_x; 305 struct vop_reg scale_yrgb_y; 306 struct vop_reg scale_cbcr_x; 307 struct vop_reg scale_cbcr_y; 308 }; 309 310 struct vop_win { 311 const struct vop_scl_regs *scl; 312 313 struct vop_reg enable; 314 struct vop_reg format; 315 struct vop_reg ymirror; 316 struct vop_reg rb_swap; 317 struct vop_reg act_info; 318 struct vop_reg dsp_info; 319 struct vop_reg dsp_st; 320 struct vop_reg yrgb_mst; 321 struct vop_reg uv_mst; 322 struct vop_reg yrgb_vir; 323 struct vop_reg uv_vir; 324 struct vop_reg alpha_mode; 325 struct vop_reg alpha_en; 326 327 struct vop_reg dst_alpha_ctl; 328 struct vop_reg src_alpha_ctl; 329 }; 330 331 struct vop_line_flag { 332 struct vop_reg line_flag_num[2]; 333 }; 334 335 #define VOP_FEATURE_OUTPUT_10BIT BIT(0) 336 337 struct vop_data { 338 uint32_t version; 339 const struct vop_ctrl *ctrl; 340 const struct vop_win *win; 341 const struct vop_line_flag *line_flag; 342 int win_offset; 343 int reg_len; 344 u64 feature; 345 }; 346 347 struct vop { 348 u32 *regsbak; 349 void *regs; 350 351 uint32_t version; 352 const struct vop_ctrl *ctrl; 353 const struct vop_win *win; 354 const struct vop_line_flag *line_flag; 355 int win_offset; 356 }; 357 358 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 359 { 360 writel(v, vop->regs + offset); 361 vop->regsbak[offset >> 2] = v; 362 } 363 364 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 365 { 366 return readl(vop->regs + offset); 367 } 368 369 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 370 const struct vop_reg *reg) 371 { 372 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 373 } 374 375 static inline void vop_mask_write(struct vop *vop, uint32_t offset, 376 uint32_t mask, uint32_t shift, uint32_t v, 377 bool write_mask) 378 { 379 if (!mask) 380 return; 381 382 if (write_mask) { 383 v = ((v & mask) << shift) | (mask << (shift + 16)); 384 } else { 385 uint32_t cached_val = vop->regsbak[offset >> 2]; 386 387 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 388 vop->regsbak[offset >> 2] = v; 389 } 390 391 writel(v, vop->regs + offset); 392 } 393 394 static inline void vop_cfg_done(struct vop *vop) 395 { 396 VOP_CTRL_SET(vop, cfg_done, 1); 397 } 398 399 /** 400 * drm_format_horz_chroma_subsampling - get the horizontal chroma subsampling factor 401 * @format: pixel format (DRM_FORMAT_*) 402 * 403 * Returns: 404 * The horizontal chroma subsampling factor for the 405 * specified pixel format. 406 */ 407 static inline int drm_format_horz_chroma_subsampling(uint32_t format) 408 { 409 /* uboot only support RGB format */ 410 return 1; 411 } 412 413 /** 414 * drm_format_vert_chroma_subsampling - get the vertical chroma subsampling factor 415 * @format: pixel format (DRM_FORMAT_*) 416 * 417 * Returns: 418 * The vertical chroma subsampling factor for the 419 * specified pixel format. 420 */ 421 static inline int drm_format_vert_chroma_subsampling(uint32_t format) 422 { 423 /* uboot only support RGB format */ 424 return 1; 425 } 426 427 #endif 428