1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ROCKCHIP_VOP_H_ 8 #define _ROCKCHIP_VOP_H_ 9 #include "rockchip_display.h" 10 #include <asm/gpio.h> 11 12 /* 13 * major: IP major vertion, used for IP structure 14 * minor: big feature change under same structure 15 */ 16 #define VOP_VERSION(major, minor) ((major) << 8 | (minor)) 17 #define VOP_MAJOR(version) ((version) >> 8) 18 #define VOP_MINOR(version) ((version) & 0xff) 19 20 #define VOP_REG_SUPPORT(vop, reg) \ 21 (reg.mask && \ 22 (!reg.major || \ 23 (reg.major == VOP_MAJOR(vop->version) && \ 24 reg.begin_minor <= VOP_MINOR(vop->version) && \ 25 reg.end_minor >= VOP_MINOR(vop->version)))) 26 27 #define VOP_WIN_SUPPORT(vop, win, name) \ 28 VOP_REG_SUPPORT(vop, win->name) 29 30 #define VOP_CTRL_SUPPORT(vop, name) \ 31 VOP_REG_SUPPORT(vop, vop->ctrl->name) 32 33 #define __REG_SET(x, off, mask, shift, v, write_mask) \ 34 vop_mask_write(x, off, mask, shift, v, write_mask) 35 36 #define _REG_SET(vop, name, off, reg, mask, v) \ 37 do { \ 38 if (VOP_REG_SUPPORT(vop, reg)) \ 39 __REG_SET(vop, off + reg.offset, mask, reg.shift, \ 40 v, reg.write_mask); \ 41 else \ 42 debug("Warning: not support "#name"\n"); \ 43 } while(0) 44 45 #define REG_SET(x, name, off, reg, v) \ 46 _REG_SET(x, name, off, reg, reg.mask, v) 47 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \ 48 _REG_SET(x, name, off, reg, reg.mask & mask, v) 49 50 #define VOP_WIN_SET(x, name, v) \ 51 REG_SET(x, name, x->win_offset, x->win->name, v) 52 #define VOP_WIN_SET_EXT(x, ext, name, v) \ 53 REG_SET(x, name, x->win_offset, x->win->ext->name, v) 54 #define VOP_SCL_SET(x, name, v) \ 55 REG_SET(x, name, x->win_offset, x->win->scl->name, v) 56 #define VOP_SCL_SET_EXT(x, name, v) \ 57 REG_SET(x, name, x->win_offset, x->win->scl->ext->name, v) 58 59 #define VOP_CTRL_SET(x, name, v) \ 60 REG_SET(x, name, 0, (x)->ctrl->name, v) 61 #define VOP_LINE_FLAG_SET(x, name, v) \ 62 REG_SET(x, name, 0, (x)->line_flag->name, v) 63 #define VOP_WIN_CSC_SET(x, name, v) \ 64 REG_SET(x, name, 0, (x)->win_csc->name, v) 65 66 #define VOP_CTRL_GET(x, name) \ 67 vop_read_reg(x, 0, &vop->ctrl->name) 68 69 #define VOP_WIN_GET(x, name) \ 70 vop_read_reg(x, vop->win->offset, &vop->win->name) 71 72 #define VOP_GRF_SET(vop, name, v) \ 73 do { \ 74 if (vop->grf_ctrl) { \ 75 vop_grf_writel(vop, vop->grf_ctrl->name, v); \ 76 } \ 77 } while (0) 78 79 #define CVBS_PAL_VDISPLAY 288 80 81 enum alpha_mode { 82 ALPHA_STRAIGHT, 83 ALPHA_INVERSE, 84 }; 85 86 enum global_blend_mode { 87 ALPHA_GLOBAL, 88 ALPHA_PER_PIX, 89 ALPHA_PER_PIX_GLOBAL, 90 }; 91 92 enum alpha_cal_mode { 93 ALPHA_SATURATION, 94 ALPHA_NO_SATURATION, 95 }; 96 97 enum color_mode { 98 ALPHA_SRC_PRE_MUL, 99 ALPHA_SRC_NO_PRE_MUL, 100 }; 101 102 enum factor_mode { 103 ALPHA_ZERO, 104 ALPHA_ONE, 105 ALPHA_SRC, 106 ALPHA_SRC_INVERSE, 107 ALPHA_SRC_GLOBAL, 108 }; 109 110 enum scale_mode { 111 SCALE_NONE = 0x0, 112 SCALE_UP = 0x1, 113 SCALE_DOWN = 0x2 114 }; 115 116 enum lb_mode { 117 LB_YUV_3840X5 = 0x0, 118 LB_YUV_2560X8 = 0x1, 119 LB_RGB_3840X2 = 0x2, 120 LB_RGB_2560X4 = 0x3, 121 LB_RGB_1920X5 = 0x4, 122 LB_RGB_1280X8 = 0x5 123 }; 124 125 enum sacle_up_mode { 126 SCALE_UP_BIL = 0x0, 127 SCALE_UP_BIC = 0x1 128 }; 129 130 enum scale_down_mode { 131 SCALE_DOWN_BIL = 0x0, 132 SCALE_DOWN_AVG = 0x1 133 }; 134 135 enum dither_down_mode { 136 RGB888_TO_RGB565 = 0x0, 137 RGB888_TO_RGB666 = 0x1 138 }; 139 140 enum dither_down_mode_sel { 141 DITHER_DOWN_ALLEGRO = 0x0, 142 DITHER_DOWN_FRC = 0x1 143 }; 144 145 enum vop_csc_format { 146 CSC_BT601L, 147 CSC_BT709L, 148 CSC_BT601F, 149 CSC_BT2020, 150 }; 151 152 #define DSP_BG_SWAP 0x1 153 #define DSP_RB_SWAP 0x2 154 #define DSP_RG_SWAP 0x4 155 #define DSP_DELTA_SWAP 0x8 156 157 #define PRE_DITHER_DOWN_EN(x) ((x) << 0) 158 #define DITHER_DOWN_EN(x) ((x) << 1) 159 #define DITHER_DOWN_MODE(x) ((x) << 2) 160 #define DITHER_DOWN_MODE_SEL(x) ((x) << 3) 161 162 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 163 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12 164 #define SCL_MAX_VSKIPLINES 4 165 #define MIN_SCL_FT_AFTER_VSKIP 1 166 167 static inline uint16_t scl_cal_scale(int src, int dst, int shift) 168 { 169 return ((src * 2 - 3) << (shift - 1)) / (dst - 1); 170 } 171 172 static inline uint16_t scl_cal_scale2(int src, int dst) 173 { 174 return ((src - 1) << 12) / (dst - 1); 175 } 176 177 #define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12) 178 #define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16) 179 #define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16) 180 181 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h, 182 int vskiplines) 183 { 184 int act_height; 185 186 act_height = (src_h + vskiplines - 1) / vskiplines; 187 188 return GET_SCL_FT_BILI_DN(act_height, dst_h); 189 } 190 191 static inline enum scale_mode scl_get_scl_mode(int src, int dst) 192 { 193 if (src < dst) 194 return SCALE_UP; 195 else if (src > dst) 196 return SCALE_DOWN; 197 198 return SCALE_NONE; 199 } 200 201 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth) 202 { 203 uint32_t vskiplines; 204 205 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2) 206 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP) 207 break; 208 209 return vskiplines; 210 } 211 212 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv) 213 { 214 int lb_mode; 215 216 if (width > 2560) 217 lb_mode = LB_RGB_3840X2; 218 else if (width > 1920) 219 lb_mode = LB_RGB_2560X4; 220 else if (!is_yuv) 221 lb_mode = LB_RGB_1920X5; 222 else if (width > 1280) 223 lb_mode = LB_YUV_3840X5; 224 else 225 lb_mode = LB_YUV_2560X8; 226 227 return lb_mode; 228 } 229 230 struct vop_reg_data { 231 uint32_t offset; 232 uint32_t value; 233 }; 234 235 struct vop_reg { 236 uint32_t mask; 237 uint32_t offset:17; 238 uint32_t shift:5; 239 uint32_t begin_minor:4; 240 uint32_t end_minor:4; 241 uint32_t reserved:2; 242 uint32_t major:3; 243 uint32_t write_mask:1; 244 }; 245 246 struct vop_ctrl { 247 struct vop_reg standby; 248 struct vop_reg axi_outstanding_max_num; 249 struct vop_reg axi_max_outstanding_en; 250 struct vop_reg htotal_pw; 251 struct vop_reg hact_st_end; 252 struct vop_reg vtotal_pw; 253 struct vop_reg vact_st_end; 254 struct vop_reg vact_st_end_f1; 255 struct vop_reg vs_st_end_f1; 256 struct vop_reg hpost_st_end; 257 struct vop_reg vpost_st_end; 258 struct vop_reg vpost_st_end_f1; 259 struct vop_reg post_scl_factor; 260 struct vop_reg post_scl_ctrl; 261 struct vop_reg dsp_interlace; 262 struct vop_reg global_regdone_en; 263 struct vop_reg auto_gate_en; 264 struct vop_reg post_lb_mode; 265 struct vop_reg dsp_layer_sel; 266 struct vop_reg overlay_mode; 267 struct vop_reg core_dclk_div; 268 struct vop_reg dclk_ddr; 269 struct vop_reg p2i_en; 270 struct vop_reg hdmi_dclk_out_en; 271 struct vop_reg rgb_en; 272 struct vop_reg lvds_en; 273 struct vop_reg edp_en; 274 struct vop_reg hdmi_en; 275 struct vop_reg mipi_en; 276 struct vop_reg data01_swap; 277 struct vop_reg mipi_dual_channel_en; 278 struct vop_reg dp_en; 279 struct vop_reg dclk_pol; 280 struct vop_reg pin_pol; 281 struct vop_reg rgb_dclk_pol; 282 struct vop_reg rgb_pin_pol; 283 struct vop_reg lvds_dclk_pol; 284 struct vop_reg lvds_pin_pol; 285 struct vop_reg hdmi_dclk_pol; 286 struct vop_reg hdmi_pin_pol; 287 struct vop_reg edp_dclk_pol; 288 struct vop_reg edp_pin_pol; 289 struct vop_reg mipi_dclk_pol; 290 struct vop_reg mipi_pin_pol; 291 struct vop_reg dp_dclk_pol; 292 struct vop_reg dp_pin_pol; 293 294 struct vop_reg dither_up; 295 struct vop_reg dither_down; 296 297 struct vop_reg sw_dac_sel; 298 struct vop_reg tve_sw_mode; 299 struct vop_reg tve_dclk_pol; 300 struct vop_reg tve_dclk_en; 301 struct vop_reg sw_genlock; 302 struct vop_reg sw_uv_offset_en; 303 304 struct vop_reg dsp_out_yuv; 305 struct vop_reg dsp_data_swap; 306 struct vop_reg dsp_ccir656_avg; 307 struct vop_reg dsp_black; 308 struct vop_reg dsp_blank; 309 struct vop_reg dsp_outzero; 310 struct vop_reg dsp_lut_en; 311 struct vop_reg update_gamma_lut; 312 313 struct vop_reg out_mode; 314 315 struct vop_reg xmirror; 316 struct vop_reg ymirror; 317 struct vop_reg dsp_background; 318 319 /* CABC */ 320 struct vop_reg cabc_total_num; 321 struct vop_reg cabc_config_mode; 322 struct vop_reg cabc_stage_up_mode; 323 struct vop_reg cabc_scale_cfg_value; 324 struct vop_reg cabc_scale_cfg_enable; 325 struct vop_reg cabc_global_dn_limit_en; 326 struct vop_reg cabc_lut_en; 327 struct vop_reg cabc_en; 328 struct vop_reg cabc_handle_en; 329 struct vop_reg cabc_stage_up; 330 struct vop_reg cabc_stage_down; 331 struct vop_reg cabc_global_dn; 332 struct vop_reg cabc_calc_pixel_num; 333 334 struct vop_reg win_gate[4]; 335 struct vop_reg win_channel[4]; 336 337 /* BCSH */ 338 struct vop_reg bcsh_brightness; 339 struct vop_reg bcsh_contrast; 340 struct vop_reg bcsh_sat_con; 341 struct vop_reg bcsh_sin_hue; 342 struct vop_reg bcsh_cos_hue; 343 struct vop_reg bcsh_r2y_csc_mode; 344 struct vop_reg bcsh_r2y_en; 345 struct vop_reg bcsh_y2r_csc_mode; 346 struct vop_reg bcsh_y2r_en; 347 struct vop_reg bcsh_color_bar; 348 struct vop_reg bcsh_out_mode; 349 struct vop_reg bcsh_en; 350 struct vop_reg reg_done_frm; 351 352 /* MCU OUTPUT */ 353 struct vop_reg mcu_pix_total; 354 struct vop_reg mcu_cs_pst; 355 struct vop_reg mcu_cs_pend; 356 struct vop_reg mcu_rw_pst; 357 struct vop_reg mcu_rw_pend; 358 struct vop_reg mcu_clk_sel; 359 struct vop_reg mcu_hold_mode; 360 struct vop_reg mcu_frame_st; 361 struct vop_reg mcu_rs; 362 struct vop_reg mcu_bypass; 363 struct vop_reg mcu_type; 364 struct vop_reg mcu_rw_bypass_port; 365 366 367 struct vop_reg cfg_done; 368 }; 369 370 struct vop_scl_extension { 371 struct vop_reg cbcr_vsd_mode; 372 struct vop_reg cbcr_vsu_mode; 373 struct vop_reg cbcr_hsd_mode; 374 struct vop_reg cbcr_ver_scl_mode; 375 struct vop_reg cbcr_hor_scl_mode; 376 struct vop_reg yrgb_vsd_mode; 377 struct vop_reg yrgb_vsu_mode; 378 struct vop_reg yrgb_hsd_mode; 379 struct vop_reg yrgb_ver_scl_mode; 380 struct vop_reg yrgb_hor_scl_mode; 381 struct vop_reg line_load_mode; 382 struct vop_reg cbcr_axi_gather_num; 383 struct vop_reg yrgb_axi_gather_num; 384 struct vop_reg vsd_cbcr_gt2; 385 struct vop_reg vsd_cbcr_gt4; 386 struct vop_reg vsd_yrgb_gt2; 387 struct vop_reg vsd_yrgb_gt4; 388 struct vop_reg bic_coe_sel; 389 struct vop_reg cbcr_axi_gather_en; 390 struct vop_reg yrgb_axi_gather_en; 391 struct vop_reg lb_mode; 392 }; 393 394 struct vop_scl_regs { 395 const struct vop_scl_extension *ext; 396 397 struct vop_reg scale_yrgb_x; 398 struct vop_reg scale_yrgb_y; 399 struct vop_reg scale_cbcr_x; 400 struct vop_reg scale_cbcr_y; 401 }; 402 403 struct vop_win { 404 const struct vop_scl_regs *scl; 405 406 struct vop_reg gate; 407 struct vop_reg enable; 408 struct vop_reg format; 409 struct vop_reg ymirror; 410 struct vop_reg rb_swap; 411 struct vop_reg act_info; 412 struct vop_reg dsp_info; 413 struct vop_reg dsp_st; 414 struct vop_reg yrgb_mst; 415 struct vop_reg uv_mst; 416 struct vop_reg yrgb_vir; 417 struct vop_reg uv_vir; 418 struct vop_reg alpha_mode; 419 struct vop_reg alpha_en; 420 421 struct vop_reg dst_alpha_ctl; 422 struct vop_reg src_alpha_ctl; 423 }; 424 425 struct vop_line_flag { 426 struct vop_reg line_flag_num[2]; 427 }; 428 429 struct vop_grf_ctrl { 430 struct vop_reg grf_dclk_inv; 431 }; 432 433 struct vop_csc_table { 434 const uint32_t *r2y_bt601; 435 const uint32_t *r2y_bt601_12_235; 436 const uint32_t *r2y_bt709; 437 const uint32_t *r2y_bt2020; 438 }; 439 440 struct vop_csc { 441 struct vop_reg y2r_en; 442 struct vop_reg r2r_en; 443 struct vop_reg r2y_en; 444 445 uint32_t y2r_offset; 446 uint32_t r2r_offset; 447 uint32_t r2y_offset; 448 }; 449 450 #define VOP_FEATURE_OUTPUT_10BIT BIT(0) 451 452 struct vop_data { 453 uint32_t version; 454 const struct vop_ctrl *ctrl; 455 const struct vop_win *win; 456 const struct vop_line_flag *line_flag; 457 const struct vop_grf_ctrl *grf_ctrl; 458 const struct vop_csc_table *csc_table; 459 const struct vop_csc *win_csc; 460 int win_offset; 461 int reg_len; 462 u64 feature; 463 struct vop_rect max_output; 464 }; 465 466 struct vop { 467 u32 *regsbak; 468 void *regs; 469 void *grf; 470 471 uint32_t version; 472 const struct vop_ctrl *ctrl; 473 const struct vop_win *win; 474 const struct vop_line_flag *line_flag; 475 const struct vop_grf_ctrl *grf_ctrl; 476 const struct vop_csc_table *csc_table; 477 const struct vop_csc *win_csc; 478 int win_offset; 479 480 struct gpio_desc mcu_rs_gpio; 481 }; 482 483 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 484 { 485 writel(v, vop->regs + offset); 486 vop->regsbak[offset >> 2] = v; 487 } 488 489 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 490 { 491 return readl(vop->regs + offset); 492 } 493 494 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 495 const struct vop_reg *reg) 496 { 497 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 498 } 499 500 static inline void vop_mask_write(struct vop *vop, uint32_t offset, 501 uint32_t mask, uint32_t shift, uint32_t v, 502 bool write_mask) 503 { 504 if (!mask) 505 return; 506 507 if (write_mask) { 508 v = ((v & mask) << shift) | (mask << (shift + 16)); 509 } else { 510 uint32_t cached_val = vop->regsbak[offset >> 2]; 511 512 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 513 vop->regsbak[offset >> 2] = v; 514 } 515 516 writel(v, vop->regs + offset); 517 } 518 519 static inline void vop_cfg_done(struct vop *vop) 520 { 521 VOP_CTRL_SET(vop, cfg_done, 1); 522 } 523 524 static inline void vop_grf_writel(struct vop *vop, struct vop_reg reg, u32 v) 525 { 526 u32 val = 0; 527 528 if (VOP_REG_SUPPORT(vop, reg)) { 529 val = (v << reg.shift) | (reg.mask << (reg.shift + 16)); 530 writel(val, vop->grf + reg.offset); 531 } 532 } 533 534 /** 535 * drm_format_horz_chroma_subsampling - get the horizontal chroma subsampling factor 536 * @format: pixel format (DRM_FORMAT_*) 537 * 538 * Returns: 539 * The horizontal chroma subsampling factor for the 540 * specified pixel format. 541 */ 542 static inline int drm_format_horz_chroma_subsampling(uint32_t format) 543 { 544 /* uboot only support RGB format */ 545 return 1; 546 } 547 548 /** 549 * drm_format_vert_chroma_subsampling - get the vertical chroma subsampling factor 550 * @format: pixel format (DRM_FORMAT_*) 551 * 552 * Returns: 553 * The vertical chroma subsampling factor for the 554 * specified pixel format. 555 */ 556 static inline int drm_format_vert_chroma_subsampling(uint32_t format) 557 { 558 /* uboot only support RGB format */ 559 return 1; 560 } 561 562 #endif 563