1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ROCKCHIP_VOP_H_ 8 #define _ROCKCHIP_VOP_H_ 9 #include "rockchip_display.h" 10 #include <asm/gpio.h> 11 12 13 #define VOP_REG_SUPPORT(vop, reg) \ 14 (reg.mask && \ 15 (!reg.major || \ 16 (reg.major == VOP_MAJOR(vop->version) && \ 17 reg.begin_minor <= VOP_MINOR(vop->version) && \ 18 reg.end_minor >= VOP_MINOR(vop->version)))) 19 20 #define VOP_WIN_SUPPORT(vop, win, name) \ 21 VOP_REG_SUPPORT(vop, win->name) 22 23 #define VOP_CTRL_SUPPORT(vop, name) \ 24 VOP_REG_SUPPORT(vop, vop->ctrl->name) 25 26 #define __REG_SET(x, off, mask, shift, v, write_mask) \ 27 vop_mask_write(x, off, mask, shift, v, write_mask) 28 29 #define _REG_SET(vop, name, off, reg, mask, v) \ 30 do { \ 31 if (VOP_REG_SUPPORT(vop, reg)) \ 32 __REG_SET(vop, off + reg.offset, mask, reg.shift, \ 33 v, reg.write_mask); \ 34 else \ 35 debug("Warning: not support "#name"\n"); \ 36 } while(0) 37 38 #define REG_SET(x, name, off, reg, v) \ 39 _REG_SET(x, name, off, reg, reg.mask, v) 40 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \ 41 _REG_SET(x, name, off, reg, reg.mask & mask, v) 42 43 #define VOP_WIN_SET(x, name, v) \ 44 REG_SET(x, name, x->win_offset, x->win->name, v) 45 #define VOP_WIN_SET_EXT(x, ext, name, v) \ 46 REG_SET(x, name, x->win_offset, x->win->ext->name, v) 47 #define VOP_SCL_SET(x, name, v) \ 48 REG_SET(x, name, x->win_offset, x->win->scl->name, v) 49 #define VOP_SCL_SET_EXT(x, name, v) \ 50 REG_SET(x, name, x->win_offset, x->win->scl->ext->name, v) 51 52 #define VOP_CTRL_SET(x, name, v) \ 53 REG_SET(x, name, 0, (x)->ctrl->name, v) 54 #define VOP_LINE_FLAG_SET(x, name, v) \ 55 REG_SET(x, name, 0, (x)->line_flag->name, v) 56 #define VOP_WIN_CSC_SET(x, name, v) \ 57 REG_SET(x, name, 0, (x)->win_csc->name, v) 58 59 #define VOP_CTRL_GET(x, name) \ 60 vop_read_reg(x, 0, &vop->ctrl->name) 61 62 #define VOP_WIN_GET(x, name) \ 63 vop_read_reg(x, vop->win->offset, &vop->win->name) 64 65 #define VOP_GRF_SET(vop, name, v) \ 66 do { \ 67 if (vop->grf_ctrl) { \ 68 vop_grf_writel(vop, vop->grf_ctrl->name, v); \ 69 } \ 70 } while (0) 71 72 #define CVBS_PAL_VDISPLAY 288 73 74 enum alpha_mode { 75 ALPHA_STRAIGHT, 76 ALPHA_INVERSE, 77 }; 78 79 enum global_blend_mode { 80 ALPHA_GLOBAL, 81 ALPHA_PER_PIX, 82 ALPHA_PER_PIX_GLOBAL, 83 }; 84 85 enum alpha_cal_mode { 86 ALPHA_SATURATION, 87 ALPHA_NO_SATURATION, 88 }; 89 90 enum color_mode { 91 ALPHA_SRC_PRE_MUL, 92 ALPHA_SRC_NO_PRE_MUL, 93 }; 94 95 enum factor_mode { 96 ALPHA_ZERO, 97 ALPHA_ONE, 98 ALPHA_SRC, 99 ALPHA_SRC_INVERSE, 100 ALPHA_SRC_GLOBAL, 101 }; 102 103 enum scale_mode { 104 SCALE_NONE = 0x0, 105 SCALE_UP = 0x1, 106 SCALE_DOWN = 0x2 107 }; 108 109 enum lb_mode { 110 LB_YUV_3840X5 = 0x0, 111 LB_YUV_2560X8 = 0x1, 112 LB_RGB_3840X2 = 0x2, 113 LB_RGB_2560X4 = 0x3, 114 LB_RGB_1920X5 = 0x4, 115 LB_RGB_1280X8 = 0x5 116 }; 117 118 enum sacle_up_mode { 119 SCALE_UP_BIL = 0x0, 120 SCALE_UP_BIC = 0x1 121 }; 122 123 enum scale_down_mode { 124 SCALE_DOWN_BIL = 0x0, 125 SCALE_DOWN_AVG = 0x1 126 }; 127 128 enum dither_down_mode { 129 RGB888_TO_RGB565 = 0x0, 130 RGB888_TO_RGB666 = 0x1 131 }; 132 133 enum dither_down_mode_sel { 134 DITHER_DOWN_ALLEGRO = 0x0, 135 DITHER_DOWN_FRC = 0x1 136 }; 137 138 enum vop_csc_format { 139 CSC_BT601L, 140 CSC_BT709L, 141 CSC_BT601F, 142 CSC_BT2020, 143 }; 144 145 #define DSP_BG_SWAP 0x1 146 #define DSP_RB_SWAP 0x2 147 #define DSP_RG_SWAP 0x4 148 #define DSP_DELTA_SWAP 0x8 149 150 #define PRE_DITHER_DOWN_EN(x) ((x) << 0) 151 #define DITHER_DOWN_EN(x) ((x) << 1) 152 #define DITHER_DOWN_MODE(x) ((x) << 2) 153 #define DITHER_DOWN_MODE_SEL(x) ((x) << 3) 154 155 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 156 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12 157 #define SCL_MAX_VSKIPLINES 4 158 #define MIN_SCL_FT_AFTER_VSKIP 1 159 160 #define VOP_PLANE_NO_SCALING BIT(16) 161 162 static inline uint16_t scl_cal_scale(int src, int dst, int shift) 163 { 164 return ((src * 2 - 3) << (shift - 1)) / (dst - 1); 165 } 166 167 static inline uint16_t scl_cal_scale2(int src, int dst) 168 { 169 return ((src - 1) << 12) / (dst - 1); 170 } 171 172 #define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12) 173 #define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16) 174 #define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16) 175 176 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h, 177 int vskiplines) 178 { 179 int act_height; 180 181 act_height = (src_h + vskiplines - 1) / vskiplines; 182 183 return GET_SCL_FT_BILI_DN(act_height, dst_h); 184 } 185 186 static inline enum scale_mode scl_get_scl_mode(int src, int dst) 187 { 188 if (src < dst) 189 return SCALE_UP; 190 else if (src > dst) 191 return SCALE_DOWN; 192 193 return SCALE_NONE; 194 } 195 196 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth) 197 { 198 uint32_t vskiplines; 199 200 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2) 201 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP) 202 break; 203 204 return vskiplines; 205 } 206 207 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv) 208 { 209 int lb_mode; 210 211 if (width > 2560) 212 lb_mode = LB_RGB_3840X2; 213 else if (width > 1920) 214 lb_mode = LB_RGB_2560X4; 215 else if (!is_yuv) 216 lb_mode = LB_RGB_1920X5; 217 else if (width > 1280) 218 lb_mode = LB_YUV_3840X5; 219 else 220 lb_mode = LB_YUV_2560X8; 221 222 return lb_mode; 223 } 224 225 struct vop_reg_data { 226 uint32_t offset; 227 uint32_t value; 228 }; 229 230 struct vop_reg { 231 uint32_t mask; 232 uint32_t offset:17; 233 uint32_t shift:5; 234 uint32_t begin_minor:4; 235 uint32_t end_minor:4; 236 uint32_t reserved:2; 237 uint32_t major:3; 238 uint32_t write_mask:1; 239 }; 240 241 struct vop_ctrl { 242 struct vop_reg standby; 243 struct vop_reg axi_outstanding_max_num; 244 struct vop_reg axi_max_outstanding_en; 245 struct vop_reg htotal_pw; 246 struct vop_reg hact_st_end; 247 struct vop_reg vtotal_pw; 248 struct vop_reg vact_st_end; 249 struct vop_reg vact_st_end_f1; 250 struct vop_reg vs_st_end_f1; 251 struct vop_reg hpost_st_end; 252 struct vop_reg vpost_st_end; 253 struct vop_reg vpost_st_end_f1; 254 struct vop_reg post_scl_factor; 255 struct vop_reg post_scl_ctrl; 256 struct vop_reg dsp_interlace; 257 struct vop_reg global_regdone_en; 258 struct vop_reg auto_gate_en; 259 struct vop_reg post_lb_mode; 260 struct vop_reg dsp_layer_sel; 261 struct vop_reg overlay_mode; 262 struct vop_reg core_dclk_div; 263 struct vop_reg dclk_ddr; 264 struct vop_reg p2i_en; 265 struct vop_reg hdmi_dclk_out_en; 266 struct vop_reg rgb_en; 267 struct vop_reg lvds_en; 268 struct vop_reg edp_en; 269 struct vop_reg hdmi_en; 270 struct vop_reg mipi_en; 271 struct vop_reg data01_swap; 272 struct vop_reg mipi_dual_channel_en; 273 struct vop_reg dp_en; 274 struct vop_reg dclk_pol; 275 struct vop_reg pin_pol; 276 struct vop_reg rgb_dclk_pol; 277 struct vop_reg rgb_pin_pol; 278 struct vop_reg lvds_dclk_pol; 279 struct vop_reg lvds_pin_pol; 280 struct vop_reg hdmi_dclk_pol; 281 struct vop_reg hdmi_pin_pol; 282 struct vop_reg edp_dclk_pol; 283 struct vop_reg edp_pin_pol; 284 struct vop_reg mipi_dclk_pol; 285 struct vop_reg mipi_pin_pol; 286 struct vop_reg dp_dclk_pol; 287 struct vop_reg dp_pin_pol; 288 289 struct vop_reg dither_up; 290 struct vop_reg dither_down; 291 292 struct vop_reg sw_dac_sel; 293 struct vop_reg tve_sw_mode; 294 struct vop_reg tve_dclk_pol; 295 struct vop_reg tve_dclk_en; 296 struct vop_reg sw_genlock; 297 struct vop_reg sw_uv_offset_en; 298 299 struct vop_reg dsp_out_yuv; 300 struct vop_reg dsp_data_swap; 301 struct vop_reg dsp_bg_swap; 302 struct vop_reg dsp_rb_swap; 303 struct vop_reg dsp_rg_swap; 304 struct vop_reg dsp_delta_swap; 305 struct vop_reg dsp_dummy_swap; 306 struct vop_reg dsp_ccir656_avg; 307 struct vop_reg dsp_black; 308 struct vop_reg dsp_blank; 309 struct vop_reg dsp_outzero; 310 struct vop_reg dsp_lut_en; 311 struct vop_reg update_gamma_lut; 312 313 struct vop_reg out_mode; 314 315 struct vop_reg xmirror; 316 struct vop_reg ymirror; 317 struct vop_reg dsp_background; 318 319 /* CABC */ 320 struct vop_reg cabc_total_num; 321 struct vop_reg cabc_config_mode; 322 struct vop_reg cabc_stage_up_mode; 323 struct vop_reg cabc_scale_cfg_value; 324 struct vop_reg cabc_scale_cfg_enable; 325 struct vop_reg cabc_global_dn_limit_en; 326 struct vop_reg cabc_lut_en; 327 struct vop_reg cabc_en; 328 struct vop_reg cabc_handle_en; 329 struct vop_reg cabc_stage_up; 330 struct vop_reg cabc_stage_down; 331 struct vop_reg cabc_global_dn; 332 struct vop_reg cabc_calc_pixel_num; 333 334 struct vop_reg win_gate[4]; 335 struct vop_reg win_channel[4]; 336 337 /* BCSH */ 338 struct vop_reg bcsh_brightness; 339 struct vop_reg bcsh_contrast; 340 struct vop_reg bcsh_sat_con; 341 struct vop_reg bcsh_sin_hue; 342 struct vop_reg bcsh_cos_hue; 343 struct vop_reg bcsh_r2y_csc_mode; 344 struct vop_reg bcsh_r2y_en; 345 struct vop_reg bcsh_y2r_csc_mode; 346 struct vop_reg bcsh_y2r_en; 347 struct vop_reg bcsh_color_bar; 348 struct vop_reg bcsh_out_mode; 349 struct vop_reg bcsh_en; 350 struct vop_reg reg_done_frm; 351 352 /* MCU OUTPUT */ 353 struct vop_reg mcu_pix_total; 354 struct vop_reg mcu_cs_pst; 355 struct vop_reg mcu_cs_pend; 356 struct vop_reg mcu_rw_pst; 357 struct vop_reg mcu_rw_pend; 358 struct vop_reg mcu_clk_sel; 359 struct vop_reg mcu_hold_mode; 360 struct vop_reg mcu_frame_st; 361 struct vop_reg mcu_rs; 362 struct vop_reg mcu_bypass; 363 struct vop_reg mcu_type; 364 struct vop_reg mcu_rw_bypass_port; 365 366 /* bt1120 */ 367 struct vop_reg bt1120_yc_swap; 368 struct vop_reg bt1120_en; 369 370 /* bt656 */ 371 struct vop_reg bt656_en; 372 373 struct vop_reg cfg_done; 374 }; 375 376 struct vop_scl_extension { 377 struct vop_reg cbcr_vsd_mode; 378 struct vop_reg cbcr_vsu_mode; 379 struct vop_reg cbcr_hsd_mode; 380 struct vop_reg cbcr_ver_scl_mode; 381 struct vop_reg cbcr_hor_scl_mode; 382 struct vop_reg yrgb_vsd_mode; 383 struct vop_reg yrgb_vsu_mode; 384 struct vop_reg yrgb_hsd_mode; 385 struct vop_reg yrgb_ver_scl_mode; 386 struct vop_reg yrgb_hor_scl_mode; 387 struct vop_reg line_load_mode; 388 struct vop_reg cbcr_axi_gather_num; 389 struct vop_reg yrgb_axi_gather_num; 390 struct vop_reg vsd_cbcr_gt2; 391 struct vop_reg vsd_cbcr_gt4; 392 struct vop_reg vsd_yrgb_gt2; 393 struct vop_reg vsd_yrgb_gt4; 394 struct vop_reg bic_coe_sel; 395 struct vop_reg cbcr_axi_gather_en; 396 struct vop_reg yrgb_axi_gather_en; 397 struct vop_reg lb_mode; 398 }; 399 400 struct vop_scl_regs { 401 const struct vop_scl_extension *ext; 402 403 struct vop_reg scale_yrgb_x; 404 struct vop_reg scale_yrgb_y; 405 struct vop_reg scale_cbcr_x; 406 struct vop_reg scale_cbcr_y; 407 }; 408 409 struct vop_win { 410 const struct vop_scl_regs *scl; 411 412 struct vop_reg gate; 413 struct vop_reg enable; 414 struct vop_reg format; 415 struct vop_reg interlace_read; 416 struct vop_reg ymirror; 417 struct vop_reg rb_swap; 418 struct vop_reg act_info; 419 struct vop_reg dsp_info; 420 struct vop_reg dsp_st; 421 struct vop_reg yrgb_mst; 422 struct vop_reg uv_mst; 423 struct vop_reg yrgb_vir; 424 struct vop_reg uv_vir; 425 struct vop_reg alpha_mode; 426 struct vop_reg alpha_en; 427 428 struct vop_reg dst_alpha_ctl; 429 struct vop_reg src_alpha_ctl; 430 }; 431 432 struct vop_line_flag { 433 struct vop_reg line_flag_num[2]; 434 }; 435 436 struct vop_grf_ctrl { 437 struct vop_reg grf_dclk_inv; 438 }; 439 440 struct vop_csc_table { 441 const uint32_t *r2y_bt601; 442 const uint32_t *r2y_bt601_12_235; 443 const uint32_t *r2y_bt709; 444 const uint32_t *r2y_bt2020; 445 }; 446 447 struct vop_csc { 448 struct vop_reg y2r_en; 449 struct vop_reg r2r_en; 450 struct vop_reg r2y_en; 451 452 uint32_t y2r_offset; 453 uint32_t r2r_offset; 454 uint32_t r2y_offset; 455 }; 456 457 #define VOP_FEATURE_OUTPUT_10BIT BIT(0) 458 459 struct vop_data { 460 uint32_t version; 461 const struct vop_ctrl *ctrl; 462 const struct vop_win *win; 463 const struct vop_line_flag *line_flag; 464 const struct vop_grf_ctrl *grf_ctrl; 465 const struct vop_csc_table *csc_table; 466 const struct vop_csc *win_csc; 467 int win_offset; 468 int reg_len; 469 u64 feature; 470 struct vop_rect max_output; 471 }; 472 473 struct vop { 474 u32 *regsbak; 475 void *regs; 476 void *grf; 477 478 uint32_t version; 479 const struct vop_ctrl *ctrl; 480 const struct vop_win *win; 481 const struct vop_line_flag *line_flag; 482 const struct vop_grf_ctrl *grf_ctrl; 483 const struct vop_csc_table *csc_table; 484 const struct vop_csc *win_csc; 485 int win_offset; 486 487 struct gpio_desc mcu_rs_gpio; 488 }; 489 490 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 491 { 492 writel(v, vop->regs + offset); 493 vop->regsbak[offset >> 2] = v; 494 } 495 496 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset) 497 { 498 return readl(vop->regs + offset); 499 } 500 501 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, 502 const struct vop_reg *reg) 503 { 504 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; 505 } 506 507 static inline void vop_mask_write(struct vop *vop, uint32_t offset, 508 uint32_t mask, uint32_t shift, uint32_t v, 509 bool write_mask) 510 { 511 if (!mask) 512 return; 513 514 if (write_mask) { 515 v = ((v & mask) << shift) | (mask << (shift + 16)); 516 } else { 517 uint32_t cached_val = vop->regsbak[offset >> 2]; 518 519 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 520 vop->regsbak[offset >> 2] = v; 521 } 522 523 writel(v, vop->regs + offset); 524 } 525 526 static inline void vop_cfg_done(struct vop *vop) 527 { 528 VOP_CTRL_SET(vop, cfg_done, 1); 529 } 530 531 static inline void vop_grf_writel(struct vop *vop, struct vop_reg reg, u32 v) 532 { 533 u32 val = 0; 534 535 if (VOP_REG_SUPPORT(vop, reg)) { 536 val = (v << reg.shift) | (reg.mask << (reg.shift + 16)); 537 writel(val, vop->grf + reg.offset); 538 } 539 } 540 541 /** 542 * drm_format_horz_chroma_subsampling - get the horizontal chroma subsampling factor 543 * @format: pixel format (DRM_FORMAT_*) 544 * 545 * Returns: 546 * The horizontal chroma subsampling factor for the 547 * specified pixel format. 548 */ 549 static inline int drm_format_horz_chroma_subsampling(uint32_t format) 550 { 551 /* uboot only support RGB format */ 552 return 1; 553 } 554 555 /** 556 * drm_format_vert_chroma_subsampling - get the vertical chroma subsampling factor 557 * @format: pixel format (DRM_FORMAT_*) 558 * 559 * Returns: 560 * The vertical chroma subsampling factor for the 561 * specified pixel format. 562 */ 563 static inline int drm_format_vert_chroma_subsampling(uint32_t format) 564 { 565 /* uboot only support RGB format */ 566 return 1; 567 } 568 569 #endif 570