1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Author: Guochun Huang <hero.huang@rock-chips.com> 7 */ 8 9 #include <drm/drm_mipi_dsi.h> 10 11 #include <config.h> 12 #include <common.h> 13 #include <errno.h> 14 #include <asm/unaligned.h> 15 #include <asm/io.h> 16 #include <asm/hardware.h> 17 #include <dm/device.h> 18 #include <dm/read.h> 19 #include <dm/of_access.h> 20 #include <regmap.h> 21 #include <syscon.h> 22 #include <asm/arch-rockchip/clock.h> 23 #include <linux/iopoll.h> 24 25 #include "rockchip_display.h" 26 #include "rockchip_crtc.h" 27 #include "rockchip_connector.h" 28 #include "rockchip_panel.h" 29 #include "rockchip_phy.h" 30 31 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) 32 33 #define DSI2_PWR_UP 0x000c 34 #define RESET 0 35 #define POWER_UP BIT(0) 36 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 37 #define DSI2_SOFT_RESET 0x0010 38 #define SYS_RSTN BIT(2) 39 #define PHY_RSTN BIT(1) 40 #define IPI_RSTN BIT(0) 41 #define INT_ST_MAIN 0x0014 42 #define DSI2_MODE_CTRL 0x0018 43 #define DSI2_MODE_STATUS 0x001c 44 #define DSI2_CORE_STATUS 0x0020 45 #define PRI_RD_DATA_AVAIL BIT(26) 46 #define PRI_FIFOS_NOT_EMPTY BIT(25) 47 #define PRI_BUSY BIT(24) 48 #define CRI_RD_DATA_AVAIL BIT(18) 49 #define CRT_FIFOS_NOT_EMPTY BIT(17) 50 #define CRI_BUSY BIT(16) 51 #define IPI_FIFOS_NOT_EMPTY BIT(9) 52 #define IPI_BUSY BIT(8) 53 #define CORE_FIFOS_NOT_EMPTY BIT(1) 54 #define CORE_BUSY BIT(0) 55 #define MANUAL_MODE_CFG 0x0024 56 #define MANUAL_MODE_EN BIT(0) 57 #define DSI2_TIMEOUT_HSTX_CFG 0x0048 58 #define TO_HSTX(x) UPDATE(x, 15, 0) 59 #define DSI2_TIMEOUT_HSTXRDY_CFG 0x004c 60 #define TO_HSTXRDY(x) UPDATE(x, 15, 0) 61 #define DSI2_TIMEOUT_LPRX_CFG 0x0050 62 #define TO_LPRXRDY(x) UPDATE(x, 15, 0) 63 #define DSI2_TIMEOUT_LPTXRDY_CFG 0x0054 64 #define TO_LPTXRDY(x) UPDATE(x, 15, 0) 65 #define DSI2_TIMEOUT_LPTXTRIG_CFG 0x0058 66 #define TO_LPTXTRIG(x) UPDATE(x, 15, 0) 67 #define DSI2_TIMEOUT_LPTXULPS_CFG 0x005c 68 #define TO_LPTXULPS(x) UPDATE(x, 15, 0) 69 #define DSI2_TIMEOUT_BTA_CFG 0x60 70 #define TO_BTA(x) UPDATE(x, 15, 0) 71 72 #define DSI2_PHY_MODE_CFG 0x0100 73 #define PPI_WIDTH(x) UPDATE(x, 9, 8) 74 #define PHY_LANES(x) UPDATE(x - 1, 5, 4) 75 #define PHY_TYPE(x) UPDATE(x, 0, 0) 76 #define DSI2_PHY_CLK_CFG 0X0104 77 #define PHY_LPTX_CLK_DIV(x) UPDATE(x, 12, 8) 78 #define NON_CONTINUOUS_CLK BIT(0) 79 #define DSI2_PHY_LP2HS_MAN_CFG 0x010c 80 #define PHY_LP2HS_TIME(x) UPDATE(x, 28, 0) 81 #define DSI2_PHY_HS2LP_MAN_CFG 0x0114 82 #define PHY_HS2LP_TIME(x) UPDATE(x, 28, 0) 83 #define DSI2_PHY_MAX_RD_T_MAN_CFG 0x011c 84 #define PHY_MAX_RD_TIME(x) UPDATE(x, 26, 0) 85 #define DSI2_PHY_ESC_CMD_T_MAN_CFG 0x0124 86 #define PHY_ESC_CMD_TIME(x) UPDATE(x, 28, 0) 87 #define DSI2_PHY_ESC_BYTE_T_MAN_CFG 0x012c 88 #define PHY_ESC_BYTE_TIME(x) UPDATE(x, 28, 0) 89 90 #define DSI2_PHY_IPI_RATIO_MAN_CFG 0x0134 91 #define PHY_IPI_RATIO(x) UPDATE(x, 21, 0) 92 #define DSI2_PHY_SYS_RATIO_MAN_CFG 0x013C 93 #define PHY_SYS_RATIO(x) UPDATE(x, 16, 0) 94 95 #define DSI2_DSI_GENERAL_CFG 0x0200 96 #define BTA_EN BIT(1) 97 #define EOTP_TX_EN BIT(0) 98 #define DSI2_DSI_VCID_CFG 0x0204 99 #define TX_VCID(x) UPDATE(x, 1, 0) 100 #define DSI2_DSI_SCRAMBLING_CFG 0x0208 101 #define SCRAMBLING_SEED(x) UPDATE(x, 31, 16) 102 #define SCRAMBLING_EN BIT(0) 103 #define DSI2_DSI_VID_TX_CFG 0x020c 104 #define LPDT_DISPLAY_CMD_EN BIT(20) 105 #define BLK_VFP_HS_EN BIT(14) 106 #define BLK_VBP_HS_EN BIT(13) 107 #define BLK_VSA_HS_EN BIT(12) 108 #define BLK_HFP_HS_EN BIT(6) 109 #define BLK_HBP_HS_EN BIT(5) 110 #define BLK_HSA_HS_EN BIT(4) 111 #define VID_MODE_TYPE(x) UPDATE(x, 1, 0) 112 #define DSI2_CRI_TX_HDR 0x02c0 113 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 114 #define DSI2_CRI_TX_PLD 0x02c4 115 #define DSI2_CRI_RX_HDR 0x02c8 116 #define DSI2_CRI_RX_PLD 0x02cc 117 118 #define DSI2_IPI_COLOR_MAN_CFG 0x0300 119 #define IPI_DEPTH(x) UPDATE(x, 7, 4) 120 #define IPI_DEPTH_5_6_5_BITS 0x02 121 #define IPI_DEPTH_6_BITS 0x03 122 #define IPI_DEPTH_8_BITS 0x05 123 #define IPI_DEPTH_10_BITS 0x06 124 #define IPI_FORMAT(x) UPDATE(x, 3, 0) 125 #define IPI_FORMAT_RGB 0x0 126 #define IPI_FORMAT_DSC 0x0b 127 #define DSI2_IPI_VID_HSA_MAN_CFG 0x0304 128 #define VID_HSA_TIME(x) UPDATE(x, 29, 0) 129 #define DSI2_IPI_VID_HBP_MAN_CFG 0x030c 130 #define VID_HBP_TIME(x) UPDATE(x, 29, 0) 131 #define DSI2_IPI_VID_HACT_MAN_CFG 0x0314 132 #define VID_HACT_TIME(x) UPDATE(x, 29, 0) 133 #define DSI2_IPI_VID_HLINE_MAN_CFG 0x031c 134 #define VID_HLINE_TIME(x) UPDATE(x, 29, 0) 135 #define DSI2_IPI_VID_VSA_MAN_CFG 0x0324 136 #define VID_VSA_LINES(x) UPDATE(x, 9, 0) 137 #define DSI2_IPI_VID_VBP_MAN_CFG 0X032C 138 #define VID_VBP_LINES(x) UPDATE(x, 9, 0) 139 #define DSI2_IPI_VID_VACT_MAN_CFG 0X0334 140 #define VID_VACT_LINES(x) UPDATE(x, 13, 0) 141 #define DSI2_IPI_VID_VFP_MAN_CFG 0X033C 142 #define VID_VFP_LINES(x) UPDATE(x, 9, 0) 143 #define DSI2_IPI_PIX_PKT_CFG 0x0344 144 #define MAX_PIX_PKT(x) UPDATE(x, 15, 0) 145 146 #define DSI2_INT_ST_PHY 0x0400 147 #define DSI2_INT_MASK_PHY 0x0404 148 #define DSI2_INT_ST_TO 0x0410 149 #define DSI2_INT_MASK_TO 0x0414 150 #define DSI2_INT_ST_ACK 0x0420 151 #define DSI2_INT_MASK_ACK 0x0424 152 #define DSI2_INT_ST_IPI 0x0430 153 #define DSI2_INT_MASK_IPI 0x0434 154 #define DSI2_INT_ST_FIFO 0x0440 155 #define DSI2_INT_MASK_FIFO 0x0444 156 #define DSI2_INT_ST_PRI 0x0450 157 #define DSI2_INT_MASK_PRI 0x0454 158 #define DSI2_INT_ST_CRI 0x0460 159 #define DSI2_INT_MASK_CRI 0x0464 160 #define DSI2_INT_FORCE_CRI 0x0468 161 #define DSI2_MAX_REGISGER DSI2_INT_FORCE_CRI 162 163 #define CMD_PKT_STATUS_TIMEOUT_US 1000 164 #define MODE_STATUS_TIMEOUT_US 20000 165 #define SYS_CLK 351000000LL 166 #define PSEC_PER_SEC 1000000000000LL 167 #define USEC_PER_SEC 1000000L 168 #define MSEC_PER_SEC 1000L 169 170 #define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 16) | ((lsb) << 8) | (msb)) 171 172 enum vid_mode_type { 173 VID_MODE_TYPE_NON_BURST_SYNC_PULSES, 174 VID_MODE_TYPE_NON_BURST_SYNC_EVENTS, 175 VID_MODE_TYPE_BURST, 176 }; 177 178 enum mode_ctrl { 179 IDLE_MODE, 180 AUTOCALC_MODE, 181 COMMAND_MODE, 182 VIDEO_MODE, 183 DATA_STREAM_MODE, 184 VIDE_TEST_MODE, 185 DATA_STREAM_TEST_MODE, 186 }; 187 188 enum grf_reg_fields { 189 TXREQCLKHS_EN, 190 GATING_EN, 191 IPI_SHUTDN, 192 IPI_COLORM, 193 IPI_COLOR_DEPTH, 194 IPI_FORMAT, 195 MAX_FIELDS, 196 }; 197 198 enum phy_type { 199 DPHY, 200 CPHY, 201 }; 202 203 enum ppi_width { 204 PPI_WIDTH_8_BITS, 205 PPI_WIDTH_16_BITS, 206 PPI_WIDTH_32_BITS, 207 }; 208 209 struct rockchip_cmd_header { 210 u8 data_type; 211 u8 delay_ms; 212 u8 payload_length; 213 }; 214 215 struct dw_mipi_dsi2_plat_data { 216 const u32 *dsi0_grf_reg_fields; 217 const u32 *dsi1_grf_reg_fields; 218 unsigned long long dphy_max_bit_rate_per_lane; 219 unsigned long long cphy_max_symbol_rate_per_lane; 220 }; 221 222 struct mipi_dcphy { 223 /* Non-SNPS PHY */ 224 struct rockchip_phy *phy; 225 226 u16 input_div; 227 u16 feedback_div; 228 }; 229 230 /** 231 * struct mipi_dphy_configure - MIPI D-PHY configuration set 232 * 233 * This structure is used to represent the configuration state of a 234 * MIPI D-PHY phy. 235 */ 236 struct mipi_dphy_configure { 237 unsigned int clk_miss; 238 unsigned int clk_post; 239 unsigned int clk_pre; 240 unsigned int clk_prepare; 241 unsigned int clk_settle; 242 unsigned int clk_term_en; 243 unsigned int clk_trail; 244 unsigned int clk_zero; 245 unsigned int d_term_en; 246 unsigned int eot; 247 unsigned int hs_exit; 248 unsigned int hs_prepare; 249 unsigned int hs_settle; 250 unsigned int hs_skip; 251 unsigned int hs_trail; 252 unsigned int hs_zero; 253 unsigned int init; 254 unsigned int lpx; 255 unsigned int ta_get; 256 unsigned int ta_go; 257 unsigned int ta_sure; 258 unsigned int wakeup; 259 unsigned long hs_clk_rate; 260 unsigned long lp_clk_rate; 261 unsigned char lanes; 262 }; 263 264 struct dw_mipi_dsi2 { 265 struct rockchip_connector connector; 266 struct udevice *dev; 267 void *base; 268 void *grf; 269 int id; 270 struct dw_mipi_dsi2 *master; 271 struct dw_mipi_dsi2 *slave; 272 bool prepared; 273 274 bool c_option; 275 bool dsc_enable; 276 bool scrambling_en; 277 unsigned int slice_width; 278 unsigned int slice_height; 279 u32 version_major; 280 u32 version_minor; 281 282 unsigned int lane_hs_rate; /* Kbps/Ksps per lane */ 283 u32 channel; 284 u32 lanes; 285 u32 format; 286 u32 mode_flags; 287 struct mipi_dcphy dcphy; 288 struct drm_display_mode mode; 289 bool data_swap; 290 291 struct mipi_dphy_configure mipi_dphy_cfg; 292 const struct dw_mipi_dsi2_plat_data *pdata; 293 struct drm_dsc_picture_parameter_set *pps; 294 }; 295 296 static inline void dsi_write(struct dw_mipi_dsi2 *dsi2, u32 reg, u32 val) 297 { 298 writel(val, dsi2->base + reg); 299 } 300 301 static inline u32 dsi_read(struct dw_mipi_dsi2 *dsi2, u32 reg) 302 { 303 return readl(dsi2->base + reg); 304 } 305 306 static inline void dsi_update_bits(struct dw_mipi_dsi2 *dsi2, 307 u32 reg, u32 mask, u32 val) 308 { 309 u32 orig, tmp; 310 311 orig = dsi_read(dsi2, reg); 312 tmp = orig & ~mask; 313 tmp |= val & mask; 314 dsi_write(dsi2, reg, tmp); 315 } 316 317 static void grf_field_write(struct dw_mipi_dsi2 *dsi2, enum grf_reg_fields index, 318 unsigned int val) 319 { 320 const u32 field = dsi2->id ? dsi2->pdata->dsi1_grf_reg_fields[index] : 321 dsi2->pdata->dsi0_grf_reg_fields[index]; 322 u16 reg; 323 u8 msb, lsb; 324 325 if (!field) 326 return; 327 328 reg = (field >> 16) & 0xffff; 329 lsb = (field >> 8) & 0xff; 330 msb = (field >> 0) & 0xff; 331 332 regmap_write(dsi2->grf, reg, GENMASK(msb, lsb) << 16 | val << lsb); 333 } 334 335 static unsigned long dw_mipi_dsi2_get_lane_rate(struct dw_mipi_dsi2 *dsi2) 336 { 337 const struct drm_display_mode *mode = &dsi2->mode; 338 u64 max_lane_rate, lane_rate; 339 unsigned int value; 340 int bpp, lanes; 341 u64 tmp; 342 343 max_lane_rate = (dsi2->c_option) ? 344 dsi2->pdata->cphy_max_symbol_rate_per_lane : 345 dsi2->pdata->dphy_max_bit_rate_per_lane; 346 347 /* 348 * optional override of the desired bandwidth 349 * High-Speed mode: Differential and terminated: 80Mbps ~ 4500 Mbps 350 */ 351 value = dev_read_u32_default(dsi2->dev, "rockchip,lane-rate", 0); 352 if (value >= 80000 && value <= 4500000) 353 return value * MSEC_PER_SEC; 354 else if (value >= 80 && value <= 4500) 355 return value * USEC_PER_SEC; 356 357 bpp = mipi_dsi_pixel_format_to_bpp(dsi2->format); 358 if (bpp < 0) 359 bpp = 24; 360 361 lanes = dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes; 362 tmp = (u64)mode->crtc_clock * 1000 * bpp; 363 do_div(tmp, lanes); 364 365 if (dsi2->c_option) 366 tmp = DIV_ROUND_CLOSEST(tmp * 100, 228); 367 368 /* set BW a little larger only in video burst mode in 369 * consideration of the protocol overhead and HS mode 370 * switching to BLLP mode, take 1 / 0.9, since Mbps must 371 * big than bandwidth of RGB 372 */ 373 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { 374 tmp *= 10; 375 do_div(tmp, 9); 376 } 377 378 if (tmp > max_lane_rate) 379 lane_rate = max_lane_rate; 380 else 381 lane_rate = tmp; 382 383 return lane_rate; 384 } 385 386 static int cri_fifos_wait_avail(struct dw_mipi_dsi2 *dsi2) 387 { 388 u32 sts, mask; 389 int ret; 390 391 mask = CRI_BUSY | CRT_FIFOS_NOT_EMPTY; 392 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 393 sts, !(sts & mask), 394 CMD_PKT_STATUS_TIMEOUT_US); 395 if (ret < 0) { 396 printf("command interface is busy: 0x%x\n", sts); 397 return ret; 398 } 399 400 return 0; 401 } 402 403 static int dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 *dsi2, 404 const struct mipi_dsi_msg *msg) 405 { 406 u8 *payload = msg->rx_buf; 407 u8 data_type; 408 u16 wc; 409 int i, j, ret, len = msg->rx_len; 410 unsigned int vrefresh = drm_mode_vrefresh(&dsi2->mode); 411 u32 val; 412 413 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 414 val, val & CRI_RD_DATA_AVAIL, 415 DIV_ROUND_UP(1000000, vrefresh)); 416 if (ret) { 417 printf("CRI has no available read data\n"); 418 return ret; 419 } 420 421 val = dsi_read(dsi2, DSI2_CRI_RX_HDR); 422 data_type = val & 0x3f; 423 424 if (mipi_dsi_packet_format_is_short(data_type)) { 425 for (i = 0; i < len && i < 2; i++) 426 payload[i] = (val >> (8 * (i + 1))) & 0xff; 427 428 return 0; 429 } 430 431 wc = (val >> 8) & 0xffff; 432 /* Receive payload */ 433 for (i = 0; i < len && i < wc; i += 4) { 434 val = dsi_read(dsi2, DSI2_CRI_RX_PLD); 435 for (j = 0; j < 4 && j + i < len && j + i < wc; j++) 436 payload[i + j] = val >> (8 * j); 437 } 438 439 return 0; 440 } 441 442 static ssize_t dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 *dsi2, 443 const struct mipi_dsi_msg *msg) 444 { 445 struct mipi_dsi_packet packet; 446 int ret; 447 int val; 448 u32 mode; 449 450 dsi_update_bits(dsi2, DSI2_DSI_VID_TX_CFG, LPDT_DISPLAY_CMD_EN, 451 msg->flags & MIPI_DSI_MSG_USE_LPM ? 452 LPDT_DISPLAY_CMD_EN : 0); 453 454 /* create a packet to the DSI protocol */ 455 ret = mipi_dsi_create_packet(&packet, msg); 456 if (ret) { 457 printf("failed to create packet: %d\n", ret); 458 return ret; 459 } 460 461 /* check cri interface is not busy */ 462 ret = cri_fifos_wait_avail(dsi2); 463 if (ret) 464 return ret; 465 466 /* Send payload */ 467 while (DIV_ROUND_UP(packet.payload_length, 4)) { 468 if (packet.payload_length < 4) { 469 /* send residu payload */ 470 val = 0; 471 memcpy(&val, packet.payload, packet.payload_length); 472 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 473 packet.payload_length = 0; 474 } else { 475 val = get_unaligned_le32(packet.payload); 476 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 477 packet.payload += 4; 478 packet.payload_length -= 4; 479 } 480 } 481 482 /* Send packet header */ 483 mode = CMD_TX_MODE(msg->flags & MIPI_DSI_MSG_USE_LPM ? 1 : 0); 484 val = get_unaligned_le32(packet.header); 485 dsi_write(dsi2, DSI2_CRI_TX_HDR, mode | val); 486 487 ret = cri_fifos_wait_avail(dsi2); 488 if (ret) 489 return ret; 490 491 if (msg->rx_len) { 492 ret = dw_mipi_dsi2_read_from_fifo(dsi2, msg); 493 if (ret < 0) 494 return ret; 495 } 496 497 if (dsi2->slave) { 498 ret = dw_mipi_dsi2_transfer(dsi2->slave, msg); 499 if (ret < 0) 500 return ret; 501 } 502 503 return msg->rx_len ? msg->rx_len : msg->tx_len; 504 } 505 506 static void dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 *dsi2) 507 { 508 u32 val, color_depth; 509 510 switch (dsi2->format) { 511 case MIPI_DSI_FMT_RGB666: 512 case MIPI_DSI_FMT_RGB666_PACKED: 513 color_depth = IPI_DEPTH_6_BITS; 514 break; 515 case MIPI_DSI_FMT_RGB565: 516 color_depth = IPI_DEPTH_5_6_5_BITS; 517 break; 518 case MIPI_DSI_FMT_RGB888: 519 default: 520 color_depth = IPI_DEPTH_8_BITS; 521 break; 522 } 523 524 val = IPI_DEPTH(color_depth) | 525 IPI_FORMAT(dsi2->dsc_enable ? IPI_FORMAT_DSC : IPI_FORMAT_RGB); 526 dsi_write(dsi2, DSI2_IPI_COLOR_MAN_CFG, val); 527 grf_field_write(dsi2, IPI_COLOR_DEPTH, color_depth); 528 529 if (dsi2->dsc_enable) 530 grf_field_write(dsi2, IPI_FORMAT, IPI_FORMAT_DSC); 531 } 532 533 static void dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 *dsi2) 534 { 535 struct drm_display_mode *mode = &dsi2->mode; 536 u32 hline, hsa, hbp, hact; 537 u64 hline_time, hsa_time, hbp_time, hact_time, tmp; 538 u64 pixel_clk, phy_hs_clk; 539 u32 vact, vsa, vfp, vbp; 540 u16 val; 541 542 if (dsi2->slave || dsi2->master) 543 val = mode->hdisplay / 2; 544 else 545 val = mode->hdisplay; 546 547 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val)); 548 549 dw_mipi_dsi2_ipi_color_coding_cfg(dsi2); 550 551 /* 552 * if the controller is intended to operate in data stream mode, 553 * no more steps are required. 554 */ 555 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) 556 return; 557 558 vact = mode->vdisplay; 559 vsa = mode->vsync_end - mode->vsync_start; 560 vfp = mode->vsync_start - mode->vdisplay; 561 vbp = mode->vtotal - mode->vsync_end; 562 hact = mode->hdisplay; 563 hsa = mode->hsync_end - mode->hsync_start; 564 hbp = mode->htotal - mode->hsync_end; 565 hline = mode->htotal; 566 567 pixel_clk = mode->crtc_clock * MSEC_PER_SEC; 568 569 if (dsi2->c_option) 570 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 571 else 572 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 573 574 tmp = hsa * phy_hs_clk; 575 hsa_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 576 dsi_write(dsi2, DSI2_IPI_VID_HSA_MAN_CFG, VID_HSA_TIME(hsa_time)); 577 578 tmp = hbp * phy_hs_clk; 579 hbp_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 580 dsi_write(dsi2, DSI2_IPI_VID_HBP_MAN_CFG, VID_HBP_TIME(hbp_time)); 581 582 tmp = hact * phy_hs_clk; 583 hact_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 584 dsi_write(dsi2, DSI2_IPI_VID_HACT_MAN_CFG, VID_HACT_TIME(hact_time)); 585 586 tmp = hline * phy_hs_clk; 587 hline_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 588 dsi_write(dsi2, DSI2_IPI_VID_HLINE_MAN_CFG, VID_HLINE_TIME(hline_time)); 589 590 dsi_write(dsi2, DSI2_IPI_VID_VSA_MAN_CFG, VID_VSA_LINES(vsa)); 591 dsi_write(dsi2, DSI2_IPI_VID_VBP_MAN_CFG, VID_VBP_LINES(vbp)); 592 dsi_write(dsi2, DSI2_IPI_VID_VACT_MAN_CFG, VID_VACT_LINES(vact)); 593 dsi_write(dsi2, DSI2_IPI_VID_VFP_MAN_CFG, VID_VFP_LINES(vfp)); 594 } 595 596 static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2) 597 { 598 u32 val = 0, mode; 599 int ret; 600 601 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) 602 val |= BLK_HFP_HS_EN; 603 604 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) 605 val |= BLK_HBP_HS_EN; 606 607 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HSA) 608 val |= BLK_HSA_HS_EN; 609 610 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 611 val |= VID_MODE_TYPE_BURST; 612 else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 613 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 614 else 615 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 616 617 dsi_write(dsi2, DSI2_DSI_VID_TX_CFG, val); 618 619 dsi_write(dsi2, DSI2_MODE_CTRL, VIDEO_MODE); 620 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 621 mode, mode & VIDEO_MODE, 622 MODE_STATUS_TIMEOUT_US); 623 if (ret < 0) 624 printf("failed to enter video mode\n"); 625 } 626 627 static void dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 *dsi2) 628 { 629 u32 mode; 630 int ret; 631 632 dsi_write(dsi2, DSI2_MODE_CTRL, DATA_STREAM_MODE); 633 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 634 mode, mode & DATA_STREAM_MODE, 635 MODE_STATUS_TIMEOUT_US); 636 if (ret < 0) 637 printf("failed to enter data stream mode\n"); 638 } 639 640 static void dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 *dsi2) 641 { 642 u32 mode; 643 int ret; 644 645 dsi_write(dsi2, DSI2_MODE_CTRL, COMMAND_MODE); 646 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 647 mode, mode & COMMAND_MODE, 648 MODE_STATUS_TIMEOUT_US); 649 if (ret < 0) 650 printf("failed to enter cmd mode\n"); 651 } 652 653 static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2) 654 { 655 dw_mipi_dsi2_ipi_set(dsi2); 656 657 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO) 658 dw_mipi_dsi2_set_vid_mode(dsi2); 659 else 660 dw_mipi_dsi2_set_data_stream_mode(dsi2); 661 662 if (dsi2->slave) 663 dw_mipi_dsi2_enable(dsi2->slave); 664 } 665 666 static void dw_mipi_dsi2_disable(struct dw_mipi_dsi2 *dsi2) 667 { 668 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, 0); 669 dw_mipi_dsi2_set_cmd_mode(dsi2); 670 671 if (dsi2->slave) 672 dw_mipi_dsi2_disable(dsi2->slave); 673 } 674 675 static void dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 *dsi2) 676 { 677 if (!dsi2->prepared) 678 return; 679 680 dsi_write(dsi2, DSI2_PWR_UP, RESET); 681 682 if (dsi2->dcphy.phy) 683 rockchip_phy_power_off(dsi2->dcphy.phy); 684 685 dsi2->prepared = false; 686 687 if (dsi2->slave) 688 dw_mipi_dsi2_post_disable(dsi2->slave); 689 } 690 691 static int dw_mipi_dsi2_connector_pre_init(struct rockchip_connector *conn, 692 struct display_state *state) 693 { 694 struct connector_state *conn_state = &state->conn_state; 695 696 conn_state->type = DRM_MODE_CONNECTOR_DSI; 697 698 return 0; 699 } 700 701 static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2) 702 { 703 struct udevice *dev = NULL; 704 struct rockchip_cmd_header *header; 705 struct drm_dsc_picture_parameter_set *pps = NULL; 706 u8 *dsc_packed_pps; 707 const void *data; 708 int len; 709 int ret; 710 711 ret = device_find_first_child(dsi2->dev, &dev); 712 if (ret) 713 return ret; 714 715 dsi2->c_option = dev_read_bool(dev, "phy-c-option"); 716 dsi2->scrambling_en = dev_read_bool(dev, "scrambling-enable"); 717 dsi2->dsc_enable = dev_read_bool(dev, "compressed-data"); 718 719 if (dsi2->slave) { 720 dsi2->slave->c_option = dsi2->c_option; 721 dsi2->slave->scrambling_en = dsi2->scrambling_en; 722 dsi2->slave->dsc_enable = dsi2->dsc_enable; 723 } 724 725 dsi2->slice_width = dev_read_u32_default(dev, "slice-width", 0); 726 dsi2->slice_height = dev_read_u32_default(dev, "slice-height", 0); 727 dsi2->version_major = dev_read_u32_default(dev, "version-major", 0); 728 dsi2->version_minor = dev_read_u32_default(dev, "version-minor", 0); 729 730 data = dev_read_prop(dev, "panel-init-sequence", &len); 731 if (!data) 732 return -EINVAL; 733 734 while (len > sizeof(*header)) { 735 header = (struct rockchip_cmd_header *)data; 736 data += sizeof(*header); 737 len -= sizeof(*header); 738 739 if (header->payload_length > len) 740 return -EINVAL; 741 742 if (header->data_type == MIPI_DSI_PICTURE_PARAMETER_SET) { 743 dsc_packed_pps = calloc(1, header->payload_length); 744 if (!dsc_packed_pps) 745 return -ENOMEM; 746 747 memcpy(dsc_packed_pps, data, header->payload_length); 748 pps = (struct drm_dsc_picture_parameter_set *)dsc_packed_pps; 749 break; 750 } 751 752 data += header->payload_length; 753 len -= header->payload_length; 754 } 755 756 dsi2->pps = pps; 757 758 return 0; 759 } 760 761 static int dw_mipi_dsi2_connector_init(struct rockchip_connector *conn, struct display_state *state) 762 { 763 struct connector_state *conn_state = &state->conn_state; 764 struct crtc_state *cstate = &state->crtc_state; 765 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 766 struct rockchip_phy *phy = NULL; 767 struct udevice *phy_dev; 768 struct udevice *dev; 769 int ret; 770 771 772 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dsi2->id); 773 dsi2->dcphy.phy = conn->phy; 774 775 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 776 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 777 conn_state->output_if |= 778 dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0; 779 780 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) { 781 conn_state->output_flags |= ROCKCHIP_OUTPUT_MIPI_DS_MODE; 782 conn_state->hold_mode = true; 783 } 784 785 if (dsi2->lanes > 4) { 786 ret = uclass_get_device_by_name(UCLASS_DISPLAY, 787 "dsi@fde30000", 788 &dev); 789 if (ret) 790 return ret; 791 792 dsi2->slave = dev_get_priv(dev); 793 if (!dsi2->slave) 794 return -ENODEV; 795 796 dsi2->slave->master = dsi2; 797 dsi2->lanes /= 2; 798 dsi2->slave->lanes = dsi2->lanes; 799 dsi2->slave->format = dsi2->format; 800 dsi2->slave->mode_flags = dsi2->mode_flags; 801 dsi2->slave->channel = dsi2->channel; 802 conn_state->output_flags |= 803 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; 804 if (dsi2->data_swap) 805 conn_state->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP; 806 807 conn_state->output_if |= VOP_OUTPUT_IF_MIPI1; 808 809 ret = uclass_get_device_by_phandle(UCLASS_PHY, dev, 810 "phys", &phy_dev); 811 if (ret) 812 return -ENODEV; 813 814 phy = (struct rockchip_phy *)dev_get_driver_data(phy_dev); 815 if (!phy) 816 return -ENODEV; 817 818 dsi2->slave->dcphy.phy = phy; 819 if (phy->funcs && phy->funcs->init) 820 return phy->funcs->init(phy); 821 } 822 823 dw_mipi_dsi2_get_dsc_params_from_sink(dsi2); 824 825 if (dsi2->dsc_enable) { 826 cstate->dsc_enable = 1; 827 cstate->dsc_sink_cap.version_major = dsi2->version_major; 828 cstate->dsc_sink_cap.version_minor = dsi2->version_minor; 829 cstate->dsc_sink_cap.slice_width = dsi2->slice_width; 830 cstate->dsc_sink_cap.slice_height = dsi2->slice_height; 831 /* only can support rgb888 panel now */ 832 cstate->dsc_sink_cap.target_bits_per_pixel_x16 = 8 << 4; 833 cstate->dsc_sink_cap.native_420 = 0; 834 memcpy(&cstate->pps, dsi2->pps, sizeof(struct drm_dsc_picture_parameter_set)); 835 } 836 837 return 0; 838 } 839 840 /* 841 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived 842 * from the valid ranges specified in Section 6.9, Table 14, Page 41 843 * of the D-PHY specification (v2.1). 844 */ 845 int mipi_dphy_get_default_config(unsigned long long hs_clk_rate, 846 struct mipi_dphy_configure *cfg) 847 { 848 unsigned long long ui; 849 850 if (!cfg) 851 return -EINVAL; 852 853 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); 854 do_div(ui, hs_clk_rate); 855 856 cfg->clk_miss = 0; 857 cfg->clk_post = 60000 + 52 * ui; 858 cfg->clk_pre = 8000; 859 cfg->clk_prepare = 38000; 860 cfg->clk_settle = 95000; 861 cfg->clk_term_en = 0; 862 cfg->clk_trail = 60000; 863 cfg->clk_zero = 262000; 864 cfg->d_term_en = 0; 865 cfg->eot = 0; 866 cfg->hs_exit = 100000; 867 cfg->hs_prepare = 40000 + 4 * ui; 868 cfg->hs_zero = 105000 + 6 * ui; 869 cfg->hs_settle = 85000 + 6 * ui; 870 cfg->hs_skip = 40000; 871 872 /* 873 * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40) 874 * contains this formula as: 875 * 876 * T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui) 877 * 878 * where n = 1 for forward-direction HS mode and n = 4 for reverse- 879 * direction HS mode. There's only one setting and this function does 880 * not parameterize on anything other that ui, so this code will 881 * assumes that reverse-direction HS mode is supported and uses n = 4. 882 */ 883 cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui); 884 885 cfg->init = 100; 886 cfg->lpx = 60000; 887 cfg->ta_get = 5 * cfg->lpx; 888 cfg->ta_go = 4 * cfg->lpx; 889 cfg->ta_sure = 2 * cfg->lpx; 890 cfg->wakeup = 1000; 891 892 return 0; 893 } 894 895 static void dw_mipi_dsi2_set_hs_clk(struct dw_mipi_dsi2 *dsi2, unsigned long rate) 896 { 897 mipi_dphy_get_default_config(rate, &dsi2->mipi_dphy_cfg); 898 899 if (!dsi2->c_option) 900 rockchip_phy_set_mode(dsi2->dcphy.phy, PHY_MODE_MIPI_DPHY); 901 902 rate = rockchip_phy_set_pll(dsi2->dcphy.phy, rate); 903 dsi2->lane_hs_rate = DIV_ROUND_CLOSEST(rate, MSEC_PER_SEC); 904 } 905 906 static void dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 *dsi2) 907 { 908 dsi_write(dsi2, DSI2_SOFT_RESET, 0X0); 909 udelay(100); 910 dsi_write(dsi2, DSI2_SOFT_RESET, SYS_RSTN | PHY_RSTN | IPI_RSTN); 911 } 912 913 static void 914 dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 *dsi2, u32 mode) 915 { 916 /* 917 * select controller work in Manual mode 918 * Manual: MANUAL_MODE_EN 919 * Automatic: 0 920 */ 921 dsi_write(dsi2, MANUAL_MODE_CFG, mode); 922 } 923 924 static void dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 *dsi2) 925 { 926 u32 val = 0; 927 928 /* PPI width is fixed to 16 bits in DCPHY */ 929 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes); 930 val |= PHY_TYPE(dsi2->c_option ? CPHY : DPHY); 931 dsi_write(dsi2, DSI2_PHY_MODE_CFG, val); 932 } 933 934 static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2) 935 { 936 u32 sys_clk = SYS_CLK / USEC_PER_SEC; 937 u32 esc_clk_div; 938 u32 val = 0; 939 940 if (dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 941 val |= NON_CONTINUOUS_CLK; 942 943 /* The Escape clock ranges from 1MHz to 20MHz. */ 944 esc_clk_div = DIV_ROUND_UP(sys_clk, 20 * 2); 945 val |= PHY_LPTX_CLK_DIV(esc_clk_div); 946 947 dsi_write(dsi2, DSI2_PHY_CLK_CFG, val); 948 } 949 950 static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2) 951 { 952 struct drm_display_mode *mode = &dsi2->mode; 953 u64 pixel_clk, ipi_clk, phy_hsclk, tmp; 954 955 /* 956 * in DPHY mode, the phy_hstx_clk is exactly 1/16 the Lane high-speed 957 * data rate; In CPHY mode, the phy_hstx_clk is exactly 1/7 the trio 958 * high speed symbol rate. 959 */ 960 if (dsi2->c_option) 961 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 962 963 else 964 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 965 966 /* IPI_RATIO_MAN_CFG = PHY_HSTX_CLK / IPI_CLK */ 967 pixel_clk = mode->crtc_clock * MSEC_PER_SEC; 968 ipi_clk = pixel_clk / 4; 969 970 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, ipi_clk); 971 dsi_write(dsi2, DSI2_PHY_IPI_RATIO_MAN_CFG, PHY_IPI_RATIO(tmp)); 972 973 /* SYS_RATIO_MAN_CFG = MIPI_DCPHY_HSCLK_Freq / SYS_CLK */ 974 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, SYS_CLK); 975 dsi_write(dsi2, DSI2_PHY_SYS_RATIO_MAN_CFG, PHY_SYS_RATIO(tmp)); 976 } 977 978 static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2) 979 { 980 struct mipi_dphy_configure *cfg = &dsi2->mipi_dphy_cfg; 981 unsigned long long tmp, ui; 982 unsigned long long hstx_clk; 983 984 hstx_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 985 986 ui = ALIGN(PSEC_PER_SEC, hstx_clk); 987 do_div(ui, hstx_clk); 988 989 /* PHY_LP2HS_TIME = (TLPX + THS-PREPARE + THS-ZERO) / Tphy_hstx_clk */ 990 tmp = cfg->lpx + cfg->hs_prepare + cfg->hs_zero; 991 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 992 dsi_write(dsi2, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(tmp)); 993 994 /* PHY_HS2LP_TIME = (THS-TRAIL + THS-EXIT) / Tphy_hstx_clk */ 995 tmp = cfg->hs_trail + cfg->hs_exit; 996 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 997 dsi_write(dsi2, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(tmp)); 998 } 999 1000 static void dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 *dsi2) 1001 { 1002 dw_mipi_dsi2_phy_mode_cfg(dsi2); 1003 dw_mipi_dsi2_phy_clk_mode_cfg(dsi2); 1004 dw_mipi_dsi2_phy_ratio_cfg(dsi2); 1005 dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(dsi2); 1006 1007 /* phy configuration 8 - 10 */ 1008 } 1009 1010 static void dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 *dsi2) 1011 { 1012 u32 val; 1013 1014 val = BTA_EN | EOTP_TX_EN; 1015 1016 if (dsi2->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 1017 val &= ~EOTP_TX_EN; 1018 1019 dsi_write(dsi2, DSI2_DSI_GENERAL_CFG, val); 1020 dsi_write(dsi2, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel)); 1021 1022 if (dsi2->scrambling_en) 1023 dsi_write(dsi2, DSI2_DSI_SCRAMBLING_CFG, SCRAMBLING_EN); 1024 } 1025 1026 static void dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 *dsi2, bool enable) 1027 { 1028 if (enable) { 1029 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x1); 1030 dsi_write(dsi2, DSI2_INT_MASK_TO, 0xf); 1031 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x1); 1032 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x1); 1033 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x1); 1034 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x1); 1035 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x1); 1036 } else { 1037 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x0); 1038 dsi_write(dsi2, DSI2_INT_MASK_TO, 0x0); 1039 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x0); 1040 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x0); 1041 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x0); 1042 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x0); 1043 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x0); 1044 }; 1045 } 1046 1047 static void mipi_dcphy_power_on(struct dw_mipi_dsi2 *dsi2) 1048 { 1049 if (!dsi2->dcphy.phy) 1050 return; 1051 1052 rockchip_phy_power_on(dsi2->dcphy.phy); 1053 } 1054 1055 static void dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 *dsi2) 1056 { 1057 if (dsi2->prepared) 1058 return; 1059 1060 dw_mipi_dsi2_host_softrst(dsi2); 1061 dsi_write(dsi2, DSI2_PWR_UP, RESET); 1062 1063 dw_mipi_dsi2_work_mode(dsi2, MANUAL_MODE_EN); 1064 dw_mipi_dsi2_phy_init(dsi2); 1065 dw_mipi_dsi2_tx_option_set(dsi2); 1066 dw_mipi_dsi2_irq_enable(dsi2, 0); 1067 mipi_dcphy_power_on(dsi2); 1068 dsi_write(dsi2, DSI2_PWR_UP, POWER_UP); 1069 dw_mipi_dsi2_set_cmd_mode(dsi2); 1070 1071 dsi2->prepared = true; 1072 1073 if (dsi2->slave) 1074 dw_mipi_dsi2_pre_enable(dsi2->slave); 1075 } 1076 1077 static int dw_mipi_dsi2_connector_prepare(struct rockchip_connector *conn, 1078 struct display_state *state) 1079 { 1080 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1081 struct connector_state *conn_state = &state->conn_state; 1082 unsigned long lane_rate; 1083 1084 memcpy(&dsi2->mode, &conn_state->mode, sizeof(struct drm_display_mode)); 1085 if (dsi2->slave) 1086 memcpy(&dsi2->slave->mode, &dsi2->mode, 1087 sizeof(struct drm_display_mode)); 1088 1089 lane_rate = dw_mipi_dsi2_get_lane_rate(dsi2); 1090 if (dsi2->dcphy.phy) 1091 dw_mipi_dsi2_set_hs_clk(dsi2, lane_rate); 1092 1093 if (dsi2->slave && dsi2->slave->dcphy.phy) 1094 dw_mipi_dsi2_set_hs_clk(dsi2->slave, lane_rate); 1095 1096 printf("final DSI-Link bandwidth: %u %s x %d\n", 1097 dsi2->lane_hs_rate, dsi2->c_option ? "Ksps" : "Kbps", 1098 dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes); 1099 1100 dw_mipi_dsi2_pre_enable(dsi2); 1101 1102 return 0; 1103 } 1104 1105 static void dw_mipi_dsi2_connector_unprepare(struct rockchip_connector *conn, 1106 struct display_state *state) 1107 { 1108 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1109 1110 dw_mipi_dsi2_post_disable(dsi2); 1111 } 1112 1113 static int dw_mipi_dsi2_connector_enable(struct rockchip_connector *conn, 1114 struct display_state *state) 1115 { 1116 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1117 1118 dw_mipi_dsi2_enable(dsi2); 1119 1120 return 0; 1121 } 1122 1123 static int dw_mipi_dsi2_connector_disable(struct rockchip_connector *conn, 1124 struct display_state *state) 1125 { 1126 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1127 1128 dw_mipi_dsi2_disable(dsi2); 1129 1130 return 0; 1131 } 1132 1133 static int dw_mipi_dsi2_connector_mode_valid(struct rockchip_connector *conn, 1134 struct display_state *state) 1135 { 1136 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1137 struct connector_state *conn_state = &state->conn_state; 1138 u8 min_pixels = dsi2->slave ? 8 : 4; 1139 struct videomode vm; 1140 1141 drm_display_mode_to_videomode(&conn_state->mode, &vm); 1142 1143 /* 1144 * the minimum region size (HSA,HBP,HACT,HFP) is 4 pixels 1145 * which is the ip known issues and limitations. 1146 */ 1147 if (!(vm.hsync_len < min_pixels || vm.hback_porch < min_pixels || 1148 vm.hfront_porch < min_pixels || vm.hactive < min_pixels)) 1149 return MODE_OK; 1150 1151 if (vm.hsync_len < min_pixels) 1152 vm.hsync_len = min_pixels; 1153 1154 if (vm.hback_porch < min_pixels) 1155 vm.hback_porch = min_pixels; 1156 1157 if (vm.hfront_porch < min_pixels) 1158 vm.hfront_porch = min_pixels; 1159 1160 if (vm.hactive < min_pixels) 1161 vm.hactive = min_pixels; 1162 1163 drm_display_mode_from_videomode(&vm, &conn_state->mode); 1164 1165 return MODE_OK; 1166 } 1167 1168 static const struct rockchip_connector_funcs dw_mipi_dsi2_connector_funcs = { 1169 .pre_init = dw_mipi_dsi2_connector_pre_init, 1170 .init = dw_mipi_dsi2_connector_init, 1171 .prepare = dw_mipi_dsi2_connector_prepare, 1172 .unprepare = dw_mipi_dsi2_connector_unprepare, 1173 .enable = dw_mipi_dsi2_connector_enable, 1174 .disable = dw_mipi_dsi2_connector_disable, 1175 .mode_valid = dw_mipi_dsi2_connector_mode_valid, 1176 }; 1177 1178 static int dw_mipi_dsi2_probe(struct udevice *dev) 1179 { 1180 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(dev); 1181 const struct dw_mipi_dsi2_plat_data *pdata = 1182 (const struct dw_mipi_dsi2_plat_data *)dev_get_driver_data(dev); 1183 struct udevice *syscon; 1184 int id, ret; 1185 1186 dsi2->base = dev_read_addr_ptr(dev); 1187 1188 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1189 &syscon); 1190 if (!ret) { 1191 dsi2->grf = syscon_get_regmap(syscon); 1192 if (!dsi2->grf) 1193 return -ENODEV; 1194 } 1195 1196 id = of_alias_get_id(ofnode_to_np(dev->node), "dsi"); 1197 if (id < 0) 1198 id = 0; 1199 1200 dsi2->dev = dev; 1201 dsi2->pdata = pdata; 1202 dsi2->id = id; 1203 dsi2->data_swap = dev_read_bool(dsi2->dev, "rockchip,data-swap"); 1204 1205 rockchip_connector_bind(&dsi2->connector, dev, id, &dw_mipi_dsi2_connector_funcs, NULL, 1206 DRM_MODE_CONNECTOR_DSI); 1207 1208 return 0; 1209 } 1210 1211 static const u32 rk3588_dsi0_grf_reg_fields[MAX_FIELDS] = { 1212 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0000, 11, 11), 1213 [GATING_EN] = GRF_REG_FIELD(0x0000, 10, 10), 1214 [IPI_SHUTDN] = GRF_REG_FIELD(0x0000, 9, 9), 1215 [IPI_COLORM] = GRF_REG_FIELD(0x0000, 8, 8), 1216 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0000, 4, 7), 1217 [IPI_FORMAT] = GRF_REG_FIELD(0x0000, 0, 3), 1218 }; 1219 1220 static const u32 rk3588_dsi1_grf_reg_fields[MAX_FIELDS] = { 1221 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0004, 11, 11), 1222 [GATING_EN] = GRF_REG_FIELD(0x0004, 10, 10), 1223 [IPI_SHUTDN] = GRF_REG_FIELD(0x0004, 9, 9), 1224 [IPI_COLORM] = GRF_REG_FIELD(0x0004, 8, 8), 1225 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0004, 4, 7), 1226 [IPI_FORMAT] = GRF_REG_FIELD(0x0004, 0, 3), 1227 }; 1228 1229 static const struct dw_mipi_dsi2_plat_data rk3588_mipi_dsi2_plat_data = { 1230 .dsi0_grf_reg_fields = rk3588_dsi0_grf_reg_fields, 1231 .dsi1_grf_reg_fields = rk3588_dsi1_grf_reg_fields, 1232 .dphy_max_bit_rate_per_lane = 4500000000ULL, 1233 .cphy_max_symbol_rate_per_lane = 2000000000ULL, 1234 }; 1235 1236 static const struct udevice_id dw_mipi_dsi2_ids[] = { 1237 { 1238 .compatible = "rockchip,rk3588-mipi-dsi2", 1239 .data = (ulong)&rk3588_mipi_dsi2_plat_data, 1240 }, 1241 {} 1242 }; 1243 1244 static ssize_t dw_mipi_dsi2_host_transfer(struct mipi_dsi_host *host, 1245 const struct mipi_dsi_msg *msg) 1246 { 1247 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1248 1249 return dw_mipi_dsi2_transfer(dsi2, msg); 1250 } 1251 1252 static int dw_mipi_dsi2_host_attach(struct mipi_dsi_host *host, 1253 struct mipi_dsi_device *device) 1254 { 1255 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1256 1257 if (device->lanes < 1 || device->lanes > 8) 1258 return -EINVAL; 1259 1260 dsi2->lanes = device->lanes; 1261 dsi2->channel = device->channel; 1262 dsi2->format = device->format; 1263 dsi2->mode_flags = device->mode_flags; 1264 1265 return 0; 1266 } 1267 1268 static const struct mipi_dsi_host_ops dw_mipi_dsi2_host_ops = { 1269 .attach = dw_mipi_dsi2_host_attach, 1270 .transfer = dw_mipi_dsi2_host_transfer, 1271 }; 1272 1273 static int dw_mipi_dsi2_bind(struct udevice *dev) 1274 { 1275 struct mipi_dsi_host *host = dev_get_platdata(dev); 1276 1277 host->dev = dev; 1278 host->ops = &dw_mipi_dsi2_host_ops; 1279 1280 return dm_scan_fdt_dev(dev); 1281 } 1282 1283 static int dw_mipi_dsi2_child_post_bind(struct udevice *dev) 1284 { 1285 struct mipi_dsi_host *host = dev_get_platdata(dev->parent); 1286 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1287 char name[20]; 1288 1289 sprintf(name, "%s.%d", host->dev->name, device->channel); 1290 device_set_name(dev, name); 1291 1292 device->dev = dev; 1293 device->host = host; 1294 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4); 1295 device->format = dev_read_u32_default(dev, "dsi,format", 1296 MIPI_DSI_FMT_RGB888); 1297 device->mode_flags = dev_read_u32_default(dev, "dsi,flags", 1298 MIPI_DSI_MODE_VIDEO | 1299 MIPI_DSI_MODE_VIDEO_BURST | 1300 MIPI_DSI_MODE_VIDEO_HBP | 1301 MIPI_DSI_MODE_LPM | 1302 MIPI_DSI_MODE_EOT_PACKET); 1303 device->channel = dev_read_u32_default(dev, "reg", 0); 1304 1305 return 0; 1306 } 1307 1308 static int dw_mipi_dsi2_child_pre_probe(struct udevice *dev) 1309 { 1310 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1311 int ret; 1312 1313 ret = mipi_dsi_attach(device); 1314 if (ret) { 1315 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret); 1316 return ret; 1317 } 1318 1319 return 0; 1320 } 1321 1322 U_BOOT_DRIVER(dw_mipi_dsi2) = { 1323 .name = "dw_mipi_dsi2", 1324 .id = UCLASS_DISPLAY, 1325 .of_match = dw_mipi_dsi2_ids, 1326 .probe = dw_mipi_dsi2_probe, 1327 .bind = dw_mipi_dsi2_bind, 1328 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi2), 1329 .per_child_platdata_auto_alloc_size = sizeof(struct mipi_dsi_device), 1330 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_host), 1331 .child_post_bind = dw_mipi_dsi2_child_post_bind, 1332 .child_pre_probe = dw_mipi_dsi2_child_pre_probe, 1333 }; 1334