1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Author: Guochun Huang <hero.huang@rock-chips.com> 7 */ 8 9 #include <drm/drm_mipi_dsi.h> 10 11 #include <config.h> 12 #include <common.h> 13 #include <errno.h> 14 #include <asm/unaligned.h> 15 #include <asm/io.h> 16 #include <asm/hardware.h> 17 #include <dm/device.h> 18 #include <dm/read.h> 19 #include <dm/of_access.h> 20 #include <regmap.h> 21 #include <syscon.h> 22 #include <asm/arch-rockchip/clock.h> 23 #include <linux/iopoll.h> 24 25 #include "rockchip_display.h" 26 #include "rockchip_crtc.h" 27 #include "rockchip_connector.h" 28 #include "rockchip_panel.h" 29 #include "rockchip_phy.h" 30 31 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) 32 33 #define DSI2_PWR_UP 0x000c 34 #define RESET 0 35 #define POWER_UP BIT(0) 36 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 37 #define DSI2_SOFT_RESET 0x0010 38 #define SYS_RSTN BIT(2) 39 #define PHY_RSTN BIT(1) 40 #define IPI_RSTN BIT(0) 41 #define INT_ST_MAIN 0x0014 42 #define DSI2_MODE_CTRL 0x0018 43 #define DSI2_MODE_STATUS 0x001c 44 #define DSI2_CORE_STATUS 0x0020 45 #define PRI_RD_DATA_AVAIL BIT(26) 46 #define PRI_FIFOS_NOT_EMPTY BIT(25) 47 #define PRI_BUSY BIT(24) 48 #define CRI_RD_DATA_AVAIL BIT(18) 49 #define CRT_FIFOS_NOT_EMPTY BIT(17) 50 #define CRI_BUSY BIT(16) 51 #define IPI_FIFOS_NOT_EMPTY BIT(9) 52 #define IPI_BUSY BIT(8) 53 #define CORE_FIFOS_NOT_EMPTY BIT(1) 54 #define CORE_BUSY BIT(0) 55 #define MANUAL_MODE_CFG 0x0024 56 #define MANUAL_MODE_EN BIT(0) 57 #define DSI2_TIMEOUT_HSTX_CFG 0x0048 58 #define TO_HSTX(x) UPDATE(x, 15, 0) 59 #define DSI2_TIMEOUT_HSTXRDY_CFG 0x004c 60 #define TO_HSTXRDY(x) UPDATE(x, 15, 0) 61 #define DSI2_TIMEOUT_LPRX_CFG 0x0050 62 #define TO_LPRXRDY(x) UPDATE(x, 15, 0) 63 #define DSI2_TIMEOUT_LPTXRDY_CFG 0x0054 64 #define TO_LPTXRDY(x) UPDATE(x, 15, 0) 65 #define DSI2_TIMEOUT_LPTXTRIG_CFG 0x0058 66 #define TO_LPTXTRIG(x) UPDATE(x, 15, 0) 67 #define DSI2_TIMEOUT_LPTXULPS_CFG 0x005c 68 #define TO_LPTXULPS(x) UPDATE(x, 15, 0) 69 #define DSI2_TIMEOUT_BTA_CFG 0x60 70 #define TO_BTA(x) UPDATE(x, 15, 0) 71 72 #define DSI2_PHY_MODE_CFG 0x0100 73 #define PPI_WIDTH(x) UPDATE(x, 9, 8) 74 #define PHY_LANES(x) UPDATE(x - 1, 5, 4) 75 #define PHY_TYPE(x) UPDATE(x, 0, 0) 76 #define DSI2_PHY_CLK_CFG 0X0104 77 #define PHY_LPTX_CLK_DIV(x) UPDATE(x, 12, 8) 78 #define NON_CONTINUOUS_CLK BIT(0) 79 #define DSI2_PHY_LP2HS_MAN_CFG 0x010c 80 #define PHY_LP2HS_TIME(x) UPDATE(x, 28, 0) 81 #define DSI2_PHY_HS2LP_MAN_CFG 0x0114 82 #define PHY_HS2LP_TIME(x) UPDATE(x, 28, 0) 83 #define DSI2_PHY_MAX_RD_T_MAN_CFG 0x011c 84 #define PHY_MAX_RD_TIME(x) UPDATE(x, 26, 0) 85 #define DSI2_PHY_ESC_CMD_T_MAN_CFG 0x0124 86 #define PHY_ESC_CMD_TIME(x) UPDATE(x, 28, 0) 87 #define DSI2_PHY_ESC_BYTE_T_MAN_CFG 0x012c 88 #define PHY_ESC_BYTE_TIME(x) UPDATE(x, 28, 0) 89 90 #define DSI2_PHY_IPI_RATIO_MAN_CFG 0x0134 91 #define PHY_IPI_RATIO(x) UPDATE(x, 21, 0) 92 #define DSI2_PHY_SYS_RATIO_MAN_CFG 0x013C 93 #define PHY_SYS_RATIO(x) UPDATE(x, 16, 0) 94 95 #define DSI2_DSI_GENERAL_CFG 0x0200 96 #define BTA_EN BIT(1) 97 #define EOTP_TX_EN BIT(0) 98 #define DSI2_DSI_VCID_CFG 0x0204 99 #define TX_VCID(x) UPDATE(x, 1, 0) 100 #define DSI2_DSI_SCRAMBLING_CFG 0x0208 101 #define SCRAMBLING_SEED(x) UPDATE(x, 31, 16) 102 #define SCRAMBLING_EN BIT(0) 103 #define DSI2_DSI_VID_TX_CFG 0x020c 104 #define LPDT_DISPLAY_CMD_EN BIT(20) 105 #define BLK_VFP_HS_EN BIT(14) 106 #define BLK_VBP_HS_EN BIT(13) 107 #define BLK_VSA_HS_EN BIT(12) 108 #define BLK_HFP_HS_EN BIT(6) 109 #define BLK_HBP_HS_EN BIT(5) 110 #define BLK_HSA_HS_EN BIT(4) 111 #define VID_MODE_TYPE(x) UPDATE(x, 1, 0) 112 #define DSI2_CRI_TX_HDR 0x02c0 113 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 114 #define DSI2_CRI_TX_PLD 0x02c4 115 #define DSI2_CRI_RX_HDR 0x02c8 116 #define DSI2_CRI_RX_PLD 0x02cc 117 118 #define DSI2_IPI_COLOR_MAN_CFG 0x0300 119 #define IPI_DEPTH(x) UPDATE(x, 7, 4) 120 #define IPI_DEPTH_5_6_5_BITS 0x02 121 #define IPI_DEPTH_6_BITS 0x03 122 #define IPI_DEPTH_8_BITS 0x05 123 #define IPI_DEPTH_10_BITS 0x06 124 #define IPI_FORMAT(x) UPDATE(x, 3, 0) 125 #define IPI_FORMAT_RGB 0x0 126 #define IPI_FORMAT_DSC 0x0b 127 #define DSI2_IPI_VID_HSA_MAN_CFG 0x0304 128 #define VID_HSA_TIME(x) UPDATE(x, 29, 0) 129 #define DSI2_IPI_VID_HBP_MAN_CFG 0x030c 130 #define VID_HBP_TIME(x) UPDATE(x, 29, 0) 131 #define DSI2_IPI_VID_HACT_MAN_CFG 0x0314 132 #define VID_HACT_TIME(x) UPDATE(x, 29, 0) 133 #define DSI2_IPI_VID_HLINE_MAN_CFG 0x031c 134 #define VID_HLINE_TIME(x) UPDATE(x, 29, 0) 135 #define DSI2_IPI_VID_VSA_MAN_CFG 0x0324 136 #define VID_VSA_LINES(x) UPDATE(x, 9, 0) 137 #define DSI2_IPI_VID_VBP_MAN_CFG 0X032C 138 #define VID_VBP_LINES(x) UPDATE(x, 9, 0) 139 #define DSI2_IPI_VID_VACT_MAN_CFG 0X0334 140 #define VID_VACT_LINES(x) UPDATE(x, 13, 0) 141 #define DSI2_IPI_VID_VFP_MAN_CFG 0X033C 142 #define VID_VFP_LINES(x) UPDATE(x, 9, 0) 143 #define DSI2_IPI_PIX_PKT_CFG 0x0344 144 #define MAX_PIX_PKT(x) UPDATE(x, 15, 0) 145 146 #define DSI2_INT_ST_PHY 0x0400 147 #define DSI2_INT_MASK_PHY 0x0404 148 #define DSI2_INT_ST_TO 0x0410 149 #define DSI2_INT_MASK_TO 0x0414 150 #define DSI2_INT_ST_ACK 0x0420 151 #define DSI2_INT_MASK_ACK 0x0424 152 #define DSI2_INT_ST_IPI 0x0430 153 #define DSI2_INT_MASK_IPI 0x0434 154 #define DSI2_INT_ST_FIFO 0x0440 155 #define DSI2_INT_MASK_FIFO 0x0444 156 #define DSI2_INT_ST_PRI 0x0450 157 #define DSI2_INT_MASK_PRI 0x0454 158 #define DSI2_INT_ST_CRI 0x0460 159 #define DSI2_INT_MASK_CRI 0x0464 160 #define DSI2_INT_FORCE_CRI 0x0468 161 #define DSI2_MAX_REGISGER DSI2_INT_FORCE_CRI 162 163 #define CMD_PKT_STATUS_TIMEOUT_US 1000 164 #define MODE_STATUS_TIMEOUT_US 20000 165 #define SYS_CLK 351000000LL 166 #define PSEC_PER_SEC 1000000000000LL 167 #define USEC_PER_SEC 1000000L 168 #define MSEC_PER_SEC 1000L 169 170 #define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 16) | ((lsb) << 8) | (msb)) 171 172 enum vid_mode_type { 173 VID_MODE_TYPE_NON_BURST_SYNC_PULSES, 174 VID_MODE_TYPE_NON_BURST_SYNC_EVENTS, 175 VID_MODE_TYPE_BURST, 176 }; 177 178 enum mode_ctrl { 179 IDLE_MODE, 180 AUTOCALC_MODE, 181 COMMAND_MODE, 182 VIDEO_MODE, 183 DATA_STREAM_MODE, 184 VIDE_TEST_MODE, 185 DATA_STREAM_TEST_MODE, 186 }; 187 188 enum grf_reg_fields { 189 TXREQCLKHS_EN, 190 GATING_EN, 191 IPI_SHUTDN, 192 IPI_COLORM, 193 IPI_COLOR_DEPTH, 194 IPI_FORMAT, 195 MAX_FIELDS, 196 }; 197 198 enum phy_type { 199 DPHY, 200 CPHY, 201 }; 202 203 enum ppi_width { 204 PPI_WIDTH_8_BITS, 205 PPI_WIDTH_16_BITS, 206 PPI_WIDTH_32_BITS, 207 }; 208 209 struct rockchip_cmd_header { 210 u8 data_type; 211 u8 delay_ms; 212 u8 payload_length; 213 }; 214 215 struct dw_mipi_dsi2_plat_data { 216 const u32 *dsi0_grf_reg_fields; 217 const u32 *dsi1_grf_reg_fields; 218 unsigned long long dphy_max_bit_rate_per_lane; 219 unsigned long long cphy_max_symbol_rate_per_lane; 220 }; 221 222 struct mipi_dcphy { 223 /* Non-SNPS PHY */ 224 struct rockchip_phy *phy; 225 226 u16 input_div; 227 u16 feedback_div; 228 }; 229 230 /** 231 * struct mipi_dphy_configure - MIPI D-PHY configuration set 232 * 233 * This structure is used to represent the configuration state of a 234 * MIPI D-PHY phy. 235 */ 236 struct mipi_dphy_configure { 237 unsigned int clk_miss; 238 unsigned int clk_post; 239 unsigned int clk_pre; 240 unsigned int clk_prepare; 241 unsigned int clk_settle; 242 unsigned int clk_term_en; 243 unsigned int clk_trail; 244 unsigned int clk_zero; 245 unsigned int d_term_en; 246 unsigned int eot; 247 unsigned int hs_exit; 248 unsigned int hs_prepare; 249 unsigned int hs_settle; 250 unsigned int hs_skip; 251 unsigned int hs_trail; 252 unsigned int hs_zero; 253 unsigned int init; 254 unsigned int lpx; 255 unsigned int ta_get; 256 unsigned int ta_go; 257 unsigned int ta_sure; 258 unsigned int wakeup; 259 unsigned long hs_clk_rate; 260 unsigned long lp_clk_rate; 261 unsigned char lanes; 262 }; 263 264 struct dw_mipi_dsi2 { 265 struct udevice *dev; 266 void *base; 267 void *grf; 268 int id; 269 struct dw_mipi_dsi2 *master; 270 struct dw_mipi_dsi2 *slave; 271 bool prepared; 272 273 bool c_option; 274 bool dsc_enable; 275 bool scrambling_en; 276 unsigned int slice_width; 277 unsigned int slice_height; 278 u32 version_major; 279 u32 version_minor; 280 281 unsigned int lane_hs_rate; /* Kbps/Ksps per lane */ 282 u32 channel; 283 u32 lanes; 284 u32 format; 285 u32 mode_flags; 286 struct mipi_dcphy dcphy; 287 struct drm_display_mode mode; 288 bool data_swap; 289 290 struct mipi_dphy_configure mipi_dphy_cfg; 291 const struct dw_mipi_dsi2_plat_data *pdata; 292 struct drm_dsc_picture_parameter_set *pps; 293 }; 294 295 static inline void dsi_write(struct dw_mipi_dsi2 *dsi2, u32 reg, u32 val) 296 { 297 writel(val, dsi2->base + reg); 298 } 299 300 static inline u32 dsi_read(struct dw_mipi_dsi2 *dsi2, u32 reg) 301 { 302 return readl(dsi2->base + reg); 303 } 304 305 static inline void dsi_update_bits(struct dw_mipi_dsi2 *dsi2, 306 u32 reg, u32 mask, u32 val) 307 { 308 u32 orig, tmp; 309 310 orig = dsi_read(dsi2, reg); 311 tmp = orig & ~mask; 312 tmp |= val & mask; 313 dsi_write(dsi2, reg, tmp); 314 } 315 316 static void grf_field_write(struct dw_mipi_dsi2 *dsi2, enum grf_reg_fields index, 317 unsigned int val) 318 { 319 const u32 field = dsi2->id ? dsi2->pdata->dsi1_grf_reg_fields[index] : 320 dsi2->pdata->dsi0_grf_reg_fields[index]; 321 u16 reg; 322 u8 msb, lsb; 323 324 if (!field) 325 return; 326 327 reg = (field >> 16) & 0xffff; 328 lsb = (field >> 8) & 0xff; 329 msb = (field >> 0) & 0xff; 330 331 regmap_write(dsi2->grf, reg, GENMASK(msb, lsb) << 16 | val << lsb); 332 } 333 334 static unsigned long dw_mipi_dsi2_get_lane_rate(struct dw_mipi_dsi2 *dsi2) 335 { 336 const struct drm_display_mode *mode = &dsi2->mode; 337 u64 max_lane_rate, lane_rate; 338 unsigned int value; 339 int bpp, lanes; 340 u64 tmp; 341 342 max_lane_rate = (dsi2->c_option) ? 343 dsi2->pdata->cphy_max_symbol_rate_per_lane : 344 dsi2->pdata->dphy_max_bit_rate_per_lane; 345 346 /* 347 * optional override of the desired bandwidth 348 * High-Speed mode: Differential and terminated: 80Mbps ~ 4500 Mbps 349 */ 350 value = dev_read_u32_default(dsi2->dev, "rockchip,lane-rate", 0); 351 if (value >= 80000 && value <= 4500000) 352 return value * MSEC_PER_SEC; 353 else if (value >= 80 && value <= 4500) 354 return value * USEC_PER_SEC; 355 356 bpp = mipi_dsi_pixel_format_to_bpp(dsi2->format); 357 if (bpp < 0) 358 bpp = 24; 359 360 lanes = dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes; 361 tmp = (u64)mode->crtc_clock * 1000 * bpp; 362 do_div(tmp, lanes); 363 364 if (dsi2->c_option) 365 tmp = DIV_ROUND_CLOSEST(tmp * 100, 228); 366 367 /* set BW a little larger only in video burst mode in 368 * consideration of the protocol overhead and HS mode 369 * switching to BLLP mode, take 1 / 0.9, since Mbps must 370 * big than bandwidth of RGB 371 */ 372 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { 373 tmp *= 10; 374 do_div(tmp, 9); 375 } 376 377 if (tmp > max_lane_rate) 378 lane_rate = max_lane_rate; 379 else 380 lane_rate = tmp; 381 382 return lane_rate; 383 } 384 385 static int cri_fifos_wait_avail(struct dw_mipi_dsi2 *dsi2) 386 { 387 u32 sts, mask; 388 int ret; 389 390 mask = CRI_BUSY | CRT_FIFOS_NOT_EMPTY; 391 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 392 sts, !(sts & mask), 393 CMD_PKT_STATUS_TIMEOUT_US); 394 if (ret < 0) { 395 printf("command interface is busy: 0x%x\n", sts); 396 return ret; 397 } 398 399 return 0; 400 } 401 402 static int dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 *dsi2, 403 const struct mipi_dsi_msg *msg) 404 { 405 u8 *payload = msg->rx_buf; 406 u8 data_type; 407 u16 wc; 408 int i, j, ret, len = msg->rx_len; 409 unsigned int vrefresh = drm_mode_vrefresh(&dsi2->mode); 410 u32 val; 411 412 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 413 val, val & CRI_RD_DATA_AVAIL, 414 DIV_ROUND_UP(1000000, vrefresh)); 415 if (ret) { 416 printf("CRI has no available read data\n"); 417 return ret; 418 } 419 420 val = dsi_read(dsi2, DSI2_CRI_RX_HDR); 421 data_type = val & 0x3f; 422 423 if (mipi_dsi_packet_format_is_short(data_type)) { 424 for (i = 0; i < len && i < 2; i++) 425 payload[i] = (val >> (8 * (i + 1))) & 0xff; 426 427 return 0; 428 } 429 430 wc = (val >> 8) & 0xffff; 431 /* Receive payload */ 432 for (i = 0; i < len && i < wc; i += 4) { 433 val = dsi_read(dsi2, DSI2_CRI_RX_PLD); 434 for (j = 0; j < 4 && j + i < len && j + i < wc; j++) 435 payload[i + j] = val >> (8 * j); 436 } 437 438 return 0; 439 } 440 441 static ssize_t dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 *dsi2, 442 const struct mipi_dsi_msg *msg) 443 { 444 struct mipi_dsi_packet packet; 445 int ret; 446 int val; 447 u32 mode; 448 449 dsi_update_bits(dsi2, DSI2_DSI_VID_TX_CFG, LPDT_DISPLAY_CMD_EN, 450 msg->flags & MIPI_DSI_MSG_USE_LPM ? 451 LPDT_DISPLAY_CMD_EN : 0); 452 453 /* create a packet to the DSI protocol */ 454 ret = mipi_dsi_create_packet(&packet, msg); 455 if (ret) { 456 printf("failed to create packet: %d\n", ret); 457 return ret; 458 } 459 460 /* check cri interface is not busy */ 461 ret = cri_fifos_wait_avail(dsi2); 462 if (ret) 463 return ret; 464 465 /* Send payload */ 466 while (DIV_ROUND_UP(packet.payload_length, 4)) { 467 if (packet.payload_length < 4) { 468 /* send residu payload */ 469 val = 0; 470 memcpy(&val, packet.payload, packet.payload_length); 471 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 472 packet.payload_length = 0; 473 } else { 474 val = get_unaligned_le32(packet.payload); 475 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 476 packet.payload += 4; 477 packet.payload_length -= 4; 478 } 479 } 480 481 /* Send packet header */ 482 mode = CMD_TX_MODE(msg->flags & MIPI_DSI_MSG_USE_LPM ? 1 : 0); 483 val = get_unaligned_le32(packet.header); 484 dsi_write(dsi2, DSI2_CRI_TX_HDR, mode | val); 485 486 ret = cri_fifos_wait_avail(dsi2); 487 if (ret) 488 return ret; 489 490 if (msg->rx_len) { 491 ret = dw_mipi_dsi2_read_from_fifo(dsi2, msg); 492 if (ret < 0) 493 return ret; 494 } 495 496 if (dsi2->slave) { 497 ret = dw_mipi_dsi2_transfer(dsi2->slave, msg); 498 if (ret < 0) 499 return ret; 500 } 501 502 return msg->rx_len ? msg->rx_len : msg->tx_len; 503 } 504 505 static void dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 *dsi2) 506 { 507 u32 val, color_depth; 508 509 switch (dsi2->format) { 510 case MIPI_DSI_FMT_RGB666: 511 case MIPI_DSI_FMT_RGB666_PACKED: 512 color_depth = IPI_DEPTH_6_BITS; 513 break; 514 case MIPI_DSI_FMT_RGB565: 515 color_depth = IPI_DEPTH_5_6_5_BITS; 516 break; 517 case MIPI_DSI_FMT_RGB888: 518 default: 519 color_depth = IPI_DEPTH_8_BITS; 520 break; 521 } 522 523 val = IPI_DEPTH(color_depth) | 524 IPI_FORMAT(dsi2->dsc_enable ? IPI_FORMAT_DSC : IPI_FORMAT_RGB); 525 dsi_write(dsi2, DSI2_IPI_COLOR_MAN_CFG, val); 526 grf_field_write(dsi2, IPI_COLOR_DEPTH, color_depth); 527 528 if (dsi2->dsc_enable) 529 grf_field_write(dsi2, IPI_FORMAT, IPI_FORMAT_DSC); 530 } 531 532 static void dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 *dsi2) 533 { 534 struct drm_display_mode *mode = &dsi2->mode; 535 u32 hline, hsa, hbp, hact; 536 u64 hline_time, hsa_time, hbp_time, hact_time, tmp; 537 u64 pixel_clk, phy_hs_clk; 538 u32 vact, vsa, vfp, vbp; 539 u16 val; 540 541 if (dsi2->slave || dsi2->master) 542 val = mode->hdisplay / 2; 543 else 544 val = mode->hdisplay; 545 546 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val)); 547 548 dw_mipi_dsi2_ipi_color_coding_cfg(dsi2); 549 550 /* 551 * if the controller is intended to operate in data stream mode, 552 * no more steps are required. 553 */ 554 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) 555 return; 556 557 vact = mode->vdisplay; 558 vsa = mode->vsync_end - mode->vsync_start; 559 vfp = mode->vsync_start - mode->vdisplay; 560 vbp = mode->vtotal - mode->vsync_end; 561 hact = mode->hdisplay; 562 hsa = mode->hsync_end - mode->hsync_start; 563 hbp = mode->htotal - mode->hsync_end; 564 hline = mode->htotal; 565 566 pixel_clk = mode->crtc_clock * MSEC_PER_SEC; 567 568 if (dsi2->c_option) 569 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 570 else 571 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 572 573 tmp = hsa * phy_hs_clk; 574 hsa_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 575 dsi_write(dsi2, DSI2_IPI_VID_HSA_MAN_CFG, VID_HSA_TIME(hsa_time)); 576 577 tmp = hbp * phy_hs_clk; 578 hbp_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 579 dsi_write(dsi2, DSI2_IPI_VID_HBP_MAN_CFG, VID_HBP_TIME(hbp_time)); 580 581 tmp = hact * phy_hs_clk; 582 hact_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 583 dsi_write(dsi2, DSI2_IPI_VID_HACT_MAN_CFG, VID_HACT_TIME(hact_time)); 584 585 tmp = hline * phy_hs_clk; 586 hline_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 587 dsi_write(dsi2, DSI2_IPI_VID_HLINE_MAN_CFG, VID_HLINE_TIME(hline_time)); 588 589 dsi_write(dsi2, DSI2_IPI_VID_VSA_MAN_CFG, VID_VSA_LINES(vsa)); 590 dsi_write(dsi2, DSI2_IPI_VID_VBP_MAN_CFG, VID_VBP_LINES(vbp)); 591 dsi_write(dsi2, DSI2_IPI_VID_VACT_MAN_CFG, VID_VACT_LINES(vact)); 592 dsi_write(dsi2, DSI2_IPI_VID_VFP_MAN_CFG, VID_VFP_LINES(vfp)); 593 } 594 595 static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2) 596 { 597 u32 val = 0, mode; 598 int ret; 599 600 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 601 val |= VID_MODE_TYPE_BURST; 602 else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 603 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 604 605 else 606 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 607 608 dsi_write(dsi2, DSI2_DSI_VID_TX_CFG, val); 609 610 611 dsi_write(dsi2, DSI2_MODE_CTRL, VIDEO_MODE); 612 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 613 mode, mode & VIDEO_MODE, 614 MODE_STATUS_TIMEOUT_US); 615 if (ret < 0) 616 printf("failed to enter video mode\n"); 617 } 618 619 static void dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 *dsi2) 620 { 621 u32 mode; 622 int ret; 623 624 dsi_write(dsi2, DSI2_MODE_CTRL, DATA_STREAM_MODE); 625 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 626 mode, mode & DATA_STREAM_MODE, 627 MODE_STATUS_TIMEOUT_US); 628 if (ret < 0) 629 printf("failed to enter data stream mode\n"); 630 } 631 632 static void dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 *dsi2) 633 { 634 u32 mode; 635 int ret; 636 637 dsi_write(dsi2, DSI2_MODE_CTRL, COMMAND_MODE); 638 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 639 mode, mode & COMMAND_MODE, 640 MODE_STATUS_TIMEOUT_US); 641 if (ret < 0) 642 printf("failed to enter cmd mode\n"); 643 } 644 645 static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2) 646 { 647 dw_mipi_dsi2_ipi_set(dsi2); 648 649 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO) 650 dw_mipi_dsi2_set_vid_mode(dsi2); 651 else 652 dw_mipi_dsi2_set_data_stream_mode(dsi2); 653 654 if (dsi2->slave) 655 dw_mipi_dsi2_enable(dsi2->slave); 656 } 657 658 static void dw_mipi_dsi2_disable(struct dw_mipi_dsi2 *dsi2) 659 { 660 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, 0); 661 dw_mipi_dsi2_set_cmd_mode(dsi2); 662 663 if (dsi2->slave) 664 dw_mipi_dsi2_disable(dsi2->slave); 665 } 666 667 static void dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 *dsi2) 668 { 669 if (!dsi2->prepared) 670 return; 671 672 dsi_write(dsi2, DSI2_PWR_UP, RESET); 673 674 if (dsi2->dcphy.phy) 675 rockchip_phy_power_off(dsi2->dcphy.phy); 676 677 dsi2->prepared = false; 678 679 if (dsi2->slave) 680 dw_mipi_dsi2_post_disable(dsi2->slave); 681 } 682 683 static int dw_mipi_dsi2_connector_pre_init(struct display_state *state) 684 { 685 struct connector_state *conn_state = &state->conn_state; 686 687 conn_state->type = DRM_MODE_CONNECTOR_DSI; 688 689 return 0; 690 } 691 692 static int dw_mipi_dsi2_connector_init(struct display_state *state) 693 { 694 struct connector_state *conn_state = &state->conn_state; 695 struct crtc_state *cstate = &state->crtc_state; 696 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 697 struct rockchip_phy *phy = NULL; 698 struct udevice *phy_dev; 699 struct udevice *dev; 700 int ret; 701 702 703 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dsi2->id); 704 dsi2->dcphy.phy = conn_state->phy; 705 706 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 707 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 708 conn_state->output_if |= 709 dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0; 710 711 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) { 712 conn_state->output_flags |= ROCKCHIP_OUTPUT_MIPI_DS_MODE; 713 conn_state->hold_mode = true; 714 } 715 716 if (dsi2->lanes > 4) { 717 ret = uclass_get_device_by_name(UCLASS_DISPLAY, 718 "dsi@fde30000", 719 &dev); 720 if (ret) 721 return ret; 722 723 dsi2->slave = dev_get_priv(dev); 724 if (!dsi2->slave) 725 return -ENODEV; 726 727 dsi2->slave->master = dsi2; 728 dsi2->lanes /= 2; 729 dsi2->slave->lanes = dsi2->lanes; 730 dsi2->slave->format = dsi2->format; 731 dsi2->slave->mode_flags = dsi2->mode_flags; 732 dsi2->slave->channel = dsi2->channel; 733 conn_state->output_flags |= 734 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; 735 if (dsi2->data_swap) 736 conn_state->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP; 737 738 conn_state->output_if |= VOP_OUTPUT_IF_MIPI1; 739 740 ret = uclass_get_device_by_phandle(UCLASS_PHY, dev, 741 "phys", &phy_dev); 742 if (ret) 743 return -ENODEV; 744 745 phy = (struct rockchip_phy *)dev_get_driver_data(phy_dev); 746 if (!phy) 747 return -ENODEV; 748 749 dsi2->slave->dcphy.phy = phy; 750 if (phy->funcs && phy->funcs->init) 751 return phy->funcs->init(phy); 752 } 753 754 if (dsi2->dsc_enable) { 755 cstate->dsc_enable = 1; 756 cstate->dsc_sink_cap.version_major = dsi2->version_major; 757 cstate->dsc_sink_cap.version_minor = dsi2->version_minor; 758 cstate->dsc_sink_cap.slice_width = dsi2->slice_width; 759 cstate->dsc_sink_cap.slice_height = dsi2->slice_height; 760 /* only can support rgb888 panel now */ 761 cstate->dsc_sink_cap.target_bits_per_pixel_x16 = 8 << 4; 762 cstate->dsc_sink_cap.native_420 = 0; 763 memcpy(&cstate->pps, dsi2->pps, sizeof(struct drm_dsc_picture_parameter_set)); 764 } 765 766 return 0; 767 } 768 769 /* 770 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived 771 * from the valid ranges specified in Section 6.9, Table 14, Page 41 772 * of the D-PHY specification (v2.1). 773 */ 774 int mipi_dphy_get_default_config(unsigned long long hs_clk_rate, 775 struct mipi_dphy_configure *cfg) 776 { 777 unsigned long long ui; 778 779 if (!cfg) 780 return -EINVAL; 781 782 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); 783 do_div(ui, hs_clk_rate); 784 785 cfg->clk_miss = 0; 786 cfg->clk_post = 60000 + 52 * ui; 787 cfg->clk_pre = 8000; 788 cfg->clk_prepare = 38000; 789 cfg->clk_settle = 95000; 790 cfg->clk_term_en = 0; 791 cfg->clk_trail = 60000; 792 cfg->clk_zero = 262000; 793 cfg->d_term_en = 0; 794 cfg->eot = 0; 795 cfg->hs_exit = 100000; 796 cfg->hs_prepare = 40000 + 4 * ui; 797 cfg->hs_zero = 105000 + 6 * ui; 798 cfg->hs_settle = 85000 + 6 * ui; 799 cfg->hs_skip = 40000; 800 801 /* 802 * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40) 803 * contains this formula as: 804 * 805 * T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui) 806 * 807 * where n = 1 for forward-direction HS mode and n = 4 for reverse- 808 * direction HS mode. There's only one setting and this function does 809 * not parameterize on anything other that ui, so this code will 810 * assumes that reverse-direction HS mode is supported and uses n = 4. 811 */ 812 cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui); 813 814 cfg->init = 100; 815 cfg->lpx = 60000; 816 cfg->ta_get = 5 * cfg->lpx; 817 cfg->ta_go = 4 * cfg->lpx; 818 cfg->ta_sure = 2 * cfg->lpx; 819 cfg->wakeup = 1000; 820 821 return 0; 822 } 823 824 static void dw_mipi_dsi2_set_hs_clk(struct dw_mipi_dsi2 *dsi2, unsigned long rate) 825 { 826 mipi_dphy_get_default_config(rate, &dsi2->mipi_dphy_cfg); 827 828 if (!dsi2->c_option) 829 rockchip_phy_set_mode(dsi2->dcphy.phy, PHY_MODE_MIPI_DPHY); 830 831 rate = rockchip_phy_set_pll(dsi2->dcphy.phy, rate); 832 dsi2->lane_hs_rate = DIV_ROUND_CLOSEST(rate, MSEC_PER_SEC); 833 } 834 835 static void dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 *dsi2) 836 { 837 dsi_write(dsi2, DSI2_SOFT_RESET, 0X0); 838 udelay(100); 839 dsi_write(dsi2, DSI2_SOFT_RESET, SYS_RSTN | PHY_RSTN | IPI_RSTN); 840 } 841 842 static void 843 dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 *dsi2, u32 mode) 844 { 845 /* 846 * select controller work in Manual mode 847 * Manual: MANUAL_MODE_EN 848 * Automatic: 0 849 */ 850 dsi_write(dsi2, MANUAL_MODE_CFG, mode); 851 } 852 853 static void dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 *dsi2) 854 { 855 u32 val = 0; 856 857 /* PPI width is fixed to 16 bits in DCPHY */ 858 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes); 859 val |= PHY_TYPE(dsi2->c_option ? CPHY : DPHY); 860 dsi_write(dsi2, DSI2_PHY_MODE_CFG, val); 861 } 862 863 static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2) 864 { 865 u32 sys_clk = SYS_CLK / MSEC_PER_SEC; 866 u32 esc_clk_div; 867 u32 val = 0; 868 869 if (dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 870 val |= NON_CONTINUOUS_CLK; 871 872 /* The Escape clock ranges from 1MHz to 20MHz. */ 873 esc_clk_div = DIV_ROUND_UP(sys_clk, 10 * 2); 874 val |= PHY_LPTX_CLK_DIV(esc_clk_div); 875 876 dsi_write(dsi2, DSI2_PHY_CLK_CFG, val); 877 } 878 879 static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2) 880 { 881 struct drm_display_mode *mode = &dsi2->mode; 882 u64 pixel_clk, ipi_clk, phy_hsclk, tmp; 883 884 /* 885 * in DPHY mode, the phy_hstx_clk is exactly 1/16 the Lane high-speed 886 * data rate; In CPHY mode, the phy_hstx_clk is exactly 1/7 the trio 887 * high speed symbol rate. 888 */ 889 if (dsi2->c_option) 890 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 891 892 else 893 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 894 895 /* IPI_RATIO_MAN_CFG = PHY_HSTX_CLK / IPI_CLK */ 896 pixel_clk = mode->crtc_clock * MSEC_PER_SEC; 897 ipi_clk = pixel_clk / 4; 898 899 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, ipi_clk); 900 dsi_write(dsi2, DSI2_PHY_IPI_RATIO_MAN_CFG, PHY_IPI_RATIO(tmp)); 901 902 /* SYS_RATIO_MAN_CFG = MIPI_DCPHY_HSCLK_Freq / SYS_CLK */ 903 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, SYS_CLK); 904 dsi_write(dsi2, DSI2_PHY_SYS_RATIO_MAN_CFG, PHY_SYS_RATIO(tmp)); 905 } 906 907 static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2) 908 { 909 struct mipi_dphy_configure *cfg = &dsi2->mipi_dphy_cfg; 910 unsigned long long tmp, ui; 911 unsigned long long hstx_clk; 912 913 hstx_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 914 915 ui = ALIGN(PSEC_PER_SEC, hstx_clk); 916 do_div(ui, hstx_clk); 917 918 /* PHY_LP2HS_TIME = (TLPX + THS-PREPARE + THS-ZERO) / Tphy_hstx_clk */ 919 tmp = cfg->lpx + cfg->hs_prepare + cfg->hs_zero; 920 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 921 dsi_write(dsi2, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(tmp)); 922 923 /* PHY_HS2LP_TIME = (THS-TRAIL + THS-EXIT) / Tphy_hstx_clk */ 924 tmp = cfg->hs_trail + cfg->hs_exit; 925 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 926 dsi_write(dsi2, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(tmp)); 927 } 928 929 static void dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 *dsi2) 930 { 931 dw_mipi_dsi2_phy_mode_cfg(dsi2); 932 dw_mipi_dsi2_phy_clk_mode_cfg(dsi2); 933 dw_mipi_dsi2_phy_ratio_cfg(dsi2); 934 dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(dsi2); 935 936 /* phy configuration 8 - 10 */ 937 } 938 939 static void dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 *dsi2) 940 { 941 u32 val; 942 943 val = BTA_EN | EOTP_TX_EN; 944 945 if (dsi2->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 946 val &= ~EOTP_TX_EN; 947 948 dsi_write(dsi2, DSI2_DSI_GENERAL_CFG, val); 949 dsi_write(dsi2, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel)); 950 951 if (dsi2->scrambling_en) 952 dsi_write(dsi2, DSI2_DSI_SCRAMBLING_CFG, SCRAMBLING_EN); 953 954 val = 0; 955 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) 956 val |= BLK_HFP_HS_EN; 957 958 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) 959 val |= BLK_HBP_HS_EN; 960 961 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HSA) 962 val |= BLK_HSA_HS_EN; 963 964 dsi_write(dsi2, DSI2_DSI_VID_TX_CFG, val); 965 966 /* configure the maximum return packet size that periphera can send */ 967 } 968 969 static void dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 *dsi2, bool enable) 970 { 971 if (enable) { 972 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x1); 973 dsi_write(dsi2, DSI2_INT_MASK_TO, 0xf); 974 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x1); 975 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x1); 976 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x1); 977 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x1); 978 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x1); 979 } else { 980 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x0); 981 dsi_write(dsi2, DSI2_INT_MASK_TO, 0x0); 982 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x0); 983 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x0); 984 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x0); 985 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x0); 986 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x0); 987 }; 988 } 989 990 static void mipi_dcphy_power_on(struct dw_mipi_dsi2 *dsi2) 991 { 992 if (!dsi2->dcphy.phy) 993 return; 994 995 rockchip_phy_power_on(dsi2->dcphy.phy); 996 } 997 998 static void dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 *dsi2) 999 { 1000 if (dsi2->prepared) 1001 return; 1002 1003 dw_mipi_dsi2_host_softrst(dsi2); 1004 dsi_write(dsi2, DSI2_PWR_UP, RESET); 1005 1006 dw_mipi_dsi2_work_mode(dsi2, MANUAL_MODE_EN); 1007 dw_mipi_dsi2_phy_init(dsi2); 1008 dw_mipi_dsi2_tx_option_set(dsi2); 1009 dw_mipi_dsi2_irq_enable(dsi2, 0); 1010 mipi_dcphy_power_on(dsi2); 1011 dsi_write(dsi2, DSI2_PWR_UP, POWER_UP); 1012 dw_mipi_dsi2_set_cmd_mode(dsi2); 1013 1014 dsi2->prepared = true; 1015 1016 if (dsi2->slave) 1017 dw_mipi_dsi2_pre_enable(dsi2->slave); 1018 } 1019 1020 static int dw_mipi_dsi2_connector_prepare(struct display_state *state) 1021 { 1022 struct connector_state *conn_state = &state->conn_state; 1023 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 1024 unsigned long lane_rate; 1025 1026 memcpy(&dsi2->mode, &conn_state->mode, sizeof(struct drm_display_mode)); 1027 if (dsi2->slave) 1028 memcpy(&dsi2->slave->mode, &dsi2->mode, 1029 sizeof(struct drm_display_mode)); 1030 1031 lane_rate = dw_mipi_dsi2_get_lane_rate(dsi2); 1032 if (dsi2->dcphy.phy) 1033 dw_mipi_dsi2_set_hs_clk(dsi2, lane_rate); 1034 1035 if (dsi2->slave && dsi2->slave->dcphy.phy) 1036 dw_mipi_dsi2_set_hs_clk(dsi2->slave, lane_rate); 1037 1038 printf("final DSI-Link bandwidth: %u %s x %d\n", 1039 dsi2->lane_hs_rate, dsi2->c_option ? "Ksps" : "Kbps", 1040 dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes); 1041 1042 dw_mipi_dsi2_pre_enable(dsi2); 1043 1044 return 0; 1045 } 1046 1047 static void dw_mipi_dsi2_connector_unprepare(struct display_state *state) 1048 { 1049 struct connector_state *conn_state = &state->conn_state; 1050 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 1051 1052 dw_mipi_dsi2_post_disable(dsi2); 1053 } 1054 1055 static int dw_mipi_dsi2_connector_enable(struct display_state *state) 1056 { 1057 struct connector_state *conn_state = &state->conn_state; 1058 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 1059 1060 dw_mipi_dsi2_enable(dsi2); 1061 1062 return 0; 1063 } 1064 1065 static int dw_mipi_dsi2_connector_disable(struct display_state *state) 1066 { 1067 struct connector_state *conn_state = &state->conn_state; 1068 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 1069 1070 dw_mipi_dsi2_disable(dsi2); 1071 1072 return 0; 1073 } 1074 1075 static const struct rockchip_connector_funcs dw_mipi_dsi2_connector_funcs = { 1076 .pre_init = dw_mipi_dsi2_connector_pre_init, 1077 .init = dw_mipi_dsi2_connector_init, 1078 .prepare = dw_mipi_dsi2_connector_prepare, 1079 .unprepare = dw_mipi_dsi2_connector_unprepare, 1080 .enable = dw_mipi_dsi2_connector_enable, 1081 .disable = dw_mipi_dsi2_connector_disable, 1082 }; 1083 1084 static int dw_mipi_dsi2_probe(struct udevice *dev) 1085 { 1086 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(dev); 1087 const struct rockchip_connector *connector = 1088 (const struct rockchip_connector *)dev_get_driver_data(dev); 1089 const struct dw_mipi_dsi2_plat_data *pdata = connector->data; 1090 struct udevice *syscon; 1091 int id, ret; 1092 1093 dsi2->base = dev_read_addr_ptr(dev); 1094 1095 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1096 &syscon); 1097 if (!ret) { 1098 dsi2->grf = syscon_get_regmap(syscon); 1099 if (!dsi2->grf) 1100 return -ENODEV; 1101 } 1102 1103 id = of_alias_get_id(ofnode_to_np(dev->node), "dsi"); 1104 if (id < 0) 1105 id = 0; 1106 1107 dsi2->dev = dev; 1108 dsi2->pdata = pdata; 1109 dsi2->id = id; 1110 dsi2->data_swap = dev_read_bool(dsi2->dev, "rockchip,data-swap"); 1111 1112 return 0; 1113 } 1114 1115 static const u32 rk3588_dsi0_grf_reg_fields[MAX_FIELDS] = { 1116 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0000, 11, 11), 1117 [GATING_EN] = GRF_REG_FIELD(0x0000, 10, 10), 1118 [IPI_SHUTDN] = GRF_REG_FIELD(0x0000, 9, 9), 1119 [IPI_COLORM] = GRF_REG_FIELD(0x0000, 8, 8), 1120 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0000, 4, 7), 1121 [IPI_FORMAT] = GRF_REG_FIELD(0x0000, 0, 3), 1122 }; 1123 1124 static const u32 rk3588_dsi1_grf_reg_fields[MAX_FIELDS] = { 1125 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0004, 11, 11), 1126 [GATING_EN] = GRF_REG_FIELD(0x0004, 10, 10), 1127 [IPI_SHUTDN] = GRF_REG_FIELD(0x0004, 9, 9), 1128 [IPI_COLORM] = GRF_REG_FIELD(0x0004, 8, 8), 1129 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0004, 4, 7), 1130 [IPI_FORMAT] = GRF_REG_FIELD(0x0004, 0, 3), 1131 }; 1132 1133 static const struct dw_mipi_dsi2_plat_data rk3588_mipi_dsi2_plat_data = { 1134 .dsi0_grf_reg_fields = rk3588_dsi0_grf_reg_fields, 1135 .dsi1_grf_reg_fields = rk3588_dsi1_grf_reg_fields, 1136 .dphy_max_bit_rate_per_lane = 4500000000ULL, 1137 .cphy_max_symbol_rate_per_lane = 2000000000ULL, 1138 }; 1139 static const struct rockchip_connector rk3588_mipi_dsi2_driver_data = { 1140 .funcs = &dw_mipi_dsi2_connector_funcs, 1141 .data = &rk3588_mipi_dsi2_plat_data, 1142 }; 1143 1144 static const struct udevice_id dw_mipi_dsi2_ids[] = { 1145 { 1146 .compatible = "rockchip,rk3588-mipi-dsi2", 1147 .data = (ulong)&rk3588_mipi_dsi2_driver_data, 1148 }, 1149 {} 1150 }; 1151 1152 static ssize_t dw_mipi_dsi2_host_transfer(struct mipi_dsi_host *host, 1153 const struct mipi_dsi_msg *msg) 1154 { 1155 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1156 1157 return dw_mipi_dsi2_transfer(dsi2, msg); 1158 } 1159 1160 static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2) 1161 { 1162 struct udevice *dev = NULL; 1163 struct rockchip_cmd_header *header; 1164 struct drm_dsc_picture_parameter_set *pps = NULL; 1165 u8 *dsc_packed_pps; 1166 const void *data; 1167 int len; 1168 int ret; 1169 1170 ret = device_find_first_child(dsi2->dev, &dev); 1171 if (ret) 1172 return ret; 1173 1174 dsi2->c_option = dev_read_bool(dev, "phy-c-option"); 1175 dsi2->scrambling_en = dev_read_bool(dev, "scrambling-enable"); 1176 dsi2->dsc_enable = dev_read_bool(dev, "compressed-data"); 1177 1178 if (dsi2->slave) { 1179 dsi2->slave->c_option = dsi2->c_option; 1180 dsi2->slave->scrambling_en = dsi2->scrambling_en; 1181 dsi2->slave->dsc_enable = dsi2->dsc_enable; 1182 } 1183 1184 dsi2->slice_width = dev_read_u32_default(dev, "slice-width", 0); 1185 dsi2->slice_height = dev_read_u32_default(dev, "slice-height", 0); 1186 dsi2->version_major = dev_read_u32_default(dev, "version-major", 0); 1187 dsi2->version_minor = dev_read_u32_default(dev, "version-minor", 0); 1188 1189 data = dev_read_prop(dev, "panel-init-sequence", &len); 1190 if (!data) 1191 return -EINVAL; 1192 1193 while (len > sizeof(*header)) { 1194 header = (struct rockchip_cmd_header *)data; 1195 data += sizeof(*header); 1196 len -= sizeof(*header); 1197 1198 if (header->payload_length > len) 1199 return -EINVAL; 1200 1201 if (header->data_type == MIPI_DSI_PICTURE_PARAMETER_SET) { 1202 dsc_packed_pps = calloc(1, header->payload_length); 1203 if (!dsc_packed_pps) 1204 return -ENOMEM; 1205 1206 memcpy(dsc_packed_pps, data, header->payload_length); 1207 pps = (struct drm_dsc_picture_parameter_set *)dsc_packed_pps; 1208 break; 1209 } 1210 1211 data += header->payload_length; 1212 len -= header->payload_length; 1213 } 1214 1215 dsi2->pps = pps; 1216 1217 return 0; 1218 } 1219 1220 static int dw_mipi_dsi2_host_attach(struct mipi_dsi_host *host, 1221 struct mipi_dsi_device *device) 1222 { 1223 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1224 1225 if (device->lanes < 1 || device->lanes > 8) 1226 return -EINVAL; 1227 1228 dsi2->lanes = device->lanes; 1229 dsi2->channel = device->channel; 1230 dsi2->format = device->format; 1231 dsi2->mode_flags = device->mode_flags; 1232 1233 dw_mipi_dsi2_get_dsc_params_from_sink(dsi2); 1234 1235 return 0; 1236 } 1237 1238 static const struct mipi_dsi_host_ops dw_mipi_dsi2_host_ops = { 1239 .attach = dw_mipi_dsi2_host_attach, 1240 .transfer = dw_mipi_dsi2_host_transfer, 1241 }; 1242 1243 static int dw_mipi_dsi2_bind(struct udevice *dev) 1244 { 1245 struct mipi_dsi_host *host = dev_get_platdata(dev); 1246 1247 host->dev = dev; 1248 host->ops = &dw_mipi_dsi2_host_ops; 1249 1250 return dm_scan_fdt_dev(dev); 1251 } 1252 1253 static int dw_mipi_dsi2_child_post_bind(struct udevice *dev) 1254 { 1255 struct mipi_dsi_host *host = dev_get_platdata(dev->parent); 1256 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1257 char name[20]; 1258 1259 sprintf(name, "%s.%d", host->dev->name, device->channel); 1260 device_set_name(dev, name); 1261 1262 device->dev = dev; 1263 device->host = host; 1264 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4); 1265 device->format = dev_read_u32_default(dev, "dsi,format", 1266 MIPI_DSI_FMT_RGB888); 1267 device->mode_flags = dev_read_u32_default(dev, "dsi,flags", 1268 MIPI_DSI_MODE_VIDEO | 1269 MIPI_DSI_MODE_VIDEO_BURST | 1270 MIPI_DSI_MODE_VIDEO_HBP | 1271 MIPI_DSI_MODE_LPM | 1272 MIPI_DSI_MODE_EOT_PACKET); 1273 device->channel = dev_read_u32_default(dev, "reg", 0); 1274 1275 return 0; 1276 } 1277 1278 static int dw_mipi_dsi2_child_pre_probe(struct udevice *dev) 1279 { 1280 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1281 int ret; 1282 1283 ret = mipi_dsi_attach(device); 1284 if (ret) { 1285 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret); 1286 return ret; 1287 } 1288 1289 return 0; 1290 } 1291 1292 U_BOOT_DRIVER(dw_mipi_dsi2) = { 1293 .name = "dw_mipi_dsi2", 1294 .id = UCLASS_DISPLAY, 1295 .of_match = dw_mipi_dsi2_ids, 1296 .probe = dw_mipi_dsi2_probe, 1297 .bind = dw_mipi_dsi2_bind, 1298 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi2), 1299 .per_child_platdata_auto_alloc_size = sizeof(struct mipi_dsi_device), 1300 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_host), 1301 .child_post_bind = dw_mipi_dsi2_child_post_bind, 1302 .child_pre_probe = dw_mipi_dsi2_child_pre_probe, 1303 }; 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