1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Author: Guochun Huang <hero.huang@rock-chips.com> 7 */ 8 9 #include <drm/drm_mipi_dsi.h> 10 11 #include <config.h> 12 #include <common.h> 13 #include <errno.h> 14 #include <asm/unaligned.h> 15 #include <asm/gpio.h> 16 #include <asm/io.h> 17 #include <asm/hardware.h> 18 #include <dm/device.h> 19 #include <dm/read.h> 20 #include <dm/of_access.h> 21 #include <regmap.h> 22 #include <syscon.h> 23 #include <asm/arch-rockchip/clock.h> 24 #include <linux/iopoll.h> 25 26 #include "rockchip_display.h" 27 #include "rockchip_crtc.h" 28 #include "rockchip_connector.h" 29 #include "rockchip_panel.h" 30 #include "rockchip_phy.h" 31 32 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) 33 34 #define DSI2_PWR_UP 0x000c 35 #define RESET 0 36 #define POWER_UP BIT(0) 37 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 38 #define DSI2_SOFT_RESET 0x0010 39 #define SYS_RSTN BIT(2) 40 #define PHY_RSTN BIT(1) 41 #define IPI_RSTN BIT(0) 42 #define INT_ST_MAIN 0x0014 43 #define DSI2_MODE_CTRL 0x0018 44 #define DSI2_MODE_STATUS 0x001c 45 #define DSI2_CORE_STATUS 0x0020 46 #define PRI_RD_DATA_AVAIL BIT(26) 47 #define PRI_FIFOS_NOT_EMPTY BIT(25) 48 #define PRI_BUSY BIT(24) 49 #define CRI_RD_DATA_AVAIL BIT(18) 50 #define CRT_FIFOS_NOT_EMPTY BIT(17) 51 #define CRI_BUSY BIT(16) 52 #define IPI_FIFOS_NOT_EMPTY BIT(9) 53 #define IPI_BUSY BIT(8) 54 #define CORE_FIFOS_NOT_EMPTY BIT(1) 55 #define CORE_BUSY BIT(0) 56 #define MANUAL_MODE_CFG 0x0024 57 #define MANUAL_MODE_EN BIT(0) 58 #define DSI2_TIMEOUT_HSTX_CFG 0x0048 59 #define TO_HSTX(x) UPDATE(x, 15, 0) 60 #define DSI2_TIMEOUT_HSTXRDY_CFG 0x004c 61 #define TO_HSTXRDY(x) UPDATE(x, 15, 0) 62 #define DSI2_TIMEOUT_LPRX_CFG 0x0050 63 #define TO_LPRXRDY(x) UPDATE(x, 15, 0) 64 #define DSI2_TIMEOUT_LPTXRDY_CFG 0x0054 65 #define TO_LPTXRDY(x) UPDATE(x, 15, 0) 66 #define DSI2_TIMEOUT_LPTXTRIG_CFG 0x0058 67 #define TO_LPTXTRIG(x) UPDATE(x, 15, 0) 68 #define DSI2_TIMEOUT_LPTXULPS_CFG 0x005c 69 #define TO_LPTXULPS(x) UPDATE(x, 15, 0) 70 #define DSI2_TIMEOUT_BTA_CFG 0x60 71 #define TO_BTA(x) UPDATE(x, 15, 0) 72 73 #define DSI2_PHY_MODE_CFG 0x0100 74 #define PPI_WIDTH(x) UPDATE(x, 9, 8) 75 #define PHY_LANES(x) UPDATE(x - 1, 5, 4) 76 #define PHY_TYPE(x) UPDATE(x, 0, 0) 77 #define DSI2_PHY_CLK_CFG 0X0104 78 #define PHY_LPTX_CLK_DIV(x) UPDATE(x, 12, 8) 79 #define NON_CONTINUOUS_CLK BIT(0) 80 #define DSI2_PHY_LP2HS_MAN_CFG 0x010c 81 #define PHY_LP2HS_TIME(x) UPDATE(x, 28, 0) 82 #define DSI2_PHY_HS2LP_MAN_CFG 0x0114 83 #define PHY_HS2LP_TIME(x) UPDATE(x, 28, 0) 84 #define DSI2_PHY_MAX_RD_T_MAN_CFG 0x011c 85 #define PHY_MAX_RD_TIME(x) UPDATE(x, 26, 0) 86 #define DSI2_PHY_ESC_CMD_T_MAN_CFG 0x0124 87 #define PHY_ESC_CMD_TIME(x) UPDATE(x, 28, 0) 88 #define DSI2_PHY_ESC_BYTE_T_MAN_CFG 0x012c 89 #define PHY_ESC_BYTE_TIME(x) UPDATE(x, 28, 0) 90 91 #define DSI2_PHY_IPI_RATIO_MAN_CFG 0x0134 92 #define PHY_IPI_RATIO(x) UPDATE(x, 21, 0) 93 #define DSI2_PHY_SYS_RATIO_MAN_CFG 0x013C 94 #define PHY_SYS_RATIO(x) UPDATE(x, 16, 0) 95 96 #define DSI2_DSI_GENERAL_CFG 0x0200 97 #define BTA_EN BIT(1) 98 #define EOTP_TX_EN BIT(0) 99 #define DSI2_DSI_VCID_CFG 0x0204 100 #define TX_VCID(x) UPDATE(x, 1, 0) 101 #define DSI2_DSI_SCRAMBLING_CFG 0x0208 102 #define SCRAMBLING_SEED(x) UPDATE(x, 31, 16) 103 #define SCRAMBLING_EN BIT(0) 104 #define DSI2_DSI_VID_TX_CFG 0x020c 105 #define LPDT_DISPLAY_CMD_EN BIT(20) 106 #define BLK_VFP_HS_EN BIT(14) 107 #define BLK_VBP_HS_EN BIT(13) 108 #define BLK_VSA_HS_EN BIT(12) 109 #define BLK_HFP_HS_EN BIT(6) 110 #define BLK_HBP_HS_EN BIT(5) 111 #define BLK_HSA_HS_EN BIT(4) 112 #define VID_MODE_TYPE(x) UPDATE(x, 1, 0) 113 #define DSI2_CRI_TX_HDR 0x02c0 114 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 115 #define DSI2_CRI_TX_PLD 0x02c4 116 #define DSI2_CRI_RX_HDR 0x02c8 117 #define DSI2_CRI_RX_PLD 0x02cc 118 119 #define DSI2_IPI_COLOR_MAN_CFG 0x0300 120 #define IPI_DEPTH(x) UPDATE(x, 7, 4) 121 #define IPI_DEPTH_5_6_5_BITS 0x02 122 #define IPI_DEPTH_6_BITS 0x03 123 #define IPI_DEPTH_8_BITS 0x05 124 #define IPI_DEPTH_10_BITS 0x06 125 #define IPI_FORMAT(x) UPDATE(x, 3, 0) 126 #define IPI_FORMAT_RGB 0x0 127 #define IPI_FORMAT_DSC 0x0b 128 #define DSI2_IPI_VID_HSA_MAN_CFG 0x0304 129 #define VID_HSA_TIME(x) UPDATE(x, 29, 0) 130 #define DSI2_IPI_VID_HBP_MAN_CFG 0x030c 131 #define VID_HBP_TIME(x) UPDATE(x, 29, 0) 132 #define DSI2_IPI_VID_HACT_MAN_CFG 0x0314 133 #define VID_HACT_TIME(x) UPDATE(x, 29, 0) 134 #define DSI2_IPI_VID_HLINE_MAN_CFG 0x031c 135 #define VID_HLINE_TIME(x) UPDATE(x, 29, 0) 136 #define DSI2_IPI_VID_VSA_MAN_CFG 0x0324 137 #define VID_VSA_LINES(x) UPDATE(x, 9, 0) 138 #define DSI2_IPI_VID_VBP_MAN_CFG 0X032C 139 #define VID_VBP_LINES(x) UPDATE(x, 9, 0) 140 #define DSI2_IPI_VID_VACT_MAN_CFG 0X0334 141 #define VID_VACT_LINES(x) UPDATE(x, 13, 0) 142 #define DSI2_IPI_VID_VFP_MAN_CFG 0X033C 143 #define VID_VFP_LINES(x) UPDATE(x, 9, 0) 144 #define DSI2_IPI_PIX_PKT_CFG 0x0344 145 #define MAX_PIX_PKT(x) UPDATE(x, 15, 0) 146 147 #define DSI2_INT_ST_PHY 0x0400 148 #define DSI2_INT_MASK_PHY 0x0404 149 #define DSI2_INT_ST_TO 0x0410 150 #define DSI2_INT_MASK_TO 0x0414 151 #define DSI2_INT_ST_ACK 0x0420 152 #define DSI2_INT_MASK_ACK 0x0424 153 #define DSI2_INT_ST_IPI 0x0430 154 #define DSI2_INT_MASK_IPI 0x0434 155 #define DSI2_INT_ST_FIFO 0x0440 156 #define DSI2_INT_MASK_FIFO 0x0444 157 #define DSI2_INT_ST_PRI 0x0450 158 #define DSI2_INT_MASK_PRI 0x0454 159 #define DSI2_INT_ST_CRI 0x0460 160 #define DSI2_INT_MASK_CRI 0x0464 161 #define DSI2_INT_FORCE_CRI 0x0468 162 #define DSI2_MAX_REGISGER DSI2_INT_FORCE_CRI 163 164 #define CMD_PKT_STATUS_TIMEOUT_US 1000 165 #define MODE_STATUS_TIMEOUT_US 20000 166 #define SYS_CLK 351000000LL 167 #define PSEC_PER_SEC 1000000000000LL 168 #define USEC_PER_SEC 1000000L 169 #define MSEC_PER_SEC 1000L 170 171 #define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 16) | ((lsb) << 8) | (msb)) 172 173 enum vid_mode_type { 174 VID_MODE_TYPE_NON_BURST_SYNC_PULSES, 175 VID_MODE_TYPE_NON_BURST_SYNC_EVENTS, 176 VID_MODE_TYPE_BURST, 177 }; 178 179 enum mode_ctrl { 180 IDLE_MODE, 181 AUTOCALC_MODE, 182 COMMAND_MODE, 183 VIDEO_MODE, 184 DATA_STREAM_MODE, 185 VIDE_TEST_MODE, 186 DATA_STREAM_TEST_MODE, 187 }; 188 189 enum grf_reg_fields { 190 TXREQCLKHS_EN, 191 GATING_EN, 192 IPI_SHUTDN, 193 IPI_COLORM, 194 IPI_COLOR_DEPTH, 195 IPI_FORMAT, 196 MAX_FIELDS, 197 }; 198 199 enum phy_type { 200 DPHY, 201 CPHY, 202 }; 203 204 enum ppi_width { 205 PPI_WIDTH_8_BITS, 206 PPI_WIDTH_16_BITS, 207 PPI_WIDTH_32_BITS, 208 }; 209 210 struct rockchip_cmd_header { 211 u8 data_type; 212 u8 delay_ms; 213 u8 payload_length; 214 }; 215 216 struct dw_mipi_dsi2_plat_data { 217 const u32 *dsi0_grf_reg_fields; 218 const u32 *dsi1_grf_reg_fields; 219 unsigned long long dphy_max_bit_rate_per_lane; 220 unsigned long long cphy_max_symbol_rate_per_lane; 221 }; 222 223 struct mipi_dcphy { 224 /* Non-SNPS PHY */ 225 struct rockchip_phy *phy; 226 227 u16 input_div; 228 u16 feedback_div; 229 }; 230 231 /** 232 * struct mipi_dphy_configure - MIPI D-PHY configuration set 233 * 234 * This structure is used to represent the configuration state of a 235 * MIPI D-PHY phy. 236 */ 237 struct mipi_dphy_configure { 238 unsigned int clk_miss; 239 unsigned int clk_post; 240 unsigned int clk_pre; 241 unsigned int clk_prepare; 242 unsigned int clk_settle; 243 unsigned int clk_term_en; 244 unsigned int clk_trail; 245 unsigned int clk_zero; 246 unsigned int d_term_en; 247 unsigned int eot; 248 unsigned int hs_exit; 249 unsigned int hs_prepare; 250 unsigned int hs_settle; 251 unsigned int hs_skip; 252 unsigned int hs_trail; 253 unsigned int hs_zero; 254 unsigned int init; 255 unsigned int lpx; 256 unsigned int ta_get; 257 unsigned int ta_go; 258 unsigned int ta_sure; 259 unsigned int wakeup; 260 unsigned long hs_clk_rate; 261 unsigned long lp_clk_rate; 262 unsigned char lanes; 263 }; 264 265 struct dw_mipi_dsi2 { 266 struct rockchip_connector connector; 267 struct udevice *dev; 268 void *base; 269 void *grf; 270 int id; 271 struct dw_mipi_dsi2 *master; 272 struct dw_mipi_dsi2 *slave; 273 bool prepared; 274 275 bool auto_calc_mode; 276 bool c_option; 277 bool dsc_enable; 278 bool scrambling_en; 279 unsigned int slice_width; 280 unsigned int slice_height; 281 u32 version_major; 282 u32 version_minor; 283 284 unsigned int lane_hs_rate; /* Kbps/Ksps per lane */ 285 u32 channel; 286 u32 lanes; 287 u32 format; 288 u32 mode_flags; 289 u64 mipi_pixel_rate; 290 struct mipi_dcphy dcphy; 291 struct drm_display_mode mode; 292 bool data_swap; 293 294 struct gpio_desc te_gpio; 295 struct mipi_dsi_device *device; 296 struct mipi_dphy_configure mipi_dphy_cfg; 297 const struct dw_mipi_dsi2_plat_data *pdata; 298 struct drm_dsc_picture_parameter_set *pps; 299 }; 300 301 static inline void dsi_write(struct dw_mipi_dsi2 *dsi2, u32 reg, u32 val) 302 { 303 writel(val, dsi2->base + reg); 304 } 305 306 static inline u32 dsi_read(struct dw_mipi_dsi2 *dsi2, u32 reg) 307 { 308 return readl(dsi2->base + reg); 309 } 310 311 static inline void dsi_update_bits(struct dw_mipi_dsi2 *dsi2, 312 u32 reg, u32 mask, u32 val) 313 { 314 u32 orig, tmp; 315 316 orig = dsi_read(dsi2, reg); 317 tmp = orig & ~mask; 318 tmp |= val & mask; 319 dsi_write(dsi2, reg, tmp); 320 } 321 322 static void grf_field_write(struct dw_mipi_dsi2 *dsi2, enum grf_reg_fields index, 323 unsigned int val) 324 { 325 const u32 field = dsi2->id ? dsi2->pdata->dsi1_grf_reg_fields[index] : 326 dsi2->pdata->dsi0_grf_reg_fields[index]; 327 u16 reg; 328 u8 msb, lsb; 329 330 if (!field) 331 return; 332 333 reg = (field >> 16) & 0xffff; 334 lsb = (field >> 8) & 0xff; 335 msb = (field >> 0) & 0xff; 336 337 regmap_write(dsi2->grf, reg, GENMASK(msb, lsb) << 16 | val << lsb); 338 } 339 340 static unsigned long dw_mipi_dsi2_get_lane_rate(struct dw_mipi_dsi2 *dsi2) 341 { 342 const struct drm_display_mode *mode = &dsi2->mode; 343 u64 max_lane_rate, lane_rate; 344 unsigned int value; 345 int bpp, lanes; 346 u64 tmp; 347 348 max_lane_rate = (dsi2->c_option) ? 349 dsi2->pdata->cphy_max_symbol_rate_per_lane : 350 dsi2->pdata->dphy_max_bit_rate_per_lane; 351 352 /* 353 * optional override of the desired bandwidth 354 * High-Speed mode: Differential and terminated: 80Mbps ~ 4500 Mbps 355 */ 356 value = dev_read_u32_default(dsi2->dev, "rockchip,lane-rate", 0); 357 if (value >= 80000 && value <= 4500000) 358 return value * MSEC_PER_SEC; 359 else if (value >= 80 && value <= 4500) 360 return value * USEC_PER_SEC; 361 362 bpp = mipi_dsi_pixel_format_to_bpp(dsi2->format); 363 if (bpp < 0) 364 bpp = 24; 365 366 lanes = dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes; 367 tmp = (u64)mode->crtc_clock * 1000 * bpp; 368 do_div(tmp, lanes); 369 370 if (dsi2->c_option) 371 tmp = DIV_ROUND_CLOSEST(tmp * 100, 228); 372 373 /* set BW a little larger only in video burst mode in 374 * consideration of the protocol overhead and HS mode 375 * switching to BLLP mode, take 1 / 0.9, since Mbps must 376 * big than bandwidth of RGB 377 */ 378 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { 379 tmp *= 10; 380 do_div(tmp, 9); 381 } 382 383 if (tmp > max_lane_rate) 384 lane_rate = max_lane_rate; 385 else 386 lane_rate = tmp; 387 388 return lane_rate; 389 } 390 391 static int cri_fifos_wait_avail(struct dw_mipi_dsi2 *dsi2) 392 { 393 u32 sts, mask; 394 int ret; 395 396 mask = CRI_BUSY | CRT_FIFOS_NOT_EMPTY; 397 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 398 sts, !(sts & mask), 399 CMD_PKT_STATUS_TIMEOUT_US); 400 if (ret < 0) { 401 printf("command interface is busy: 0x%x\n", sts); 402 return ret; 403 } 404 405 return 0; 406 } 407 408 static int dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 *dsi2, 409 const struct mipi_dsi_msg *msg) 410 { 411 u8 *payload = msg->rx_buf; 412 u8 data_type; 413 u16 wc; 414 int i, j, ret, len = msg->rx_len; 415 unsigned int vrefresh = drm_mode_vrefresh(&dsi2->mode); 416 u32 val; 417 418 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 419 val, val & CRI_RD_DATA_AVAIL, 420 DIV_ROUND_UP(1000000, vrefresh)); 421 if (ret) { 422 printf("CRI has no available read data\n"); 423 return ret; 424 } 425 426 val = dsi_read(dsi2, DSI2_CRI_RX_HDR); 427 data_type = val & 0x3f; 428 429 if (mipi_dsi_packet_format_is_short(data_type)) { 430 for (i = 0; i < len && i < 2; i++) 431 payload[i] = (val >> (8 * (i + 1))) & 0xff; 432 433 return 0; 434 } 435 436 wc = (val >> 8) & 0xffff; 437 /* Receive payload */ 438 for (i = 0; i < len && i < wc; i += 4) { 439 val = dsi_read(dsi2, DSI2_CRI_RX_PLD); 440 for (j = 0; j < 4 && j + i < len && j + i < wc; j++) 441 payload[i + j] = val >> (8 * j); 442 } 443 444 return 0; 445 } 446 447 static ssize_t dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 *dsi2, 448 const struct mipi_dsi_msg *msg) 449 { 450 struct mipi_dsi_packet packet; 451 int ret; 452 int val; 453 u32 mode; 454 455 dsi_update_bits(dsi2, DSI2_DSI_VID_TX_CFG, LPDT_DISPLAY_CMD_EN, 456 msg->flags & MIPI_DSI_MSG_USE_LPM ? 457 LPDT_DISPLAY_CMD_EN : 0); 458 459 /* create a packet to the DSI protocol */ 460 ret = mipi_dsi_create_packet(&packet, msg); 461 if (ret) { 462 printf("failed to create packet: %d\n", ret); 463 return ret; 464 } 465 466 /* check cri interface is not busy */ 467 ret = cri_fifos_wait_avail(dsi2); 468 if (ret) 469 return ret; 470 471 /* Send payload */ 472 while (DIV_ROUND_UP(packet.payload_length, 4)) { 473 if (packet.payload_length < 4) { 474 /* send residu payload */ 475 val = 0; 476 memcpy(&val, packet.payload, packet.payload_length); 477 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 478 packet.payload_length = 0; 479 } else { 480 val = get_unaligned_le32(packet.payload); 481 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 482 packet.payload += 4; 483 packet.payload_length -= 4; 484 } 485 } 486 487 /* Send packet header */ 488 mode = CMD_TX_MODE(msg->flags & MIPI_DSI_MSG_USE_LPM ? 1 : 0); 489 val = get_unaligned_le32(packet.header); 490 dsi_write(dsi2, DSI2_CRI_TX_HDR, mode | val); 491 492 ret = cri_fifos_wait_avail(dsi2); 493 if (ret) 494 return ret; 495 496 if (msg->rx_len) { 497 ret = dw_mipi_dsi2_read_from_fifo(dsi2, msg); 498 if (ret < 0) 499 return ret; 500 } 501 502 if (dsi2->slave) { 503 ret = dw_mipi_dsi2_transfer(dsi2->slave, msg); 504 if (ret < 0) 505 return ret; 506 } 507 508 return msg->rx_len ? msg->rx_len : msg->tx_len; 509 } 510 511 static void dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 *dsi2) 512 { 513 u32 val, color_depth; 514 515 switch (dsi2->format) { 516 case MIPI_DSI_FMT_RGB666: 517 case MIPI_DSI_FMT_RGB666_PACKED: 518 color_depth = IPI_DEPTH_6_BITS; 519 break; 520 case MIPI_DSI_FMT_RGB565: 521 color_depth = IPI_DEPTH_5_6_5_BITS; 522 break; 523 case MIPI_DSI_FMT_RGB888: 524 default: 525 color_depth = IPI_DEPTH_8_BITS; 526 break; 527 } 528 529 val = IPI_DEPTH(color_depth) | 530 IPI_FORMAT(dsi2->dsc_enable ? IPI_FORMAT_DSC : IPI_FORMAT_RGB); 531 dsi_write(dsi2, DSI2_IPI_COLOR_MAN_CFG, val); 532 grf_field_write(dsi2, IPI_COLOR_DEPTH, color_depth); 533 534 if (dsi2->dsc_enable) 535 grf_field_write(dsi2, IPI_FORMAT, IPI_FORMAT_DSC); 536 } 537 538 static void dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 *dsi2) 539 { 540 struct drm_display_mode *mode = &dsi2->mode; 541 u32 hline, hsa, hbp, hact; 542 u64 hline_time, hsa_time, hbp_time, hact_time, tmp; 543 u64 pixel_clk, phy_hs_clk; 544 u32 vact, vsa, vfp, vbp; 545 u16 val; 546 547 if (dsi2->slave || dsi2->master) 548 val = mode->hdisplay / 2; 549 else 550 val = mode->hdisplay; 551 552 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val)); 553 554 dw_mipi_dsi2_ipi_color_coding_cfg(dsi2); 555 556 if (dsi2->auto_calc_mode) 557 return; 558 559 /* 560 * if the controller is intended to operate in data stream mode, 561 * no more steps are required. 562 */ 563 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) 564 return; 565 566 vact = mode->vdisplay; 567 vsa = mode->vsync_end - mode->vsync_start; 568 vfp = mode->vsync_start - mode->vdisplay; 569 vbp = mode->vtotal - mode->vsync_end; 570 hact = mode->hdisplay; 571 hsa = mode->hsync_end - mode->hsync_start; 572 hbp = mode->htotal - mode->hsync_end; 573 hline = mode->htotal; 574 575 pixel_clk = mode->crtc_clock * MSEC_PER_SEC; 576 577 if (dsi2->c_option) 578 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 579 else 580 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 581 582 tmp = hsa * phy_hs_clk; 583 hsa_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 584 dsi_write(dsi2, DSI2_IPI_VID_HSA_MAN_CFG, VID_HSA_TIME(hsa_time)); 585 586 tmp = hbp * phy_hs_clk; 587 hbp_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 588 dsi_write(dsi2, DSI2_IPI_VID_HBP_MAN_CFG, VID_HBP_TIME(hbp_time)); 589 590 tmp = hact * phy_hs_clk; 591 hact_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 592 dsi_write(dsi2, DSI2_IPI_VID_HACT_MAN_CFG, VID_HACT_TIME(hact_time)); 593 594 tmp = hline * phy_hs_clk; 595 hline_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 596 dsi_write(dsi2, DSI2_IPI_VID_HLINE_MAN_CFG, VID_HLINE_TIME(hline_time)); 597 598 dsi_write(dsi2, DSI2_IPI_VID_VSA_MAN_CFG, VID_VSA_LINES(vsa)); 599 dsi_write(dsi2, DSI2_IPI_VID_VBP_MAN_CFG, VID_VBP_LINES(vbp)); 600 dsi_write(dsi2, DSI2_IPI_VID_VACT_MAN_CFG, VID_VACT_LINES(vact)); 601 dsi_write(dsi2, DSI2_IPI_VID_VFP_MAN_CFG, VID_VFP_LINES(vfp)); 602 } 603 604 static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2) 605 { 606 u32 val = 0, mode; 607 int ret; 608 609 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) 610 val |= BLK_HFP_HS_EN; 611 612 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) 613 val |= BLK_HBP_HS_EN; 614 615 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HSA) 616 val |= BLK_HSA_HS_EN; 617 618 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 619 val |= VID_MODE_TYPE_BURST; 620 else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 621 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 622 else 623 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 624 625 dsi_write(dsi2, DSI2_DSI_VID_TX_CFG, val); 626 627 dsi_write(dsi2, DSI2_MODE_CTRL, VIDEO_MODE); 628 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 629 mode, mode & VIDEO_MODE, 630 MODE_STATUS_TIMEOUT_US); 631 if (ret < 0) 632 printf("failed to enter video mode\n"); 633 } 634 635 static void dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 *dsi2) 636 { 637 u32 mode; 638 int ret; 639 640 dsi_write(dsi2, DSI2_MODE_CTRL, DATA_STREAM_MODE); 641 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 642 mode, mode & DATA_STREAM_MODE, 643 MODE_STATUS_TIMEOUT_US); 644 if (ret < 0) 645 printf("failed to enter data stream mode\n"); 646 } 647 648 static void dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 *dsi2) 649 { 650 u32 mode; 651 int ret; 652 653 dsi_write(dsi2, DSI2_MODE_CTRL, COMMAND_MODE); 654 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 655 mode, mode & COMMAND_MODE, 656 MODE_STATUS_TIMEOUT_US); 657 if (ret < 0) 658 printf("failed to enter cmd mode\n"); 659 } 660 661 static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2) 662 { 663 u32 mode; 664 int ret; 665 666 dw_mipi_dsi2_ipi_set(dsi2); 667 668 if (dsi2->auto_calc_mode) { 669 dsi_write(dsi2, DSI2_MODE_CTRL, AUTOCALC_MODE); 670 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 671 mode, mode == IDLE_MODE, 672 MODE_STATUS_TIMEOUT_US); 673 if (ret < 0) 674 printf("auto calculation training failed\n"); 675 } 676 677 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO) 678 dw_mipi_dsi2_set_vid_mode(dsi2); 679 else 680 dw_mipi_dsi2_set_data_stream_mode(dsi2); 681 682 if (dsi2->slave) 683 dw_mipi_dsi2_enable(dsi2->slave); 684 } 685 686 static void dw_mipi_dsi2_disable(struct dw_mipi_dsi2 *dsi2) 687 { 688 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, 0); 689 dw_mipi_dsi2_set_cmd_mode(dsi2); 690 691 if (dsi2->slave) 692 dw_mipi_dsi2_disable(dsi2->slave); 693 } 694 695 static void dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 *dsi2) 696 { 697 if (!dsi2->prepared) 698 return; 699 700 dsi_write(dsi2, DSI2_PWR_UP, RESET); 701 702 if (dsi2->dcphy.phy) 703 rockchip_phy_power_off(dsi2->dcphy.phy); 704 705 dsi2->prepared = false; 706 707 if (dsi2->slave) 708 dw_mipi_dsi2_post_disable(dsi2->slave); 709 } 710 711 static int dw_mipi_dsi2_connector_pre_init(struct rockchip_connector *conn, 712 struct display_state *state) 713 { 714 struct connector_state *conn_state = &state->conn_state; 715 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 716 struct mipi_dsi_host *host = dev_get_platdata(dsi2->dev); 717 struct mipi_dsi_device *device; 718 char name[20]; 719 720 conn_state->type = DRM_MODE_CONNECTOR_DSI; 721 722 if (conn->bridge) { 723 device = dev_get_platdata(conn->bridge->dev); 724 if (!device) 725 return -ENODEV; 726 727 device->host = host; 728 sprintf(name, "%s.%d", host->dev->name, device->channel); 729 device_set_name(conn->bridge->dev, name); 730 mipi_dsi_attach(device); 731 } 732 733 return 0; 734 } 735 736 static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2) 737 { 738 struct udevice *dev = dsi2->device->dev; 739 struct rockchip_cmd_header *header; 740 struct drm_dsc_picture_parameter_set *pps = NULL; 741 u8 *dsc_packed_pps; 742 const void *data; 743 int len; 744 745 dsi2->c_option = dev_read_bool(dev, "phy-c-option"); 746 dsi2->scrambling_en = dev_read_bool(dev, "scrambling-enable"); 747 dsi2->dsc_enable = dev_read_bool(dev, "compressed-data"); 748 749 if (dsi2->slave) { 750 dsi2->slave->c_option = dsi2->c_option; 751 dsi2->slave->scrambling_en = dsi2->scrambling_en; 752 dsi2->slave->dsc_enable = dsi2->dsc_enable; 753 } 754 755 if (!dsi2->dsc_enable) 756 return 0; 757 758 dsi2->slice_width = dev_read_u32_default(dev, "slice-width", 0); 759 dsi2->slice_height = dev_read_u32_default(dev, "slice-height", 0); 760 dsi2->version_major = dev_read_u32_default(dev, "version-major", 0); 761 dsi2->version_minor = dev_read_u32_default(dev, "version-minor", 0); 762 763 data = dev_read_prop(dev, "panel-init-sequence", &len); 764 if (!data) 765 return -EINVAL; 766 767 while (len > sizeof(*header)) { 768 header = (struct rockchip_cmd_header *)data; 769 data += sizeof(*header); 770 len -= sizeof(*header); 771 772 if (header->payload_length > len) 773 return -EINVAL; 774 775 if (header->data_type == MIPI_DSI_PICTURE_PARAMETER_SET) { 776 dsc_packed_pps = calloc(1, header->payload_length); 777 if (!dsc_packed_pps) 778 return -ENOMEM; 779 780 memcpy(dsc_packed_pps, data, header->payload_length); 781 pps = (struct drm_dsc_picture_parameter_set *)dsc_packed_pps; 782 break; 783 } 784 785 data += header->payload_length; 786 len -= header->payload_length; 787 } 788 789 if (!pps) { 790 printf("not found dsc pps definition\n"); 791 return -EINVAL; 792 } 793 794 dsi2->pps = pps; 795 796 if (dsi2->slave) { 797 u16 pic_width = be16_to_cpu(pps->pic_width) / 2; 798 799 dsi2->pps->pic_width = cpu_to_be16(pic_width); 800 printf("dsc pic_width change from %d to %d\n", pic_width * 2, pic_width); 801 } 802 803 return 0; 804 } 805 806 static int dw_mipi_dsi2_connector_init(struct rockchip_connector *conn, struct display_state *state) 807 { 808 struct connector_state *conn_state = &state->conn_state; 809 struct crtc_state *cstate = &state->crtc_state; 810 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 811 struct rockchip_phy *phy = NULL; 812 struct udevice *phy_dev; 813 struct udevice *dev; 814 int ret; 815 816 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dsi2->id); 817 dsi2->dcphy.phy = conn->phy; 818 819 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 820 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 821 conn_state->output_if |= 822 dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0; 823 824 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) { 825 conn_state->output_flags |= ROCKCHIP_OUTPUT_MIPI_DS_MODE; 826 conn_state->hold_mode = true; 827 } 828 829 if (dsi2->lanes > 4) { 830 ret = uclass_get_device_by_name(UCLASS_DISPLAY, 831 "dsi@fde30000", 832 &dev); 833 if (ret) 834 return ret; 835 836 dsi2->slave = dev_get_priv(dev); 837 if (!dsi2->slave) 838 return -ENODEV; 839 840 dsi2->slave->master = dsi2; 841 dsi2->lanes /= 2; 842 843 dsi2->slave->auto_calc_mode = dsi2->auto_calc_mode; 844 dsi2->slave->lanes = dsi2->lanes; 845 dsi2->slave->format = dsi2->format; 846 dsi2->slave->mode_flags = dsi2->mode_flags; 847 dsi2->slave->channel = dsi2->channel; 848 conn_state->output_flags |= 849 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; 850 if (dsi2->data_swap) 851 conn_state->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP; 852 853 conn_state->output_if |= VOP_OUTPUT_IF_MIPI1; 854 855 ret = uclass_get_device_by_phandle(UCLASS_PHY, dev, 856 "phys", &phy_dev); 857 if (ret) 858 return -ENODEV; 859 860 phy = (struct rockchip_phy *)dev_get_driver_data(phy_dev); 861 if (!phy) 862 return -ENODEV; 863 864 dsi2->slave->dcphy.phy = phy; 865 if (phy->funcs && phy->funcs->init) 866 return phy->funcs->init(phy); 867 } 868 869 dw_mipi_dsi2_get_dsc_params_from_sink(dsi2); 870 871 if (dm_gpio_is_valid(&dsi2->te_gpio)) { 872 cstate->soft_te = true; 873 conn_state->te_gpio = &dsi2->te_gpio; 874 } 875 876 if (dsi2->dsc_enable) { 877 cstate->dsc_enable = 1; 878 cstate->dsc_sink_cap.version_major = dsi2->version_major; 879 cstate->dsc_sink_cap.version_minor = dsi2->version_minor; 880 cstate->dsc_sink_cap.slice_width = dsi2->slice_width; 881 cstate->dsc_sink_cap.slice_height = dsi2->slice_height; 882 /* only can support rgb888 panel now */ 883 cstate->dsc_sink_cap.target_bits_per_pixel_x16 = 8 << 4; 884 cstate->dsc_sink_cap.native_420 = 0; 885 memcpy(&cstate->pps, dsi2->pps, sizeof(struct drm_dsc_picture_parameter_set)); 886 } 887 888 return 0; 889 } 890 891 /* 892 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived 893 * from the valid ranges specified in Section 6.9, Table 14, Page 41 894 * of the D-PHY specification (v2.1). 895 */ 896 int mipi_dphy_get_default_config(unsigned long long hs_clk_rate, 897 struct mipi_dphy_configure *cfg) 898 { 899 unsigned long long ui; 900 901 if (!cfg) 902 return -EINVAL; 903 904 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); 905 do_div(ui, hs_clk_rate); 906 907 cfg->clk_miss = 0; 908 cfg->clk_post = 60000 + 52 * ui; 909 cfg->clk_pre = 8000; 910 cfg->clk_prepare = 38000; 911 cfg->clk_settle = 95000; 912 cfg->clk_term_en = 0; 913 cfg->clk_trail = 60000; 914 cfg->clk_zero = 262000; 915 cfg->d_term_en = 0; 916 cfg->eot = 0; 917 cfg->hs_exit = 100000; 918 cfg->hs_prepare = 40000 + 4 * ui; 919 cfg->hs_zero = 105000 + 6 * ui; 920 cfg->hs_settle = 85000 + 6 * ui; 921 cfg->hs_skip = 40000; 922 923 /* 924 * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40) 925 * contains this formula as: 926 * 927 * T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui) 928 * 929 * where n = 1 for forward-direction HS mode and n = 4 for reverse- 930 * direction HS mode. There's only one setting and this function does 931 * not parameterize on anything other that ui, so this code will 932 * assumes that reverse-direction HS mode is supported and uses n = 4. 933 */ 934 cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui); 935 936 cfg->init = 100; 937 cfg->lpx = 60000; 938 cfg->ta_get = 5 * cfg->lpx; 939 cfg->ta_go = 4 * cfg->lpx; 940 cfg->ta_sure = 2 * cfg->lpx; 941 cfg->wakeup = 1000; 942 943 return 0; 944 } 945 946 static void dw_mipi_dsi2_set_hs_clk(struct dw_mipi_dsi2 *dsi2, unsigned long rate) 947 { 948 mipi_dphy_get_default_config(rate, &dsi2->mipi_dphy_cfg); 949 950 if (!dsi2->c_option) 951 rockchip_phy_set_mode(dsi2->dcphy.phy, PHY_MODE_MIPI_DPHY); 952 953 rate = rockchip_phy_set_pll(dsi2->dcphy.phy, rate); 954 dsi2->lane_hs_rate = DIV_ROUND_CLOSEST(rate, MSEC_PER_SEC); 955 } 956 957 static void dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 *dsi2) 958 { 959 dsi_write(dsi2, DSI2_SOFT_RESET, 0X0); 960 udelay(100); 961 dsi_write(dsi2, DSI2_SOFT_RESET, SYS_RSTN | PHY_RSTN | IPI_RSTN); 962 } 963 964 static void 965 dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 *dsi2, u32 mode) 966 { 967 /* 968 * select controller work in Manual mode 969 * Manual: MANUAL_MODE_EN 970 * Automatic: 0 971 */ 972 dsi_write(dsi2, MANUAL_MODE_CFG, mode); 973 } 974 975 static void dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 *dsi2) 976 { 977 u32 val = 0; 978 979 /* PPI width is fixed to 16 bits in DCPHY */ 980 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes); 981 val |= PHY_TYPE(dsi2->c_option ? CPHY : DPHY); 982 dsi_write(dsi2, DSI2_PHY_MODE_CFG, val); 983 } 984 985 static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2) 986 { 987 u32 sys_clk = SYS_CLK / USEC_PER_SEC; 988 u32 esc_clk_div; 989 u32 val = 0; 990 991 if (dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 992 val |= NON_CONTINUOUS_CLK; 993 994 /* The Escape clock ranges from 1MHz to 20MHz. */ 995 esc_clk_div = DIV_ROUND_UP(sys_clk, 20 * 2); 996 val |= PHY_LPTX_CLK_DIV(esc_clk_div); 997 998 dsi_write(dsi2, DSI2_PHY_CLK_CFG, val); 999 } 1000 1001 static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2) 1002 { 1003 u64 ipi_clk, phy_hsclk, tmp; 1004 1005 /* 1006 * in DPHY mode, the phy_hstx_clk is exactly 1/16 the Lane high-speed 1007 * data rate; In CPHY mode, the phy_hstx_clk is exactly 1/7 the trio 1008 * high speed symbol rate. 1009 */ 1010 if (dsi2->c_option) 1011 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 1012 1013 else 1014 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 1015 1016 /* IPI_RATIO_MAN_CFG = PHY_HSTX_CLK / IPI_CLK */ 1017 ipi_clk = dsi2->mipi_pixel_rate; 1018 1019 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, ipi_clk); 1020 dsi_write(dsi2, DSI2_PHY_IPI_RATIO_MAN_CFG, PHY_IPI_RATIO(tmp)); 1021 1022 /* SYS_RATIO_MAN_CFG = MIPI_DCPHY_HSCLK_Freq / SYS_CLK */ 1023 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, SYS_CLK); 1024 dsi_write(dsi2, DSI2_PHY_SYS_RATIO_MAN_CFG, PHY_SYS_RATIO(tmp)); 1025 } 1026 1027 static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2) 1028 { 1029 struct mipi_dphy_configure *cfg = &dsi2->mipi_dphy_cfg; 1030 unsigned long long tmp, ui; 1031 unsigned long long hstx_clk; 1032 1033 hstx_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 1034 1035 ui = ALIGN(PSEC_PER_SEC, hstx_clk); 1036 do_div(ui, hstx_clk); 1037 1038 /* PHY_LP2HS_TIME = (TLPX + THS-PREPARE + THS-ZERO) / Tphy_hstx_clk */ 1039 tmp = cfg->lpx + cfg->hs_prepare + cfg->hs_zero; 1040 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 1041 dsi_write(dsi2, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(tmp)); 1042 1043 /* PHY_HS2LP_TIME = (THS-TRAIL + THS-EXIT) / Tphy_hstx_clk */ 1044 tmp = cfg->hs_trail + cfg->hs_exit; 1045 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 1046 dsi_write(dsi2, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(tmp)); 1047 } 1048 1049 static void dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 *dsi2) 1050 { 1051 dw_mipi_dsi2_phy_mode_cfg(dsi2); 1052 dw_mipi_dsi2_phy_clk_mode_cfg(dsi2); 1053 1054 if (dsi2->auto_calc_mode) 1055 return; 1056 1057 dw_mipi_dsi2_phy_ratio_cfg(dsi2); 1058 dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(dsi2); 1059 1060 /* phy configuration 8 - 10 */ 1061 } 1062 1063 static void dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 *dsi2) 1064 { 1065 u32 val; 1066 1067 val = BTA_EN | EOTP_TX_EN; 1068 1069 if (dsi2->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 1070 val &= ~EOTP_TX_EN; 1071 1072 dsi_write(dsi2, DSI2_DSI_GENERAL_CFG, val); 1073 dsi_write(dsi2, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel)); 1074 1075 if (dsi2->scrambling_en) 1076 dsi_write(dsi2, DSI2_DSI_SCRAMBLING_CFG, SCRAMBLING_EN); 1077 } 1078 1079 static void dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 *dsi2, bool enable) 1080 { 1081 if (enable) { 1082 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x1); 1083 dsi_write(dsi2, DSI2_INT_MASK_TO, 0xf); 1084 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x1); 1085 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x1); 1086 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x1); 1087 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x1); 1088 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x1); 1089 } else { 1090 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x0); 1091 dsi_write(dsi2, DSI2_INT_MASK_TO, 0x0); 1092 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x0); 1093 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x0); 1094 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x0); 1095 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x0); 1096 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x0); 1097 }; 1098 } 1099 1100 static void mipi_dcphy_power_on(struct dw_mipi_dsi2 *dsi2) 1101 { 1102 if (!dsi2->dcphy.phy) 1103 return; 1104 1105 rockchip_phy_power_on(dsi2->dcphy.phy); 1106 } 1107 1108 static void dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 *dsi2) 1109 { 1110 if (dsi2->prepared) 1111 return; 1112 1113 dw_mipi_dsi2_host_softrst(dsi2); 1114 dsi_write(dsi2, DSI2_PWR_UP, RESET); 1115 1116 dw_mipi_dsi2_work_mode(dsi2, dsi2->auto_calc_mode ? 0 : MANUAL_MODE_EN); 1117 dw_mipi_dsi2_phy_init(dsi2); 1118 dw_mipi_dsi2_tx_option_set(dsi2); 1119 dw_mipi_dsi2_irq_enable(dsi2, 0); 1120 mipi_dcphy_power_on(dsi2); 1121 dsi_write(dsi2, DSI2_PWR_UP, POWER_UP); 1122 dw_mipi_dsi2_set_cmd_mode(dsi2); 1123 1124 dsi2->prepared = true; 1125 1126 if (dsi2->slave) 1127 dw_mipi_dsi2_pre_enable(dsi2->slave); 1128 } 1129 1130 static void dw_mipi_dsi2_get_mipi_pixel_clk(struct dw_mipi_dsi2 *dsi2, 1131 struct crtc_state *s) 1132 { 1133 struct drm_display_mode *mode = &dsi2->mode; 1134 u8 k = dsi2->slave ? 2 : 1; 1135 1136 /* 1.When MIPI works in uncompressed mode: 1137 * (Video Timing Pixel Rate)/(4)=(MIPI Pixel ClockxK)=(dclk_out×K)=dclk_core 1138 * 2.When MIPI works in compressed mode: 1139 * MIPI Pixel Clock = cds_clk / 2 1140 * MIPI is configured as double channel display mode, K=2, otherwise K=1. 1141 */ 1142 if (dsi2->dsc_enable) { 1143 dsi2->mipi_pixel_rate = s->dsc_cds_clk_rate / 2; 1144 if (dsi2->slave) 1145 dsi2->slave->mipi_pixel_rate = dsi2->mipi_pixel_rate; 1146 1147 return; 1148 } 1149 1150 dsi2->mipi_pixel_rate = (mode->crtc_clock * MSEC_PER_SEC) / (4 * k); 1151 if (dsi2->slave) 1152 dsi2->slave->mipi_pixel_rate = dsi2->mipi_pixel_rate; 1153 } 1154 1155 static int dw_mipi_dsi2_connector_prepare(struct rockchip_connector *conn, 1156 struct display_state *state) 1157 { 1158 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1159 struct connector_state *conn_state = &state->conn_state; 1160 struct crtc_state *cstate = &state->crtc_state; 1161 unsigned long lane_rate; 1162 1163 memcpy(&dsi2->mode, &conn_state->mode, sizeof(struct drm_display_mode)); 1164 if (dsi2->slave) 1165 memcpy(&dsi2->slave->mode, &dsi2->mode, 1166 sizeof(struct drm_display_mode)); 1167 1168 dw_mipi_dsi2_get_mipi_pixel_clk(dsi2, cstate); 1169 1170 lane_rate = dw_mipi_dsi2_get_lane_rate(dsi2); 1171 if (dsi2->dcphy.phy) 1172 dw_mipi_dsi2_set_hs_clk(dsi2, lane_rate); 1173 1174 if (dsi2->slave && dsi2->slave->dcphy.phy) 1175 dw_mipi_dsi2_set_hs_clk(dsi2->slave, lane_rate); 1176 1177 printf("final DSI-Link bandwidth: %u %s x %d\n", 1178 dsi2->lane_hs_rate, dsi2->c_option ? "Ksps" : "Kbps", 1179 dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes); 1180 1181 dw_mipi_dsi2_pre_enable(dsi2); 1182 1183 return 0; 1184 } 1185 1186 static void dw_mipi_dsi2_connector_unprepare(struct rockchip_connector *conn, 1187 struct display_state *state) 1188 { 1189 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1190 1191 dw_mipi_dsi2_post_disable(dsi2); 1192 } 1193 1194 static int dw_mipi_dsi2_connector_enable(struct rockchip_connector *conn, 1195 struct display_state *state) 1196 { 1197 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1198 1199 dw_mipi_dsi2_enable(dsi2); 1200 1201 return 0; 1202 } 1203 1204 static int dw_mipi_dsi2_connector_disable(struct rockchip_connector *conn, 1205 struct display_state *state) 1206 { 1207 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1208 1209 dw_mipi_dsi2_disable(dsi2); 1210 1211 return 0; 1212 } 1213 1214 static int dw_mipi_dsi2_connector_mode_valid(struct rockchip_connector *conn, 1215 struct display_state *state) 1216 { 1217 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1218 struct connector_state *conn_state = &state->conn_state; 1219 u8 min_pixels = dsi2->slave ? 8 : 4; 1220 struct videomode vm; 1221 1222 drm_display_mode_to_videomode(&conn_state->mode, &vm); 1223 1224 /* 1225 * the minimum region size (HSA,HBP,HACT,HFP) is 4 pixels 1226 * which is the ip known issues and limitations. 1227 */ 1228 if (!(vm.hsync_len < min_pixels || vm.hback_porch < min_pixels || 1229 vm.hfront_porch < min_pixels || vm.hactive < min_pixels)) 1230 return MODE_OK; 1231 1232 if (vm.hsync_len < min_pixels) 1233 vm.hsync_len = min_pixels; 1234 1235 if (vm.hback_porch < min_pixels) 1236 vm.hback_porch = min_pixels; 1237 1238 if (vm.hfront_porch < min_pixels) 1239 vm.hfront_porch = min_pixels; 1240 1241 if (vm.hactive < min_pixels) 1242 vm.hactive = min_pixels; 1243 1244 memset(&conn_state->mode, 0, sizeof(struct drm_display_mode)); 1245 drm_display_mode_from_videomode(&vm, &conn_state->mode); 1246 conn_state->mode.vrefresh = drm_mode_vrefresh(&conn_state->mode); 1247 1248 return MODE_OK; 1249 } 1250 1251 static const struct rockchip_connector_funcs dw_mipi_dsi2_connector_funcs = { 1252 .pre_init = dw_mipi_dsi2_connector_pre_init, 1253 .init = dw_mipi_dsi2_connector_init, 1254 .prepare = dw_mipi_dsi2_connector_prepare, 1255 .unprepare = dw_mipi_dsi2_connector_unprepare, 1256 .enable = dw_mipi_dsi2_connector_enable, 1257 .disable = dw_mipi_dsi2_connector_disable, 1258 .mode_valid = dw_mipi_dsi2_connector_mode_valid, 1259 }; 1260 1261 static int dw_mipi_dsi2_probe(struct udevice *dev) 1262 { 1263 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(dev); 1264 const struct dw_mipi_dsi2_plat_data *pdata = 1265 (const struct dw_mipi_dsi2_plat_data *)dev_get_driver_data(dev); 1266 struct udevice *syscon; 1267 int id, ret; 1268 1269 dsi2->base = dev_read_addr_ptr(dev); 1270 1271 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1272 &syscon); 1273 if (!ret) { 1274 dsi2->grf = syscon_get_regmap(syscon); 1275 if (!dsi2->grf) 1276 return -ENODEV; 1277 } 1278 1279 id = of_alias_get_id(ofnode_to_np(dev->node), "dsi"); 1280 if (id < 0) 1281 id = 0; 1282 1283 ret = gpio_request_by_name(dev, "te-gpios", 0, 1284 &dsi2->te_gpio, GPIOD_IS_IN); 1285 if (ret && ret != -ENOENT) { 1286 printf("%s: Cannot get TE GPIO: %d\n", __func__, ret); 1287 return ret; 1288 } 1289 1290 dsi2->dev = dev; 1291 dsi2->pdata = pdata; 1292 dsi2->id = id; 1293 dsi2->data_swap = dev_read_bool(dsi2->dev, "rockchip,data-swap"); 1294 dsi2->auto_calc_mode = dev_read_bool(dsi2->dev, "auto-calculation-mode"); 1295 1296 rockchip_connector_bind(&dsi2->connector, dev, id, &dw_mipi_dsi2_connector_funcs, NULL, 1297 DRM_MODE_CONNECTOR_DSI); 1298 1299 return 0; 1300 } 1301 1302 static const u32 rk3588_dsi0_grf_reg_fields[MAX_FIELDS] = { 1303 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0000, 11, 11), 1304 [GATING_EN] = GRF_REG_FIELD(0x0000, 10, 10), 1305 [IPI_SHUTDN] = GRF_REG_FIELD(0x0000, 9, 9), 1306 [IPI_COLORM] = GRF_REG_FIELD(0x0000, 8, 8), 1307 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0000, 4, 7), 1308 [IPI_FORMAT] = GRF_REG_FIELD(0x0000, 0, 3), 1309 }; 1310 1311 static const u32 rk3588_dsi1_grf_reg_fields[MAX_FIELDS] = { 1312 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0004, 11, 11), 1313 [GATING_EN] = GRF_REG_FIELD(0x0004, 10, 10), 1314 [IPI_SHUTDN] = GRF_REG_FIELD(0x0004, 9, 9), 1315 [IPI_COLORM] = GRF_REG_FIELD(0x0004, 8, 8), 1316 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0004, 4, 7), 1317 [IPI_FORMAT] = GRF_REG_FIELD(0x0004, 0, 3), 1318 }; 1319 1320 static const struct dw_mipi_dsi2_plat_data rk3588_mipi_dsi2_plat_data = { 1321 .dsi0_grf_reg_fields = rk3588_dsi0_grf_reg_fields, 1322 .dsi1_grf_reg_fields = rk3588_dsi1_grf_reg_fields, 1323 .dphy_max_bit_rate_per_lane = 4500000000ULL, 1324 .cphy_max_symbol_rate_per_lane = 2000000000ULL, 1325 }; 1326 1327 static const struct udevice_id dw_mipi_dsi2_ids[] = { 1328 { 1329 .compatible = "rockchip,rk3588-mipi-dsi2", 1330 .data = (ulong)&rk3588_mipi_dsi2_plat_data, 1331 }, 1332 {} 1333 }; 1334 1335 static ssize_t dw_mipi_dsi2_host_transfer(struct mipi_dsi_host *host, 1336 const struct mipi_dsi_msg *msg) 1337 { 1338 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1339 1340 return dw_mipi_dsi2_transfer(dsi2, msg); 1341 } 1342 1343 static int dw_mipi_dsi2_host_attach(struct mipi_dsi_host *host, 1344 struct mipi_dsi_device *device) 1345 { 1346 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1347 1348 if (device->lanes < 1 || device->lanes > 8) 1349 return -EINVAL; 1350 1351 dsi2->lanes = device->lanes; 1352 dsi2->channel = device->channel; 1353 dsi2->format = device->format; 1354 dsi2->mode_flags = device->mode_flags; 1355 dsi2->device = device; 1356 1357 return 0; 1358 } 1359 1360 static const struct mipi_dsi_host_ops dw_mipi_dsi2_host_ops = { 1361 .attach = dw_mipi_dsi2_host_attach, 1362 .transfer = dw_mipi_dsi2_host_transfer, 1363 }; 1364 1365 static int dw_mipi_dsi2_bind(struct udevice *dev) 1366 { 1367 struct mipi_dsi_host *host = dev_get_platdata(dev); 1368 1369 host->dev = dev; 1370 host->ops = &dw_mipi_dsi2_host_ops; 1371 1372 return dm_scan_fdt_dev(dev); 1373 } 1374 1375 static int dw_mipi_dsi2_child_post_bind(struct udevice *dev) 1376 { 1377 struct mipi_dsi_host *host = dev_get_platdata(dev->parent); 1378 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1379 char name[20]; 1380 1381 sprintf(name, "%s.%d", host->dev->name, device->channel); 1382 device_set_name(dev, name); 1383 1384 device->dev = dev; 1385 device->host = host; 1386 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4); 1387 device->format = dev_read_u32_default(dev, "dsi,format", 1388 MIPI_DSI_FMT_RGB888); 1389 device->mode_flags = dev_read_u32_default(dev, "dsi,flags", 1390 MIPI_DSI_MODE_VIDEO | 1391 MIPI_DSI_MODE_VIDEO_BURST | 1392 MIPI_DSI_MODE_VIDEO_HBP | 1393 MIPI_DSI_MODE_LPM | 1394 MIPI_DSI_MODE_EOT_PACKET); 1395 device->channel = dev_read_u32_default(dev, "reg", 0); 1396 1397 return 0; 1398 } 1399 1400 static int dw_mipi_dsi2_child_pre_probe(struct udevice *dev) 1401 { 1402 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1403 int ret; 1404 1405 ret = mipi_dsi_attach(device); 1406 if (ret) { 1407 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret); 1408 return ret; 1409 } 1410 1411 return 0; 1412 } 1413 1414 U_BOOT_DRIVER(dw_mipi_dsi2) = { 1415 .name = "dw_mipi_dsi2", 1416 .id = UCLASS_DISPLAY, 1417 .of_match = dw_mipi_dsi2_ids, 1418 .probe = dw_mipi_dsi2_probe, 1419 .bind = dw_mipi_dsi2_bind, 1420 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi2), 1421 .per_child_platdata_auto_alloc_size = sizeof(struct mipi_dsi_device), 1422 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_host), 1423 .child_post_bind = dw_mipi_dsi2_child_post_bind, 1424 .child_pre_probe = dw_mipi_dsi2_child_pre_probe, 1425 }; 1426