1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Author: Guochun Huang <hero.huang@rock-chips.com> 7 */ 8 9 #include <drm/drm_mipi_dsi.h> 10 11 #include <config.h> 12 #include <common.h> 13 #include <errno.h> 14 #include <asm/unaligned.h> 15 #include <asm/io.h> 16 #include <asm/hardware.h> 17 #include <dm/device.h> 18 #include <dm/read.h> 19 #include <dm/of_access.h> 20 #include <syscon.h> 21 #include <asm/arch-rockchip/clock.h> 22 #include <linux/iopoll.h> 23 24 #include "rockchip_display.h" 25 #include "rockchip_crtc.h" 26 #include "rockchip_connector.h" 27 #include "rockchip_panel.h" 28 #include "rockchip_phy.h" 29 30 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) 31 32 #define DSI2_PWR_UP 0x000c 33 #define RESET 0 34 #define POWER_UP BIT(0) 35 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 36 #define DSI2_SOFT_RESET 0x0010 37 #define SYS_RSTN BIT(2) 38 #define PHY_RSTN BIT(1) 39 #define IPI_RSTN BIT(0) 40 #define INT_ST_MAIN 0x0014 41 #define DSI2_MODE_CTRL 0x0018 42 #define DSI2_MODE_STATUS 0x001c 43 #define DSI2_CORE_STATUS 0x0020 44 #define PRI_RD_DATA_AVAIL BIT(26) 45 #define PRI_FIFOS_NOT_EMPTY BIT(25) 46 #define PRI_BUSY BIT(24) 47 #define CRI_RD_DATA_AVAIL BIT(18) 48 #define CRT_FIFOS_NOT_EMPTY BIT(17) 49 #define CRI_BUSY BIT(16) 50 #define IPI_FIFOS_NOT_EMPTY BIT(9) 51 #define IPI_BUSY BIT(8) 52 #define CORE_FIFOS_NOT_EMPTY BIT(1) 53 #define CORE_BUSY BIT(0) 54 #define MANUAL_MODE_CFG 0x0024 55 #define MANUAL_MODE_EN BIT(0) 56 #define DSI2_TIMEOUT_HSTX_CFG 0x0048 57 #define TO_HSTX(x) UPDATE(x, 15, 0) 58 #define DSI2_TIMEOUT_HSTXRDY_CFG 0x004c 59 #define TO_HSTXRDY(x) UPDATE(x, 15, 0) 60 #define DSI2_TIMEOUT_LPRX_CFG 0x0050 61 #define TO_LPRXRDY(x) UPDATE(x, 15, 0) 62 #define DSI2_TIMEOUT_LPTXRDY_CFG 0x0054 63 #define TO_LPTXRDY(x) UPDATE(x, 15, 0) 64 #define DSI2_TIMEOUT_LPTXTRIG_CFG 0x0058 65 #define TO_LPTXTRIG(x) UPDATE(x, 15, 0) 66 #define DSI2_TIMEOUT_LPTXULPS_CFG 0x005c 67 #define TO_LPTXULPS(x) UPDATE(x, 15, 0) 68 #define DSI2_TIMEOUT_BTA_CFG 0x60 69 #define TO_BTA(x) UPDATE(x, 15, 0) 70 71 #define DSI2_PHY_MODE_CFG 0x0100 72 #define PPI_WIDTH(x) UPDATE(x, 9, 8) 73 #define PHY_LANES(x) UPDATE(x - 1, 5, 4) 74 #define PHY_TYPE(x) UPDATE(x, 0, 0) 75 #define DSI2_PHY_CLK_CFG 0X0104 76 #define PHY_LPTX_CLK_DIV(x) UPDATE(x, 12, 8) 77 #define NON_CONTINUOUS_CLK BIT(0) 78 #define DSI2_PHY_LP2HS_MAN_CFG 0x010c 79 #define PHY_LP2HS_TIME(x) UPDATE(x, 28, 0) 80 #define DSI2_PHY_HS2LP_MAN_CFG 0x0114 81 #define PHY_HS2LP_TIME(x) UPDATE(x, 28, 0) 82 #define DSI2_PHY_MAX_RD_T_MAN_CFG 0x011c 83 #define PHY_MAX_RD_TIME(x) UPDATE(x, 26, 0) 84 #define DSI2_PHY_ESC_CMD_T_MAN_CFG 0x0124 85 #define PHY_ESC_CMD_TIME(x) UPDATE(x, 28, 0) 86 #define DSI2_PHY_ESC_BYTE_T_MAN_CFG 0x012c 87 #define PHY_ESC_BYTE_TIME(x) UPDATE(x, 28, 0) 88 89 #define DSI2_PHY_IPI_RATIO_MAN_CFG 0x0134 90 #define PHY_IPI_RATIO(x) UPDATE(x, 21, 0) 91 #define DSI2_PHY_SYS_RATIO_MAN_CFG 0x013C 92 #define PHY_SYS_RATIO(x) UPDATE(x, 16, 0) 93 94 #define DSI2_DSI_GENERAL_CFG 0x0200 95 #define BTA_EN BIT(1) 96 #define EOTP_TX_EN BIT(0) 97 #define DSI2_DSI_VCID_CFG 0x0204 98 #define TX_VCID(x) UPDATE(x, 1, 0) 99 #define DSI2_DSI_SCRAMBLING_CFG 0x0208 100 #define SCRAMBLING_SEED(x) UPDATE(x, 31, 16) 101 #define SCRAMBLING_EN BIT(0) 102 #define DSI2_DSI_VID_TX_CFG 0x020c 103 #define LPDT_DISPLAY_CMD_EN BIT(20) 104 #define BLK_VFP_HS_EN BIT(14) 105 #define BLK_VBP_HS_EN BIT(13) 106 #define BLK_VSA_HS_EN BIT(12) 107 #define BLK_HFP_HS_EN BIT(6) 108 #define BLK_HBP_HS_EN BIT(5) 109 #define BLK_HSA_HS_EN BIT(4) 110 #define VID_MODE_TYPE(x) UPDATE(x, 1, 0) 111 #define DSI2_CRI_TX_HDR 0x02c0 112 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 113 #define DSI2_CRI_TX_PLD 0x02c4 114 #define DSI2_CRI_RX_HDR 0x02c8 115 #define DSI2_CRI_RX_PLD 0x02cc 116 117 #define DSI2_IPI_COLOR_MAN_CFG 0x0300 118 #define IPI_DEPTH(x) UPDATE(x, 7, 4) 119 #define IPI_DEPTH_5_6_5_BITS 0x02 120 #define IPI_DEPTH_6_BITS 0x03 121 #define IPI_DEPTH_8_BITS 0x05 122 #define IPI_DEPTH_10_BITS 0x06 123 #define IPI_FORMAT(x) UPDATE(x, 3, 0) 124 #define IPI_FORMAT_RGB 0x0 125 #define IPI_FORMAT_DSC 0x0b 126 #define DSI2_IPI_VID_HSA_MAN_CFG 0x0304 127 #define VID_HSA_TIME(x) UPDATE(x, 29, 0) 128 #define DSI2_IPI_VID_HBP_MAN_CFG 0x030c 129 #define VID_HBP_TIME(x) UPDATE(x, 29, 0) 130 #define DSI2_IPI_VID_HACT_MAN_CFG 0x0314 131 #define VID_HACT_TIME(x) UPDATE(x, 29, 0) 132 #define DSI2_IPI_VID_HLINE_MAN_CFG 0x031c 133 #define VID_HLINE_TIME(x) UPDATE(x, 29, 0) 134 #define DSI2_IPI_VID_VSA_MAN_CFG 0x0324 135 #define VID_VSA_LINES(x) UPDATE(x, 9, 0) 136 #define DSI2_IPI_VID_VBP_MAN_CFG 0X032C 137 #define VID_VBP_LINES(x) UPDATE(x, 9, 0) 138 #define DSI2_IPI_VID_VACT_MAN_CFG 0X0334 139 #define VID_VACT_LINES(x) UPDATE(x, 13, 0) 140 #define DSI2_IPI_VID_VFP_MAN_CFG 0X033C 141 #define VID_VFP_LINES(x) UPDATE(x, 9, 0) 142 #define DSI2_IPI_PIX_PKT_CFG 0x0344 143 #define MAX_PIX_PKT(x) UPDATE(x, 15, 0) 144 145 #define DSI2_INT_ST_PHY 0x0400 146 #define DSI2_INT_MASK_PHY 0x0404 147 #define DSI2_INT_ST_TO 0x0410 148 #define DSI2_INT_MASK_TO 0x0414 149 #define DSI2_INT_ST_ACK 0x0420 150 #define DSI2_INT_MASK_ACK 0x0424 151 #define DSI2_INT_ST_IPI 0x0430 152 #define DSI2_INT_MASK_IPI 0x0434 153 #define DSI2_INT_ST_FIFO 0x0440 154 #define DSI2_INT_MASK_FIFO 0x0444 155 #define DSI2_INT_ST_PRI 0x0450 156 #define DSI2_INT_MASK_PRI 0x0454 157 #define DSI2_INT_ST_CRI 0x0460 158 #define DSI2_INT_MASK_CRI 0x0464 159 #define DSI2_INT_FORCE_CRI 0x0468 160 #define DSI2_MAX_REGISGER DSI2_INT_FORCE_CRI 161 162 #define CMD_PKT_STATUS_TIMEOUT_US 20000 163 #define MODE_STATUS_TIMEOUT_US 20000 164 #define SYS_CLK 351000L 165 #define PSEC_PER_SEC 1000000000000LL 166 #define USEC_PER_SEC 1000000L 167 #define MSEC_PER_SEC 1000L 168 169 #define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 16) | ((lsb) << 8) | (msb)) 170 171 enum vid_mode_type { 172 VID_MODE_TYPE_NON_BURST_SYNC_PULSES, 173 VID_MODE_TYPE_NON_BURST_SYNC_EVENTS, 174 VID_MODE_TYPE_BURST, 175 }; 176 177 enum mode_ctrl { 178 IDLE_MODE, 179 AUTOCALC_MODE, 180 COMMAND_MODE, 181 VIDEO_MODE, 182 DATA_STREAM_MODE, 183 VIDE_TEST_MODE, 184 DATA_STREAM_TEST_MODE, 185 }; 186 187 enum grf_reg_fields { 188 TXREQCLKHS_EN, 189 GATING_EN, 190 IPI_SHUTDN, 191 IPI_COLORM, 192 IPI_COLOR_DEPTH, 193 IPI_FORMAT, 194 MAX_FIELDS, 195 }; 196 197 enum phy_type { 198 DPHY, 199 CPHY, 200 }; 201 202 enum ppi_width { 203 PPI_WIDTH_8_BITS, 204 PPI_WIDTH_16_BITS, 205 PPI_WIDTH_32_BITS, 206 }; 207 208 struct dw_mipi_dsi2_plat_data { 209 const u32 *dsi0_grf_reg_fields; 210 const u32 *dsi1_grf_reg_fields; 211 unsigned long long dphy_max_bit_rate_per_lane; 212 unsigned long long cphy_max_symbol_rate_per_lane; 213 }; 214 215 struct mipi_dcphy { 216 /* Non-SNPS PHY */ 217 struct rockchip_phy *phy; 218 219 u16 input_div; 220 u16 feedback_div; 221 }; 222 223 /** 224 * struct mipi_dphy_configure - MIPI D-PHY configuration set 225 * 226 * This structure is used to represent the configuration state of a 227 * MIPI D-PHY phy. 228 */ 229 struct mipi_dphy_configure { 230 unsigned int clk_miss; 231 unsigned int clk_post; 232 unsigned int clk_pre; 233 unsigned int clk_prepare; 234 unsigned int clk_settle; 235 unsigned int clk_term_en; 236 unsigned int clk_trail; 237 unsigned int clk_zero; 238 unsigned int d_term_en; 239 unsigned int eot; 240 unsigned int hs_exit; 241 unsigned int hs_prepare; 242 unsigned int hs_settle; 243 unsigned int hs_skip; 244 unsigned int hs_trail; 245 unsigned int hs_zero; 246 unsigned int init; 247 unsigned int lpx; 248 unsigned int ta_get; 249 unsigned int ta_go; 250 unsigned int ta_sure; 251 unsigned int wakeup; 252 unsigned long hs_clk_rate; 253 unsigned long lp_clk_rate; 254 unsigned char lanes; 255 }; 256 257 struct dw_mipi_dsi2 { 258 struct udevice *dev; 259 void *base; 260 void *grf; 261 int id; 262 struct dw_mipi_dsi2 *master; 263 struct dw_mipi_dsi2 *slave; 264 bool prepared; 265 266 bool c_option; 267 bool dsc_enable; 268 bool scrambling_en; 269 unsigned int slice_width; 270 unsigned int slice_height; 271 u32 version_major; 272 u32 version_minor; 273 274 unsigned int lane_hs_rate; /* per lane */ 275 u32 channel; 276 u32 lanes; 277 u32 format; 278 u32 mode_flags; 279 struct mipi_dcphy dcphy; 280 struct drm_display_mode mode; 281 bool data_swap; 282 283 struct mipi_dphy_configure mipi_dphy_cfg; 284 const struct dw_mipi_dsi2_plat_data *pdata; 285 }; 286 287 static inline void dsi_write(struct dw_mipi_dsi2 *dsi2, u32 reg, u32 val) 288 { 289 writel(val, dsi2->base + reg); 290 } 291 292 static inline u32 dsi_read(struct dw_mipi_dsi2 *dsi2, u32 reg) 293 { 294 return readl(dsi2->base + reg); 295 } 296 297 static inline void dsi_update_bits(struct dw_mipi_dsi2 *dsi2, 298 u32 reg, u32 mask, u32 val) 299 { 300 u32 orig, tmp; 301 302 orig = dsi_read(dsi2, reg); 303 tmp = orig & ~mask; 304 tmp |= val & mask; 305 dsi_write(dsi2, reg, tmp); 306 } 307 308 static void grf_field_write(struct dw_mipi_dsi2 *dsi2, enum grf_reg_fields index, 309 unsigned int val) 310 { 311 const u32 field = dsi2->id ? dsi2->pdata->dsi1_grf_reg_fields[index] : 312 dsi2->pdata->dsi0_grf_reg_fields[index]; 313 u16 reg; 314 u8 msb, lsb; 315 316 if (!field) 317 return; 318 319 reg = (field >> 16) & 0xffff; 320 lsb = (field >> 8) & 0xff; 321 msb = (field >> 0) & 0xff; 322 323 rk_clrsetreg(dsi2->grf + reg, GENMASK(msb, lsb), val << lsb); 324 } 325 326 static unsigned long dw_mipi_dsi2_get_lane_rate(struct dw_mipi_dsi2 *dsi2) 327 { 328 const struct drm_display_mode *mode = &dsi2->mode; 329 u64 max_lane_rate, lane_rate; 330 unsigned int value; 331 int bpp, lanes; 332 u64 tmp; 333 334 max_lane_rate = (dsi2->c_option) ? 335 dsi2->pdata->cphy_max_symbol_rate_per_lane : 336 dsi2->pdata->dphy_max_bit_rate_per_lane; 337 338 /* optional override of the desired bandwidth */ 339 value = dev_read_u32_default(dsi2->dev, "rockchip,lane-rate", 0); 340 if (value > 0) 341 return value * 1000 * 1000; 342 343 bpp = mipi_dsi_pixel_format_to_bpp(dsi2->format); 344 if (bpp < 0) 345 bpp = 24; 346 347 lanes = dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes; 348 tmp = (u64)mode->clock * 1000 * bpp; 349 do_div(tmp, lanes); 350 351 if (dsi2->c_option) 352 tmp = DIV_ROUND_CLOSEST(tmp * 100, 228); 353 354 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */ 355 tmp *= 10; 356 do_div(tmp, 9); 357 358 if (tmp > max_lane_rate) 359 lane_rate = max_lane_rate; 360 else 361 lane_rate = tmp; 362 363 return lane_rate; 364 } 365 366 static int cri_fifos_wait_avail(struct dw_mipi_dsi2 *dsi2) 367 { 368 u32 sts, mask; 369 int ret; 370 371 mask = CRI_BUSY | CRT_FIFOS_NOT_EMPTY; 372 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 373 sts, !(sts & mask), 374 CMD_PKT_STATUS_TIMEOUT_US); 375 if (ret < 0) { 376 printf("command interface is busy: 0x%x\n", sts); 377 return ret; 378 } 379 380 return 0; 381 } 382 383 static int dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 *dsi2, 384 const struct mipi_dsi_msg *msg) 385 { 386 u8 *payload = msg->rx_buf; 387 u8 data_type; 388 u16 wc; 389 int i, j, ret, len = msg->rx_len; 390 unsigned int vrefresh = drm_mode_vrefresh(&dsi2->mode); 391 u32 val; 392 393 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 394 val, val & CRI_RD_DATA_AVAIL, 395 DIV_ROUND_UP(1000000, vrefresh)); 396 if (ret) { 397 printf("CRI has no available read data\n"); 398 return ret; 399 } 400 401 val = dsi_read(dsi2, DSI2_CRI_RX_HDR); 402 data_type = val & 0x3f; 403 404 if (mipi_dsi_packet_format_is_short(data_type)) { 405 for (i = 0; i < len && i < 2; i++) 406 payload[i] = (val >> (8 * (i + 1))) & 0xff; 407 408 return 0; 409 } 410 411 wc = (val >> 8) & 0xffff; 412 /* Receive payload */ 413 for (i = 0; i < len && i < wc; i += 4) { 414 val = dsi_read(dsi2, DSI2_CRI_RX_PLD); 415 for (j = 0; j < 4 && j + i < len && j + i < wc; j++) 416 payload[i + j] = val >> (8 * j); 417 } 418 419 return 0; 420 } 421 422 static ssize_t dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 *dsi2, 423 const struct mipi_dsi_msg *msg) 424 { 425 struct mipi_dsi_packet packet; 426 int ret; 427 int val; 428 u32 mode; 429 430 dsi_update_bits(dsi2, DSI2_DSI_VID_TX_CFG, LPDT_DISPLAY_CMD_EN, 431 msg->flags & MIPI_DSI_MSG_USE_LPM ? 432 LPDT_DISPLAY_CMD_EN : 0); 433 434 /* create a packet to the DSI protocol */ 435 ret = mipi_dsi_create_packet(&packet, msg); 436 if (ret) { 437 printf("failed to create packet: %d\n", ret); 438 return ret; 439 } 440 441 /* check cri interface is not busy */ 442 ret = cri_fifos_wait_avail(dsi2); 443 if (ret) 444 return ret; 445 446 /* Send payload */ 447 while (DIV_ROUND_UP(packet.payload_length, 4)) { 448 if (packet.payload_length < 4) { 449 /* send residu payload */ 450 val = 0; 451 memcpy(&val, packet.payload, packet.payload_length); 452 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 453 packet.payload_length = 0; 454 } else { 455 val = get_unaligned_le32(packet.payload); 456 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 457 packet.payload += 4; 458 packet.payload_length -= 4; 459 } 460 } 461 462 /* Send packet header */ 463 mode = CMD_TX_MODE(msg->flags & MIPI_DSI_MSG_USE_LPM ? 1 : 0); 464 val = get_unaligned_le32(packet.header); 465 dsi_write(dsi2, DSI2_CRI_TX_HDR, mode | val); 466 467 ret = cri_fifos_wait_avail(dsi2); 468 if (ret) 469 return ret; 470 471 if (msg->rx_len) { 472 ret = dw_mipi_dsi2_read_from_fifo(dsi2, msg); 473 if (ret < 0) 474 return ret; 475 } 476 477 if (dsi2->slave) { 478 ret = dw_mipi_dsi2_transfer(dsi2->slave, msg); 479 if (ret < 0) 480 return ret; 481 } 482 483 return msg->rx_len ? msg->rx_len : msg->tx_len; 484 } 485 486 static void dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 *dsi2) 487 { 488 u32 val, color_depth; 489 490 switch (dsi2->format) { 491 case MIPI_DSI_FMT_RGB666: 492 case MIPI_DSI_FMT_RGB666_PACKED: 493 color_depth = IPI_DEPTH_6_BITS; 494 break; 495 case MIPI_DSI_FMT_RGB565: 496 color_depth = IPI_DEPTH_5_6_5_BITS; 497 break; 498 case MIPI_DSI_FMT_RGB888: 499 default: 500 color_depth = IPI_DEPTH_8_BITS; 501 break; 502 } 503 504 val = IPI_DEPTH(color_depth) | 505 IPI_FORMAT(dsi2->dsc_enable ? IPI_FORMAT_DSC : IPI_FORMAT_RGB); 506 dsi_write(dsi2, DSI2_IPI_COLOR_MAN_CFG, val); 507 grf_field_write(dsi2, IPI_COLOR_DEPTH, color_depth); 508 509 if (dsi2->dsc_enable) 510 grf_field_write(dsi2, IPI_FORMAT, IPI_FORMAT_DSC); 511 } 512 513 static void dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 *dsi2) 514 { 515 struct drm_display_mode *mode = &dsi2->mode; 516 u32 hline, hsa, hbp, hact; 517 u64 hline_time, hsa_time, hbp_time, hact_time, tmp; 518 u32 vact, vsa, vfp, vbp; 519 u32 pixel_clk, phy_hs_clk; 520 u16 val; 521 522 if (dsi2->slave || dsi2->master) 523 val = mode->hdisplay / 2; 524 else 525 val = mode->hdisplay; 526 527 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val)); 528 529 dw_mipi_dsi2_ipi_color_coding_cfg(dsi2); 530 531 /* 532 * if the controller is intended to operate in data stream mode, 533 * no more steps are required. 534 */ 535 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) 536 return; 537 538 vact = mode->vdisplay; 539 vsa = mode->vsync_end - mode->vsync_start; 540 vfp = mode->vsync_start - mode->vdisplay; 541 vbp = mode->vtotal - mode->vsync_end; 542 hact = mode->hdisplay; 543 hsa = mode->hsync_end - mode->hsync_start; 544 hbp = mode->htotal - mode->hsync_end; 545 hline = mode->htotal; 546 547 pixel_clk = mode->clock / 1000; 548 549 if (dsi2->c_option) 550 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate, 7); 551 else 552 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate, 16); 553 554 tmp = hsa * phy_hs_clk; 555 hsa_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 556 dsi_write(dsi2, DSI2_IPI_VID_HSA_MAN_CFG, VID_HSA_TIME(hsa_time)); 557 558 tmp = hbp * phy_hs_clk; 559 hbp_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 560 dsi_write(dsi2, DSI2_IPI_VID_HBP_MAN_CFG, VID_HBP_TIME(hbp_time)); 561 562 tmp = hact * phy_hs_clk; 563 hact_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 564 dsi_write(dsi2, DSI2_IPI_VID_HACT_MAN_CFG, VID_HACT_TIME(hact_time)); 565 566 tmp = hline * phy_hs_clk; 567 hline_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 568 dsi_write(dsi2, DSI2_IPI_VID_HLINE_MAN_CFG, VID_HLINE_TIME(hline_time)); 569 570 dsi_write(dsi2, DSI2_IPI_VID_VSA_MAN_CFG, VID_VSA_LINES(vsa)); 571 dsi_write(dsi2, DSI2_IPI_VID_VBP_MAN_CFG, VID_VBP_LINES(vbp)); 572 dsi_write(dsi2, DSI2_IPI_VID_VACT_MAN_CFG, VID_VACT_LINES(vact)); 573 dsi_write(dsi2, DSI2_IPI_VID_VFP_MAN_CFG, VID_VFP_LINES(vfp)); 574 } 575 576 static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2) 577 { 578 u32 val = 0, mode; 579 int ret; 580 581 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 582 val |= VID_MODE_TYPE_BURST; 583 else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 584 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 585 586 else 587 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 588 589 dsi_write(dsi2, DSI2_DSI_VID_TX_CFG, val); 590 591 592 dsi_write(dsi2, DSI2_MODE_CTRL, VIDEO_MODE); 593 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 594 mode, mode & VIDEO_MODE, 595 MODE_STATUS_TIMEOUT_US); 596 if (ret < 0) 597 printf("failed to enter video mode\n"); 598 } 599 600 static void dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 *dsi2) 601 { 602 u32 mode; 603 int ret; 604 605 dsi_write(dsi2, DSI2_MODE_CTRL, DATA_STREAM_MODE); 606 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 607 mode, mode & DATA_STREAM_MODE, 608 MODE_STATUS_TIMEOUT_US); 609 if (ret < 0) 610 printf("failed to enter data stream mode\n"); 611 } 612 613 static void dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 *dsi2) 614 { 615 u32 mode; 616 int ret; 617 618 dsi_write(dsi2, DSI2_MODE_CTRL, COMMAND_MODE); 619 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 620 mode, mode & COMMAND_MODE, 621 MODE_STATUS_TIMEOUT_US); 622 if (ret < 0) 623 printf("failed to enter cmd mode\n"); 624 } 625 626 627 static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2) 628 { 629 dw_mipi_dsi2_ipi_set(dsi2); 630 631 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO) 632 dw_mipi_dsi2_set_vid_mode(dsi2); 633 else 634 dw_mipi_dsi2_set_data_stream_mode(dsi2); 635 636 if (dsi2->slave) 637 dw_mipi_dsi2_enable(dsi2->slave); 638 } 639 640 static void dw_mipi_dsi2_disable(struct dw_mipi_dsi2 *dsi2) 641 { 642 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, 0); 643 dw_mipi_dsi2_set_cmd_mode(dsi2); 644 645 if (dsi2->slave) 646 dw_mipi_dsi2_disable(dsi2->slave); 647 } 648 649 static void dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 *dsi2) 650 { 651 if (!dsi2->prepared) 652 return; 653 654 dsi_write(dsi2, DSI2_PWR_UP, RESET); 655 656 if (dsi2->dcphy.phy) 657 rockchip_phy_power_off(dsi2->dcphy.phy); 658 659 dsi2->prepared = false; 660 661 if (dsi2->slave) 662 dw_mipi_dsi2_post_disable(dsi2->slave); 663 } 664 665 static int dw_mipi_dsi2_connector_pre_init(struct display_state *state) 666 { 667 struct connector_state *conn_state = &state->conn_state; 668 669 conn_state->type = DRM_MODE_CONNECTOR_DSI; 670 671 return 0; 672 } 673 674 static int dw_mipi_dsi2_connector_init(struct display_state *state) 675 { 676 struct connector_state *conn_state = &state->conn_state; 677 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 678 struct rockchip_phy *phy = NULL; 679 struct udevice *phy_dev; 680 struct udevice *dev; 681 int ret; 682 683 684 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dsi2->id); 685 dsi2->dcphy.phy = conn_state->phy; 686 687 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 688 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 689 conn_state->output_if |= 690 dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0; 691 692 if (dsi2->lanes > 4) { 693 ret = uclass_get_device_by_name(UCLASS_DISPLAY, 694 "dsi@fde30000", 695 &dev); 696 if (ret) 697 return ret; 698 699 dsi2->slave = dev_get_priv(dev); 700 if (!dsi2->slave) 701 return -ENODEV; 702 703 dsi2->slave->master = dsi2; 704 dsi2->lanes /= 2; 705 dsi2->slave->lanes = dsi2->lanes; 706 dsi2->slave->format = dsi2->format; 707 dsi2->slave->mode_flags = dsi2->mode_flags; 708 dsi2->slave->channel = dsi2->channel; 709 conn_state->output_flags = 710 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; 711 if (dsi2->data_swap) 712 conn_state->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP; 713 714 conn_state->output_if |= VOP_OUTPUT_IF_MIPI1; 715 716 ret = uclass_get_device_by_phandle(UCLASS_PHY, dev, 717 "phys", &phy_dev); 718 if (ret) 719 return -ENODEV; 720 721 phy = (struct rockchip_phy *)dev_get_driver_data(phy_dev); 722 if (!phy) 723 return -ENODEV; 724 725 dsi2->slave->dcphy.phy = phy; 726 if (phy->funcs && phy->funcs->init) 727 return phy->funcs->init(phy); 728 } 729 730 return 0; 731 } 732 733 /* 734 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived 735 * from the valid ranges specified in Section 6.9, Table 14, Page 41 736 * of the D-PHY specification (v2.1). 737 */ 738 int mipi_dphy_get_default_config(unsigned long long hs_clk_rate, 739 struct mipi_dphy_configure *cfg) 740 { 741 unsigned long long ui; 742 743 if (!cfg) 744 return -EINVAL; 745 746 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); 747 do_div(ui, hs_clk_rate); 748 749 cfg->clk_miss = 0; 750 cfg->clk_post = 60000 + 52 * ui; 751 cfg->clk_pre = 8000; 752 cfg->clk_prepare = 38000; 753 cfg->clk_settle = 95000; 754 cfg->clk_term_en = 0; 755 cfg->clk_trail = 60000; 756 cfg->clk_zero = 262000; 757 cfg->d_term_en = 0; 758 cfg->eot = 0; 759 cfg->hs_exit = 100000; 760 cfg->hs_prepare = 40000 + 4 * ui; 761 cfg->hs_zero = 105000 + 6 * ui; 762 cfg->hs_settle = 85000 + 6 * ui; 763 cfg->hs_skip = 40000; 764 765 /* 766 * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40) 767 * contains this formula as: 768 * 769 * T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui) 770 * 771 * where n = 1 for forward-direction HS mode and n = 4 for reverse- 772 * direction HS mode. There's only one setting and this function does 773 * not parameterize on anything other that ui, so this code will 774 * assumes that reverse-direction HS mode is supported and uses n = 4. 775 */ 776 cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui); 777 778 cfg->init = 100; 779 cfg->lpx = 60000; 780 cfg->ta_get = 5 * cfg->lpx; 781 cfg->ta_go = 4 * cfg->lpx; 782 cfg->ta_sure = 2 * cfg->lpx; 783 cfg->wakeup = 1000; 784 785 return 0; 786 } 787 788 static void dw_mipi_dsi2_set_hs_clk(struct dw_mipi_dsi2 *dsi2, unsigned long rate) 789 { 790 mipi_dphy_get_default_config(rate, &dsi2->mipi_dphy_cfg); 791 rate = rockchip_phy_set_pll(dsi2->dcphy.phy, rate); 792 dsi2->lane_hs_rate = rate / 1000 / 1000; 793 } 794 795 static void dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 *dsi2) 796 { 797 dsi_write(dsi2, DSI2_SOFT_RESET, 0X0); 798 udelay(100); 799 dsi_write(dsi2, DSI2_SOFT_RESET, SYS_RSTN | PHY_RSTN | IPI_RSTN); 800 } 801 802 static void 803 dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 *dsi2, u32 mode) 804 { 805 /* 806 * select controller work in Manual mode 807 * Manual: MANUAL_MODE_EN 808 * Automatic: 0 809 */ 810 dsi_write(dsi2, MANUAL_MODE_CFG, mode); 811 } 812 813 static void dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 *dsi2) 814 { 815 u32 val = 0; 816 817 /* PPI width is fixed to 16 bits in DCPHY */ 818 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes); 819 val |= PHY_TYPE(dsi2->c_option ? CPHY : DPHY); 820 dsi_write(dsi2, DSI2_PHY_MODE_CFG, val); 821 } 822 823 static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2) 824 { 825 u32 sys_clk = SYS_CLK / MSEC_PER_SEC; 826 u32 esc_clk_div; 827 u32 val = 0; 828 829 if (dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 830 val |= NON_CONTINUOUS_CLK; 831 832 /* The maximum value of the escape clock frequency is 20MHz */ 833 esc_clk_div = DIV_ROUND_UP(sys_clk, 20 * 2); 834 val |= PHY_LPTX_CLK_DIV(esc_clk_div); 835 836 dsi_write(dsi2, DSI2_PHY_CLK_CFG, val); 837 } 838 839 static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2) 840 { 841 struct drm_display_mode *mode = &dsi2->mode; 842 u32 pixel_clk, ipi_clk, phy_hsclk; 843 u64 tmp; 844 845 /* 846 * in DPHY mode, the phy_hstx_clk is exactly 1/16 the Lane high-speed 847 * data rate; In CPHY mode, the phy_hstx_clk is exactly 1/7 the trio 848 * high speed symbol rate. 849 */ 850 if (dsi2->c_option) 851 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 852 else 853 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 854 855 /* IPI_RATIO_MAN_CFG = PHY_HSTX_CLK / IPI_CLK */ 856 pixel_clk = mode->clock; 857 ipi_clk = pixel_clk / 4; 858 859 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, ipi_clk); 860 dsi_write(dsi2, DSI2_PHY_IPI_RATIO_MAN_CFG, PHY_IPI_RATIO(tmp)); 861 862 /* 863 * SYS_RATIO_MAN_CFG = MIPI_DCPHY_HSCLK_Freq / MIPI_DCPHY_HSCLK_Freq 864 */ 865 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, SYS_CLK); 866 dsi_write(dsi2, DSI2_PHY_SYS_RATIO_MAN_CFG, PHY_SYS_RATIO(tmp)); 867 } 868 869 static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2) 870 { 871 struct mipi_dphy_configure *cfg = &dsi2->mipi_dphy_cfg; 872 unsigned long long tmp, ui; 873 unsigned long long hstx_clk; 874 875 hstx_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * USEC_PER_SEC, 16); 876 877 ui = ALIGN(PSEC_PER_SEC, hstx_clk); 878 do_div(ui, hstx_clk); 879 880 /* PHY_LP2HS_TIME = (TLPX + THS-PREPARE + THS-ZERO) / Tphy_hstx_clk */ 881 tmp = cfg->lpx + cfg->hs_prepare + cfg->hs_zero; 882 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 883 dsi_write(dsi2, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(tmp)); 884 885 /* PHY_HS2LP_TIME = (THS-TRAIL + THS-EXIT) / Tphy_hstx_clk */ 886 tmp = cfg->hs_trail + cfg->hs_exit; 887 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 888 dsi_write(dsi2, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(tmp)); 889 } 890 891 static void dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 *dsi2) 892 { 893 dw_mipi_dsi2_phy_mode_cfg(dsi2); 894 dw_mipi_dsi2_phy_clk_mode_cfg(dsi2); 895 dw_mipi_dsi2_phy_ratio_cfg(dsi2); 896 dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(dsi2); 897 898 /* phy configuration 8 - 10 */ 899 } 900 901 static void dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 *dsi2) 902 { 903 u32 val; 904 905 val = BTA_EN | EOTP_TX_EN; 906 907 if (dsi2->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 908 val &= ~EOTP_TX_EN; 909 910 dsi_write(dsi2, DSI2_DSI_GENERAL_CFG, val); 911 dsi_write(dsi2, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel)); 912 913 if (dsi2->scrambling_en) 914 dsi_write(dsi2, DSI2_DSI_SCRAMBLING_CFG, SCRAMBLING_EN); 915 916 val = 0; 917 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) 918 val |= BLK_HFP_HS_EN; 919 920 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) 921 val |= BLK_HBP_HS_EN; 922 923 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HSA) 924 val |= BLK_HSA_HS_EN; 925 926 dsi_write(dsi2, DSI2_DSI_VID_TX_CFG, val); 927 928 /* configure the maximum return packet size that periphera can send */ 929 } 930 931 static void dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 *dsi2, bool enable) 932 { 933 if (enable) { 934 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x1); 935 dsi_write(dsi2, DSI2_INT_MASK_TO, 0xf); 936 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x1); 937 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x1); 938 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x1); 939 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x1); 940 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x1); 941 } else { 942 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x0); 943 dsi_write(dsi2, DSI2_INT_MASK_TO, 0x0); 944 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x0); 945 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x0); 946 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x0); 947 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x0); 948 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x0); 949 }; 950 } 951 952 static void mipi_dcphy_power_on(struct dw_mipi_dsi2 *dsi2) 953 { 954 if (!dsi2->dcphy.phy) 955 return; 956 957 if (!dsi2->c_option) 958 rockchip_phy_set_mode(dsi2->dcphy.phy, PHY_MODE_MIPI_DPHY); 959 960 rockchip_phy_power_on(dsi2->dcphy.phy); 961 } 962 963 static void dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 *dsi2) 964 { 965 if (dsi2->prepared) 966 return; 967 968 dw_mipi_dsi2_host_softrst(dsi2); 969 dsi_write(dsi2, DSI2_PWR_UP, RESET); 970 971 dw_mipi_dsi2_work_mode(dsi2, MANUAL_MODE_EN); 972 dw_mipi_dsi2_phy_init(dsi2); 973 dw_mipi_dsi2_tx_option_set(dsi2); 974 dw_mipi_dsi2_irq_enable(dsi2, 0); 975 mipi_dcphy_power_on(dsi2); 976 dsi_write(dsi2, DSI2_PWR_UP, POWER_UP); 977 dw_mipi_dsi2_set_cmd_mode(dsi2); 978 979 dsi2->prepared = true; 980 981 if (dsi2->slave) 982 dw_mipi_dsi2_pre_enable(dsi2->slave); 983 } 984 985 static int dw_mipi_dsi2_connector_prepare(struct display_state *state) 986 { 987 struct connector_state *conn_state = &state->conn_state; 988 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 989 unsigned long lane_rate; 990 991 memcpy(&dsi2->mode, &conn_state->mode, sizeof(struct drm_display_mode)); 992 if (dsi2->slave) 993 memcpy(&dsi2->slave->mode, &dsi2->mode, 994 sizeof(struct drm_display_mode)); 995 996 lane_rate = dw_mipi_dsi2_get_lane_rate(dsi2); 997 if (dsi2->dcphy.phy) 998 dw_mipi_dsi2_set_hs_clk(dsi2, lane_rate); 999 1000 if (dsi2->slave && dsi2->slave->dcphy.phy) 1001 dw_mipi_dsi2_set_hs_clk(dsi2->slave, lane_rate); 1002 1003 printf("final DSI-Link bandwidth: %u %s x %d\n", 1004 dsi2->lane_hs_rate, dsi2->c_option ? "Msps" : "Mbps", 1005 dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes); 1006 1007 dw_mipi_dsi2_pre_enable(dsi2); 1008 1009 return 0; 1010 } 1011 1012 static void dw_mipi_dsi2_connector_unprepare(struct display_state *state) 1013 { 1014 struct connector_state *conn_state = &state->conn_state; 1015 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 1016 1017 dw_mipi_dsi2_post_disable(dsi2); 1018 } 1019 1020 static int dw_mipi_dsi2_connector_enable(struct display_state *state) 1021 { 1022 struct connector_state *conn_state = &state->conn_state; 1023 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 1024 1025 dw_mipi_dsi2_enable(dsi2); 1026 1027 return 0; 1028 } 1029 1030 static int dw_mipi_dsi2_connector_disable(struct display_state *state) 1031 { 1032 struct connector_state *conn_state = &state->conn_state; 1033 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 1034 1035 dw_mipi_dsi2_disable(dsi2); 1036 1037 return 0; 1038 } 1039 1040 static const struct rockchip_connector_funcs dw_mipi_dsi2_connector_funcs = { 1041 .pre_init = dw_mipi_dsi2_connector_pre_init, 1042 .init = dw_mipi_dsi2_connector_init, 1043 .prepare = dw_mipi_dsi2_connector_prepare, 1044 .unprepare = dw_mipi_dsi2_connector_unprepare, 1045 .enable = dw_mipi_dsi2_connector_enable, 1046 .disable = dw_mipi_dsi2_connector_disable, 1047 }; 1048 1049 static int dw_mipi_dsi2_probe(struct udevice *dev) 1050 { 1051 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(dev); 1052 const struct rockchip_connector *connector = 1053 (const struct rockchip_connector *)dev_get_driver_data(dev); 1054 const struct dw_mipi_dsi2_plat_data *pdata = connector->data; 1055 int id; 1056 1057 dsi2->base = dev_read_addr_ptr(dev); 1058 dsi2->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1059 if (IS_ERR(dsi2->grf)) 1060 return PTR_ERR(dsi2->grf); 1061 1062 id = of_alias_get_id(ofnode_to_np(dev->node), "dsi"); 1063 if (id < 0) 1064 id = 0; 1065 1066 dsi2->dev = dev; 1067 dsi2->pdata = pdata; 1068 dsi2->id = id; 1069 dsi2->data_swap = dev_read_bool(dsi2->dev, "rockchip,data-swap"); 1070 1071 return 0; 1072 } 1073 1074 static const u32 rk3588_dsi0_grf_reg_fields[MAX_FIELDS] = { 1075 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0000, 11, 11), 1076 [GATING_EN] = GRF_REG_FIELD(0x0000, 10, 10), 1077 [IPI_SHUTDN] = GRF_REG_FIELD(0x0000, 9, 9), 1078 [IPI_COLORM] = GRF_REG_FIELD(0x0000, 8, 8), 1079 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0000, 4, 7), 1080 [IPI_FORMAT] = GRF_REG_FIELD(0x0000, 0, 3), 1081 }; 1082 1083 static const u32 rk3588_dsi1_grf_reg_fields[MAX_FIELDS] = { 1084 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0004, 11, 11), 1085 [GATING_EN] = GRF_REG_FIELD(0x0004, 10, 10), 1086 [IPI_SHUTDN] = GRF_REG_FIELD(0x0004, 9, 9), 1087 [IPI_COLORM] = GRF_REG_FIELD(0x0004, 8, 8), 1088 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0004, 4, 7), 1089 [IPI_FORMAT] = GRF_REG_FIELD(0x0004, 0, 3), 1090 }; 1091 1092 static const struct dw_mipi_dsi2_plat_data rk3588_mipi_dsi2_plat_data = { 1093 .dsi0_grf_reg_fields = rk3588_dsi0_grf_reg_fields, 1094 .dsi1_grf_reg_fields = rk3588_dsi1_grf_reg_fields, 1095 .dphy_max_bit_rate_per_lane = 4500000000ULL, 1096 .cphy_max_symbol_rate_per_lane = 2000000000ULL, 1097 }; 1098 static const struct rockchip_connector rk3588_mipi_dsi2_driver_data = { 1099 .funcs = &dw_mipi_dsi2_connector_funcs, 1100 .data = &rk3588_mipi_dsi2_plat_data, 1101 }; 1102 1103 static const struct udevice_id dw_mipi_dsi2_ids[] = { 1104 { 1105 .compatible = "rockchip,rk3588-mipi-dsi2", 1106 .data = (ulong)&rk3588_mipi_dsi2_driver_data, 1107 }, 1108 {} 1109 }; 1110 1111 static ssize_t dw_mipi_dsi2_host_transfer(struct mipi_dsi_host *host, 1112 const struct mipi_dsi_msg *msg) 1113 { 1114 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1115 1116 return dw_mipi_dsi2_transfer(dsi2, msg); 1117 } 1118 1119 static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2) 1120 { 1121 struct udevice *dev = NULL; 1122 int ret; 1123 1124 ret = device_find_first_child(dsi2->dev, &dev); 1125 if (ret) 1126 return ret; 1127 1128 dsi2->c_option = dev_read_bool(dev, "phy-c-option"); 1129 dsi2->scrambling_en = dev_read_bool(dev, "scrambling-enable"); 1130 dsi2->dsc_enable = dev_read_bool(dev, "compressed-data"); 1131 1132 if (dsi2->slave) { 1133 dsi2->slave->c_option = dsi2->c_option; 1134 dsi2->slave->scrambling_en = dsi2->scrambling_en; 1135 dsi2->slave->dsc_enable = dsi2->dsc_enable; 1136 } 1137 1138 dsi2->slice_width = dev_read_u32_default(dev, "slice_width", 0); 1139 dsi2->slice_height = dev_read_u32_default(dev, "slice_height", 0); 1140 dsi2->version_major = dev_read_u32_default(dev, "version_major", 0); 1141 dsi2->version_minor = dev_read_u32_default(dev, "version_minor", 0); 1142 1143 return 0; 1144 } 1145 1146 static int dw_mipi_dsi2_host_attach(struct mipi_dsi_host *host, 1147 struct mipi_dsi_device *device) 1148 { 1149 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1150 1151 if (device->lanes < 1 || device->lanes > 8) 1152 return -EINVAL; 1153 1154 dsi2->lanes = device->lanes; 1155 dsi2->channel = device->channel; 1156 dsi2->format = device->format; 1157 dsi2->mode_flags = device->mode_flags; 1158 1159 dw_mipi_dsi2_get_dsc_params_from_sink(dsi2); 1160 1161 return 0; 1162 } 1163 1164 static const struct mipi_dsi_host_ops dw_mipi_dsi2_host_ops = { 1165 .attach = dw_mipi_dsi2_host_attach, 1166 .transfer = dw_mipi_dsi2_host_transfer, 1167 }; 1168 1169 static int dw_mipi_dsi2_bind(struct udevice *dev) 1170 { 1171 struct mipi_dsi_host *host = dev_get_platdata(dev); 1172 1173 host->dev = dev; 1174 host->ops = &dw_mipi_dsi2_host_ops; 1175 1176 return dm_scan_fdt_dev(dev); 1177 } 1178 1179 static int dw_mipi_dsi2_child_post_bind(struct udevice *dev) 1180 { 1181 struct mipi_dsi_host *host = dev_get_platdata(dev->parent); 1182 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1183 char name[20]; 1184 1185 sprintf(name, "%s.%d", host->dev->name, device->channel); 1186 device_set_name(dev, name); 1187 1188 device->dev = dev; 1189 device->host = host; 1190 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4); 1191 device->format = dev_read_u32_default(dev, "dsi,format", 1192 MIPI_DSI_FMT_RGB888); 1193 device->mode_flags = dev_read_u32_default(dev, "dsi,flags", 1194 MIPI_DSI_MODE_VIDEO | 1195 MIPI_DSI_MODE_VIDEO_BURST | 1196 MIPI_DSI_MODE_VIDEO_HBP | 1197 MIPI_DSI_MODE_LPM | 1198 MIPI_DSI_MODE_EOT_PACKET); 1199 device->channel = dev_read_u32_default(dev, "reg", 0); 1200 1201 return 0; 1202 } 1203 1204 static int dw_mipi_dsi2_child_pre_probe(struct udevice *dev) 1205 { 1206 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1207 int ret; 1208 1209 ret = mipi_dsi_attach(device); 1210 if (ret) { 1211 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret); 1212 return ret; 1213 } 1214 1215 return 0; 1216 } 1217 1218 U_BOOT_DRIVER(dw_mipi_dsi2) = { 1219 .name = "dw_mipi_dsi2", 1220 .id = UCLASS_DISPLAY, 1221 .of_match = dw_mipi_dsi2_ids, 1222 .probe = dw_mipi_dsi2_probe, 1223 .bind = dw_mipi_dsi2_bind, 1224 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi2), 1225 .per_child_platdata_auto_alloc_size = sizeof(struct mipi_dsi_device), 1226 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_host), 1227 .child_post_bind = dw_mipi_dsi2_child_post_bind, 1228 .child_pre_probe = dw_mipi_dsi2_child_pre_probe, 1229 }; 1230