1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Author: Guochun Huang <hero.huang@rock-chips.com> 7 */ 8 9 #include <drm/drm_mipi_dsi.h> 10 11 #include <config.h> 12 #include <common.h> 13 #include <errno.h> 14 #include <asm/unaligned.h> 15 #include <asm/io.h> 16 #include <asm/hardware.h> 17 #include <dm/device.h> 18 #include <dm/read.h> 19 #include <dm/of_access.h> 20 #include <regmap.h> 21 #include <syscon.h> 22 #include <asm/arch-rockchip/clock.h> 23 #include <linux/iopoll.h> 24 25 #include "rockchip_display.h" 26 #include "rockchip_crtc.h" 27 #include "rockchip_connector.h" 28 #include "rockchip_panel.h" 29 #include "rockchip_phy.h" 30 31 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) 32 33 #define DSI2_PWR_UP 0x000c 34 #define RESET 0 35 #define POWER_UP BIT(0) 36 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 37 #define DSI2_SOFT_RESET 0x0010 38 #define SYS_RSTN BIT(2) 39 #define PHY_RSTN BIT(1) 40 #define IPI_RSTN BIT(0) 41 #define INT_ST_MAIN 0x0014 42 #define DSI2_MODE_CTRL 0x0018 43 #define DSI2_MODE_STATUS 0x001c 44 #define DSI2_CORE_STATUS 0x0020 45 #define PRI_RD_DATA_AVAIL BIT(26) 46 #define PRI_FIFOS_NOT_EMPTY BIT(25) 47 #define PRI_BUSY BIT(24) 48 #define CRI_RD_DATA_AVAIL BIT(18) 49 #define CRT_FIFOS_NOT_EMPTY BIT(17) 50 #define CRI_BUSY BIT(16) 51 #define IPI_FIFOS_NOT_EMPTY BIT(9) 52 #define IPI_BUSY BIT(8) 53 #define CORE_FIFOS_NOT_EMPTY BIT(1) 54 #define CORE_BUSY BIT(0) 55 #define MANUAL_MODE_CFG 0x0024 56 #define MANUAL_MODE_EN BIT(0) 57 #define DSI2_TIMEOUT_HSTX_CFG 0x0048 58 #define TO_HSTX(x) UPDATE(x, 15, 0) 59 #define DSI2_TIMEOUT_HSTXRDY_CFG 0x004c 60 #define TO_HSTXRDY(x) UPDATE(x, 15, 0) 61 #define DSI2_TIMEOUT_LPRX_CFG 0x0050 62 #define TO_LPRXRDY(x) UPDATE(x, 15, 0) 63 #define DSI2_TIMEOUT_LPTXRDY_CFG 0x0054 64 #define TO_LPTXRDY(x) UPDATE(x, 15, 0) 65 #define DSI2_TIMEOUT_LPTXTRIG_CFG 0x0058 66 #define TO_LPTXTRIG(x) UPDATE(x, 15, 0) 67 #define DSI2_TIMEOUT_LPTXULPS_CFG 0x005c 68 #define TO_LPTXULPS(x) UPDATE(x, 15, 0) 69 #define DSI2_TIMEOUT_BTA_CFG 0x60 70 #define TO_BTA(x) UPDATE(x, 15, 0) 71 72 #define DSI2_PHY_MODE_CFG 0x0100 73 #define PPI_WIDTH(x) UPDATE(x, 9, 8) 74 #define PHY_LANES(x) UPDATE(x - 1, 5, 4) 75 #define PHY_TYPE(x) UPDATE(x, 0, 0) 76 #define DSI2_PHY_CLK_CFG 0X0104 77 #define PHY_LPTX_CLK_DIV(x) UPDATE(x, 12, 8) 78 #define NON_CONTINUOUS_CLK BIT(0) 79 #define DSI2_PHY_LP2HS_MAN_CFG 0x010c 80 #define PHY_LP2HS_TIME(x) UPDATE(x, 28, 0) 81 #define DSI2_PHY_HS2LP_MAN_CFG 0x0114 82 #define PHY_HS2LP_TIME(x) UPDATE(x, 28, 0) 83 #define DSI2_PHY_MAX_RD_T_MAN_CFG 0x011c 84 #define PHY_MAX_RD_TIME(x) UPDATE(x, 26, 0) 85 #define DSI2_PHY_ESC_CMD_T_MAN_CFG 0x0124 86 #define PHY_ESC_CMD_TIME(x) UPDATE(x, 28, 0) 87 #define DSI2_PHY_ESC_BYTE_T_MAN_CFG 0x012c 88 #define PHY_ESC_BYTE_TIME(x) UPDATE(x, 28, 0) 89 90 #define DSI2_PHY_IPI_RATIO_MAN_CFG 0x0134 91 #define PHY_IPI_RATIO(x) UPDATE(x, 21, 0) 92 #define DSI2_PHY_SYS_RATIO_MAN_CFG 0x013C 93 #define PHY_SYS_RATIO(x) UPDATE(x, 16, 0) 94 95 #define DSI2_DSI_GENERAL_CFG 0x0200 96 #define BTA_EN BIT(1) 97 #define EOTP_TX_EN BIT(0) 98 #define DSI2_DSI_VCID_CFG 0x0204 99 #define TX_VCID(x) UPDATE(x, 1, 0) 100 #define DSI2_DSI_SCRAMBLING_CFG 0x0208 101 #define SCRAMBLING_SEED(x) UPDATE(x, 31, 16) 102 #define SCRAMBLING_EN BIT(0) 103 #define DSI2_DSI_VID_TX_CFG 0x020c 104 #define LPDT_DISPLAY_CMD_EN BIT(20) 105 #define BLK_VFP_HS_EN BIT(14) 106 #define BLK_VBP_HS_EN BIT(13) 107 #define BLK_VSA_HS_EN BIT(12) 108 #define BLK_HFP_HS_EN BIT(6) 109 #define BLK_HBP_HS_EN BIT(5) 110 #define BLK_HSA_HS_EN BIT(4) 111 #define VID_MODE_TYPE(x) UPDATE(x, 1, 0) 112 #define DSI2_CRI_TX_HDR 0x02c0 113 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 114 #define DSI2_CRI_TX_PLD 0x02c4 115 #define DSI2_CRI_RX_HDR 0x02c8 116 #define DSI2_CRI_RX_PLD 0x02cc 117 118 #define DSI2_IPI_COLOR_MAN_CFG 0x0300 119 #define IPI_DEPTH(x) UPDATE(x, 7, 4) 120 #define IPI_DEPTH_5_6_5_BITS 0x02 121 #define IPI_DEPTH_6_BITS 0x03 122 #define IPI_DEPTH_8_BITS 0x05 123 #define IPI_DEPTH_10_BITS 0x06 124 #define IPI_FORMAT(x) UPDATE(x, 3, 0) 125 #define IPI_FORMAT_RGB 0x0 126 #define IPI_FORMAT_DSC 0x0b 127 #define DSI2_IPI_VID_HSA_MAN_CFG 0x0304 128 #define VID_HSA_TIME(x) UPDATE(x, 29, 0) 129 #define DSI2_IPI_VID_HBP_MAN_CFG 0x030c 130 #define VID_HBP_TIME(x) UPDATE(x, 29, 0) 131 #define DSI2_IPI_VID_HACT_MAN_CFG 0x0314 132 #define VID_HACT_TIME(x) UPDATE(x, 29, 0) 133 #define DSI2_IPI_VID_HLINE_MAN_CFG 0x031c 134 #define VID_HLINE_TIME(x) UPDATE(x, 29, 0) 135 #define DSI2_IPI_VID_VSA_MAN_CFG 0x0324 136 #define VID_VSA_LINES(x) UPDATE(x, 9, 0) 137 #define DSI2_IPI_VID_VBP_MAN_CFG 0X032C 138 #define VID_VBP_LINES(x) UPDATE(x, 9, 0) 139 #define DSI2_IPI_VID_VACT_MAN_CFG 0X0334 140 #define VID_VACT_LINES(x) UPDATE(x, 13, 0) 141 #define DSI2_IPI_VID_VFP_MAN_CFG 0X033C 142 #define VID_VFP_LINES(x) UPDATE(x, 9, 0) 143 #define DSI2_IPI_PIX_PKT_CFG 0x0344 144 #define MAX_PIX_PKT(x) UPDATE(x, 15, 0) 145 146 #define DSI2_INT_ST_PHY 0x0400 147 #define DSI2_INT_MASK_PHY 0x0404 148 #define DSI2_INT_ST_TO 0x0410 149 #define DSI2_INT_MASK_TO 0x0414 150 #define DSI2_INT_ST_ACK 0x0420 151 #define DSI2_INT_MASK_ACK 0x0424 152 #define DSI2_INT_ST_IPI 0x0430 153 #define DSI2_INT_MASK_IPI 0x0434 154 #define DSI2_INT_ST_FIFO 0x0440 155 #define DSI2_INT_MASK_FIFO 0x0444 156 #define DSI2_INT_ST_PRI 0x0450 157 #define DSI2_INT_MASK_PRI 0x0454 158 #define DSI2_INT_ST_CRI 0x0460 159 #define DSI2_INT_MASK_CRI 0x0464 160 #define DSI2_INT_FORCE_CRI 0x0468 161 #define DSI2_MAX_REGISGER DSI2_INT_FORCE_CRI 162 163 #define CMD_PKT_STATUS_TIMEOUT_US 1000 164 #define MODE_STATUS_TIMEOUT_US 20000 165 #define SYS_CLK 351000000LL 166 #define PSEC_PER_SEC 1000000000000LL 167 #define USEC_PER_SEC 1000000L 168 #define MSEC_PER_SEC 1000L 169 170 #define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 16) | ((lsb) << 8) | (msb)) 171 172 enum vid_mode_type { 173 VID_MODE_TYPE_NON_BURST_SYNC_PULSES, 174 VID_MODE_TYPE_NON_BURST_SYNC_EVENTS, 175 VID_MODE_TYPE_BURST, 176 }; 177 178 enum mode_ctrl { 179 IDLE_MODE, 180 AUTOCALC_MODE, 181 COMMAND_MODE, 182 VIDEO_MODE, 183 DATA_STREAM_MODE, 184 VIDE_TEST_MODE, 185 DATA_STREAM_TEST_MODE, 186 }; 187 188 enum grf_reg_fields { 189 TXREQCLKHS_EN, 190 GATING_EN, 191 IPI_SHUTDN, 192 IPI_COLORM, 193 IPI_COLOR_DEPTH, 194 IPI_FORMAT, 195 MAX_FIELDS, 196 }; 197 198 enum phy_type { 199 DPHY, 200 CPHY, 201 }; 202 203 enum ppi_width { 204 PPI_WIDTH_8_BITS, 205 PPI_WIDTH_16_BITS, 206 PPI_WIDTH_32_BITS, 207 }; 208 209 struct rockchip_cmd_header { 210 u8 data_type; 211 u8 delay_ms; 212 u8 payload_length; 213 }; 214 215 struct dw_mipi_dsi2_plat_data { 216 const u32 *dsi0_grf_reg_fields; 217 const u32 *dsi1_grf_reg_fields; 218 unsigned long long dphy_max_bit_rate_per_lane; 219 unsigned long long cphy_max_symbol_rate_per_lane; 220 }; 221 222 struct mipi_dcphy { 223 /* Non-SNPS PHY */ 224 struct rockchip_phy *phy; 225 226 u16 input_div; 227 u16 feedback_div; 228 }; 229 230 /** 231 * struct mipi_dphy_configure - MIPI D-PHY configuration set 232 * 233 * This structure is used to represent the configuration state of a 234 * MIPI D-PHY phy. 235 */ 236 struct mipi_dphy_configure { 237 unsigned int clk_miss; 238 unsigned int clk_post; 239 unsigned int clk_pre; 240 unsigned int clk_prepare; 241 unsigned int clk_settle; 242 unsigned int clk_term_en; 243 unsigned int clk_trail; 244 unsigned int clk_zero; 245 unsigned int d_term_en; 246 unsigned int eot; 247 unsigned int hs_exit; 248 unsigned int hs_prepare; 249 unsigned int hs_settle; 250 unsigned int hs_skip; 251 unsigned int hs_trail; 252 unsigned int hs_zero; 253 unsigned int init; 254 unsigned int lpx; 255 unsigned int ta_get; 256 unsigned int ta_go; 257 unsigned int ta_sure; 258 unsigned int wakeup; 259 unsigned long hs_clk_rate; 260 unsigned long lp_clk_rate; 261 unsigned char lanes; 262 }; 263 264 struct dw_mipi_dsi2 { 265 struct rockchip_connector connector; 266 struct udevice *dev; 267 void *base; 268 void *grf; 269 int id; 270 struct dw_mipi_dsi2 *master; 271 struct dw_mipi_dsi2 *slave; 272 bool prepared; 273 274 bool c_option; 275 bool dsc_enable; 276 bool scrambling_en; 277 unsigned int slice_width; 278 unsigned int slice_height; 279 u32 version_major; 280 u32 version_minor; 281 282 unsigned int lane_hs_rate; /* Kbps/Ksps per lane */ 283 u32 channel; 284 u32 lanes; 285 u32 format; 286 u32 mode_flags; 287 struct mipi_dcphy dcphy; 288 struct drm_display_mode mode; 289 bool data_swap; 290 291 struct mipi_dsi_device *device; 292 struct mipi_dphy_configure mipi_dphy_cfg; 293 const struct dw_mipi_dsi2_plat_data *pdata; 294 struct drm_dsc_picture_parameter_set *pps; 295 }; 296 297 static inline void dsi_write(struct dw_mipi_dsi2 *dsi2, u32 reg, u32 val) 298 { 299 writel(val, dsi2->base + reg); 300 } 301 302 static inline u32 dsi_read(struct dw_mipi_dsi2 *dsi2, u32 reg) 303 { 304 return readl(dsi2->base + reg); 305 } 306 307 static inline void dsi_update_bits(struct dw_mipi_dsi2 *dsi2, 308 u32 reg, u32 mask, u32 val) 309 { 310 u32 orig, tmp; 311 312 orig = dsi_read(dsi2, reg); 313 tmp = orig & ~mask; 314 tmp |= val & mask; 315 dsi_write(dsi2, reg, tmp); 316 } 317 318 static void grf_field_write(struct dw_mipi_dsi2 *dsi2, enum grf_reg_fields index, 319 unsigned int val) 320 { 321 const u32 field = dsi2->id ? dsi2->pdata->dsi1_grf_reg_fields[index] : 322 dsi2->pdata->dsi0_grf_reg_fields[index]; 323 u16 reg; 324 u8 msb, lsb; 325 326 if (!field) 327 return; 328 329 reg = (field >> 16) & 0xffff; 330 lsb = (field >> 8) & 0xff; 331 msb = (field >> 0) & 0xff; 332 333 regmap_write(dsi2->grf, reg, GENMASK(msb, lsb) << 16 | val << lsb); 334 } 335 336 static unsigned long dw_mipi_dsi2_get_lane_rate(struct dw_mipi_dsi2 *dsi2) 337 { 338 const struct drm_display_mode *mode = &dsi2->mode; 339 u64 max_lane_rate, lane_rate; 340 unsigned int value; 341 int bpp, lanes; 342 u64 tmp; 343 344 max_lane_rate = (dsi2->c_option) ? 345 dsi2->pdata->cphy_max_symbol_rate_per_lane : 346 dsi2->pdata->dphy_max_bit_rate_per_lane; 347 348 /* 349 * optional override of the desired bandwidth 350 * High-Speed mode: Differential and terminated: 80Mbps ~ 4500 Mbps 351 */ 352 value = dev_read_u32_default(dsi2->dev, "rockchip,lane-rate", 0); 353 if (value >= 80000 && value <= 4500000) 354 return value * MSEC_PER_SEC; 355 else if (value >= 80 && value <= 4500) 356 return value * USEC_PER_SEC; 357 358 bpp = mipi_dsi_pixel_format_to_bpp(dsi2->format); 359 if (bpp < 0) 360 bpp = 24; 361 362 lanes = dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes; 363 tmp = (u64)mode->crtc_clock * 1000 * bpp; 364 do_div(tmp, lanes); 365 366 if (dsi2->c_option) 367 tmp = DIV_ROUND_CLOSEST(tmp * 100, 228); 368 369 /* set BW a little larger only in video burst mode in 370 * consideration of the protocol overhead and HS mode 371 * switching to BLLP mode, take 1 / 0.9, since Mbps must 372 * big than bandwidth of RGB 373 */ 374 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { 375 tmp *= 10; 376 do_div(tmp, 9); 377 } 378 379 if (tmp > max_lane_rate) 380 lane_rate = max_lane_rate; 381 else 382 lane_rate = tmp; 383 384 return lane_rate; 385 } 386 387 static int cri_fifos_wait_avail(struct dw_mipi_dsi2 *dsi2) 388 { 389 u32 sts, mask; 390 int ret; 391 392 mask = CRI_BUSY | CRT_FIFOS_NOT_EMPTY; 393 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 394 sts, !(sts & mask), 395 CMD_PKT_STATUS_TIMEOUT_US); 396 if (ret < 0) { 397 printf("command interface is busy: 0x%x\n", sts); 398 return ret; 399 } 400 401 return 0; 402 } 403 404 static int dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 *dsi2, 405 const struct mipi_dsi_msg *msg) 406 { 407 u8 *payload = msg->rx_buf; 408 u8 data_type; 409 u16 wc; 410 int i, j, ret, len = msg->rx_len; 411 unsigned int vrefresh = drm_mode_vrefresh(&dsi2->mode); 412 u32 val; 413 414 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 415 val, val & CRI_RD_DATA_AVAIL, 416 DIV_ROUND_UP(1000000, vrefresh)); 417 if (ret) { 418 printf("CRI has no available read data\n"); 419 return ret; 420 } 421 422 val = dsi_read(dsi2, DSI2_CRI_RX_HDR); 423 data_type = val & 0x3f; 424 425 if (mipi_dsi_packet_format_is_short(data_type)) { 426 for (i = 0; i < len && i < 2; i++) 427 payload[i] = (val >> (8 * (i + 1))) & 0xff; 428 429 return 0; 430 } 431 432 wc = (val >> 8) & 0xffff; 433 /* Receive payload */ 434 for (i = 0; i < len && i < wc; i += 4) { 435 val = dsi_read(dsi2, DSI2_CRI_RX_PLD); 436 for (j = 0; j < 4 && j + i < len && j + i < wc; j++) 437 payload[i + j] = val >> (8 * j); 438 } 439 440 return 0; 441 } 442 443 static ssize_t dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 *dsi2, 444 const struct mipi_dsi_msg *msg) 445 { 446 struct mipi_dsi_packet packet; 447 int ret; 448 int val; 449 u32 mode; 450 451 dsi_update_bits(dsi2, DSI2_DSI_VID_TX_CFG, LPDT_DISPLAY_CMD_EN, 452 msg->flags & MIPI_DSI_MSG_USE_LPM ? 453 LPDT_DISPLAY_CMD_EN : 0); 454 455 /* create a packet to the DSI protocol */ 456 ret = mipi_dsi_create_packet(&packet, msg); 457 if (ret) { 458 printf("failed to create packet: %d\n", ret); 459 return ret; 460 } 461 462 /* check cri interface is not busy */ 463 ret = cri_fifos_wait_avail(dsi2); 464 if (ret) 465 return ret; 466 467 /* Send payload */ 468 while (DIV_ROUND_UP(packet.payload_length, 4)) { 469 if (packet.payload_length < 4) { 470 /* send residu payload */ 471 val = 0; 472 memcpy(&val, packet.payload, packet.payload_length); 473 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 474 packet.payload_length = 0; 475 } else { 476 val = get_unaligned_le32(packet.payload); 477 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 478 packet.payload += 4; 479 packet.payload_length -= 4; 480 } 481 } 482 483 /* Send packet header */ 484 mode = CMD_TX_MODE(msg->flags & MIPI_DSI_MSG_USE_LPM ? 1 : 0); 485 val = get_unaligned_le32(packet.header); 486 dsi_write(dsi2, DSI2_CRI_TX_HDR, mode | val); 487 488 ret = cri_fifos_wait_avail(dsi2); 489 if (ret) 490 return ret; 491 492 if (msg->rx_len) { 493 ret = dw_mipi_dsi2_read_from_fifo(dsi2, msg); 494 if (ret < 0) 495 return ret; 496 } 497 498 if (dsi2->slave) { 499 ret = dw_mipi_dsi2_transfer(dsi2->slave, msg); 500 if (ret < 0) 501 return ret; 502 } 503 504 return msg->rx_len ? msg->rx_len : msg->tx_len; 505 } 506 507 static void dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 *dsi2) 508 { 509 u32 val, color_depth; 510 511 switch (dsi2->format) { 512 case MIPI_DSI_FMT_RGB666: 513 case MIPI_DSI_FMT_RGB666_PACKED: 514 color_depth = IPI_DEPTH_6_BITS; 515 break; 516 case MIPI_DSI_FMT_RGB565: 517 color_depth = IPI_DEPTH_5_6_5_BITS; 518 break; 519 case MIPI_DSI_FMT_RGB888: 520 default: 521 color_depth = IPI_DEPTH_8_BITS; 522 break; 523 } 524 525 val = IPI_DEPTH(color_depth) | 526 IPI_FORMAT(dsi2->dsc_enable ? IPI_FORMAT_DSC : IPI_FORMAT_RGB); 527 dsi_write(dsi2, DSI2_IPI_COLOR_MAN_CFG, val); 528 grf_field_write(dsi2, IPI_COLOR_DEPTH, color_depth); 529 530 if (dsi2->dsc_enable) 531 grf_field_write(dsi2, IPI_FORMAT, IPI_FORMAT_DSC); 532 } 533 534 static void dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 *dsi2) 535 { 536 struct drm_display_mode *mode = &dsi2->mode; 537 u32 hline, hsa, hbp, hact; 538 u64 hline_time, hsa_time, hbp_time, hact_time, tmp; 539 u64 pixel_clk, phy_hs_clk; 540 u32 vact, vsa, vfp, vbp; 541 u16 val; 542 543 if (dsi2->slave || dsi2->master) 544 val = mode->hdisplay / 2; 545 else 546 val = mode->hdisplay; 547 548 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val)); 549 550 dw_mipi_dsi2_ipi_color_coding_cfg(dsi2); 551 552 /* 553 * if the controller is intended to operate in data stream mode, 554 * no more steps are required. 555 */ 556 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) 557 return; 558 559 vact = mode->vdisplay; 560 vsa = mode->vsync_end - mode->vsync_start; 561 vfp = mode->vsync_start - mode->vdisplay; 562 vbp = mode->vtotal - mode->vsync_end; 563 hact = mode->hdisplay; 564 hsa = mode->hsync_end - mode->hsync_start; 565 hbp = mode->htotal - mode->hsync_end; 566 hline = mode->htotal; 567 568 pixel_clk = mode->crtc_clock * MSEC_PER_SEC; 569 570 if (dsi2->c_option) 571 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 572 else 573 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 574 575 tmp = hsa * phy_hs_clk; 576 hsa_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 577 dsi_write(dsi2, DSI2_IPI_VID_HSA_MAN_CFG, VID_HSA_TIME(hsa_time)); 578 579 tmp = hbp * phy_hs_clk; 580 hbp_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 581 dsi_write(dsi2, DSI2_IPI_VID_HBP_MAN_CFG, VID_HBP_TIME(hbp_time)); 582 583 tmp = hact * phy_hs_clk; 584 hact_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 585 dsi_write(dsi2, DSI2_IPI_VID_HACT_MAN_CFG, VID_HACT_TIME(hact_time)); 586 587 tmp = hline * phy_hs_clk; 588 hline_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 589 dsi_write(dsi2, DSI2_IPI_VID_HLINE_MAN_CFG, VID_HLINE_TIME(hline_time)); 590 591 dsi_write(dsi2, DSI2_IPI_VID_VSA_MAN_CFG, VID_VSA_LINES(vsa)); 592 dsi_write(dsi2, DSI2_IPI_VID_VBP_MAN_CFG, VID_VBP_LINES(vbp)); 593 dsi_write(dsi2, DSI2_IPI_VID_VACT_MAN_CFG, VID_VACT_LINES(vact)); 594 dsi_write(dsi2, DSI2_IPI_VID_VFP_MAN_CFG, VID_VFP_LINES(vfp)); 595 } 596 597 static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2) 598 { 599 u32 val = 0, mode; 600 int ret; 601 602 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) 603 val |= BLK_HFP_HS_EN; 604 605 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) 606 val |= BLK_HBP_HS_EN; 607 608 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HSA) 609 val |= BLK_HSA_HS_EN; 610 611 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 612 val |= VID_MODE_TYPE_BURST; 613 else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 614 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 615 else 616 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 617 618 dsi_write(dsi2, DSI2_DSI_VID_TX_CFG, val); 619 620 dsi_write(dsi2, DSI2_MODE_CTRL, VIDEO_MODE); 621 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 622 mode, mode & VIDEO_MODE, 623 MODE_STATUS_TIMEOUT_US); 624 if (ret < 0) 625 printf("failed to enter video mode\n"); 626 } 627 628 static void dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 *dsi2) 629 { 630 u32 mode; 631 int ret; 632 633 dsi_write(dsi2, DSI2_MODE_CTRL, DATA_STREAM_MODE); 634 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 635 mode, mode & DATA_STREAM_MODE, 636 MODE_STATUS_TIMEOUT_US); 637 if (ret < 0) 638 printf("failed to enter data stream mode\n"); 639 } 640 641 static void dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 *dsi2) 642 { 643 u32 mode; 644 int ret; 645 646 dsi_write(dsi2, DSI2_MODE_CTRL, COMMAND_MODE); 647 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 648 mode, mode & COMMAND_MODE, 649 MODE_STATUS_TIMEOUT_US); 650 if (ret < 0) 651 printf("failed to enter cmd mode\n"); 652 } 653 654 static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2) 655 { 656 dw_mipi_dsi2_ipi_set(dsi2); 657 658 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO) 659 dw_mipi_dsi2_set_vid_mode(dsi2); 660 else 661 dw_mipi_dsi2_set_data_stream_mode(dsi2); 662 663 if (dsi2->slave) 664 dw_mipi_dsi2_enable(dsi2->slave); 665 } 666 667 static void dw_mipi_dsi2_disable(struct dw_mipi_dsi2 *dsi2) 668 { 669 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, 0); 670 dw_mipi_dsi2_set_cmd_mode(dsi2); 671 672 if (dsi2->slave) 673 dw_mipi_dsi2_disable(dsi2->slave); 674 } 675 676 static void dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 *dsi2) 677 { 678 if (!dsi2->prepared) 679 return; 680 681 dsi_write(dsi2, DSI2_PWR_UP, RESET); 682 683 if (dsi2->dcphy.phy) 684 rockchip_phy_power_off(dsi2->dcphy.phy); 685 686 dsi2->prepared = false; 687 688 if (dsi2->slave) 689 dw_mipi_dsi2_post_disable(dsi2->slave); 690 } 691 692 static int dw_mipi_dsi2_connector_pre_init(struct rockchip_connector *conn, 693 struct display_state *state) 694 { 695 struct connector_state *conn_state = &state->conn_state; 696 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 697 struct mipi_dsi_host *host = dev_get_platdata(dsi2->dev); 698 struct mipi_dsi_device *device; 699 char name[20]; 700 701 conn_state->type = DRM_MODE_CONNECTOR_DSI; 702 703 if (conn->bridge) { 704 device = dev_get_platdata(conn->bridge->dev); 705 if (!device) 706 return -ENODEV; 707 708 device->host = host; 709 sprintf(name, "%s.%d", host->dev->name, device->channel); 710 device_set_name(conn->bridge->dev, name); 711 mipi_dsi_attach(device); 712 } 713 714 return 0; 715 } 716 717 static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2) 718 { 719 struct udevice *dev = dsi2->device->dev; 720 struct rockchip_cmd_header *header; 721 struct drm_dsc_picture_parameter_set *pps = NULL; 722 u8 *dsc_packed_pps; 723 const void *data; 724 int len; 725 726 dsi2->c_option = dev_read_bool(dev, "phy-c-option"); 727 dsi2->scrambling_en = dev_read_bool(dev, "scrambling-enable"); 728 dsi2->dsc_enable = dev_read_bool(dev, "compressed-data"); 729 730 if (dsi2->slave) { 731 dsi2->slave->c_option = dsi2->c_option; 732 dsi2->slave->scrambling_en = dsi2->scrambling_en; 733 dsi2->slave->dsc_enable = dsi2->dsc_enable; 734 } 735 736 dsi2->slice_width = dev_read_u32_default(dev, "slice-width", 0); 737 dsi2->slice_height = dev_read_u32_default(dev, "slice-height", 0); 738 dsi2->version_major = dev_read_u32_default(dev, "version-major", 0); 739 dsi2->version_minor = dev_read_u32_default(dev, "version-minor", 0); 740 741 data = dev_read_prop(dev, "panel-init-sequence", &len); 742 if (!data) 743 return -EINVAL; 744 745 while (len > sizeof(*header)) { 746 header = (struct rockchip_cmd_header *)data; 747 data += sizeof(*header); 748 len -= sizeof(*header); 749 750 if (header->payload_length > len) 751 return -EINVAL; 752 753 if (header->data_type == MIPI_DSI_PICTURE_PARAMETER_SET) { 754 dsc_packed_pps = calloc(1, header->payload_length); 755 if (!dsc_packed_pps) 756 return -ENOMEM; 757 758 memcpy(dsc_packed_pps, data, header->payload_length); 759 pps = (struct drm_dsc_picture_parameter_set *)dsc_packed_pps; 760 break; 761 } 762 763 data += header->payload_length; 764 len -= header->payload_length; 765 } 766 767 dsi2->pps = pps; 768 769 return 0; 770 } 771 772 static int dw_mipi_dsi2_connector_init(struct rockchip_connector *conn, struct display_state *state) 773 { 774 struct connector_state *conn_state = &state->conn_state; 775 struct crtc_state *cstate = &state->crtc_state; 776 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 777 struct rockchip_phy *phy = NULL; 778 struct udevice *phy_dev; 779 struct udevice *dev; 780 int ret; 781 782 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dsi2->id); 783 dsi2->dcphy.phy = conn->phy; 784 785 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 786 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 787 conn_state->output_if |= 788 dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0; 789 790 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) { 791 conn_state->output_flags |= ROCKCHIP_OUTPUT_MIPI_DS_MODE; 792 conn_state->hold_mode = true; 793 } 794 795 if (dsi2->lanes > 4) { 796 ret = uclass_get_device_by_name(UCLASS_DISPLAY, 797 "dsi@fde30000", 798 &dev); 799 if (ret) 800 return ret; 801 802 dsi2->slave = dev_get_priv(dev); 803 if (!dsi2->slave) 804 return -ENODEV; 805 806 dsi2->slave->master = dsi2; 807 dsi2->lanes /= 2; 808 dsi2->slave->lanes = dsi2->lanes; 809 dsi2->slave->format = dsi2->format; 810 dsi2->slave->mode_flags = dsi2->mode_flags; 811 dsi2->slave->channel = dsi2->channel; 812 conn_state->output_flags |= 813 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; 814 if (dsi2->data_swap) 815 conn_state->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP; 816 817 conn_state->output_if |= VOP_OUTPUT_IF_MIPI1; 818 819 ret = uclass_get_device_by_phandle(UCLASS_PHY, dev, 820 "phys", &phy_dev); 821 if (ret) 822 return -ENODEV; 823 824 phy = (struct rockchip_phy *)dev_get_driver_data(phy_dev); 825 if (!phy) 826 return -ENODEV; 827 828 dsi2->slave->dcphy.phy = phy; 829 if (phy->funcs && phy->funcs->init) 830 return phy->funcs->init(phy); 831 } 832 833 dw_mipi_dsi2_get_dsc_params_from_sink(dsi2); 834 835 if (dsi2->dsc_enable) { 836 cstate->dsc_enable = 1; 837 cstate->dsc_sink_cap.version_major = dsi2->version_major; 838 cstate->dsc_sink_cap.version_minor = dsi2->version_minor; 839 cstate->dsc_sink_cap.slice_width = dsi2->slice_width; 840 cstate->dsc_sink_cap.slice_height = dsi2->slice_height; 841 /* only can support rgb888 panel now */ 842 cstate->dsc_sink_cap.target_bits_per_pixel_x16 = 8 << 4; 843 cstate->dsc_sink_cap.native_420 = 0; 844 memcpy(&cstate->pps, dsi2->pps, sizeof(struct drm_dsc_picture_parameter_set)); 845 } 846 847 return 0; 848 } 849 850 /* 851 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived 852 * from the valid ranges specified in Section 6.9, Table 14, Page 41 853 * of the D-PHY specification (v2.1). 854 */ 855 int mipi_dphy_get_default_config(unsigned long long hs_clk_rate, 856 struct mipi_dphy_configure *cfg) 857 { 858 unsigned long long ui; 859 860 if (!cfg) 861 return -EINVAL; 862 863 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); 864 do_div(ui, hs_clk_rate); 865 866 cfg->clk_miss = 0; 867 cfg->clk_post = 60000 + 52 * ui; 868 cfg->clk_pre = 8000; 869 cfg->clk_prepare = 38000; 870 cfg->clk_settle = 95000; 871 cfg->clk_term_en = 0; 872 cfg->clk_trail = 60000; 873 cfg->clk_zero = 262000; 874 cfg->d_term_en = 0; 875 cfg->eot = 0; 876 cfg->hs_exit = 100000; 877 cfg->hs_prepare = 40000 + 4 * ui; 878 cfg->hs_zero = 105000 + 6 * ui; 879 cfg->hs_settle = 85000 + 6 * ui; 880 cfg->hs_skip = 40000; 881 882 /* 883 * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40) 884 * contains this formula as: 885 * 886 * T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui) 887 * 888 * where n = 1 for forward-direction HS mode and n = 4 for reverse- 889 * direction HS mode. There's only one setting and this function does 890 * not parameterize on anything other that ui, so this code will 891 * assumes that reverse-direction HS mode is supported and uses n = 4. 892 */ 893 cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui); 894 895 cfg->init = 100; 896 cfg->lpx = 60000; 897 cfg->ta_get = 5 * cfg->lpx; 898 cfg->ta_go = 4 * cfg->lpx; 899 cfg->ta_sure = 2 * cfg->lpx; 900 cfg->wakeup = 1000; 901 902 return 0; 903 } 904 905 static void dw_mipi_dsi2_set_hs_clk(struct dw_mipi_dsi2 *dsi2, unsigned long rate) 906 { 907 mipi_dphy_get_default_config(rate, &dsi2->mipi_dphy_cfg); 908 909 if (!dsi2->c_option) 910 rockchip_phy_set_mode(dsi2->dcphy.phy, PHY_MODE_MIPI_DPHY); 911 912 rate = rockchip_phy_set_pll(dsi2->dcphy.phy, rate); 913 dsi2->lane_hs_rate = DIV_ROUND_CLOSEST(rate, MSEC_PER_SEC); 914 } 915 916 static void dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 *dsi2) 917 { 918 dsi_write(dsi2, DSI2_SOFT_RESET, 0X0); 919 udelay(100); 920 dsi_write(dsi2, DSI2_SOFT_RESET, SYS_RSTN | PHY_RSTN | IPI_RSTN); 921 } 922 923 static void 924 dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 *dsi2, u32 mode) 925 { 926 /* 927 * select controller work in Manual mode 928 * Manual: MANUAL_MODE_EN 929 * Automatic: 0 930 */ 931 dsi_write(dsi2, MANUAL_MODE_CFG, mode); 932 } 933 934 static void dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 *dsi2) 935 { 936 u32 val = 0; 937 938 /* PPI width is fixed to 16 bits in DCPHY */ 939 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes); 940 val |= PHY_TYPE(dsi2->c_option ? CPHY : DPHY); 941 dsi_write(dsi2, DSI2_PHY_MODE_CFG, val); 942 } 943 944 static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2) 945 { 946 u32 sys_clk = SYS_CLK / USEC_PER_SEC; 947 u32 esc_clk_div; 948 u32 val = 0; 949 950 if (dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 951 val |= NON_CONTINUOUS_CLK; 952 953 /* The Escape clock ranges from 1MHz to 20MHz. */ 954 esc_clk_div = DIV_ROUND_UP(sys_clk, 20 * 2); 955 val |= PHY_LPTX_CLK_DIV(esc_clk_div); 956 957 dsi_write(dsi2, DSI2_PHY_CLK_CFG, val); 958 } 959 960 static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2) 961 { 962 struct drm_display_mode *mode = &dsi2->mode; 963 u64 pixel_clk, ipi_clk, phy_hsclk, tmp; 964 965 /* 966 * in DPHY mode, the phy_hstx_clk is exactly 1/16 the Lane high-speed 967 * data rate; In CPHY mode, the phy_hstx_clk is exactly 1/7 the trio 968 * high speed symbol rate. 969 */ 970 if (dsi2->c_option) 971 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 972 973 else 974 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 975 976 /* IPI_RATIO_MAN_CFG = PHY_HSTX_CLK / IPI_CLK */ 977 pixel_clk = mode->crtc_clock * MSEC_PER_SEC; 978 ipi_clk = pixel_clk / 4; 979 980 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, ipi_clk); 981 dsi_write(dsi2, DSI2_PHY_IPI_RATIO_MAN_CFG, PHY_IPI_RATIO(tmp)); 982 983 /* SYS_RATIO_MAN_CFG = MIPI_DCPHY_HSCLK_Freq / SYS_CLK */ 984 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, SYS_CLK); 985 dsi_write(dsi2, DSI2_PHY_SYS_RATIO_MAN_CFG, PHY_SYS_RATIO(tmp)); 986 } 987 988 static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2) 989 { 990 struct mipi_dphy_configure *cfg = &dsi2->mipi_dphy_cfg; 991 unsigned long long tmp, ui; 992 unsigned long long hstx_clk; 993 994 hstx_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 995 996 ui = ALIGN(PSEC_PER_SEC, hstx_clk); 997 do_div(ui, hstx_clk); 998 999 /* PHY_LP2HS_TIME = (TLPX + THS-PREPARE + THS-ZERO) / Tphy_hstx_clk */ 1000 tmp = cfg->lpx + cfg->hs_prepare + cfg->hs_zero; 1001 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 1002 dsi_write(dsi2, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(tmp)); 1003 1004 /* PHY_HS2LP_TIME = (THS-TRAIL + THS-EXIT) / Tphy_hstx_clk */ 1005 tmp = cfg->hs_trail + cfg->hs_exit; 1006 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 1007 dsi_write(dsi2, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(tmp)); 1008 } 1009 1010 static void dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 *dsi2) 1011 { 1012 dw_mipi_dsi2_phy_mode_cfg(dsi2); 1013 dw_mipi_dsi2_phy_clk_mode_cfg(dsi2); 1014 dw_mipi_dsi2_phy_ratio_cfg(dsi2); 1015 dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(dsi2); 1016 1017 /* phy configuration 8 - 10 */ 1018 } 1019 1020 static void dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 *dsi2) 1021 { 1022 u32 val; 1023 1024 val = BTA_EN | EOTP_TX_EN; 1025 1026 if (dsi2->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 1027 val &= ~EOTP_TX_EN; 1028 1029 dsi_write(dsi2, DSI2_DSI_GENERAL_CFG, val); 1030 dsi_write(dsi2, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel)); 1031 1032 if (dsi2->scrambling_en) 1033 dsi_write(dsi2, DSI2_DSI_SCRAMBLING_CFG, SCRAMBLING_EN); 1034 } 1035 1036 static void dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 *dsi2, bool enable) 1037 { 1038 if (enable) { 1039 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x1); 1040 dsi_write(dsi2, DSI2_INT_MASK_TO, 0xf); 1041 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x1); 1042 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x1); 1043 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x1); 1044 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x1); 1045 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x1); 1046 } else { 1047 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x0); 1048 dsi_write(dsi2, DSI2_INT_MASK_TO, 0x0); 1049 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x0); 1050 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x0); 1051 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x0); 1052 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x0); 1053 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x0); 1054 }; 1055 } 1056 1057 static void mipi_dcphy_power_on(struct dw_mipi_dsi2 *dsi2) 1058 { 1059 if (!dsi2->dcphy.phy) 1060 return; 1061 1062 rockchip_phy_power_on(dsi2->dcphy.phy); 1063 } 1064 1065 static void dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 *dsi2) 1066 { 1067 if (dsi2->prepared) 1068 return; 1069 1070 dw_mipi_dsi2_host_softrst(dsi2); 1071 dsi_write(dsi2, DSI2_PWR_UP, RESET); 1072 1073 dw_mipi_dsi2_work_mode(dsi2, MANUAL_MODE_EN); 1074 dw_mipi_dsi2_phy_init(dsi2); 1075 dw_mipi_dsi2_tx_option_set(dsi2); 1076 dw_mipi_dsi2_irq_enable(dsi2, 0); 1077 mipi_dcphy_power_on(dsi2); 1078 dsi_write(dsi2, DSI2_PWR_UP, POWER_UP); 1079 dw_mipi_dsi2_set_cmd_mode(dsi2); 1080 1081 dsi2->prepared = true; 1082 1083 if (dsi2->slave) 1084 dw_mipi_dsi2_pre_enable(dsi2->slave); 1085 } 1086 1087 static int dw_mipi_dsi2_connector_prepare(struct rockchip_connector *conn, 1088 struct display_state *state) 1089 { 1090 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1091 struct connector_state *conn_state = &state->conn_state; 1092 unsigned long lane_rate; 1093 1094 memcpy(&dsi2->mode, &conn_state->mode, sizeof(struct drm_display_mode)); 1095 if (dsi2->slave) 1096 memcpy(&dsi2->slave->mode, &dsi2->mode, 1097 sizeof(struct drm_display_mode)); 1098 1099 lane_rate = dw_mipi_dsi2_get_lane_rate(dsi2); 1100 if (dsi2->dcphy.phy) 1101 dw_mipi_dsi2_set_hs_clk(dsi2, lane_rate); 1102 1103 if (dsi2->slave && dsi2->slave->dcphy.phy) 1104 dw_mipi_dsi2_set_hs_clk(dsi2->slave, lane_rate); 1105 1106 printf("final DSI-Link bandwidth: %u %s x %d\n", 1107 dsi2->lane_hs_rate, dsi2->c_option ? "Ksps" : "Kbps", 1108 dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes); 1109 1110 dw_mipi_dsi2_pre_enable(dsi2); 1111 1112 return 0; 1113 } 1114 1115 static void dw_mipi_dsi2_connector_unprepare(struct rockchip_connector *conn, 1116 struct display_state *state) 1117 { 1118 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1119 1120 dw_mipi_dsi2_post_disable(dsi2); 1121 } 1122 1123 static int dw_mipi_dsi2_connector_enable(struct rockchip_connector *conn, 1124 struct display_state *state) 1125 { 1126 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1127 1128 dw_mipi_dsi2_enable(dsi2); 1129 1130 return 0; 1131 } 1132 1133 static int dw_mipi_dsi2_connector_disable(struct rockchip_connector *conn, 1134 struct display_state *state) 1135 { 1136 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1137 1138 dw_mipi_dsi2_disable(dsi2); 1139 1140 return 0; 1141 } 1142 1143 static int dw_mipi_dsi2_connector_mode_valid(struct rockchip_connector *conn, 1144 struct display_state *state) 1145 { 1146 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1147 struct connector_state *conn_state = &state->conn_state; 1148 u8 min_pixels = dsi2->slave ? 8 : 4; 1149 struct videomode vm; 1150 1151 drm_display_mode_to_videomode(&conn_state->mode, &vm); 1152 1153 /* 1154 * the minimum region size (HSA,HBP,HACT,HFP) is 4 pixels 1155 * which is the ip known issues and limitations. 1156 */ 1157 if (!(vm.hsync_len < min_pixels || vm.hback_porch < min_pixels || 1158 vm.hfront_porch < min_pixels || vm.hactive < min_pixels)) 1159 return MODE_OK; 1160 1161 if (vm.hsync_len < min_pixels) 1162 vm.hsync_len = min_pixels; 1163 1164 if (vm.hback_porch < min_pixels) 1165 vm.hback_porch = min_pixels; 1166 1167 if (vm.hfront_porch < min_pixels) 1168 vm.hfront_porch = min_pixels; 1169 1170 if (vm.hactive < min_pixels) 1171 vm.hactive = min_pixels; 1172 1173 drm_display_mode_from_videomode(&vm, &conn_state->mode); 1174 1175 return MODE_OK; 1176 } 1177 1178 static const struct rockchip_connector_funcs dw_mipi_dsi2_connector_funcs = { 1179 .pre_init = dw_mipi_dsi2_connector_pre_init, 1180 .init = dw_mipi_dsi2_connector_init, 1181 .prepare = dw_mipi_dsi2_connector_prepare, 1182 .unprepare = dw_mipi_dsi2_connector_unprepare, 1183 .enable = dw_mipi_dsi2_connector_enable, 1184 .disable = dw_mipi_dsi2_connector_disable, 1185 .mode_valid = dw_mipi_dsi2_connector_mode_valid, 1186 }; 1187 1188 static int dw_mipi_dsi2_probe(struct udevice *dev) 1189 { 1190 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(dev); 1191 const struct dw_mipi_dsi2_plat_data *pdata = 1192 (const struct dw_mipi_dsi2_plat_data *)dev_get_driver_data(dev); 1193 struct udevice *syscon; 1194 int id, ret; 1195 1196 dsi2->base = dev_read_addr_ptr(dev); 1197 1198 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1199 &syscon); 1200 if (!ret) { 1201 dsi2->grf = syscon_get_regmap(syscon); 1202 if (!dsi2->grf) 1203 return -ENODEV; 1204 } 1205 1206 id = of_alias_get_id(ofnode_to_np(dev->node), "dsi"); 1207 if (id < 0) 1208 id = 0; 1209 1210 dsi2->dev = dev; 1211 dsi2->pdata = pdata; 1212 dsi2->id = id; 1213 dsi2->data_swap = dev_read_bool(dsi2->dev, "rockchip,data-swap"); 1214 1215 rockchip_connector_bind(&dsi2->connector, dev, id, &dw_mipi_dsi2_connector_funcs, NULL, 1216 DRM_MODE_CONNECTOR_DSI); 1217 1218 return 0; 1219 } 1220 1221 static const u32 rk3588_dsi0_grf_reg_fields[MAX_FIELDS] = { 1222 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0000, 11, 11), 1223 [GATING_EN] = GRF_REG_FIELD(0x0000, 10, 10), 1224 [IPI_SHUTDN] = GRF_REG_FIELD(0x0000, 9, 9), 1225 [IPI_COLORM] = GRF_REG_FIELD(0x0000, 8, 8), 1226 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0000, 4, 7), 1227 [IPI_FORMAT] = GRF_REG_FIELD(0x0000, 0, 3), 1228 }; 1229 1230 static const u32 rk3588_dsi1_grf_reg_fields[MAX_FIELDS] = { 1231 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0004, 11, 11), 1232 [GATING_EN] = GRF_REG_FIELD(0x0004, 10, 10), 1233 [IPI_SHUTDN] = GRF_REG_FIELD(0x0004, 9, 9), 1234 [IPI_COLORM] = GRF_REG_FIELD(0x0004, 8, 8), 1235 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0004, 4, 7), 1236 [IPI_FORMAT] = GRF_REG_FIELD(0x0004, 0, 3), 1237 }; 1238 1239 static const struct dw_mipi_dsi2_plat_data rk3588_mipi_dsi2_plat_data = { 1240 .dsi0_grf_reg_fields = rk3588_dsi0_grf_reg_fields, 1241 .dsi1_grf_reg_fields = rk3588_dsi1_grf_reg_fields, 1242 .dphy_max_bit_rate_per_lane = 4500000000ULL, 1243 .cphy_max_symbol_rate_per_lane = 2000000000ULL, 1244 }; 1245 1246 static const struct udevice_id dw_mipi_dsi2_ids[] = { 1247 { 1248 .compatible = "rockchip,rk3588-mipi-dsi2", 1249 .data = (ulong)&rk3588_mipi_dsi2_plat_data, 1250 }, 1251 {} 1252 }; 1253 1254 static ssize_t dw_mipi_dsi2_host_transfer(struct mipi_dsi_host *host, 1255 const struct mipi_dsi_msg *msg) 1256 { 1257 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1258 1259 return dw_mipi_dsi2_transfer(dsi2, msg); 1260 } 1261 1262 static int dw_mipi_dsi2_host_attach(struct mipi_dsi_host *host, 1263 struct mipi_dsi_device *device) 1264 { 1265 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1266 1267 if (device->lanes < 1 || device->lanes > 8) 1268 return -EINVAL; 1269 1270 dsi2->lanes = device->lanes; 1271 dsi2->channel = device->channel; 1272 dsi2->format = device->format; 1273 dsi2->mode_flags = device->mode_flags; 1274 dsi2->device = device; 1275 1276 return 0; 1277 } 1278 1279 static const struct mipi_dsi_host_ops dw_mipi_dsi2_host_ops = { 1280 .attach = dw_mipi_dsi2_host_attach, 1281 .transfer = dw_mipi_dsi2_host_transfer, 1282 }; 1283 1284 static int dw_mipi_dsi2_bind(struct udevice *dev) 1285 { 1286 struct mipi_dsi_host *host = dev_get_platdata(dev); 1287 1288 host->dev = dev; 1289 host->ops = &dw_mipi_dsi2_host_ops; 1290 1291 return dm_scan_fdt_dev(dev); 1292 } 1293 1294 static int dw_mipi_dsi2_child_post_bind(struct udevice *dev) 1295 { 1296 struct mipi_dsi_host *host = dev_get_platdata(dev->parent); 1297 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1298 char name[20]; 1299 1300 sprintf(name, "%s.%d", host->dev->name, device->channel); 1301 device_set_name(dev, name); 1302 1303 device->dev = dev; 1304 device->host = host; 1305 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4); 1306 device->format = dev_read_u32_default(dev, "dsi,format", 1307 MIPI_DSI_FMT_RGB888); 1308 device->mode_flags = dev_read_u32_default(dev, "dsi,flags", 1309 MIPI_DSI_MODE_VIDEO | 1310 MIPI_DSI_MODE_VIDEO_BURST | 1311 MIPI_DSI_MODE_VIDEO_HBP | 1312 MIPI_DSI_MODE_LPM | 1313 MIPI_DSI_MODE_EOT_PACKET); 1314 device->channel = dev_read_u32_default(dev, "reg", 0); 1315 1316 return 0; 1317 } 1318 1319 static int dw_mipi_dsi2_child_pre_probe(struct udevice *dev) 1320 { 1321 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1322 int ret; 1323 1324 ret = mipi_dsi_attach(device); 1325 if (ret) { 1326 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret); 1327 return ret; 1328 } 1329 1330 return 0; 1331 } 1332 1333 U_BOOT_DRIVER(dw_mipi_dsi2) = { 1334 .name = "dw_mipi_dsi2", 1335 .id = UCLASS_DISPLAY, 1336 .of_match = dw_mipi_dsi2_ids, 1337 .probe = dw_mipi_dsi2_probe, 1338 .bind = dw_mipi_dsi2_bind, 1339 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi2), 1340 .per_child_platdata_auto_alloc_size = sizeof(struct mipi_dsi_device), 1341 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_host), 1342 .child_post_bind = dw_mipi_dsi2_child_post_bind, 1343 .child_pre_probe = dw_mipi_dsi2_child_pre_probe, 1344 }; 1345