1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Author: Guochun Huang <hero.huang@rock-chips.com> 7 */ 8 9 #include <drm/drm_mipi_dsi.h> 10 11 #include <config.h> 12 #include <common.h> 13 #include <errno.h> 14 #include <asm/unaligned.h> 15 #include <asm/gpio.h> 16 #include <asm/io.h> 17 #include <asm/hardware.h> 18 #include <dm/device.h> 19 #include <dm/read.h> 20 #include <dm/of_access.h> 21 #include <regmap.h> 22 #include <syscon.h> 23 #include <asm/arch-rockchip/clock.h> 24 #include <linux/iopoll.h> 25 26 #include "rockchip_display.h" 27 #include "rockchip_crtc.h" 28 #include "rockchip_connector.h" 29 #include "rockchip_panel.h" 30 #include "rockchip_phy.h" 31 32 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) 33 34 #define DSI2_PWR_UP 0x000c 35 #define RESET 0 36 #define POWER_UP BIT(0) 37 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 38 #define DSI2_SOFT_RESET 0x0010 39 #define SYS_RSTN BIT(2) 40 #define PHY_RSTN BIT(1) 41 #define IPI_RSTN BIT(0) 42 #define INT_ST_MAIN 0x0014 43 #define DSI2_MODE_CTRL 0x0018 44 #define DSI2_MODE_STATUS 0x001c 45 #define DSI2_CORE_STATUS 0x0020 46 #define PRI_RD_DATA_AVAIL BIT(26) 47 #define PRI_FIFOS_NOT_EMPTY BIT(25) 48 #define PRI_BUSY BIT(24) 49 #define CRI_RD_DATA_AVAIL BIT(18) 50 #define CRT_FIFOS_NOT_EMPTY BIT(17) 51 #define CRI_BUSY BIT(16) 52 #define IPI_FIFOS_NOT_EMPTY BIT(9) 53 #define IPI_BUSY BIT(8) 54 #define CORE_FIFOS_NOT_EMPTY BIT(1) 55 #define CORE_BUSY BIT(0) 56 #define MANUAL_MODE_CFG 0x0024 57 #define MANUAL_MODE_EN BIT(0) 58 #define DSI2_TIMEOUT_HSTX_CFG 0x0048 59 #define TO_HSTX(x) UPDATE(x, 15, 0) 60 #define DSI2_TIMEOUT_HSTXRDY_CFG 0x004c 61 #define TO_HSTXRDY(x) UPDATE(x, 15, 0) 62 #define DSI2_TIMEOUT_LPRX_CFG 0x0050 63 #define TO_LPRXRDY(x) UPDATE(x, 15, 0) 64 #define DSI2_TIMEOUT_LPTXRDY_CFG 0x0054 65 #define TO_LPTXRDY(x) UPDATE(x, 15, 0) 66 #define DSI2_TIMEOUT_LPTXTRIG_CFG 0x0058 67 #define TO_LPTXTRIG(x) UPDATE(x, 15, 0) 68 #define DSI2_TIMEOUT_LPTXULPS_CFG 0x005c 69 #define TO_LPTXULPS(x) UPDATE(x, 15, 0) 70 #define DSI2_TIMEOUT_BTA_CFG 0x60 71 #define TO_BTA(x) UPDATE(x, 15, 0) 72 73 #define DSI2_PHY_MODE_CFG 0x0100 74 #define PPI_WIDTH(x) UPDATE(x, 9, 8) 75 #define PHY_LANES(x) UPDATE(x - 1, 5, 4) 76 #define PHY_TYPE(x) UPDATE(x, 0, 0) 77 #define DSI2_PHY_CLK_CFG 0X0104 78 #define PHY_LPTX_CLK_DIV(x) UPDATE(x, 12, 8) 79 #define CLK_TYPE_MASK BIT(0) 80 #define NON_CONTINUOUS_CLK BIT(0) 81 #define CONTIUOUS_CLK 0 82 #define DSI2_PHY_LP2HS_MAN_CFG 0x010c 83 #define PHY_LP2HS_TIME(x) UPDATE(x, 28, 0) 84 #define DSI2_PHY_HS2LP_MAN_CFG 0x0114 85 #define PHY_HS2LP_TIME(x) UPDATE(x, 28, 0) 86 #define DSI2_PHY_MAX_RD_T_MAN_CFG 0x011c 87 #define PHY_MAX_RD_TIME(x) UPDATE(x, 26, 0) 88 #define DSI2_PHY_ESC_CMD_T_MAN_CFG 0x0124 89 #define PHY_ESC_CMD_TIME(x) UPDATE(x, 28, 0) 90 #define DSI2_PHY_ESC_BYTE_T_MAN_CFG 0x012c 91 #define PHY_ESC_BYTE_TIME(x) UPDATE(x, 28, 0) 92 93 #define DSI2_PHY_IPI_RATIO_MAN_CFG 0x0134 94 #define PHY_IPI_RATIO(x) UPDATE(x, 21, 0) 95 #define DSI2_PHY_SYS_RATIO_MAN_CFG 0x013C 96 #define PHY_SYS_RATIO(x) UPDATE(x, 16, 0) 97 98 #define DSI2_DSI_GENERAL_CFG 0x0200 99 #define BTA_EN BIT(1) 100 #define EOTP_TX_EN BIT(0) 101 #define DSI2_DSI_VCID_CFG 0x0204 102 #define TX_VCID(x) UPDATE(x, 1, 0) 103 #define DSI2_DSI_SCRAMBLING_CFG 0x0208 104 #define SCRAMBLING_SEED(x) UPDATE(x, 31, 16) 105 #define SCRAMBLING_EN BIT(0) 106 #define DSI2_DSI_VID_TX_CFG 0x020c 107 #define LPDT_DISPLAY_CMD_EN BIT(20) 108 #define BLK_VFP_HS_EN BIT(14) 109 #define BLK_VBP_HS_EN BIT(13) 110 #define BLK_VSA_HS_EN BIT(12) 111 #define BLK_HFP_HS_EN BIT(6) 112 #define BLK_HBP_HS_EN BIT(5) 113 #define BLK_HSA_HS_EN BIT(4) 114 #define VID_MODE_TYPE(x) UPDATE(x, 1, 0) 115 #define DSI2_CRI_TX_HDR 0x02c0 116 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 117 #define DSI2_CRI_TX_PLD 0x02c4 118 #define DSI2_CRI_RX_HDR 0x02c8 119 #define DSI2_CRI_RX_PLD 0x02cc 120 121 #define DSI2_IPI_COLOR_MAN_CFG 0x0300 122 #define IPI_DEPTH(x) UPDATE(x, 7, 4) 123 #define IPI_DEPTH_5_6_5_BITS 0x02 124 #define IPI_DEPTH_6_BITS 0x03 125 #define IPI_DEPTH_8_BITS 0x05 126 #define IPI_DEPTH_10_BITS 0x06 127 #define IPI_FORMAT(x) UPDATE(x, 3, 0) 128 #define IPI_FORMAT_RGB 0x0 129 #define IPI_FORMAT_DSC 0x0b 130 #define DSI2_IPI_VID_HSA_MAN_CFG 0x0304 131 #define VID_HSA_TIME(x) UPDATE(x, 29, 0) 132 #define DSI2_IPI_VID_HBP_MAN_CFG 0x030c 133 #define VID_HBP_TIME(x) UPDATE(x, 29, 0) 134 #define DSI2_IPI_VID_HACT_MAN_CFG 0x0314 135 #define VID_HACT_TIME(x) UPDATE(x, 29, 0) 136 #define DSI2_IPI_VID_HLINE_MAN_CFG 0x031c 137 #define VID_HLINE_TIME(x) UPDATE(x, 29, 0) 138 #define DSI2_IPI_VID_VSA_MAN_CFG 0x0324 139 #define VID_VSA_LINES(x) UPDATE(x, 9, 0) 140 #define DSI2_IPI_VID_VBP_MAN_CFG 0X032C 141 #define VID_VBP_LINES(x) UPDATE(x, 9, 0) 142 #define DSI2_IPI_VID_VACT_MAN_CFG 0X0334 143 #define VID_VACT_LINES(x) UPDATE(x, 13, 0) 144 #define DSI2_IPI_VID_VFP_MAN_CFG 0X033C 145 #define VID_VFP_LINES(x) UPDATE(x, 9, 0) 146 #define DSI2_IPI_PIX_PKT_CFG 0x0344 147 #define MAX_PIX_PKT(x) UPDATE(x, 15, 0) 148 149 #define DSI2_INT_ST_PHY 0x0400 150 #define DSI2_INT_MASK_PHY 0x0404 151 #define DSI2_INT_ST_TO 0x0410 152 #define DSI2_INT_MASK_TO 0x0414 153 #define DSI2_INT_ST_ACK 0x0420 154 #define DSI2_INT_MASK_ACK 0x0424 155 #define DSI2_INT_ST_IPI 0x0430 156 #define DSI2_INT_MASK_IPI 0x0434 157 #define DSI2_INT_ST_FIFO 0x0440 158 #define DSI2_INT_MASK_FIFO 0x0444 159 #define DSI2_INT_ST_PRI 0x0450 160 #define DSI2_INT_MASK_PRI 0x0454 161 #define DSI2_INT_ST_CRI 0x0460 162 #define DSI2_INT_MASK_CRI 0x0464 163 #define DSI2_INT_FORCE_CRI 0x0468 164 #define DSI2_MAX_REGISGER DSI2_INT_FORCE_CRI 165 166 #define CMD_PKT_STATUS_TIMEOUT_US 1000 167 #define MODE_STATUS_TIMEOUT_US 20000 168 #define PSEC_PER_SEC 1000000000000LL 169 #define USEC_PER_SEC 1000000L 170 #define MSEC_PER_SEC 1000L 171 172 #define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 16) | ((lsb) << 8) | (msb)) 173 174 enum vid_mode_type { 175 VID_MODE_TYPE_NON_BURST_SYNC_PULSES, 176 VID_MODE_TYPE_NON_BURST_SYNC_EVENTS, 177 VID_MODE_TYPE_BURST, 178 }; 179 180 enum mode_ctrl { 181 IDLE_MODE, 182 AUTOCALC_MODE, 183 COMMAND_MODE, 184 VIDEO_MODE, 185 DATA_STREAM_MODE, 186 VIDE_TEST_MODE, 187 DATA_STREAM_TEST_MODE, 188 }; 189 190 enum grf_reg_fields { 191 TXREQCLKHS_EN, 192 GATING_EN, 193 IPI_SHUTDN, 194 IPI_COLORM, 195 IPI_COLOR_DEPTH, 196 IPI_FORMAT, 197 MAX_FIELDS, 198 }; 199 200 enum phy_type { 201 DPHY, 202 CPHY, 203 }; 204 205 enum ppi_width { 206 PPI_WIDTH_8_BITS, 207 PPI_WIDTH_16_BITS, 208 PPI_WIDTH_32_BITS, 209 }; 210 211 struct rockchip_cmd_header { 212 u8 data_type; 213 u8 delay_ms; 214 u8 payload_length; 215 }; 216 217 struct dw_mipi_dsi2_plat_data { 218 bool dsc; 219 const u32 *dsi0_grf_reg_fields; 220 const u32 *dsi1_grf_reg_fields; 221 unsigned long long dphy_max_bit_rate_per_lane; 222 unsigned long long cphy_max_symbol_rate_per_lane; 223 }; 224 225 struct mipi_dcphy { 226 /* Non-SNPS PHY */ 227 struct rockchip_phy *phy; 228 229 u16 input_div; 230 u16 feedback_div; 231 }; 232 233 /** 234 * struct mipi_dphy_configure - MIPI D-PHY configuration set 235 * 236 * This structure is used to represent the configuration state of a 237 * MIPI D-PHY phy. 238 */ 239 struct mipi_dphy_configure { 240 unsigned int clk_miss; 241 unsigned int clk_post; 242 unsigned int clk_pre; 243 unsigned int clk_prepare; 244 unsigned int clk_settle; 245 unsigned int clk_term_en; 246 unsigned int clk_trail; 247 unsigned int clk_zero; 248 unsigned int d_term_en; 249 unsigned int eot; 250 unsigned int hs_exit; 251 unsigned int hs_prepare; 252 unsigned int hs_settle; 253 unsigned int hs_skip; 254 unsigned int hs_trail; 255 unsigned int hs_zero; 256 unsigned int init; 257 unsigned int lpx; 258 unsigned int ta_get; 259 unsigned int ta_go; 260 unsigned int ta_sure; 261 unsigned int wakeup; 262 unsigned long hs_clk_rate; 263 unsigned long lp_clk_rate; 264 unsigned char lanes; 265 }; 266 267 struct dw_mipi_dsi2 { 268 struct rockchip_connector connector; 269 struct udevice *dev; 270 void *base; 271 void *grf; 272 int id; 273 struct dw_mipi_dsi2 *master; 274 struct dw_mipi_dsi2 *slave; 275 bool prepared; 276 277 bool disable_hold_mode; 278 bool auto_calc_mode; 279 bool c_option; 280 bool dsc_enable; 281 bool scrambling_en; 282 unsigned int slice_width; 283 unsigned int slice_height; 284 u32 version_major; 285 u32 version_minor; 286 struct clk sys_clk; 287 288 unsigned int lane_hs_rate; /* Kbps/Ksps per lane */ 289 u32 channel; 290 u32 lanes; 291 u32 format; 292 u32 mode_flags; 293 u64 mipi_pixel_rate; 294 struct mipi_dcphy dcphy; 295 struct drm_display_mode mode; 296 bool data_swap; 297 bool dual_channel; 298 299 struct gpio_desc te_gpio; 300 struct mipi_dsi_device *device; 301 struct mipi_dphy_configure mipi_dphy_cfg; 302 const struct dw_mipi_dsi2_plat_data *pdata; 303 struct drm_dsc_picture_parameter_set *pps; 304 }; 305 306 static inline void dsi_write(struct dw_mipi_dsi2 *dsi2, u32 reg, u32 val) 307 { 308 writel(val, dsi2->base + reg); 309 } 310 311 static inline u32 dsi_read(struct dw_mipi_dsi2 *dsi2, u32 reg) 312 { 313 return readl(dsi2->base + reg); 314 } 315 316 static inline void dsi_update_bits(struct dw_mipi_dsi2 *dsi2, 317 u32 reg, u32 mask, u32 val) 318 { 319 u32 orig, tmp; 320 321 orig = dsi_read(dsi2, reg); 322 tmp = orig & ~mask; 323 tmp |= val & mask; 324 dsi_write(dsi2, reg, tmp); 325 } 326 327 static void grf_field_write(struct dw_mipi_dsi2 *dsi2, enum grf_reg_fields index, 328 unsigned int val) 329 { 330 const u32 field = dsi2->id ? dsi2->pdata->dsi1_grf_reg_fields[index] : 331 dsi2->pdata->dsi0_grf_reg_fields[index]; 332 u16 reg; 333 u8 msb, lsb; 334 335 if (!field) 336 return; 337 338 reg = (field >> 16) & 0xffff; 339 lsb = (field >> 8) & 0xff; 340 msb = (field >> 0) & 0xff; 341 342 regmap_write(dsi2->grf, reg, GENMASK(msb, lsb) << 16 | val << lsb); 343 } 344 345 static unsigned long dw_mipi_dsi2_get_lane_rate(struct dw_mipi_dsi2 *dsi2) 346 { 347 const struct drm_display_mode *mode = &dsi2->mode; 348 u64 max_lane_rate, lane_rate; 349 unsigned int value; 350 int bpp, lanes; 351 u64 tmp; 352 353 max_lane_rate = (dsi2->c_option) ? 354 dsi2->pdata->cphy_max_symbol_rate_per_lane : 355 dsi2->pdata->dphy_max_bit_rate_per_lane; 356 357 /* 358 * optional override of the desired bandwidth 359 * High-Speed mode: Differential and terminated: 80Mbps ~ 4500 Mbps 360 */ 361 value = dev_read_u32_default(dsi2->dev, "rockchip,lane-rate", 0); 362 if (value >= 80000 && value <= 4500000) 363 return value * MSEC_PER_SEC; 364 else if (value >= 80 && value <= 4500) 365 return value * USEC_PER_SEC; 366 367 bpp = mipi_dsi_pixel_format_to_bpp(dsi2->format); 368 if (bpp < 0) 369 bpp = 24; 370 371 lanes = dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes; 372 tmp = (u64)mode->crtc_clock * 1000 * bpp; 373 do_div(tmp, lanes); 374 375 if (dsi2->c_option) 376 tmp = DIV_ROUND_CLOSEST(tmp * 100, 228); 377 378 /* set BW a little larger only in video burst mode in 379 * consideration of the protocol overhead and HS mode 380 * switching to BLLP mode, take 1 / 0.9, since Mbps must 381 * big than bandwidth of RGB 382 */ 383 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { 384 tmp *= 10; 385 do_div(tmp, 9); 386 } 387 388 if (tmp > max_lane_rate) 389 lane_rate = max_lane_rate; 390 else 391 lane_rate = tmp; 392 393 return lane_rate; 394 } 395 396 static int cri_fifos_wait_avail(struct dw_mipi_dsi2 *dsi2) 397 { 398 u32 sts, mask; 399 int ret; 400 401 mask = CRI_BUSY | CRT_FIFOS_NOT_EMPTY; 402 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 403 sts, !(sts & mask), 404 CMD_PKT_STATUS_TIMEOUT_US); 405 if (ret < 0) { 406 printf("command interface is busy: 0x%x\n", sts); 407 return ret; 408 } 409 410 return 0; 411 } 412 413 static int dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 *dsi2, 414 const struct mipi_dsi_msg *msg) 415 { 416 u8 *payload = msg->rx_buf; 417 u8 data_type; 418 u16 wc; 419 int i, j, ret, len = msg->rx_len; 420 unsigned int vrefresh = drm_mode_vrefresh(&dsi2->mode); 421 u32 val; 422 423 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 424 val, val & CRI_RD_DATA_AVAIL, 425 DIV_ROUND_UP(1000000, vrefresh)); 426 if (ret) { 427 printf("CRI has no available read data\n"); 428 return ret; 429 } 430 431 val = dsi_read(dsi2, DSI2_CRI_RX_HDR); 432 data_type = val & 0x3f; 433 434 if (mipi_dsi_packet_format_is_short(data_type)) { 435 for (i = 0; i < len && i < 2; i++) 436 payload[i] = (val >> (8 * (i + 1))) & 0xff; 437 438 return 0; 439 } 440 441 wc = (val >> 8) & 0xffff; 442 /* Receive payload */ 443 for (i = 0; i < len && i < wc; i += 4) { 444 val = dsi_read(dsi2, DSI2_CRI_RX_PLD); 445 for (j = 0; j < 4 && j + i < len && j + i < wc; j++) 446 payload[i + j] = val >> (8 * j); 447 } 448 449 return 0; 450 } 451 452 static void dw_mipi_dsi2_clk_management(struct dw_mipi_dsi2 *dsi2) 453 { 454 u32 clk_type; 455 456 /* 457 * initial deskew calibration is send after phy_power_on, 458 * then we can configure clk_type. 459 */ 460 if (dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 461 clk_type = NON_CONTINUOUS_CLK; 462 else 463 clk_type = CONTIUOUS_CLK; 464 465 dsi_update_bits(dsi2, DSI2_PHY_CLK_CFG, CLK_TYPE_MASK, clk_type); 466 } 467 468 static ssize_t dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 *dsi2, 469 const struct mipi_dsi_msg *msg) 470 { 471 struct mipi_dsi_packet packet; 472 int ret; 473 int val; 474 u32 mode; 475 476 dw_mipi_dsi2_clk_management(dsi2); 477 dsi_update_bits(dsi2, DSI2_DSI_VID_TX_CFG, LPDT_DISPLAY_CMD_EN, 478 msg->flags & MIPI_DSI_MSG_USE_LPM ? 479 LPDT_DISPLAY_CMD_EN : 0); 480 481 /* create a packet to the DSI protocol */ 482 ret = mipi_dsi_create_packet(&packet, msg); 483 if (ret) { 484 printf("failed to create packet: %d\n", ret); 485 return ret; 486 } 487 488 /* check cri interface is not busy */ 489 ret = cri_fifos_wait_avail(dsi2); 490 if (ret) 491 return ret; 492 493 /* Send payload */ 494 while (DIV_ROUND_UP(packet.payload_length, 4)) { 495 if (packet.payload_length < 4) { 496 /* send residu payload */ 497 val = 0; 498 memcpy(&val, packet.payload, packet.payload_length); 499 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 500 packet.payload_length = 0; 501 } else { 502 val = get_unaligned_le32(packet.payload); 503 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 504 packet.payload += 4; 505 packet.payload_length -= 4; 506 } 507 } 508 509 /* Send packet header */ 510 mode = CMD_TX_MODE(msg->flags & MIPI_DSI_MSG_USE_LPM ? 1 : 0); 511 val = get_unaligned_le32(packet.header); 512 dsi_write(dsi2, DSI2_CRI_TX_HDR, mode | val); 513 514 ret = cri_fifos_wait_avail(dsi2); 515 if (ret) 516 return ret; 517 518 if (msg->rx_len) { 519 ret = dw_mipi_dsi2_read_from_fifo(dsi2, msg); 520 if (ret < 0) 521 return ret; 522 } 523 524 if (dsi2->slave) { 525 ret = dw_mipi_dsi2_transfer(dsi2->slave, msg); 526 if (ret < 0) 527 return ret; 528 } 529 530 return msg->rx_len ? msg->rx_len : msg->tx_len; 531 } 532 533 static void dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 *dsi2) 534 { 535 u32 val, color_depth; 536 537 switch (dsi2->format) { 538 case MIPI_DSI_FMT_RGB666: 539 case MIPI_DSI_FMT_RGB666_PACKED: 540 color_depth = IPI_DEPTH_6_BITS; 541 break; 542 case MIPI_DSI_FMT_RGB565: 543 color_depth = IPI_DEPTH_5_6_5_BITS; 544 break; 545 case MIPI_DSI_FMT_RGB888: 546 default: 547 color_depth = IPI_DEPTH_8_BITS; 548 break; 549 } 550 551 val = IPI_DEPTH(color_depth) | 552 IPI_FORMAT(dsi2->dsc_enable ? IPI_FORMAT_DSC : IPI_FORMAT_RGB); 553 dsi_write(dsi2, DSI2_IPI_COLOR_MAN_CFG, val); 554 grf_field_write(dsi2, IPI_COLOR_DEPTH, color_depth); 555 556 if (dsi2->dsc_enable) 557 grf_field_write(dsi2, IPI_FORMAT, IPI_FORMAT_DSC); 558 } 559 560 static void dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 *dsi2) 561 { 562 struct drm_display_mode *mode = &dsi2->mode; 563 u32 hline, hsa, hbp, hact; 564 u64 hline_time, hsa_time, hbp_time, hact_time, tmp; 565 u64 pixel_clk, phy_hs_clk; 566 u32 vact, vsa, vfp, vbp; 567 u16 val; 568 569 if (dsi2->slave || dsi2->master) 570 val = mode->hdisplay / 2; 571 else 572 val = mode->hdisplay; 573 574 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val)); 575 576 dw_mipi_dsi2_ipi_color_coding_cfg(dsi2); 577 578 if (dsi2->auto_calc_mode) 579 return; 580 581 /* 582 * if the controller is intended to operate in data stream mode, 583 * no more steps are required. 584 */ 585 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) 586 return; 587 588 vact = mode->vdisplay; 589 vsa = mode->vsync_end - mode->vsync_start; 590 vfp = mode->vsync_start - mode->vdisplay; 591 vbp = mode->vtotal - mode->vsync_end; 592 hact = mode->hdisplay; 593 hsa = mode->hsync_end - mode->hsync_start; 594 hbp = mode->htotal - mode->hsync_end; 595 hline = mode->htotal; 596 597 pixel_clk = mode->crtc_clock * MSEC_PER_SEC; 598 599 if (dsi2->c_option) 600 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 601 else 602 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 603 604 tmp = hsa * phy_hs_clk; 605 hsa_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 606 dsi_write(dsi2, DSI2_IPI_VID_HSA_MAN_CFG, VID_HSA_TIME(hsa_time)); 607 608 tmp = hbp * phy_hs_clk; 609 hbp_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 610 dsi_write(dsi2, DSI2_IPI_VID_HBP_MAN_CFG, VID_HBP_TIME(hbp_time)); 611 612 tmp = hact * phy_hs_clk; 613 hact_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 614 dsi_write(dsi2, DSI2_IPI_VID_HACT_MAN_CFG, VID_HACT_TIME(hact_time)); 615 616 tmp = hline * phy_hs_clk; 617 hline_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 618 dsi_write(dsi2, DSI2_IPI_VID_HLINE_MAN_CFG, VID_HLINE_TIME(hline_time)); 619 620 dsi_write(dsi2, DSI2_IPI_VID_VSA_MAN_CFG, VID_VSA_LINES(vsa)); 621 dsi_write(dsi2, DSI2_IPI_VID_VBP_MAN_CFG, VID_VBP_LINES(vbp)); 622 dsi_write(dsi2, DSI2_IPI_VID_VACT_MAN_CFG, VID_VACT_LINES(vact)); 623 dsi_write(dsi2, DSI2_IPI_VID_VFP_MAN_CFG, VID_VFP_LINES(vfp)); 624 } 625 626 static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2) 627 { 628 u32 val = 0, mode; 629 int ret; 630 631 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) 632 val |= BLK_HFP_HS_EN; 633 634 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) 635 val |= BLK_HBP_HS_EN; 636 637 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HSA) 638 val |= BLK_HSA_HS_EN; 639 640 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 641 val |= VID_MODE_TYPE_BURST; 642 else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 643 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 644 else 645 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 646 647 dsi_write(dsi2, DSI2_DSI_VID_TX_CFG, val); 648 649 dsi_write(dsi2, DSI2_MODE_CTRL, VIDEO_MODE); 650 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 651 mode, mode & VIDEO_MODE, 652 MODE_STATUS_TIMEOUT_US); 653 if (ret < 0) 654 printf("failed to enter video mode\n"); 655 } 656 657 static void dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 *dsi2) 658 { 659 u32 mode; 660 int ret; 661 662 dsi_write(dsi2, DSI2_MODE_CTRL, DATA_STREAM_MODE); 663 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 664 mode, mode & DATA_STREAM_MODE, 665 MODE_STATUS_TIMEOUT_US); 666 if (ret < 0) 667 printf("failed to enter data stream mode\n"); 668 } 669 670 static void dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 *dsi2) 671 { 672 u32 mode; 673 int ret; 674 675 dsi_write(dsi2, DSI2_MODE_CTRL, COMMAND_MODE); 676 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 677 mode, mode & COMMAND_MODE, 678 MODE_STATUS_TIMEOUT_US); 679 if (ret < 0) 680 printf("failed to enter cmd mode\n"); 681 } 682 683 static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2) 684 { 685 u32 mode; 686 int ret; 687 688 dw_mipi_dsi2_clk_management(dsi2); 689 dw_mipi_dsi2_ipi_set(dsi2); 690 691 if (dsi2->auto_calc_mode) { 692 dsi_write(dsi2, DSI2_MODE_CTRL, AUTOCALC_MODE); 693 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 694 mode, mode == IDLE_MODE, 695 MODE_STATUS_TIMEOUT_US); 696 if (ret < 0) 697 printf("auto calculation training failed\n"); 698 } 699 700 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO) 701 dw_mipi_dsi2_set_vid_mode(dsi2); 702 else 703 dw_mipi_dsi2_set_data_stream_mode(dsi2); 704 705 if (dsi2->slave) 706 dw_mipi_dsi2_enable(dsi2->slave); 707 } 708 709 static void dw_mipi_dsi2_disable(struct dw_mipi_dsi2 *dsi2) 710 { 711 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, 0); 712 dw_mipi_dsi2_set_cmd_mode(dsi2); 713 714 if (dsi2->slave) 715 dw_mipi_dsi2_disable(dsi2->slave); 716 } 717 718 static void dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 *dsi2) 719 { 720 if (!dsi2->prepared) 721 return; 722 723 dsi_write(dsi2, DSI2_PWR_UP, RESET); 724 725 if (dsi2->dcphy.phy) 726 rockchip_phy_power_off(dsi2->dcphy.phy); 727 728 dsi2->prepared = false; 729 730 if (dsi2->slave) 731 dw_mipi_dsi2_post_disable(dsi2->slave); 732 } 733 734 static int dw_mipi_dsi2_connector_pre_init(struct rockchip_connector *conn, 735 struct display_state *state) 736 { 737 struct connector_state *conn_state = &state->conn_state; 738 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 739 struct mipi_dsi_host *host = dev_get_platdata(dsi2->dev); 740 struct mipi_dsi_device *device; 741 char name[20]; 742 743 conn_state->type = DRM_MODE_CONNECTOR_DSI; 744 745 if (conn->bridge) { 746 device = dev_get_platdata(conn->bridge->dev); 747 if (!device) 748 return -ENODEV; 749 750 device->host = host; 751 sprintf(name, "%s.%d", host->dev->name, device->channel); 752 device_set_name(conn->bridge->dev, name); 753 mipi_dsi_attach(device); 754 } 755 756 return 0; 757 } 758 759 static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2) 760 { 761 struct udevice *dev = dsi2->device->dev; 762 struct rockchip_cmd_header *header; 763 struct drm_dsc_picture_parameter_set *pps = NULL; 764 u8 *dsc_packed_pps; 765 const void *data; 766 int len; 767 768 dsi2->c_option = dev_read_bool(dev, "phy-c-option"); 769 dsi2->scrambling_en = dev_read_bool(dev, "scrambling-enable"); 770 dsi2->dsc_enable = dsi2->pdata->dsc ? 771 dev_read_bool(dev, "compressed-data") : false; 772 773 if (dsi2->slave) { 774 dsi2->slave->c_option = dsi2->c_option; 775 dsi2->slave->scrambling_en = dsi2->scrambling_en; 776 dsi2->slave->dsc_enable = dsi2->dsc_enable; 777 } 778 779 if (!dsi2->dsc_enable) 780 return 0; 781 782 dsi2->slice_width = dev_read_u32_default(dev, "slice-width", 0); 783 dsi2->slice_height = dev_read_u32_default(dev, "slice-height", 0); 784 dsi2->version_major = dev_read_u32_default(dev, "version-major", 0); 785 dsi2->version_minor = dev_read_u32_default(dev, "version-minor", 0); 786 787 data = dev_read_prop(dev, "panel-init-sequence", &len); 788 if (!data) 789 return -EINVAL; 790 791 while (len > sizeof(*header)) { 792 header = (struct rockchip_cmd_header *)data; 793 data += sizeof(*header); 794 len -= sizeof(*header); 795 796 if (header->payload_length > len) 797 return -EINVAL; 798 799 if (header->data_type == MIPI_DSI_PICTURE_PARAMETER_SET) { 800 dsc_packed_pps = calloc(1, header->payload_length); 801 if (!dsc_packed_pps) 802 return -ENOMEM; 803 804 memcpy(dsc_packed_pps, data, header->payload_length); 805 pps = (struct drm_dsc_picture_parameter_set *)dsc_packed_pps; 806 break; 807 } 808 809 data += header->payload_length; 810 len -= header->payload_length; 811 } 812 813 if (!pps) { 814 printf("not found dsc pps definition\n"); 815 return -EINVAL; 816 } 817 818 dsi2->pps = pps; 819 820 if (dsi2->slave) { 821 u16 pic_width = be16_to_cpu(pps->pic_width) / 2; 822 823 dsi2->pps->pic_width = cpu_to_be16(pic_width); 824 printf("dsc pic_width change from %d to %d\n", pic_width * 2, pic_width); 825 } 826 827 return 0; 828 } 829 830 static int dw_mipi_dsi2_connector_init(struct rockchip_connector *conn, struct display_state *state) 831 { 832 struct connector_state *conn_state = &state->conn_state; 833 struct crtc_state *cstate = &state->crtc_state; 834 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 835 struct rockchip_phy *phy = NULL; 836 struct udevice *phy_dev; 837 struct udevice *dev; 838 int ret; 839 840 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dsi2->id); 841 dsi2->dcphy.phy = conn->phy; 842 843 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 844 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709; 845 conn_state->color_range = DRM_COLOR_YCBCR_FULL_RANGE; 846 conn_state->output_if |= 847 dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0; 848 849 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) { 850 conn_state->output_flags |= ROCKCHIP_OUTPUT_MIPI_DS_MODE; 851 conn_state->hold_mode = dsi2->disable_hold_mode ? false : true; 852 } 853 854 if (dsi2->dual_channel) { 855 ret = uclass_get_device_by_name(UCLASS_DISPLAY, 856 "dsi@fde30000", 857 &dev); 858 if (ret) 859 return ret; 860 861 dsi2->slave = dev_get_priv(dev); 862 if (!dsi2->slave) 863 return -ENODEV; 864 865 dsi2->slave->master = dsi2; 866 dsi2->lanes /= 2; 867 868 dsi2->slave->auto_calc_mode = dsi2->auto_calc_mode; 869 dsi2->slave->lanes = dsi2->lanes; 870 dsi2->slave->format = dsi2->format; 871 dsi2->slave->mode_flags = dsi2->mode_flags; 872 dsi2->slave->channel = dsi2->channel; 873 conn_state->output_flags |= 874 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; 875 if (dsi2->data_swap) 876 conn_state->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP; 877 878 conn_state->output_if |= VOP_OUTPUT_IF_MIPI1; 879 880 ret = uclass_get_device_by_phandle(UCLASS_PHY, dev, 881 "phys", &phy_dev); 882 if (ret) 883 return -ENODEV; 884 885 phy = (struct rockchip_phy *)dev_get_driver_data(phy_dev); 886 if (!phy) 887 return -ENODEV; 888 889 dsi2->slave->dcphy.phy = phy; 890 if (phy->funcs && phy->funcs->init) 891 return phy->funcs->init(phy); 892 } 893 894 dw_mipi_dsi2_get_dsc_params_from_sink(dsi2); 895 896 if (dm_gpio_is_valid(&dsi2->te_gpio)) { 897 cstate->soft_te = true; 898 conn_state->te_gpio = &dsi2->te_gpio; 899 } 900 901 if (dsi2->dsc_enable) { 902 cstate->dsc_enable = 1; 903 cstate->dsc_sink_cap.version_major = dsi2->version_major; 904 cstate->dsc_sink_cap.version_minor = dsi2->version_minor; 905 cstate->dsc_sink_cap.slice_width = dsi2->slice_width; 906 cstate->dsc_sink_cap.slice_height = dsi2->slice_height; 907 /* only can support rgb888 panel now */ 908 cstate->dsc_sink_cap.target_bits_per_pixel_x16 = 8 << 4; 909 cstate->dsc_sink_cap.native_420 = 0; 910 memcpy(&cstate->pps, dsi2->pps, sizeof(struct drm_dsc_picture_parameter_set)); 911 } 912 913 return 0; 914 } 915 916 /* 917 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived 918 * from the valid ranges specified in Section 6.9, Table 14, Page 41 919 * of the D-PHY specification (v2.1). 920 */ 921 int mipi_dphy_get_default_config(unsigned long long hs_clk_rate, 922 struct mipi_dphy_configure *cfg) 923 { 924 unsigned long long ui; 925 926 if (!cfg) 927 return -EINVAL; 928 929 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); 930 do_div(ui, hs_clk_rate); 931 932 cfg->clk_miss = 0; 933 cfg->clk_post = 60000 + 52 * ui; 934 cfg->clk_pre = 8000; 935 cfg->clk_prepare = 38000; 936 cfg->clk_settle = 95000; 937 cfg->clk_term_en = 0; 938 cfg->clk_trail = 60000; 939 cfg->clk_zero = 262000; 940 cfg->d_term_en = 0; 941 cfg->eot = 0; 942 cfg->hs_exit = 100000; 943 cfg->hs_prepare = 40000 + 4 * ui; 944 cfg->hs_zero = 105000 + 6 * ui; 945 cfg->hs_settle = 85000 + 6 * ui; 946 cfg->hs_skip = 40000; 947 948 /* 949 * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40) 950 * contains this formula as: 951 * 952 * T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui) 953 * 954 * where n = 1 for forward-direction HS mode and n = 4 for reverse- 955 * direction HS mode. There's only one setting and this function does 956 * not parameterize on anything other that ui, so this code will 957 * assumes that reverse-direction HS mode is supported and uses n = 4. 958 */ 959 cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui); 960 961 cfg->init = 100; 962 cfg->lpx = 50000; 963 cfg->ta_get = 5 * cfg->lpx; 964 cfg->ta_go = 4 * cfg->lpx; 965 cfg->ta_sure = cfg->lpx; 966 cfg->wakeup = 1000; 967 968 return 0; 969 } 970 971 static void dw_mipi_dsi2_set_hs_clk(struct dw_mipi_dsi2 *dsi2, unsigned long rate) 972 { 973 mipi_dphy_get_default_config(rate, &dsi2->mipi_dphy_cfg); 974 975 if (!dsi2->c_option) 976 rockchip_phy_set_mode(dsi2->dcphy.phy, PHY_MODE_MIPI_DPHY); 977 978 rate = rockchip_phy_set_pll(dsi2->dcphy.phy, rate); 979 dsi2->lane_hs_rate = DIV_ROUND_CLOSEST(rate, MSEC_PER_SEC); 980 } 981 982 static void dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 *dsi2) 983 { 984 dsi_write(dsi2, DSI2_SOFT_RESET, 0X0); 985 udelay(100); 986 dsi_write(dsi2, DSI2_SOFT_RESET, SYS_RSTN | PHY_RSTN | IPI_RSTN); 987 } 988 989 static void 990 dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 *dsi2, u32 mode) 991 { 992 /* 993 * select controller work in Manual mode 994 * Manual: MANUAL_MODE_EN 995 * Automatic: 0 996 */ 997 dsi_write(dsi2, MANUAL_MODE_CFG, mode); 998 } 999 1000 static void dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 *dsi2) 1001 { 1002 u32 val = 0; 1003 1004 /* PPI width is fixed to 16 bits in DCPHY */ 1005 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes); 1006 val |= PHY_TYPE(dsi2->c_option ? CPHY : DPHY); 1007 dsi_write(dsi2, DSI2_PHY_MODE_CFG, val); 1008 } 1009 1010 static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2) 1011 { 1012 u32 sys_clk = clk_get_rate(&dsi2->sys_clk) / USEC_PER_SEC; 1013 u32 esc_clk_div; 1014 u32 val = 0; 1015 1016 /* 1017 * clk_type should be NON_CONTINUOUS_CLK before 1018 * initial deskew calibration be sent. 1019 */ 1020 val |= NON_CONTINUOUS_CLK; 1021 1022 /* The Escape clock ranges from 1MHz to 20MHz. */ 1023 esc_clk_div = DIV_ROUND_UP(sys_clk, 20 * 2); 1024 val |= PHY_LPTX_CLK_DIV(esc_clk_div); 1025 1026 dsi_write(dsi2, DSI2_PHY_CLK_CFG, val); 1027 } 1028 1029 static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2) 1030 { 1031 u64 ipi_clk, phy_hsclk, tmp; 1032 u32 sys_clk = clk_get_rate(&dsi2->sys_clk); 1033 1034 /* 1035 * in DPHY mode, the phy_hstx_clk is exactly 1/16 the Lane high-speed 1036 * data rate; In CPHY mode, the phy_hstx_clk is exactly 1/7 the trio 1037 * high speed symbol rate. 1038 */ 1039 if (dsi2->c_option) 1040 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 1041 1042 else 1043 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 1044 1045 /* IPI_RATIO_MAN_CFG = PHY_HSTX_CLK / IPI_CLK */ 1046 ipi_clk = dsi2->mipi_pixel_rate; 1047 1048 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, ipi_clk); 1049 dsi_write(dsi2, DSI2_PHY_IPI_RATIO_MAN_CFG, PHY_IPI_RATIO(tmp)); 1050 1051 /* SYS_RATIO_MAN_CFG = MIPI_DCPHY_HSCLK_Freq / SYS_CLK */ 1052 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, sys_clk); 1053 dsi_write(dsi2, DSI2_PHY_SYS_RATIO_MAN_CFG, PHY_SYS_RATIO(tmp)); 1054 } 1055 1056 static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2) 1057 { 1058 struct mipi_dphy_configure *cfg = &dsi2->mipi_dphy_cfg; 1059 unsigned long long tmp, ui; 1060 unsigned long long hstx_clk; 1061 1062 hstx_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 1063 1064 ui = ALIGN(PSEC_PER_SEC, hstx_clk); 1065 do_div(ui, hstx_clk); 1066 1067 /* PHY_LP2HS_TIME = (TLPX + THS-PREPARE + THS-ZERO) / Tphy_hstx_clk */ 1068 tmp = cfg->lpx + cfg->hs_prepare + cfg->hs_zero; 1069 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 1070 dsi_write(dsi2, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(tmp)); 1071 1072 /* PHY_HS2LP_TIME = (THS-TRAIL + THS-EXIT) / Tphy_hstx_clk */ 1073 tmp = cfg->hs_trail + cfg->hs_exit; 1074 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 1075 dsi_write(dsi2, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(tmp)); 1076 } 1077 1078 static void dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 *dsi2) 1079 { 1080 dw_mipi_dsi2_phy_mode_cfg(dsi2); 1081 dw_mipi_dsi2_phy_clk_mode_cfg(dsi2); 1082 1083 if (dsi2->auto_calc_mode) 1084 return; 1085 1086 dw_mipi_dsi2_phy_ratio_cfg(dsi2); 1087 dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(dsi2); 1088 1089 /* phy configuration 8 - 10 */ 1090 } 1091 1092 static void dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 *dsi2) 1093 { 1094 u32 val; 1095 1096 val = BTA_EN | EOTP_TX_EN; 1097 1098 if (dsi2->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 1099 val &= ~EOTP_TX_EN; 1100 1101 dsi_write(dsi2, DSI2_DSI_GENERAL_CFG, val); 1102 dsi_write(dsi2, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel)); 1103 1104 if (dsi2->scrambling_en) 1105 dsi_write(dsi2, DSI2_DSI_SCRAMBLING_CFG, SCRAMBLING_EN); 1106 } 1107 1108 static void dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 *dsi2, bool enable) 1109 { 1110 if (enable) { 1111 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x1); 1112 dsi_write(dsi2, DSI2_INT_MASK_TO, 0xf); 1113 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x1); 1114 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x1); 1115 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x1); 1116 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x1); 1117 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x1); 1118 } else { 1119 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x0); 1120 dsi_write(dsi2, DSI2_INT_MASK_TO, 0x0); 1121 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x0); 1122 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x0); 1123 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x0); 1124 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x0); 1125 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x0); 1126 }; 1127 } 1128 1129 static void mipi_dcphy_power_on(struct dw_mipi_dsi2 *dsi2) 1130 { 1131 if (!dsi2->dcphy.phy) 1132 return; 1133 1134 rockchip_phy_power_on(dsi2->dcphy.phy); 1135 } 1136 1137 static void dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 *dsi2) 1138 { 1139 if (dsi2->prepared) 1140 return; 1141 1142 dw_mipi_dsi2_host_softrst(dsi2); 1143 dsi_write(dsi2, DSI2_PWR_UP, RESET); 1144 1145 dw_mipi_dsi2_work_mode(dsi2, dsi2->auto_calc_mode ? 0 : MANUAL_MODE_EN); 1146 dw_mipi_dsi2_phy_init(dsi2); 1147 dw_mipi_dsi2_tx_option_set(dsi2); 1148 dw_mipi_dsi2_irq_enable(dsi2, 0); 1149 mipi_dcphy_power_on(dsi2); 1150 dsi_write(dsi2, DSI2_PWR_UP, POWER_UP); 1151 dw_mipi_dsi2_set_cmd_mode(dsi2); 1152 1153 dsi2->prepared = true; 1154 1155 if (dsi2->slave) 1156 dw_mipi_dsi2_pre_enable(dsi2->slave); 1157 } 1158 1159 static void dw_mipi_dsi2_get_mipi_pixel_clk(struct dw_mipi_dsi2 *dsi2, 1160 struct crtc_state *s) 1161 { 1162 struct drm_display_mode *mode = &dsi2->mode; 1163 u8 k = dsi2->slave ? 2 : 1; 1164 1165 /* 1.When MIPI works in uncompressed mode: 1166 * (Video Timing Pixel Rate)/(4)=(MIPI Pixel ClockxK)=(dclk_out×K)=dclk_core 1167 * 2.When MIPI works in compressed mode: 1168 * MIPI Pixel Clock = cds_clk / 2 1169 * MIPI is configured as double channel display mode, K=2, otherwise K=1. 1170 */ 1171 if (dsi2->dsc_enable) { 1172 dsi2->mipi_pixel_rate = s->dsc_cds_clk_rate / 2; 1173 if (dsi2->slave) 1174 dsi2->slave->mipi_pixel_rate = dsi2->mipi_pixel_rate; 1175 1176 return; 1177 } 1178 1179 dsi2->mipi_pixel_rate = (mode->crtc_clock * MSEC_PER_SEC) / (4 * k); 1180 if (dsi2->slave) 1181 dsi2->slave->mipi_pixel_rate = dsi2->mipi_pixel_rate; 1182 } 1183 1184 static int dw_mipi_dsi2_connector_prepare(struct rockchip_connector *conn, 1185 struct display_state *state) 1186 { 1187 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1188 struct connector_state *conn_state = &state->conn_state; 1189 struct crtc_state *cstate = &state->crtc_state; 1190 unsigned long lane_rate; 1191 1192 memcpy(&dsi2->mode, &conn_state->mode, sizeof(struct drm_display_mode)); 1193 if (dsi2->slave) 1194 memcpy(&dsi2->slave->mode, &dsi2->mode, 1195 sizeof(struct drm_display_mode)); 1196 1197 dw_mipi_dsi2_get_mipi_pixel_clk(dsi2, cstate); 1198 1199 lane_rate = dw_mipi_dsi2_get_lane_rate(dsi2); 1200 if (dsi2->dcphy.phy) 1201 dw_mipi_dsi2_set_hs_clk(dsi2, lane_rate); 1202 1203 if (dsi2->slave && dsi2->slave->dcphy.phy) 1204 dw_mipi_dsi2_set_hs_clk(dsi2->slave, lane_rate); 1205 1206 printf("final DSI-Link bandwidth: %u %s x %d\n", 1207 dsi2->lane_hs_rate, dsi2->c_option ? "Ksps" : "Kbps", 1208 dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes); 1209 1210 dw_mipi_dsi2_pre_enable(dsi2); 1211 1212 return 0; 1213 } 1214 1215 static void dw_mipi_dsi2_connector_unprepare(struct rockchip_connector *conn, 1216 struct display_state *state) 1217 { 1218 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1219 1220 dw_mipi_dsi2_post_disable(dsi2); 1221 } 1222 1223 static int dw_mipi_dsi2_connector_enable(struct rockchip_connector *conn, 1224 struct display_state *state) 1225 { 1226 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1227 1228 dw_mipi_dsi2_enable(dsi2); 1229 1230 return 0; 1231 } 1232 1233 static int dw_mipi_dsi2_connector_disable(struct rockchip_connector *conn, 1234 struct display_state *state) 1235 { 1236 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1237 1238 dw_mipi_dsi2_disable(dsi2); 1239 1240 return 0; 1241 } 1242 1243 static int dw_mipi_dsi2_connector_mode_valid(struct rockchip_connector *conn, 1244 struct display_state *state) 1245 { 1246 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1247 struct connector_state *conn_state = &state->conn_state; 1248 u8 min_pixels = dsi2->slave ? 8 : 4; 1249 struct videomode vm; 1250 1251 drm_display_mode_to_videomode(&conn_state->mode, &vm); 1252 1253 /* 1254 * the minimum region size (HSA,HBP,HACT,HFP) is 4 pixels 1255 * which is the ip known issues and limitations. 1256 */ 1257 if (!(vm.hsync_len < min_pixels || vm.hback_porch < min_pixels || 1258 vm.hfront_porch < min_pixels || vm.hactive < min_pixels)) 1259 return MODE_OK; 1260 1261 if (vm.hsync_len < min_pixels) 1262 vm.hsync_len = min_pixels; 1263 1264 if (vm.hback_porch < min_pixels) 1265 vm.hback_porch = min_pixels; 1266 1267 if (vm.hfront_porch < min_pixels) 1268 vm.hfront_porch = min_pixels; 1269 1270 if (vm.hactive < min_pixels) 1271 vm.hactive = min_pixels; 1272 1273 memset(&conn_state->mode, 0, sizeof(struct drm_display_mode)); 1274 drm_display_mode_from_videomode(&vm, &conn_state->mode); 1275 conn_state->mode.vrefresh = drm_mode_vrefresh(&conn_state->mode); 1276 1277 return MODE_OK; 1278 } 1279 1280 static const struct rockchip_connector_funcs dw_mipi_dsi2_connector_funcs = { 1281 .pre_init = dw_mipi_dsi2_connector_pre_init, 1282 .init = dw_mipi_dsi2_connector_init, 1283 .prepare = dw_mipi_dsi2_connector_prepare, 1284 .unprepare = dw_mipi_dsi2_connector_unprepare, 1285 .enable = dw_mipi_dsi2_connector_enable, 1286 .disable = dw_mipi_dsi2_connector_disable, 1287 .mode_valid = dw_mipi_dsi2_connector_mode_valid, 1288 }; 1289 1290 static int dw_mipi_dsi2_probe(struct udevice *dev) 1291 { 1292 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(dev); 1293 const struct dw_mipi_dsi2_plat_data *pdata = 1294 (const struct dw_mipi_dsi2_plat_data *)dev_get_driver_data(dev); 1295 struct udevice *syscon; 1296 int id, ret; 1297 1298 dsi2->base = dev_read_addr_ptr(dev); 1299 1300 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1301 &syscon); 1302 if (!ret) { 1303 dsi2->grf = syscon_get_regmap(syscon); 1304 if (!dsi2->grf) 1305 return -ENODEV; 1306 } 1307 1308 id = of_alias_get_id(ofnode_to_np(dev->node), "dsi"); 1309 if (id < 0) 1310 id = 0; 1311 1312 ret = gpio_request_by_name(dev, "te-gpios", 0, 1313 &dsi2->te_gpio, GPIOD_IS_IN); 1314 if (ret && ret != -ENOENT) { 1315 printf("%s: Cannot get TE GPIO: %d\n", __func__, ret); 1316 return ret; 1317 } 1318 1319 ret = clk_get_by_name(dev, "sys_clk", &dsi2->sys_clk); 1320 if (ret < 0) { 1321 printf("failed to get sys_clk: %d\n", ret); 1322 return ret; 1323 } 1324 1325 dsi2->dev = dev; 1326 dsi2->pdata = pdata; 1327 dsi2->id = id; 1328 dsi2->dual_channel = dev_read_bool(dsi2->dev, "rockchip,dual-channel"); 1329 dsi2->data_swap = dev_read_bool(dsi2->dev, "rockchip,data-swap"); 1330 dsi2->auto_calc_mode = dev_read_bool(dsi2->dev, "auto-calculation-mode"); 1331 dsi2->disable_hold_mode = dev_read_bool(dsi2->dev, "disable-hold-mode"); 1332 1333 rockchip_connector_bind(&dsi2->connector, dev, id, &dw_mipi_dsi2_connector_funcs, NULL, 1334 DRM_MODE_CONNECTOR_DSI); 1335 1336 return 0; 1337 } 1338 1339 static const u32 rk3576_dsi_grf_reg_fields[MAX_FIELDS] = { 1340 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0028, 1, 1), 1341 [GATING_EN] = GRF_REG_FIELD(0x0028, 0, 0), 1342 [IPI_SHUTDN] = GRF_REG_FIELD(0x0028, 3, 3), 1343 [IPI_COLORM] = GRF_REG_FIELD(0x0028, 2, 2), 1344 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0028, 8, 11), 1345 [IPI_FORMAT] = GRF_REG_FIELD(0x0028, 4, 7), 1346 }; 1347 1348 static const u32 rk3588_dsi0_grf_reg_fields[MAX_FIELDS] = { 1349 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0000, 11, 11), 1350 [GATING_EN] = GRF_REG_FIELD(0x0000, 10, 10), 1351 [IPI_SHUTDN] = GRF_REG_FIELD(0x0000, 9, 9), 1352 [IPI_COLORM] = GRF_REG_FIELD(0x0000, 8, 8), 1353 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0000, 4, 7), 1354 [IPI_FORMAT] = GRF_REG_FIELD(0x0000, 0, 3), 1355 }; 1356 1357 static const u32 rk3588_dsi1_grf_reg_fields[MAX_FIELDS] = { 1358 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0004, 11, 11), 1359 [GATING_EN] = GRF_REG_FIELD(0x0004, 10, 10), 1360 [IPI_SHUTDN] = GRF_REG_FIELD(0x0004, 9, 9), 1361 [IPI_COLORM] = GRF_REG_FIELD(0x0004, 8, 8), 1362 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0004, 4, 7), 1363 [IPI_FORMAT] = GRF_REG_FIELD(0x0004, 0, 3), 1364 }; 1365 1366 static const struct dw_mipi_dsi2_plat_data rk3576_mipi_dsi2_plat_data = { 1367 .dsc = false, 1368 .dsi0_grf_reg_fields = rk3576_dsi_grf_reg_fields, 1369 .dphy_max_bit_rate_per_lane = 2500000000ULL, 1370 .cphy_max_symbol_rate_per_lane = 1700000000ULL, 1371 }; 1372 1373 static const struct dw_mipi_dsi2_plat_data rk3588_mipi_dsi2_plat_data = { 1374 .dsc = true, 1375 .dsi0_grf_reg_fields = rk3588_dsi0_grf_reg_fields, 1376 .dsi1_grf_reg_fields = rk3588_dsi1_grf_reg_fields, 1377 .dphy_max_bit_rate_per_lane = 4500000000ULL, 1378 .cphy_max_symbol_rate_per_lane = 2000000000ULL, 1379 }; 1380 1381 static const struct udevice_id dw_mipi_dsi2_ids[] = { 1382 { 1383 .compatible = "rockchip,rk3576-mipi-dsi2", 1384 .data = (ulong)&rk3576_mipi_dsi2_plat_data, 1385 }, { 1386 .compatible = "rockchip,rk3588-mipi-dsi2", 1387 .data = (ulong)&rk3588_mipi_dsi2_plat_data, 1388 }, 1389 {} 1390 }; 1391 1392 static ssize_t dw_mipi_dsi2_host_transfer(struct mipi_dsi_host *host, 1393 const struct mipi_dsi_msg *msg) 1394 { 1395 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1396 1397 return dw_mipi_dsi2_transfer(dsi2, msg); 1398 } 1399 1400 static int dw_mipi_dsi2_host_attach(struct mipi_dsi_host *host, 1401 struct mipi_dsi_device *device) 1402 { 1403 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1404 1405 if (device->lanes < 1 || device->lanes > 8) 1406 return -EINVAL; 1407 1408 dsi2->lanes = device->lanes; 1409 dsi2->channel = device->channel; 1410 dsi2->format = device->format; 1411 dsi2->mode_flags = device->mode_flags; 1412 dsi2->device = device; 1413 1414 return 0; 1415 } 1416 1417 static const struct mipi_dsi_host_ops dw_mipi_dsi2_host_ops = { 1418 .attach = dw_mipi_dsi2_host_attach, 1419 .transfer = dw_mipi_dsi2_host_transfer, 1420 }; 1421 1422 static int dw_mipi_dsi2_bind(struct udevice *dev) 1423 { 1424 struct mipi_dsi_host *host = dev_get_platdata(dev); 1425 1426 host->dev = dev; 1427 host->ops = &dw_mipi_dsi2_host_ops; 1428 1429 return dm_scan_fdt_dev(dev); 1430 } 1431 1432 static int dw_mipi_dsi2_child_post_bind(struct udevice *dev) 1433 { 1434 struct mipi_dsi_host *host = dev_get_platdata(dev->parent); 1435 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1436 char name[20]; 1437 1438 sprintf(name, "%s.%d", host->dev->name, device->channel); 1439 device_set_name(dev, name); 1440 1441 device->dev = dev; 1442 device->host = host; 1443 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4); 1444 device->format = dev_read_u32_default(dev, "dsi,format", 1445 MIPI_DSI_FMT_RGB888); 1446 device->mode_flags = dev_read_u32_default(dev, "dsi,flags", 1447 MIPI_DSI_MODE_VIDEO | 1448 MIPI_DSI_MODE_VIDEO_BURST | 1449 MIPI_DSI_MODE_VIDEO_HBP | 1450 MIPI_DSI_MODE_LPM | 1451 MIPI_DSI_MODE_EOT_PACKET); 1452 device->channel = dev_read_u32_default(dev, "reg", 0); 1453 1454 return 0; 1455 } 1456 1457 static int dw_mipi_dsi2_child_pre_probe(struct udevice *dev) 1458 { 1459 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1460 int ret; 1461 1462 ret = mipi_dsi_attach(device); 1463 if (ret) { 1464 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret); 1465 return ret; 1466 } 1467 1468 return 0; 1469 } 1470 1471 U_BOOT_DRIVER(dw_mipi_dsi2) = { 1472 .name = "dw_mipi_dsi2", 1473 .id = UCLASS_DISPLAY, 1474 .of_match = dw_mipi_dsi2_ids, 1475 .probe = dw_mipi_dsi2_probe, 1476 .bind = dw_mipi_dsi2_bind, 1477 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi2), 1478 .per_child_platdata_auto_alloc_size = sizeof(struct mipi_dsi_device), 1479 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_host), 1480 .child_post_bind = dw_mipi_dsi2_child_post_bind, 1481 .child_pre_probe = dw_mipi_dsi2_child_pre_probe, 1482 }; 1483