1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Author: Guochun Huang <hero.huang@rock-chips.com> 7 */ 8 9 #include <drm/drm_mipi_dsi.h> 10 11 #include <config.h> 12 #include <common.h> 13 #include <errno.h> 14 #include <asm/unaligned.h> 15 #include <asm/io.h> 16 #include <asm/hardware.h> 17 #include <dm/device.h> 18 #include <dm/read.h> 19 #include <dm/of_access.h> 20 #include <regmap.h> 21 #include <syscon.h> 22 #include <asm/arch-rockchip/clock.h> 23 #include <linux/iopoll.h> 24 25 #include "rockchip_display.h" 26 #include "rockchip_crtc.h" 27 #include "rockchip_connector.h" 28 #include "rockchip_panel.h" 29 #include "rockchip_phy.h" 30 31 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) 32 33 #define DSI2_PWR_UP 0x000c 34 #define RESET 0 35 #define POWER_UP BIT(0) 36 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 37 #define DSI2_SOFT_RESET 0x0010 38 #define SYS_RSTN BIT(2) 39 #define PHY_RSTN BIT(1) 40 #define IPI_RSTN BIT(0) 41 #define INT_ST_MAIN 0x0014 42 #define DSI2_MODE_CTRL 0x0018 43 #define DSI2_MODE_STATUS 0x001c 44 #define DSI2_CORE_STATUS 0x0020 45 #define PRI_RD_DATA_AVAIL BIT(26) 46 #define PRI_FIFOS_NOT_EMPTY BIT(25) 47 #define PRI_BUSY BIT(24) 48 #define CRI_RD_DATA_AVAIL BIT(18) 49 #define CRT_FIFOS_NOT_EMPTY BIT(17) 50 #define CRI_BUSY BIT(16) 51 #define IPI_FIFOS_NOT_EMPTY BIT(9) 52 #define IPI_BUSY BIT(8) 53 #define CORE_FIFOS_NOT_EMPTY BIT(1) 54 #define CORE_BUSY BIT(0) 55 #define MANUAL_MODE_CFG 0x0024 56 #define MANUAL_MODE_EN BIT(0) 57 #define DSI2_TIMEOUT_HSTX_CFG 0x0048 58 #define TO_HSTX(x) UPDATE(x, 15, 0) 59 #define DSI2_TIMEOUT_HSTXRDY_CFG 0x004c 60 #define TO_HSTXRDY(x) UPDATE(x, 15, 0) 61 #define DSI2_TIMEOUT_LPRX_CFG 0x0050 62 #define TO_LPRXRDY(x) UPDATE(x, 15, 0) 63 #define DSI2_TIMEOUT_LPTXRDY_CFG 0x0054 64 #define TO_LPTXRDY(x) UPDATE(x, 15, 0) 65 #define DSI2_TIMEOUT_LPTXTRIG_CFG 0x0058 66 #define TO_LPTXTRIG(x) UPDATE(x, 15, 0) 67 #define DSI2_TIMEOUT_LPTXULPS_CFG 0x005c 68 #define TO_LPTXULPS(x) UPDATE(x, 15, 0) 69 #define DSI2_TIMEOUT_BTA_CFG 0x60 70 #define TO_BTA(x) UPDATE(x, 15, 0) 71 72 #define DSI2_PHY_MODE_CFG 0x0100 73 #define PPI_WIDTH(x) UPDATE(x, 9, 8) 74 #define PHY_LANES(x) UPDATE(x - 1, 5, 4) 75 #define PHY_TYPE(x) UPDATE(x, 0, 0) 76 #define DSI2_PHY_CLK_CFG 0X0104 77 #define PHY_LPTX_CLK_DIV(x) UPDATE(x, 12, 8) 78 #define NON_CONTINUOUS_CLK BIT(0) 79 #define DSI2_PHY_LP2HS_MAN_CFG 0x010c 80 #define PHY_LP2HS_TIME(x) UPDATE(x, 28, 0) 81 #define DSI2_PHY_HS2LP_MAN_CFG 0x0114 82 #define PHY_HS2LP_TIME(x) UPDATE(x, 28, 0) 83 #define DSI2_PHY_MAX_RD_T_MAN_CFG 0x011c 84 #define PHY_MAX_RD_TIME(x) UPDATE(x, 26, 0) 85 #define DSI2_PHY_ESC_CMD_T_MAN_CFG 0x0124 86 #define PHY_ESC_CMD_TIME(x) UPDATE(x, 28, 0) 87 #define DSI2_PHY_ESC_BYTE_T_MAN_CFG 0x012c 88 #define PHY_ESC_BYTE_TIME(x) UPDATE(x, 28, 0) 89 90 #define DSI2_PHY_IPI_RATIO_MAN_CFG 0x0134 91 #define PHY_IPI_RATIO(x) UPDATE(x, 21, 0) 92 #define DSI2_PHY_SYS_RATIO_MAN_CFG 0x013C 93 #define PHY_SYS_RATIO(x) UPDATE(x, 16, 0) 94 95 #define DSI2_DSI_GENERAL_CFG 0x0200 96 #define BTA_EN BIT(1) 97 #define EOTP_TX_EN BIT(0) 98 #define DSI2_DSI_VCID_CFG 0x0204 99 #define TX_VCID(x) UPDATE(x, 1, 0) 100 #define DSI2_DSI_SCRAMBLING_CFG 0x0208 101 #define SCRAMBLING_SEED(x) UPDATE(x, 31, 16) 102 #define SCRAMBLING_EN BIT(0) 103 #define DSI2_DSI_VID_TX_CFG 0x020c 104 #define LPDT_DISPLAY_CMD_EN BIT(20) 105 #define BLK_VFP_HS_EN BIT(14) 106 #define BLK_VBP_HS_EN BIT(13) 107 #define BLK_VSA_HS_EN BIT(12) 108 #define BLK_HFP_HS_EN BIT(6) 109 #define BLK_HBP_HS_EN BIT(5) 110 #define BLK_HSA_HS_EN BIT(4) 111 #define VID_MODE_TYPE(x) UPDATE(x, 1, 0) 112 #define DSI2_CRI_TX_HDR 0x02c0 113 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 114 #define DSI2_CRI_TX_PLD 0x02c4 115 #define DSI2_CRI_RX_HDR 0x02c8 116 #define DSI2_CRI_RX_PLD 0x02cc 117 118 #define DSI2_IPI_COLOR_MAN_CFG 0x0300 119 #define IPI_DEPTH(x) UPDATE(x, 7, 4) 120 #define IPI_DEPTH_5_6_5_BITS 0x02 121 #define IPI_DEPTH_6_BITS 0x03 122 #define IPI_DEPTH_8_BITS 0x05 123 #define IPI_DEPTH_10_BITS 0x06 124 #define IPI_FORMAT(x) UPDATE(x, 3, 0) 125 #define IPI_FORMAT_RGB 0x0 126 #define IPI_FORMAT_DSC 0x0b 127 #define DSI2_IPI_VID_HSA_MAN_CFG 0x0304 128 #define VID_HSA_TIME(x) UPDATE(x, 29, 0) 129 #define DSI2_IPI_VID_HBP_MAN_CFG 0x030c 130 #define VID_HBP_TIME(x) UPDATE(x, 29, 0) 131 #define DSI2_IPI_VID_HACT_MAN_CFG 0x0314 132 #define VID_HACT_TIME(x) UPDATE(x, 29, 0) 133 #define DSI2_IPI_VID_HLINE_MAN_CFG 0x031c 134 #define VID_HLINE_TIME(x) UPDATE(x, 29, 0) 135 #define DSI2_IPI_VID_VSA_MAN_CFG 0x0324 136 #define VID_VSA_LINES(x) UPDATE(x, 9, 0) 137 #define DSI2_IPI_VID_VBP_MAN_CFG 0X032C 138 #define VID_VBP_LINES(x) UPDATE(x, 9, 0) 139 #define DSI2_IPI_VID_VACT_MAN_CFG 0X0334 140 #define VID_VACT_LINES(x) UPDATE(x, 13, 0) 141 #define DSI2_IPI_VID_VFP_MAN_CFG 0X033C 142 #define VID_VFP_LINES(x) UPDATE(x, 9, 0) 143 #define DSI2_IPI_PIX_PKT_CFG 0x0344 144 #define MAX_PIX_PKT(x) UPDATE(x, 15, 0) 145 146 #define DSI2_INT_ST_PHY 0x0400 147 #define DSI2_INT_MASK_PHY 0x0404 148 #define DSI2_INT_ST_TO 0x0410 149 #define DSI2_INT_MASK_TO 0x0414 150 #define DSI2_INT_ST_ACK 0x0420 151 #define DSI2_INT_MASK_ACK 0x0424 152 #define DSI2_INT_ST_IPI 0x0430 153 #define DSI2_INT_MASK_IPI 0x0434 154 #define DSI2_INT_ST_FIFO 0x0440 155 #define DSI2_INT_MASK_FIFO 0x0444 156 #define DSI2_INT_ST_PRI 0x0450 157 #define DSI2_INT_MASK_PRI 0x0454 158 #define DSI2_INT_ST_CRI 0x0460 159 #define DSI2_INT_MASK_CRI 0x0464 160 #define DSI2_INT_FORCE_CRI 0x0468 161 #define DSI2_MAX_REGISGER DSI2_INT_FORCE_CRI 162 163 #define CMD_PKT_STATUS_TIMEOUT_US 1000 164 #define MODE_STATUS_TIMEOUT_US 20000 165 #define SYS_CLK 351000000LL 166 #define PSEC_PER_SEC 1000000000000LL 167 #define USEC_PER_SEC 1000000L 168 #define MSEC_PER_SEC 1000L 169 170 #define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 16) | ((lsb) << 8) | (msb)) 171 172 enum vid_mode_type { 173 VID_MODE_TYPE_NON_BURST_SYNC_PULSES, 174 VID_MODE_TYPE_NON_BURST_SYNC_EVENTS, 175 VID_MODE_TYPE_BURST, 176 }; 177 178 enum mode_ctrl { 179 IDLE_MODE, 180 AUTOCALC_MODE, 181 COMMAND_MODE, 182 VIDEO_MODE, 183 DATA_STREAM_MODE, 184 VIDE_TEST_MODE, 185 DATA_STREAM_TEST_MODE, 186 }; 187 188 enum grf_reg_fields { 189 TXREQCLKHS_EN, 190 GATING_EN, 191 IPI_SHUTDN, 192 IPI_COLORM, 193 IPI_COLOR_DEPTH, 194 IPI_FORMAT, 195 MAX_FIELDS, 196 }; 197 198 enum phy_type { 199 DPHY, 200 CPHY, 201 }; 202 203 enum ppi_width { 204 PPI_WIDTH_8_BITS, 205 PPI_WIDTH_16_BITS, 206 PPI_WIDTH_32_BITS, 207 }; 208 209 struct rockchip_cmd_header { 210 u8 data_type; 211 u8 delay_ms; 212 u8 payload_length; 213 }; 214 215 struct dw_mipi_dsi2_plat_data { 216 const u32 *dsi0_grf_reg_fields; 217 const u32 *dsi1_grf_reg_fields; 218 unsigned long long dphy_max_bit_rate_per_lane; 219 unsigned long long cphy_max_symbol_rate_per_lane; 220 }; 221 222 struct mipi_dcphy { 223 /* Non-SNPS PHY */ 224 struct rockchip_phy *phy; 225 226 u16 input_div; 227 u16 feedback_div; 228 }; 229 230 /** 231 * struct mipi_dphy_configure - MIPI D-PHY configuration set 232 * 233 * This structure is used to represent the configuration state of a 234 * MIPI D-PHY phy. 235 */ 236 struct mipi_dphy_configure { 237 unsigned int clk_miss; 238 unsigned int clk_post; 239 unsigned int clk_pre; 240 unsigned int clk_prepare; 241 unsigned int clk_settle; 242 unsigned int clk_term_en; 243 unsigned int clk_trail; 244 unsigned int clk_zero; 245 unsigned int d_term_en; 246 unsigned int eot; 247 unsigned int hs_exit; 248 unsigned int hs_prepare; 249 unsigned int hs_settle; 250 unsigned int hs_skip; 251 unsigned int hs_trail; 252 unsigned int hs_zero; 253 unsigned int init; 254 unsigned int lpx; 255 unsigned int ta_get; 256 unsigned int ta_go; 257 unsigned int ta_sure; 258 unsigned int wakeup; 259 unsigned long hs_clk_rate; 260 unsigned long lp_clk_rate; 261 unsigned char lanes; 262 }; 263 264 struct dw_mipi_dsi2 { 265 struct udevice *dev; 266 void *base; 267 void *grf; 268 int id; 269 struct dw_mipi_dsi2 *master; 270 struct dw_mipi_dsi2 *slave; 271 bool prepared; 272 273 bool c_option; 274 bool dsc_enable; 275 bool scrambling_en; 276 unsigned int slice_width; 277 unsigned int slice_height; 278 u32 version_major; 279 u32 version_minor; 280 281 unsigned int lane_hs_rate; /* Kbps/Ksps per lane */ 282 u32 channel; 283 u32 lanes; 284 u32 format; 285 u32 mode_flags; 286 struct mipi_dcphy dcphy; 287 struct drm_display_mode mode; 288 bool data_swap; 289 290 struct mipi_dphy_configure mipi_dphy_cfg; 291 const struct dw_mipi_dsi2_plat_data *pdata; 292 struct drm_dsc_picture_parameter_set *pps; 293 }; 294 295 static inline void dsi_write(struct dw_mipi_dsi2 *dsi2, u32 reg, u32 val) 296 { 297 writel(val, dsi2->base + reg); 298 } 299 300 static inline u32 dsi_read(struct dw_mipi_dsi2 *dsi2, u32 reg) 301 { 302 return readl(dsi2->base + reg); 303 } 304 305 static inline void dsi_update_bits(struct dw_mipi_dsi2 *dsi2, 306 u32 reg, u32 mask, u32 val) 307 { 308 u32 orig, tmp; 309 310 orig = dsi_read(dsi2, reg); 311 tmp = orig & ~mask; 312 tmp |= val & mask; 313 dsi_write(dsi2, reg, tmp); 314 } 315 316 static void grf_field_write(struct dw_mipi_dsi2 *dsi2, enum grf_reg_fields index, 317 unsigned int val) 318 { 319 const u32 field = dsi2->id ? dsi2->pdata->dsi1_grf_reg_fields[index] : 320 dsi2->pdata->dsi0_grf_reg_fields[index]; 321 u16 reg; 322 u8 msb, lsb; 323 324 if (!field) 325 return; 326 327 reg = (field >> 16) & 0xffff; 328 lsb = (field >> 8) & 0xff; 329 msb = (field >> 0) & 0xff; 330 331 regmap_write(dsi2->grf, reg, GENMASK(msb, lsb) << 16 | val << lsb); 332 } 333 334 static unsigned long dw_mipi_dsi2_get_lane_rate(struct dw_mipi_dsi2 *dsi2) 335 { 336 const struct drm_display_mode *mode = &dsi2->mode; 337 u64 max_lane_rate, lane_rate; 338 unsigned int value; 339 int bpp, lanes; 340 u64 tmp; 341 342 max_lane_rate = (dsi2->c_option) ? 343 dsi2->pdata->cphy_max_symbol_rate_per_lane : 344 dsi2->pdata->dphy_max_bit_rate_per_lane; 345 346 /* optional override of the desired bandwidth */ 347 value = dev_read_u32_default(dsi2->dev, "rockchip,lane-rate", 0); 348 if (value > 0) 349 return value * MSEC_PER_SEC; 350 351 bpp = mipi_dsi_pixel_format_to_bpp(dsi2->format); 352 if (bpp < 0) 353 bpp = 24; 354 355 lanes = dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes; 356 tmp = (u64)mode->clock * 1000 * bpp; 357 do_div(tmp, lanes); 358 359 if (dsi2->c_option) 360 tmp = DIV_ROUND_CLOSEST(tmp * 100, 228); 361 362 /* set BW a little larger only in video burst mode in 363 * consideration of the protocol overhead and HS mode 364 * switching to BLLP mode, take 1 / 0.9, since Mbps must 365 * big than bandwidth of RGB 366 */ 367 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { 368 tmp *= 10; 369 do_div(tmp, 9); 370 } 371 372 if (tmp > max_lane_rate) 373 lane_rate = max_lane_rate; 374 else 375 lane_rate = tmp; 376 377 return lane_rate; 378 } 379 380 static int cri_fifos_wait_avail(struct dw_mipi_dsi2 *dsi2) 381 { 382 u32 sts, mask; 383 int ret; 384 385 mask = CRI_BUSY | CRT_FIFOS_NOT_EMPTY; 386 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 387 sts, !(sts & mask), 388 CMD_PKT_STATUS_TIMEOUT_US); 389 if (ret < 0) { 390 printf("command interface is busy: 0x%x\n", sts); 391 return ret; 392 } 393 394 return 0; 395 } 396 397 static int dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 *dsi2, 398 const struct mipi_dsi_msg *msg) 399 { 400 u8 *payload = msg->rx_buf; 401 u8 data_type; 402 u16 wc; 403 int i, j, ret, len = msg->rx_len; 404 unsigned int vrefresh = drm_mode_vrefresh(&dsi2->mode); 405 u32 val; 406 407 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 408 val, val & CRI_RD_DATA_AVAIL, 409 DIV_ROUND_UP(1000000, vrefresh)); 410 if (ret) { 411 printf("CRI has no available read data\n"); 412 return ret; 413 } 414 415 val = dsi_read(dsi2, DSI2_CRI_RX_HDR); 416 data_type = val & 0x3f; 417 418 if (mipi_dsi_packet_format_is_short(data_type)) { 419 for (i = 0; i < len && i < 2; i++) 420 payload[i] = (val >> (8 * (i + 1))) & 0xff; 421 422 return 0; 423 } 424 425 wc = (val >> 8) & 0xffff; 426 /* Receive payload */ 427 for (i = 0; i < len && i < wc; i += 4) { 428 val = dsi_read(dsi2, DSI2_CRI_RX_PLD); 429 for (j = 0; j < 4 && j + i < len && j + i < wc; j++) 430 payload[i + j] = val >> (8 * j); 431 } 432 433 return 0; 434 } 435 436 static ssize_t dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 *dsi2, 437 const struct mipi_dsi_msg *msg) 438 { 439 struct mipi_dsi_packet packet; 440 int ret; 441 int val; 442 u32 mode; 443 444 dsi_update_bits(dsi2, DSI2_DSI_VID_TX_CFG, LPDT_DISPLAY_CMD_EN, 445 msg->flags & MIPI_DSI_MSG_USE_LPM ? 446 LPDT_DISPLAY_CMD_EN : 0); 447 448 /* create a packet to the DSI protocol */ 449 ret = mipi_dsi_create_packet(&packet, msg); 450 if (ret) { 451 printf("failed to create packet: %d\n", ret); 452 return ret; 453 } 454 455 /* check cri interface is not busy */ 456 ret = cri_fifos_wait_avail(dsi2); 457 if (ret) 458 return ret; 459 460 /* Send payload */ 461 while (DIV_ROUND_UP(packet.payload_length, 4)) { 462 if (packet.payload_length < 4) { 463 /* send residu payload */ 464 val = 0; 465 memcpy(&val, packet.payload, packet.payload_length); 466 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 467 packet.payload_length = 0; 468 } else { 469 val = get_unaligned_le32(packet.payload); 470 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 471 packet.payload += 4; 472 packet.payload_length -= 4; 473 } 474 } 475 476 /* Send packet header */ 477 mode = CMD_TX_MODE(msg->flags & MIPI_DSI_MSG_USE_LPM ? 1 : 0); 478 val = get_unaligned_le32(packet.header); 479 dsi_write(dsi2, DSI2_CRI_TX_HDR, mode | val); 480 481 ret = cri_fifos_wait_avail(dsi2); 482 if (ret) 483 return ret; 484 485 if (msg->rx_len) { 486 ret = dw_mipi_dsi2_read_from_fifo(dsi2, msg); 487 if (ret < 0) 488 return ret; 489 } 490 491 if (dsi2->slave) { 492 ret = dw_mipi_dsi2_transfer(dsi2->slave, msg); 493 if (ret < 0) 494 return ret; 495 } 496 497 return msg->rx_len ? msg->rx_len : msg->tx_len; 498 } 499 500 static void dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 *dsi2) 501 { 502 u32 val, color_depth; 503 504 switch (dsi2->format) { 505 case MIPI_DSI_FMT_RGB666: 506 case MIPI_DSI_FMT_RGB666_PACKED: 507 color_depth = IPI_DEPTH_6_BITS; 508 break; 509 case MIPI_DSI_FMT_RGB565: 510 color_depth = IPI_DEPTH_5_6_5_BITS; 511 break; 512 case MIPI_DSI_FMT_RGB888: 513 default: 514 color_depth = IPI_DEPTH_8_BITS; 515 break; 516 } 517 518 val = IPI_DEPTH(color_depth) | 519 IPI_FORMAT(dsi2->dsc_enable ? IPI_FORMAT_DSC : IPI_FORMAT_RGB); 520 dsi_write(dsi2, DSI2_IPI_COLOR_MAN_CFG, val); 521 grf_field_write(dsi2, IPI_COLOR_DEPTH, color_depth); 522 523 if (dsi2->dsc_enable) 524 grf_field_write(dsi2, IPI_FORMAT, IPI_FORMAT_DSC); 525 } 526 527 static void dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 *dsi2) 528 { 529 struct drm_display_mode *mode = &dsi2->mode; 530 u32 hline, hsa, hbp, hact; 531 u64 hline_time, hsa_time, hbp_time, hact_time, tmp; 532 u64 pixel_clk, phy_hs_clk; 533 u32 vact, vsa, vfp, vbp; 534 u16 val; 535 536 if (dsi2->slave || dsi2->master) 537 val = mode->hdisplay / 2; 538 else 539 val = mode->hdisplay; 540 541 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val)); 542 543 dw_mipi_dsi2_ipi_color_coding_cfg(dsi2); 544 545 /* 546 * if the controller is intended to operate in data stream mode, 547 * no more steps are required. 548 */ 549 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) 550 return; 551 552 vact = mode->vdisplay; 553 vsa = mode->vsync_end - mode->vsync_start; 554 vfp = mode->vsync_start - mode->vdisplay; 555 vbp = mode->vtotal - mode->vsync_end; 556 hact = mode->hdisplay; 557 hsa = mode->hsync_end - mode->hsync_start; 558 hbp = mode->htotal - mode->hsync_end; 559 hline = mode->htotal; 560 561 pixel_clk = mode->clock * MSEC_PER_SEC; 562 563 if (dsi2->c_option) 564 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 565 else 566 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 567 568 tmp = hsa * phy_hs_clk; 569 hsa_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 570 dsi_write(dsi2, DSI2_IPI_VID_HSA_MAN_CFG, VID_HSA_TIME(hsa_time)); 571 572 tmp = hbp * phy_hs_clk; 573 hbp_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 574 dsi_write(dsi2, DSI2_IPI_VID_HBP_MAN_CFG, VID_HBP_TIME(hbp_time)); 575 576 tmp = hact * phy_hs_clk; 577 hact_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 578 dsi_write(dsi2, DSI2_IPI_VID_HACT_MAN_CFG, VID_HACT_TIME(hact_time)); 579 580 tmp = hline * phy_hs_clk; 581 hline_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 582 dsi_write(dsi2, DSI2_IPI_VID_HLINE_MAN_CFG, VID_HLINE_TIME(hline_time)); 583 584 dsi_write(dsi2, DSI2_IPI_VID_VSA_MAN_CFG, VID_VSA_LINES(vsa)); 585 dsi_write(dsi2, DSI2_IPI_VID_VBP_MAN_CFG, VID_VBP_LINES(vbp)); 586 dsi_write(dsi2, DSI2_IPI_VID_VACT_MAN_CFG, VID_VACT_LINES(vact)); 587 dsi_write(dsi2, DSI2_IPI_VID_VFP_MAN_CFG, VID_VFP_LINES(vfp)); 588 } 589 590 static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2) 591 { 592 u32 val = 0, mode; 593 int ret; 594 595 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 596 val |= VID_MODE_TYPE_BURST; 597 else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 598 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 599 600 else 601 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 602 603 dsi_write(dsi2, DSI2_DSI_VID_TX_CFG, val); 604 605 606 dsi_write(dsi2, DSI2_MODE_CTRL, VIDEO_MODE); 607 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 608 mode, mode & VIDEO_MODE, 609 MODE_STATUS_TIMEOUT_US); 610 if (ret < 0) 611 printf("failed to enter video mode\n"); 612 } 613 614 static void dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 *dsi2) 615 { 616 u32 mode; 617 int ret; 618 619 dsi_write(dsi2, DSI2_MODE_CTRL, DATA_STREAM_MODE); 620 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 621 mode, mode & DATA_STREAM_MODE, 622 MODE_STATUS_TIMEOUT_US); 623 if (ret < 0) 624 printf("failed to enter data stream mode\n"); 625 } 626 627 static void dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 *dsi2) 628 { 629 u32 mode; 630 int ret; 631 632 dsi_write(dsi2, DSI2_MODE_CTRL, COMMAND_MODE); 633 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 634 mode, mode & COMMAND_MODE, 635 MODE_STATUS_TIMEOUT_US); 636 if (ret < 0) 637 printf("failed to enter cmd mode\n"); 638 } 639 640 static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2) 641 { 642 dw_mipi_dsi2_ipi_set(dsi2); 643 644 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO) 645 dw_mipi_dsi2_set_vid_mode(dsi2); 646 else 647 dw_mipi_dsi2_set_data_stream_mode(dsi2); 648 649 if (dsi2->slave) 650 dw_mipi_dsi2_enable(dsi2->slave); 651 } 652 653 static void dw_mipi_dsi2_disable(struct dw_mipi_dsi2 *dsi2) 654 { 655 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, 0); 656 dw_mipi_dsi2_set_cmd_mode(dsi2); 657 658 if (dsi2->slave) 659 dw_mipi_dsi2_disable(dsi2->slave); 660 } 661 662 static void dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 *dsi2) 663 { 664 if (!dsi2->prepared) 665 return; 666 667 dsi_write(dsi2, DSI2_PWR_UP, RESET); 668 669 if (dsi2->dcphy.phy) 670 rockchip_phy_power_off(dsi2->dcphy.phy); 671 672 dsi2->prepared = false; 673 674 if (dsi2->slave) 675 dw_mipi_dsi2_post_disable(dsi2->slave); 676 } 677 678 static int dw_mipi_dsi2_connector_pre_init(struct display_state *state) 679 { 680 struct connector_state *conn_state = &state->conn_state; 681 682 conn_state->type = DRM_MODE_CONNECTOR_DSI; 683 684 return 0; 685 } 686 687 static int dw_mipi_dsi2_connector_init(struct display_state *state) 688 { 689 struct connector_state *conn_state = &state->conn_state; 690 struct crtc_state *cstate = &state->crtc_state; 691 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 692 struct rockchip_phy *phy = NULL; 693 struct udevice *phy_dev; 694 struct udevice *dev; 695 int ret; 696 697 698 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dsi2->id); 699 dsi2->dcphy.phy = conn_state->phy; 700 701 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 702 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 703 conn_state->output_if |= 704 dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0; 705 706 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) { 707 conn_state->output_flags |= ROCKCHIP_OUTPUT_MIPI_DS_MODE; 708 conn_state->hold_mode = true; 709 } 710 711 if (dsi2->lanes > 4) { 712 ret = uclass_get_device_by_name(UCLASS_DISPLAY, 713 "dsi@fde30000", 714 &dev); 715 if (ret) 716 return ret; 717 718 dsi2->slave = dev_get_priv(dev); 719 if (!dsi2->slave) 720 return -ENODEV; 721 722 dsi2->slave->master = dsi2; 723 dsi2->lanes /= 2; 724 dsi2->slave->lanes = dsi2->lanes; 725 dsi2->slave->format = dsi2->format; 726 dsi2->slave->mode_flags = dsi2->mode_flags; 727 dsi2->slave->channel = dsi2->channel; 728 conn_state->output_flags |= 729 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; 730 if (dsi2->data_swap) 731 conn_state->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP; 732 733 conn_state->output_if |= VOP_OUTPUT_IF_MIPI1; 734 735 ret = uclass_get_device_by_phandle(UCLASS_PHY, dev, 736 "phys", &phy_dev); 737 if (ret) 738 return -ENODEV; 739 740 phy = (struct rockchip_phy *)dev_get_driver_data(phy_dev); 741 if (!phy) 742 return -ENODEV; 743 744 dsi2->slave->dcphy.phy = phy; 745 if (phy->funcs && phy->funcs->init) 746 return phy->funcs->init(phy); 747 } 748 749 if (dsi2->dsc_enable) { 750 cstate->dsc_enable = 1; 751 cstate->dsc_sink_cap.version_major = dsi2->version_major; 752 cstate->dsc_sink_cap.version_minor = dsi2->version_minor; 753 cstate->dsc_sink_cap.slice_width = dsi2->slice_width; 754 cstate->dsc_sink_cap.slice_height = dsi2->slice_height; 755 /* only can support rgb888 panel now */ 756 cstate->dsc_sink_cap.target_bits_per_pixel_x16 = 8 << 4; 757 cstate->dsc_sink_cap.native_420 = 0; 758 memcpy(&cstate->pps, dsi2->pps, sizeof(struct drm_dsc_picture_parameter_set)); 759 } 760 761 return 0; 762 } 763 764 /* 765 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived 766 * from the valid ranges specified in Section 6.9, Table 14, Page 41 767 * of the D-PHY specification (v2.1). 768 */ 769 int mipi_dphy_get_default_config(unsigned long long hs_clk_rate, 770 struct mipi_dphy_configure *cfg) 771 { 772 unsigned long long ui; 773 774 if (!cfg) 775 return -EINVAL; 776 777 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); 778 do_div(ui, hs_clk_rate); 779 780 cfg->clk_miss = 0; 781 cfg->clk_post = 60000 + 52 * ui; 782 cfg->clk_pre = 8000; 783 cfg->clk_prepare = 38000; 784 cfg->clk_settle = 95000; 785 cfg->clk_term_en = 0; 786 cfg->clk_trail = 60000; 787 cfg->clk_zero = 262000; 788 cfg->d_term_en = 0; 789 cfg->eot = 0; 790 cfg->hs_exit = 100000; 791 cfg->hs_prepare = 40000 + 4 * ui; 792 cfg->hs_zero = 105000 + 6 * ui; 793 cfg->hs_settle = 85000 + 6 * ui; 794 cfg->hs_skip = 40000; 795 796 /* 797 * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40) 798 * contains this formula as: 799 * 800 * T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui) 801 * 802 * where n = 1 for forward-direction HS mode and n = 4 for reverse- 803 * direction HS mode. There's only one setting and this function does 804 * not parameterize on anything other that ui, so this code will 805 * assumes that reverse-direction HS mode is supported and uses n = 4. 806 */ 807 cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui); 808 809 cfg->init = 100; 810 cfg->lpx = 60000; 811 cfg->ta_get = 5 * cfg->lpx; 812 cfg->ta_go = 4 * cfg->lpx; 813 cfg->ta_sure = 2 * cfg->lpx; 814 cfg->wakeup = 1000; 815 816 return 0; 817 } 818 819 static void dw_mipi_dsi2_set_hs_clk(struct dw_mipi_dsi2 *dsi2, unsigned long rate) 820 { 821 mipi_dphy_get_default_config(rate, &dsi2->mipi_dphy_cfg); 822 823 if (!dsi2->c_option) 824 rockchip_phy_set_mode(dsi2->dcphy.phy, PHY_MODE_MIPI_DPHY); 825 826 rate = rockchip_phy_set_pll(dsi2->dcphy.phy, rate); 827 dsi2->lane_hs_rate = DIV_ROUND_CLOSEST(rate, MSEC_PER_SEC); 828 } 829 830 static void dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 *dsi2) 831 { 832 dsi_write(dsi2, DSI2_SOFT_RESET, 0X0); 833 udelay(100); 834 dsi_write(dsi2, DSI2_SOFT_RESET, SYS_RSTN | PHY_RSTN | IPI_RSTN); 835 } 836 837 static void 838 dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 *dsi2, u32 mode) 839 { 840 /* 841 * select controller work in Manual mode 842 * Manual: MANUAL_MODE_EN 843 * Automatic: 0 844 */ 845 dsi_write(dsi2, MANUAL_MODE_CFG, mode); 846 } 847 848 static void dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 *dsi2) 849 { 850 u32 val = 0; 851 852 /* PPI width is fixed to 16 bits in DCPHY */ 853 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes); 854 val |= PHY_TYPE(dsi2->c_option ? CPHY : DPHY); 855 dsi_write(dsi2, DSI2_PHY_MODE_CFG, val); 856 } 857 858 static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2) 859 { 860 u32 sys_clk = SYS_CLK / MSEC_PER_SEC; 861 u32 esc_clk_div; 862 u32 val = 0; 863 864 if (dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 865 val |= NON_CONTINUOUS_CLK; 866 867 /* The Escape clock ranges from 1MHz to 20MHz. */ 868 esc_clk_div = DIV_ROUND_UP(sys_clk, 10 * 2); 869 val |= PHY_LPTX_CLK_DIV(esc_clk_div); 870 871 dsi_write(dsi2, DSI2_PHY_CLK_CFG, val); 872 } 873 874 static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2) 875 { 876 struct drm_display_mode *mode = &dsi2->mode; 877 u64 pixel_clk, ipi_clk, phy_hsclk, tmp; 878 879 /* 880 * in DPHY mode, the phy_hstx_clk is exactly 1/16 the Lane high-speed 881 * data rate; In CPHY mode, the phy_hstx_clk is exactly 1/7 the trio 882 * high speed symbol rate. 883 */ 884 if (dsi2->c_option) 885 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 886 887 else 888 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 889 890 /* IPI_RATIO_MAN_CFG = PHY_HSTX_CLK / IPI_CLK */ 891 pixel_clk = mode->clock * MSEC_PER_SEC; 892 ipi_clk = pixel_clk / 4; 893 894 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, ipi_clk); 895 dsi_write(dsi2, DSI2_PHY_IPI_RATIO_MAN_CFG, PHY_IPI_RATIO(tmp)); 896 897 /* SYS_RATIO_MAN_CFG = MIPI_DCPHY_HSCLK_Freq / SYS_CLK */ 898 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, SYS_CLK); 899 dsi_write(dsi2, DSI2_PHY_SYS_RATIO_MAN_CFG, PHY_SYS_RATIO(tmp)); 900 } 901 902 static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2) 903 { 904 struct mipi_dphy_configure *cfg = &dsi2->mipi_dphy_cfg; 905 unsigned long long tmp, ui; 906 unsigned long long hstx_clk; 907 908 hstx_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 909 910 ui = ALIGN(PSEC_PER_SEC, hstx_clk); 911 do_div(ui, hstx_clk); 912 913 /* PHY_LP2HS_TIME = (TLPX + THS-PREPARE + THS-ZERO) / Tphy_hstx_clk */ 914 tmp = cfg->lpx + cfg->hs_prepare + cfg->hs_zero; 915 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 916 dsi_write(dsi2, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(tmp)); 917 918 /* PHY_HS2LP_TIME = (THS-TRAIL + THS-EXIT) / Tphy_hstx_clk */ 919 tmp = cfg->hs_trail + cfg->hs_exit; 920 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 921 dsi_write(dsi2, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(tmp)); 922 } 923 924 static void dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 *dsi2) 925 { 926 dw_mipi_dsi2_phy_mode_cfg(dsi2); 927 dw_mipi_dsi2_phy_clk_mode_cfg(dsi2); 928 dw_mipi_dsi2_phy_ratio_cfg(dsi2); 929 dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(dsi2); 930 931 /* phy configuration 8 - 10 */ 932 } 933 934 static void dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 *dsi2) 935 { 936 u32 val; 937 938 val = BTA_EN | EOTP_TX_EN; 939 940 if (dsi2->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 941 val &= ~EOTP_TX_EN; 942 943 dsi_write(dsi2, DSI2_DSI_GENERAL_CFG, val); 944 dsi_write(dsi2, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel)); 945 946 if (dsi2->scrambling_en) 947 dsi_write(dsi2, DSI2_DSI_SCRAMBLING_CFG, SCRAMBLING_EN); 948 949 val = 0; 950 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) 951 val |= BLK_HFP_HS_EN; 952 953 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) 954 val |= BLK_HBP_HS_EN; 955 956 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HSA) 957 val |= BLK_HSA_HS_EN; 958 959 dsi_write(dsi2, DSI2_DSI_VID_TX_CFG, val); 960 961 /* configure the maximum return packet size that periphera can send */ 962 } 963 964 static void dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 *dsi2, bool enable) 965 { 966 if (enable) { 967 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x1); 968 dsi_write(dsi2, DSI2_INT_MASK_TO, 0xf); 969 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x1); 970 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x1); 971 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x1); 972 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x1); 973 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x1); 974 } else { 975 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x0); 976 dsi_write(dsi2, DSI2_INT_MASK_TO, 0x0); 977 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x0); 978 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x0); 979 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x0); 980 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x0); 981 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x0); 982 }; 983 } 984 985 static void mipi_dcphy_power_on(struct dw_mipi_dsi2 *dsi2) 986 { 987 if (!dsi2->dcphy.phy) 988 return; 989 990 rockchip_phy_power_on(dsi2->dcphy.phy); 991 } 992 993 static void dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 *dsi2) 994 { 995 if (dsi2->prepared) 996 return; 997 998 dw_mipi_dsi2_host_softrst(dsi2); 999 dsi_write(dsi2, DSI2_PWR_UP, RESET); 1000 1001 dw_mipi_dsi2_work_mode(dsi2, MANUAL_MODE_EN); 1002 dw_mipi_dsi2_phy_init(dsi2); 1003 dw_mipi_dsi2_tx_option_set(dsi2); 1004 dw_mipi_dsi2_irq_enable(dsi2, 0); 1005 mipi_dcphy_power_on(dsi2); 1006 dsi_write(dsi2, DSI2_PWR_UP, POWER_UP); 1007 dw_mipi_dsi2_set_cmd_mode(dsi2); 1008 1009 dsi2->prepared = true; 1010 1011 if (dsi2->slave) 1012 dw_mipi_dsi2_pre_enable(dsi2->slave); 1013 } 1014 1015 static int dw_mipi_dsi2_connector_prepare(struct display_state *state) 1016 { 1017 struct connector_state *conn_state = &state->conn_state; 1018 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 1019 unsigned long lane_rate; 1020 1021 memcpy(&dsi2->mode, &conn_state->mode, sizeof(struct drm_display_mode)); 1022 if (dsi2->slave) 1023 memcpy(&dsi2->slave->mode, &dsi2->mode, 1024 sizeof(struct drm_display_mode)); 1025 1026 lane_rate = dw_mipi_dsi2_get_lane_rate(dsi2); 1027 if (dsi2->dcphy.phy) 1028 dw_mipi_dsi2_set_hs_clk(dsi2, lane_rate); 1029 1030 if (dsi2->slave && dsi2->slave->dcphy.phy) 1031 dw_mipi_dsi2_set_hs_clk(dsi2->slave, lane_rate); 1032 1033 printf("final DSI-Link bandwidth: %u %s x %d\n", 1034 dsi2->lane_hs_rate, dsi2->c_option ? "Ksps" : "Kbps", 1035 dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes); 1036 1037 dw_mipi_dsi2_pre_enable(dsi2); 1038 1039 return 0; 1040 } 1041 1042 static void dw_mipi_dsi2_connector_unprepare(struct display_state *state) 1043 { 1044 struct connector_state *conn_state = &state->conn_state; 1045 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 1046 1047 dw_mipi_dsi2_post_disable(dsi2); 1048 } 1049 1050 static int dw_mipi_dsi2_connector_enable(struct display_state *state) 1051 { 1052 struct connector_state *conn_state = &state->conn_state; 1053 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 1054 1055 dw_mipi_dsi2_enable(dsi2); 1056 1057 return 0; 1058 } 1059 1060 static int dw_mipi_dsi2_connector_disable(struct display_state *state) 1061 { 1062 struct connector_state *conn_state = &state->conn_state; 1063 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 1064 1065 dw_mipi_dsi2_disable(dsi2); 1066 1067 return 0; 1068 } 1069 1070 static const struct rockchip_connector_funcs dw_mipi_dsi2_connector_funcs = { 1071 .pre_init = dw_mipi_dsi2_connector_pre_init, 1072 .init = dw_mipi_dsi2_connector_init, 1073 .prepare = dw_mipi_dsi2_connector_prepare, 1074 .unprepare = dw_mipi_dsi2_connector_unprepare, 1075 .enable = dw_mipi_dsi2_connector_enable, 1076 .disable = dw_mipi_dsi2_connector_disable, 1077 }; 1078 1079 static int dw_mipi_dsi2_probe(struct udevice *dev) 1080 { 1081 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(dev); 1082 const struct rockchip_connector *connector = 1083 (const struct rockchip_connector *)dev_get_driver_data(dev); 1084 const struct dw_mipi_dsi2_plat_data *pdata = connector->data; 1085 struct udevice *syscon; 1086 int id, ret; 1087 1088 dsi2->base = dev_read_addr_ptr(dev); 1089 1090 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1091 &syscon); 1092 if (!ret) { 1093 dsi2->grf = syscon_get_regmap(syscon); 1094 if (!dsi2->grf) 1095 return -ENODEV; 1096 } 1097 1098 id = of_alias_get_id(ofnode_to_np(dev->node), "dsi"); 1099 if (id < 0) 1100 id = 0; 1101 1102 dsi2->dev = dev; 1103 dsi2->pdata = pdata; 1104 dsi2->id = id; 1105 dsi2->data_swap = dev_read_bool(dsi2->dev, "rockchip,data-swap"); 1106 1107 return 0; 1108 } 1109 1110 static const u32 rk3588_dsi0_grf_reg_fields[MAX_FIELDS] = { 1111 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0000, 11, 11), 1112 [GATING_EN] = GRF_REG_FIELD(0x0000, 10, 10), 1113 [IPI_SHUTDN] = GRF_REG_FIELD(0x0000, 9, 9), 1114 [IPI_COLORM] = GRF_REG_FIELD(0x0000, 8, 8), 1115 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0000, 4, 7), 1116 [IPI_FORMAT] = GRF_REG_FIELD(0x0000, 0, 3), 1117 }; 1118 1119 static const u32 rk3588_dsi1_grf_reg_fields[MAX_FIELDS] = { 1120 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0004, 11, 11), 1121 [GATING_EN] = GRF_REG_FIELD(0x0004, 10, 10), 1122 [IPI_SHUTDN] = GRF_REG_FIELD(0x0004, 9, 9), 1123 [IPI_COLORM] = GRF_REG_FIELD(0x0004, 8, 8), 1124 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0004, 4, 7), 1125 [IPI_FORMAT] = GRF_REG_FIELD(0x0004, 0, 3), 1126 }; 1127 1128 static const struct dw_mipi_dsi2_plat_data rk3588_mipi_dsi2_plat_data = { 1129 .dsi0_grf_reg_fields = rk3588_dsi0_grf_reg_fields, 1130 .dsi1_grf_reg_fields = rk3588_dsi1_grf_reg_fields, 1131 .dphy_max_bit_rate_per_lane = 4500000000ULL, 1132 .cphy_max_symbol_rate_per_lane = 2000000000ULL, 1133 }; 1134 static const struct rockchip_connector rk3588_mipi_dsi2_driver_data = { 1135 .funcs = &dw_mipi_dsi2_connector_funcs, 1136 .data = &rk3588_mipi_dsi2_plat_data, 1137 }; 1138 1139 static const struct udevice_id dw_mipi_dsi2_ids[] = { 1140 { 1141 .compatible = "rockchip,rk3588-mipi-dsi2", 1142 .data = (ulong)&rk3588_mipi_dsi2_driver_data, 1143 }, 1144 {} 1145 }; 1146 1147 static ssize_t dw_mipi_dsi2_host_transfer(struct mipi_dsi_host *host, 1148 const struct mipi_dsi_msg *msg) 1149 { 1150 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1151 1152 return dw_mipi_dsi2_transfer(dsi2, msg); 1153 } 1154 1155 static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2) 1156 { 1157 struct udevice *dev = NULL; 1158 struct rockchip_cmd_header *header; 1159 struct drm_dsc_picture_parameter_set *pps = NULL; 1160 u8 *dsc_packed_pps; 1161 const void *data; 1162 int len; 1163 int ret; 1164 1165 ret = device_find_first_child(dsi2->dev, &dev); 1166 if (ret) 1167 return ret; 1168 1169 dsi2->c_option = dev_read_bool(dev, "phy-c-option"); 1170 dsi2->scrambling_en = dev_read_bool(dev, "scrambling-enable"); 1171 dsi2->dsc_enable = dev_read_bool(dev, "compressed-data"); 1172 1173 if (dsi2->slave) { 1174 dsi2->slave->c_option = dsi2->c_option; 1175 dsi2->slave->scrambling_en = dsi2->scrambling_en; 1176 dsi2->slave->dsc_enable = dsi2->dsc_enable; 1177 } 1178 1179 dsi2->slice_width = dev_read_u32_default(dev, "slice-width", 0); 1180 dsi2->slice_height = dev_read_u32_default(dev, "slice-height", 0); 1181 dsi2->version_major = dev_read_u32_default(dev, "version-major", 0); 1182 dsi2->version_minor = dev_read_u32_default(dev, "version-minor", 0); 1183 1184 data = dev_read_prop(dev, "panel-init-sequence", &len); 1185 if (!data) 1186 return -EINVAL; 1187 1188 while (len > sizeof(*header)) { 1189 header = (struct rockchip_cmd_header *)data; 1190 data += sizeof(*header); 1191 len -= sizeof(*header); 1192 1193 if (header->payload_length > len) 1194 return -EINVAL; 1195 1196 if (header->data_type == MIPI_DSI_PICTURE_PARAMETER_SET) { 1197 dsc_packed_pps = calloc(1, header->payload_length); 1198 if (!dsc_packed_pps) 1199 return -ENOMEM; 1200 1201 memcpy(dsc_packed_pps, data, header->payload_length); 1202 pps = (struct drm_dsc_picture_parameter_set *)dsc_packed_pps; 1203 break; 1204 } 1205 1206 data += header->payload_length; 1207 len -= header->payload_length; 1208 } 1209 1210 dsi2->pps = pps; 1211 1212 return 0; 1213 } 1214 1215 static int dw_mipi_dsi2_host_attach(struct mipi_dsi_host *host, 1216 struct mipi_dsi_device *device) 1217 { 1218 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1219 1220 if (device->lanes < 1 || device->lanes > 8) 1221 return -EINVAL; 1222 1223 dsi2->lanes = device->lanes; 1224 dsi2->channel = device->channel; 1225 dsi2->format = device->format; 1226 dsi2->mode_flags = device->mode_flags; 1227 1228 dw_mipi_dsi2_get_dsc_params_from_sink(dsi2); 1229 1230 return 0; 1231 } 1232 1233 static const struct mipi_dsi_host_ops dw_mipi_dsi2_host_ops = { 1234 .attach = dw_mipi_dsi2_host_attach, 1235 .transfer = dw_mipi_dsi2_host_transfer, 1236 }; 1237 1238 static int dw_mipi_dsi2_bind(struct udevice *dev) 1239 { 1240 struct mipi_dsi_host *host = dev_get_platdata(dev); 1241 1242 host->dev = dev; 1243 host->ops = &dw_mipi_dsi2_host_ops; 1244 1245 return dm_scan_fdt_dev(dev); 1246 } 1247 1248 static int dw_mipi_dsi2_child_post_bind(struct udevice *dev) 1249 { 1250 struct mipi_dsi_host *host = dev_get_platdata(dev->parent); 1251 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1252 char name[20]; 1253 1254 sprintf(name, "%s.%d", host->dev->name, device->channel); 1255 device_set_name(dev, name); 1256 1257 device->dev = dev; 1258 device->host = host; 1259 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4); 1260 device->format = dev_read_u32_default(dev, "dsi,format", 1261 MIPI_DSI_FMT_RGB888); 1262 device->mode_flags = dev_read_u32_default(dev, "dsi,flags", 1263 MIPI_DSI_MODE_VIDEO | 1264 MIPI_DSI_MODE_VIDEO_BURST | 1265 MIPI_DSI_MODE_VIDEO_HBP | 1266 MIPI_DSI_MODE_LPM | 1267 MIPI_DSI_MODE_EOT_PACKET); 1268 device->channel = dev_read_u32_default(dev, "reg", 0); 1269 1270 return 0; 1271 } 1272 1273 static int dw_mipi_dsi2_child_pre_probe(struct udevice *dev) 1274 { 1275 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1276 int ret; 1277 1278 ret = mipi_dsi_attach(device); 1279 if (ret) { 1280 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret); 1281 return ret; 1282 } 1283 1284 return 0; 1285 } 1286 1287 U_BOOT_DRIVER(dw_mipi_dsi2) = { 1288 .name = "dw_mipi_dsi2", 1289 .id = UCLASS_DISPLAY, 1290 .of_match = dw_mipi_dsi2_ids, 1291 .probe = dw_mipi_dsi2_probe, 1292 .bind = dw_mipi_dsi2_bind, 1293 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi2), 1294 .per_child_platdata_auto_alloc_size = sizeof(struct mipi_dsi_device), 1295 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_host), 1296 .child_post_bind = dw_mipi_dsi2_child_post_bind, 1297 .child_pre_probe = dw_mipi_dsi2_child_pre_probe, 1298 }; 1299