1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Author: Guochun Huang <hero.huang@rock-chips.com> 7 */ 8 9 #include <drm/drm_mipi_dsi.h> 10 11 #include <config.h> 12 #include <common.h> 13 #include <errno.h> 14 #include <asm/unaligned.h> 15 #include <asm/io.h> 16 #include <asm/hardware.h> 17 #include <dm/device.h> 18 #include <dm/read.h> 19 #include <dm/of_access.h> 20 #include <regmap.h> 21 #include <syscon.h> 22 #include <asm/arch-rockchip/clock.h> 23 #include <linux/iopoll.h> 24 25 #include "rockchip_bridge.h" 26 #include "rockchip_display.h" 27 #include "rockchip_crtc.h" 28 #include "rockchip_connector.h" 29 #include "rockchip_panel.h" 30 #include "rockchip_phy.h" 31 32 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) 33 34 #define DSI2_PWR_UP 0x000c 35 #define RESET 0 36 #define POWER_UP BIT(0) 37 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 38 #define DSI2_SOFT_RESET 0x0010 39 #define SYS_RSTN BIT(2) 40 #define PHY_RSTN BIT(1) 41 #define IPI_RSTN BIT(0) 42 #define INT_ST_MAIN 0x0014 43 #define DSI2_MODE_CTRL 0x0018 44 #define DSI2_MODE_STATUS 0x001c 45 #define DSI2_CORE_STATUS 0x0020 46 #define PRI_RD_DATA_AVAIL BIT(26) 47 #define PRI_FIFOS_NOT_EMPTY BIT(25) 48 #define PRI_BUSY BIT(24) 49 #define CRI_RD_DATA_AVAIL BIT(18) 50 #define CRT_FIFOS_NOT_EMPTY BIT(17) 51 #define CRI_BUSY BIT(16) 52 #define IPI_FIFOS_NOT_EMPTY BIT(9) 53 #define IPI_BUSY BIT(8) 54 #define CORE_FIFOS_NOT_EMPTY BIT(1) 55 #define CORE_BUSY BIT(0) 56 #define MANUAL_MODE_CFG 0x0024 57 #define MANUAL_MODE_EN BIT(0) 58 #define DSI2_TIMEOUT_HSTX_CFG 0x0048 59 #define TO_HSTX(x) UPDATE(x, 15, 0) 60 #define DSI2_TIMEOUT_HSTXRDY_CFG 0x004c 61 #define TO_HSTXRDY(x) UPDATE(x, 15, 0) 62 #define DSI2_TIMEOUT_LPRX_CFG 0x0050 63 #define TO_LPRXRDY(x) UPDATE(x, 15, 0) 64 #define DSI2_TIMEOUT_LPTXRDY_CFG 0x0054 65 #define TO_LPTXRDY(x) UPDATE(x, 15, 0) 66 #define DSI2_TIMEOUT_LPTXTRIG_CFG 0x0058 67 #define TO_LPTXTRIG(x) UPDATE(x, 15, 0) 68 #define DSI2_TIMEOUT_LPTXULPS_CFG 0x005c 69 #define TO_LPTXULPS(x) UPDATE(x, 15, 0) 70 #define DSI2_TIMEOUT_BTA_CFG 0x60 71 #define TO_BTA(x) UPDATE(x, 15, 0) 72 73 #define DSI2_PHY_MODE_CFG 0x0100 74 #define PPI_WIDTH(x) UPDATE(x, 9, 8) 75 #define PHY_LANES(x) UPDATE(x - 1, 5, 4) 76 #define PHY_TYPE(x) UPDATE(x, 0, 0) 77 #define DSI2_PHY_CLK_CFG 0X0104 78 #define PHY_LPTX_CLK_DIV(x) UPDATE(x, 12, 8) 79 #define NON_CONTINUOUS_CLK BIT(0) 80 #define DSI2_PHY_LP2HS_MAN_CFG 0x010c 81 #define PHY_LP2HS_TIME(x) UPDATE(x, 28, 0) 82 #define DSI2_PHY_HS2LP_MAN_CFG 0x0114 83 #define PHY_HS2LP_TIME(x) UPDATE(x, 28, 0) 84 #define DSI2_PHY_MAX_RD_T_MAN_CFG 0x011c 85 #define PHY_MAX_RD_TIME(x) UPDATE(x, 26, 0) 86 #define DSI2_PHY_ESC_CMD_T_MAN_CFG 0x0124 87 #define PHY_ESC_CMD_TIME(x) UPDATE(x, 28, 0) 88 #define DSI2_PHY_ESC_BYTE_T_MAN_CFG 0x012c 89 #define PHY_ESC_BYTE_TIME(x) UPDATE(x, 28, 0) 90 91 #define DSI2_PHY_IPI_RATIO_MAN_CFG 0x0134 92 #define PHY_IPI_RATIO(x) UPDATE(x, 21, 0) 93 #define DSI2_PHY_SYS_RATIO_MAN_CFG 0x013C 94 #define PHY_SYS_RATIO(x) UPDATE(x, 16, 0) 95 96 #define DSI2_DSI_GENERAL_CFG 0x0200 97 #define BTA_EN BIT(1) 98 #define EOTP_TX_EN BIT(0) 99 #define DSI2_DSI_VCID_CFG 0x0204 100 #define TX_VCID(x) UPDATE(x, 1, 0) 101 #define DSI2_DSI_SCRAMBLING_CFG 0x0208 102 #define SCRAMBLING_SEED(x) UPDATE(x, 31, 16) 103 #define SCRAMBLING_EN BIT(0) 104 #define DSI2_DSI_VID_TX_CFG 0x020c 105 #define LPDT_DISPLAY_CMD_EN BIT(20) 106 #define BLK_VFP_HS_EN BIT(14) 107 #define BLK_VBP_HS_EN BIT(13) 108 #define BLK_VSA_HS_EN BIT(12) 109 #define BLK_HFP_HS_EN BIT(6) 110 #define BLK_HBP_HS_EN BIT(5) 111 #define BLK_HSA_HS_EN BIT(4) 112 #define VID_MODE_TYPE(x) UPDATE(x, 1, 0) 113 #define DSI2_CRI_TX_HDR 0x02c0 114 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 115 #define DSI2_CRI_TX_PLD 0x02c4 116 #define DSI2_CRI_RX_HDR 0x02c8 117 #define DSI2_CRI_RX_PLD 0x02cc 118 119 #define DSI2_IPI_COLOR_MAN_CFG 0x0300 120 #define IPI_DEPTH(x) UPDATE(x, 7, 4) 121 #define IPI_DEPTH_5_6_5_BITS 0x02 122 #define IPI_DEPTH_6_BITS 0x03 123 #define IPI_DEPTH_8_BITS 0x05 124 #define IPI_DEPTH_10_BITS 0x06 125 #define IPI_FORMAT(x) UPDATE(x, 3, 0) 126 #define IPI_FORMAT_RGB 0x0 127 #define IPI_FORMAT_DSC 0x0b 128 #define DSI2_IPI_VID_HSA_MAN_CFG 0x0304 129 #define VID_HSA_TIME(x) UPDATE(x, 29, 0) 130 #define DSI2_IPI_VID_HBP_MAN_CFG 0x030c 131 #define VID_HBP_TIME(x) UPDATE(x, 29, 0) 132 #define DSI2_IPI_VID_HACT_MAN_CFG 0x0314 133 #define VID_HACT_TIME(x) UPDATE(x, 29, 0) 134 #define DSI2_IPI_VID_HLINE_MAN_CFG 0x031c 135 #define VID_HLINE_TIME(x) UPDATE(x, 29, 0) 136 #define DSI2_IPI_VID_VSA_MAN_CFG 0x0324 137 #define VID_VSA_LINES(x) UPDATE(x, 9, 0) 138 #define DSI2_IPI_VID_VBP_MAN_CFG 0X032C 139 #define VID_VBP_LINES(x) UPDATE(x, 9, 0) 140 #define DSI2_IPI_VID_VACT_MAN_CFG 0X0334 141 #define VID_VACT_LINES(x) UPDATE(x, 13, 0) 142 #define DSI2_IPI_VID_VFP_MAN_CFG 0X033C 143 #define VID_VFP_LINES(x) UPDATE(x, 9, 0) 144 #define DSI2_IPI_PIX_PKT_CFG 0x0344 145 #define MAX_PIX_PKT(x) UPDATE(x, 15, 0) 146 147 #define DSI2_INT_ST_PHY 0x0400 148 #define DSI2_INT_MASK_PHY 0x0404 149 #define DSI2_INT_ST_TO 0x0410 150 #define DSI2_INT_MASK_TO 0x0414 151 #define DSI2_INT_ST_ACK 0x0420 152 #define DSI2_INT_MASK_ACK 0x0424 153 #define DSI2_INT_ST_IPI 0x0430 154 #define DSI2_INT_MASK_IPI 0x0434 155 #define DSI2_INT_ST_FIFO 0x0440 156 #define DSI2_INT_MASK_FIFO 0x0444 157 #define DSI2_INT_ST_PRI 0x0450 158 #define DSI2_INT_MASK_PRI 0x0454 159 #define DSI2_INT_ST_CRI 0x0460 160 #define DSI2_INT_MASK_CRI 0x0464 161 #define DSI2_INT_FORCE_CRI 0x0468 162 #define DSI2_MAX_REGISGER DSI2_INT_FORCE_CRI 163 164 #define CMD_PKT_STATUS_TIMEOUT_US 1000 165 #define MODE_STATUS_TIMEOUT_US 20000 166 #define SYS_CLK 351000000LL 167 #define PSEC_PER_SEC 1000000000000LL 168 #define USEC_PER_SEC 1000000L 169 #define MSEC_PER_SEC 1000L 170 171 #define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 16) | ((lsb) << 8) | (msb)) 172 173 enum vid_mode_type { 174 VID_MODE_TYPE_NON_BURST_SYNC_PULSES, 175 VID_MODE_TYPE_NON_BURST_SYNC_EVENTS, 176 VID_MODE_TYPE_BURST, 177 }; 178 179 enum mode_ctrl { 180 IDLE_MODE, 181 AUTOCALC_MODE, 182 COMMAND_MODE, 183 VIDEO_MODE, 184 DATA_STREAM_MODE, 185 VIDE_TEST_MODE, 186 DATA_STREAM_TEST_MODE, 187 }; 188 189 enum grf_reg_fields { 190 TXREQCLKHS_EN, 191 GATING_EN, 192 IPI_SHUTDN, 193 IPI_COLORM, 194 IPI_COLOR_DEPTH, 195 IPI_FORMAT, 196 MAX_FIELDS, 197 }; 198 199 enum phy_type { 200 DPHY, 201 CPHY, 202 }; 203 204 enum ppi_width { 205 PPI_WIDTH_8_BITS, 206 PPI_WIDTH_16_BITS, 207 PPI_WIDTH_32_BITS, 208 }; 209 210 struct rockchip_cmd_header { 211 u8 data_type; 212 u8 delay_ms; 213 u8 payload_length; 214 }; 215 216 struct dw_mipi_dsi2_plat_data { 217 const u32 *dsi0_grf_reg_fields; 218 const u32 *dsi1_grf_reg_fields; 219 unsigned long long dphy_max_bit_rate_per_lane; 220 unsigned long long cphy_max_symbol_rate_per_lane; 221 }; 222 223 struct mipi_dcphy { 224 /* Non-SNPS PHY */ 225 struct rockchip_phy *phy; 226 227 u16 input_div; 228 u16 feedback_div; 229 }; 230 231 /** 232 * struct mipi_dphy_configure - MIPI D-PHY configuration set 233 * 234 * This structure is used to represent the configuration state of a 235 * MIPI D-PHY phy. 236 */ 237 struct mipi_dphy_configure { 238 unsigned int clk_miss; 239 unsigned int clk_post; 240 unsigned int clk_pre; 241 unsigned int clk_prepare; 242 unsigned int clk_settle; 243 unsigned int clk_term_en; 244 unsigned int clk_trail; 245 unsigned int clk_zero; 246 unsigned int d_term_en; 247 unsigned int eot; 248 unsigned int hs_exit; 249 unsigned int hs_prepare; 250 unsigned int hs_settle; 251 unsigned int hs_skip; 252 unsigned int hs_trail; 253 unsigned int hs_zero; 254 unsigned int init; 255 unsigned int lpx; 256 unsigned int ta_get; 257 unsigned int ta_go; 258 unsigned int ta_sure; 259 unsigned int wakeup; 260 unsigned long hs_clk_rate; 261 unsigned long lp_clk_rate; 262 unsigned char lanes; 263 }; 264 265 struct dw_mipi_dsi2 { 266 struct rockchip_connector connector; 267 struct udevice *dev; 268 void *base; 269 void *grf; 270 int id; 271 struct dw_mipi_dsi2 *master; 272 struct dw_mipi_dsi2 *slave; 273 bool prepared; 274 275 bool c_option; 276 bool dsc_enable; 277 bool scrambling_en; 278 unsigned int slice_width; 279 unsigned int slice_height; 280 u32 version_major; 281 u32 version_minor; 282 283 unsigned int lane_hs_rate; /* Kbps/Ksps per lane */ 284 u32 channel; 285 u32 lanes; 286 u32 format; 287 u32 mode_flags; 288 struct mipi_dcphy dcphy; 289 struct drm_display_mode mode; 290 bool data_swap; 291 292 struct mipi_dsi_device *device; 293 struct mipi_dphy_configure mipi_dphy_cfg; 294 const struct dw_mipi_dsi2_plat_data *pdata; 295 struct drm_dsc_picture_parameter_set *pps; 296 }; 297 298 static inline void dsi_write(struct dw_mipi_dsi2 *dsi2, u32 reg, u32 val) 299 { 300 writel(val, dsi2->base + reg); 301 } 302 303 static inline u32 dsi_read(struct dw_mipi_dsi2 *dsi2, u32 reg) 304 { 305 return readl(dsi2->base + reg); 306 } 307 308 static inline void dsi_update_bits(struct dw_mipi_dsi2 *dsi2, 309 u32 reg, u32 mask, u32 val) 310 { 311 u32 orig, tmp; 312 313 orig = dsi_read(dsi2, reg); 314 tmp = orig & ~mask; 315 tmp |= val & mask; 316 dsi_write(dsi2, reg, tmp); 317 } 318 319 static void grf_field_write(struct dw_mipi_dsi2 *dsi2, enum grf_reg_fields index, 320 unsigned int val) 321 { 322 const u32 field = dsi2->id ? dsi2->pdata->dsi1_grf_reg_fields[index] : 323 dsi2->pdata->dsi0_grf_reg_fields[index]; 324 u16 reg; 325 u8 msb, lsb; 326 327 if (!field) 328 return; 329 330 reg = (field >> 16) & 0xffff; 331 lsb = (field >> 8) & 0xff; 332 msb = (field >> 0) & 0xff; 333 334 regmap_write(dsi2->grf, reg, GENMASK(msb, lsb) << 16 | val << lsb); 335 } 336 337 static unsigned long dw_mipi_dsi2_get_lane_rate(struct dw_mipi_dsi2 *dsi2) 338 { 339 const struct drm_display_mode *mode = &dsi2->mode; 340 u64 max_lane_rate, lane_rate; 341 unsigned int value; 342 int bpp, lanes; 343 u64 tmp; 344 345 max_lane_rate = (dsi2->c_option) ? 346 dsi2->pdata->cphy_max_symbol_rate_per_lane : 347 dsi2->pdata->dphy_max_bit_rate_per_lane; 348 349 /* 350 * optional override of the desired bandwidth 351 * High-Speed mode: Differential and terminated: 80Mbps ~ 4500 Mbps 352 */ 353 value = dev_read_u32_default(dsi2->dev, "rockchip,lane-rate", 0); 354 if (value >= 80000 && value <= 4500000) 355 return value * MSEC_PER_SEC; 356 else if (value >= 80 && value <= 4500) 357 return value * USEC_PER_SEC; 358 359 bpp = mipi_dsi_pixel_format_to_bpp(dsi2->format); 360 if (bpp < 0) 361 bpp = 24; 362 363 lanes = dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes; 364 tmp = (u64)mode->crtc_clock * 1000 * bpp; 365 do_div(tmp, lanes); 366 367 if (dsi2->c_option) 368 tmp = DIV_ROUND_CLOSEST(tmp * 100, 228); 369 370 /* set BW a little larger only in video burst mode in 371 * consideration of the protocol overhead and HS mode 372 * switching to BLLP mode, take 1 / 0.9, since Mbps must 373 * big than bandwidth of RGB 374 */ 375 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { 376 tmp *= 10; 377 do_div(tmp, 9); 378 } 379 380 if (tmp > max_lane_rate) 381 lane_rate = max_lane_rate; 382 else 383 lane_rate = tmp; 384 385 return lane_rate; 386 } 387 388 static int cri_fifos_wait_avail(struct dw_mipi_dsi2 *dsi2) 389 { 390 u32 sts, mask; 391 int ret; 392 393 mask = CRI_BUSY | CRT_FIFOS_NOT_EMPTY; 394 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 395 sts, !(sts & mask), 396 CMD_PKT_STATUS_TIMEOUT_US); 397 if (ret < 0) { 398 printf("command interface is busy: 0x%x\n", sts); 399 return ret; 400 } 401 402 return 0; 403 } 404 405 static int dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 *dsi2, 406 const struct mipi_dsi_msg *msg) 407 { 408 u8 *payload = msg->rx_buf; 409 u8 data_type; 410 u16 wc; 411 int i, j, ret, len = msg->rx_len; 412 unsigned int vrefresh = drm_mode_vrefresh(&dsi2->mode); 413 u32 val; 414 415 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 416 val, val & CRI_RD_DATA_AVAIL, 417 DIV_ROUND_UP(1000000, vrefresh)); 418 if (ret) { 419 printf("CRI has no available read data\n"); 420 return ret; 421 } 422 423 val = dsi_read(dsi2, DSI2_CRI_RX_HDR); 424 data_type = val & 0x3f; 425 426 if (mipi_dsi_packet_format_is_short(data_type)) { 427 for (i = 0; i < len && i < 2; i++) 428 payload[i] = (val >> (8 * (i + 1))) & 0xff; 429 430 return 0; 431 } 432 433 wc = (val >> 8) & 0xffff; 434 /* Receive payload */ 435 for (i = 0; i < len && i < wc; i += 4) { 436 val = dsi_read(dsi2, DSI2_CRI_RX_PLD); 437 for (j = 0; j < 4 && j + i < len && j + i < wc; j++) 438 payload[i + j] = val >> (8 * j); 439 } 440 441 return 0; 442 } 443 444 static ssize_t dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 *dsi2, 445 const struct mipi_dsi_msg *msg) 446 { 447 struct mipi_dsi_packet packet; 448 int ret; 449 int val; 450 u32 mode; 451 452 dsi_update_bits(dsi2, DSI2_DSI_VID_TX_CFG, LPDT_DISPLAY_CMD_EN, 453 msg->flags & MIPI_DSI_MSG_USE_LPM ? 454 LPDT_DISPLAY_CMD_EN : 0); 455 456 /* create a packet to the DSI protocol */ 457 ret = mipi_dsi_create_packet(&packet, msg); 458 if (ret) { 459 printf("failed to create packet: %d\n", ret); 460 return ret; 461 } 462 463 /* check cri interface is not busy */ 464 ret = cri_fifos_wait_avail(dsi2); 465 if (ret) 466 return ret; 467 468 /* Send payload */ 469 while (DIV_ROUND_UP(packet.payload_length, 4)) { 470 if (packet.payload_length < 4) { 471 /* send residu payload */ 472 val = 0; 473 memcpy(&val, packet.payload, packet.payload_length); 474 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 475 packet.payload_length = 0; 476 } else { 477 val = get_unaligned_le32(packet.payload); 478 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 479 packet.payload += 4; 480 packet.payload_length -= 4; 481 } 482 } 483 484 /* Send packet header */ 485 mode = CMD_TX_MODE(msg->flags & MIPI_DSI_MSG_USE_LPM ? 1 : 0); 486 val = get_unaligned_le32(packet.header); 487 dsi_write(dsi2, DSI2_CRI_TX_HDR, mode | val); 488 489 ret = cri_fifos_wait_avail(dsi2); 490 if (ret) 491 return ret; 492 493 if (msg->rx_len) { 494 ret = dw_mipi_dsi2_read_from_fifo(dsi2, msg); 495 if (ret < 0) 496 return ret; 497 } 498 499 if (dsi2->slave) { 500 ret = dw_mipi_dsi2_transfer(dsi2->slave, msg); 501 if (ret < 0) 502 return ret; 503 } 504 505 return msg->rx_len ? msg->rx_len : msg->tx_len; 506 } 507 508 static void dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 *dsi2) 509 { 510 u32 val, color_depth; 511 512 switch (dsi2->format) { 513 case MIPI_DSI_FMT_RGB666: 514 case MIPI_DSI_FMT_RGB666_PACKED: 515 color_depth = IPI_DEPTH_6_BITS; 516 break; 517 case MIPI_DSI_FMT_RGB565: 518 color_depth = IPI_DEPTH_5_6_5_BITS; 519 break; 520 case MIPI_DSI_FMT_RGB888: 521 default: 522 color_depth = IPI_DEPTH_8_BITS; 523 break; 524 } 525 526 val = IPI_DEPTH(color_depth) | 527 IPI_FORMAT(dsi2->dsc_enable ? IPI_FORMAT_DSC : IPI_FORMAT_RGB); 528 dsi_write(dsi2, DSI2_IPI_COLOR_MAN_CFG, val); 529 grf_field_write(dsi2, IPI_COLOR_DEPTH, color_depth); 530 531 if (dsi2->dsc_enable) 532 grf_field_write(dsi2, IPI_FORMAT, IPI_FORMAT_DSC); 533 } 534 535 static void dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 *dsi2) 536 { 537 struct drm_display_mode *mode = &dsi2->mode; 538 u32 hline, hsa, hbp, hact; 539 u64 hline_time, hsa_time, hbp_time, hact_time, tmp; 540 u64 pixel_clk, phy_hs_clk; 541 u32 vact, vsa, vfp, vbp; 542 u16 val; 543 544 if (dsi2->slave || dsi2->master) 545 val = mode->hdisplay / 2; 546 else 547 val = mode->hdisplay; 548 549 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val)); 550 551 dw_mipi_dsi2_ipi_color_coding_cfg(dsi2); 552 553 /* 554 * if the controller is intended to operate in data stream mode, 555 * no more steps are required. 556 */ 557 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) 558 return; 559 560 vact = mode->vdisplay; 561 vsa = mode->vsync_end - mode->vsync_start; 562 vfp = mode->vsync_start - mode->vdisplay; 563 vbp = mode->vtotal - mode->vsync_end; 564 hact = mode->hdisplay; 565 hsa = mode->hsync_end - mode->hsync_start; 566 hbp = mode->htotal - mode->hsync_end; 567 hline = mode->htotal; 568 569 pixel_clk = mode->crtc_clock * MSEC_PER_SEC; 570 571 if (dsi2->c_option) 572 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 573 else 574 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 575 576 tmp = hsa * phy_hs_clk; 577 hsa_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 578 dsi_write(dsi2, DSI2_IPI_VID_HSA_MAN_CFG, VID_HSA_TIME(hsa_time)); 579 580 tmp = hbp * phy_hs_clk; 581 hbp_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 582 dsi_write(dsi2, DSI2_IPI_VID_HBP_MAN_CFG, VID_HBP_TIME(hbp_time)); 583 584 tmp = hact * phy_hs_clk; 585 hact_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 586 dsi_write(dsi2, DSI2_IPI_VID_HACT_MAN_CFG, VID_HACT_TIME(hact_time)); 587 588 tmp = hline * phy_hs_clk; 589 hline_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 590 dsi_write(dsi2, DSI2_IPI_VID_HLINE_MAN_CFG, VID_HLINE_TIME(hline_time)); 591 592 dsi_write(dsi2, DSI2_IPI_VID_VSA_MAN_CFG, VID_VSA_LINES(vsa)); 593 dsi_write(dsi2, DSI2_IPI_VID_VBP_MAN_CFG, VID_VBP_LINES(vbp)); 594 dsi_write(dsi2, DSI2_IPI_VID_VACT_MAN_CFG, VID_VACT_LINES(vact)); 595 dsi_write(dsi2, DSI2_IPI_VID_VFP_MAN_CFG, VID_VFP_LINES(vfp)); 596 } 597 598 static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2) 599 { 600 u32 val = 0, mode; 601 int ret; 602 603 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) 604 val |= BLK_HFP_HS_EN; 605 606 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) 607 val |= BLK_HBP_HS_EN; 608 609 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HSA) 610 val |= BLK_HSA_HS_EN; 611 612 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 613 val |= VID_MODE_TYPE_BURST; 614 else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 615 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 616 else 617 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 618 619 dsi_write(dsi2, DSI2_DSI_VID_TX_CFG, val); 620 621 dsi_write(dsi2, DSI2_MODE_CTRL, VIDEO_MODE); 622 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 623 mode, mode & VIDEO_MODE, 624 MODE_STATUS_TIMEOUT_US); 625 if (ret < 0) 626 printf("failed to enter video mode\n"); 627 } 628 629 static void dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 *dsi2) 630 { 631 u32 mode; 632 int ret; 633 634 dsi_write(dsi2, DSI2_MODE_CTRL, DATA_STREAM_MODE); 635 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 636 mode, mode & DATA_STREAM_MODE, 637 MODE_STATUS_TIMEOUT_US); 638 if (ret < 0) 639 printf("failed to enter data stream mode\n"); 640 } 641 642 static void dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 *dsi2) 643 { 644 u32 mode; 645 int ret; 646 647 dsi_write(dsi2, DSI2_MODE_CTRL, COMMAND_MODE); 648 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 649 mode, mode & COMMAND_MODE, 650 MODE_STATUS_TIMEOUT_US); 651 if (ret < 0) 652 printf("failed to enter cmd mode\n"); 653 } 654 655 static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2) 656 { 657 struct udevice *dev = dsi2->device->dev; 658 struct rockchip_cmd_header *header; 659 struct drm_dsc_picture_parameter_set *pps = NULL; 660 u8 *dsc_packed_pps; 661 const void *data; 662 int len; 663 664 dsi2->c_option = dev_read_bool(dev, "phy-c-option"); 665 dsi2->scrambling_en = dev_read_bool(dev, "scrambling-enable"); 666 dsi2->dsc_enable = dev_read_bool(dev, "compressed-data"); 667 668 if (dsi2->slave) { 669 dsi2->slave->c_option = dsi2->c_option; 670 dsi2->slave->scrambling_en = dsi2->scrambling_en; 671 dsi2->slave->dsc_enable = dsi2->dsc_enable; 672 } 673 674 dsi2->slice_width = dev_read_u32_default(dev, "slice-width", 0); 675 dsi2->slice_height = dev_read_u32_default(dev, "slice-height", 0); 676 dsi2->version_major = dev_read_u32_default(dev, "version-major", 0); 677 dsi2->version_minor = dev_read_u32_default(dev, "version-minor", 0); 678 679 data = dev_read_prop(dev, "panel-init-sequence", &len); 680 if (!data) 681 return -EINVAL; 682 683 while (len > sizeof(*header)) { 684 header = (struct rockchip_cmd_header *)data; 685 data += sizeof(*header); 686 len -= sizeof(*header); 687 688 if (header->payload_length > len) 689 return -EINVAL; 690 691 if (header->data_type == MIPI_DSI_PICTURE_PARAMETER_SET) { 692 dsc_packed_pps = calloc(1, header->payload_length); 693 if (!dsc_packed_pps) 694 return -ENOMEM; 695 696 memcpy(dsc_packed_pps, data, header->payload_length); 697 pps = (struct drm_dsc_picture_parameter_set *)dsc_packed_pps; 698 break; 699 } 700 701 data += header->payload_length; 702 len -= header->payload_length; 703 } 704 705 dsi2->pps = pps; 706 707 return 0; 708 } 709 710 static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2) 711 { 712 dw_mipi_dsi2_ipi_set(dsi2); 713 714 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO) 715 dw_mipi_dsi2_set_vid_mode(dsi2); 716 else 717 dw_mipi_dsi2_set_data_stream_mode(dsi2); 718 719 if (dsi2->slave) 720 dw_mipi_dsi2_enable(dsi2->slave); 721 } 722 723 static void dw_mipi_dsi2_disable(struct dw_mipi_dsi2 *dsi2) 724 { 725 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, 0); 726 dw_mipi_dsi2_set_cmd_mode(dsi2); 727 728 if (dsi2->slave) 729 dw_mipi_dsi2_disable(dsi2->slave); 730 } 731 732 static void dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 *dsi2) 733 { 734 if (!dsi2->prepared) 735 return; 736 737 dsi_write(dsi2, DSI2_PWR_UP, RESET); 738 739 if (dsi2->dcphy.phy) 740 rockchip_phy_power_off(dsi2->dcphy.phy); 741 742 dsi2->prepared = false; 743 744 if (dsi2->slave) 745 dw_mipi_dsi2_post_disable(dsi2->slave); 746 } 747 748 static int dw_mipi_dsi2_connector_pre_init(struct rockchip_connector *conn, 749 struct display_state *state) 750 { 751 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 752 struct mipi_dsi_host *host = dev_get_platdata(dsi2->dev); 753 struct mipi_dsi_device *device; 754 char name[20]; 755 struct udevice *dev; 756 757 device = calloc(1, sizeof(struct dw_mipi_dsi2)); 758 if (!device) 759 return -ENOMEM; 760 761 if (conn->bridge) 762 dev = conn->bridge->dev; 763 else if (conn->panel) 764 dev = conn->panel->dev; 765 else 766 return -ENODEV; 767 768 device->dev = dev; 769 device->host = host; 770 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4); 771 device->channel = dev_read_u32_default(dev, "reg", 0); 772 device->format = dev_read_u32_default(dev, "dsi,format", 773 MIPI_DSI_FMT_RGB888); 774 device->mode_flags = dev_read_u32_default(dev, "dsi,flags", 775 MIPI_DSI_MODE_VIDEO | 776 MIPI_DSI_MODE_VIDEO_BURST | 777 MIPI_DSI_MODE_VIDEO_HBP | 778 MIPI_DSI_MODE_LPM | 779 MIPI_DSI_MODE_EOT_PACKET); 780 781 sprintf(name, "%s.%d", host->dev->name, device->channel); 782 device_set_name(dev, name); 783 dsi2->device = device; 784 dev->parent_platdata = device; 785 786 mipi_dsi_attach(dsi2->device); 787 788 return 0; 789 } 790 791 static int dw_mipi_dsi2_connector_init(struct rockchip_connector *conn, struct display_state *state) 792 { 793 struct connector_state *conn_state = &state->conn_state; 794 struct crtc_state *cstate = &state->crtc_state; 795 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 796 struct rockchip_phy *phy = NULL; 797 struct udevice *phy_dev; 798 struct udevice *dev; 799 int ret; 800 801 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dsi2->id); 802 dsi2->dcphy.phy = conn->phy; 803 804 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 805 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 806 conn_state->output_if |= 807 dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0; 808 809 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) { 810 conn_state->output_flags |= ROCKCHIP_OUTPUT_MIPI_DS_MODE; 811 conn_state->hold_mode = true; 812 } 813 814 if (dsi2->lanes > 4) { 815 ret = uclass_get_device_by_name(UCLASS_DISPLAY, 816 "dsi@fde30000", 817 &dev); 818 if (ret) 819 return ret; 820 821 dsi2->slave = dev_get_priv(dev); 822 if (!dsi2->slave) 823 return -ENODEV; 824 825 dsi2->slave->master = dsi2; 826 dsi2->lanes /= 2; 827 dsi2->slave->lanes = dsi2->lanes; 828 dsi2->slave->format = dsi2->format; 829 dsi2->slave->mode_flags = dsi2->mode_flags; 830 dsi2->slave->channel = dsi2->channel; 831 conn_state->output_flags |= 832 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; 833 if (dsi2->data_swap) 834 conn_state->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP; 835 836 conn_state->output_if |= VOP_OUTPUT_IF_MIPI1; 837 838 ret = uclass_get_device_by_phandle(UCLASS_PHY, dev, 839 "phys", &phy_dev); 840 if (ret) 841 return -ENODEV; 842 843 phy = (struct rockchip_phy *)dev_get_driver_data(phy_dev); 844 if (!phy) 845 return -ENODEV; 846 847 dsi2->slave->dcphy.phy = phy; 848 if (phy->funcs && phy->funcs->init) 849 return phy->funcs->init(phy); 850 } 851 852 dw_mipi_dsi2_get_dsc_params_from_sink(dsi2); 853 854 if (dsi2->dsc_enable) { 855 cstate->dsc_enable = 1; 856 cstate->dsc_sink_cap.version_major = dsi2->version_major; 857 cstate->dsc_sink_cap.version_minor = dsi2->version_minor; 858 cstate->dsc_sink_cap.slice_width = dsi2->slice_width; 859 cstate->dsc_sink_cap.slice_height = dsi2->slice_height; 860 /* only can support rgb888 panel now */ 861 cstate->dsc_sink_cap.target_bits_per_pixel_x16 = 8 << 4; 862 cstate->dsc_sink_cap.native_420 = 0; 863 memcpy(&cstate->pps, dsi2->pps, sizeof(struct drm_dsc_picture_parameter_set)); 864 } 865 866 return 0; 867 } 868 869 /* 870 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived 871 * from the valid ranges specified in Section 6.9, Table 14, Page 41 872 * of the D-PHY specification (v2.1). 873 */ 874 int mipi_dphy_get_default_config(unsigned long long hs_clk_rate, 875 struct mipi_dphy_configure *cfg) 876 { 877 unsigned long long ui; 878 879 if (!cfg) 880 return -EINVAL; 881 882 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); 883 do_div(ui, hs_clk_rate); 884 885 cfg->clk_miss = 0; 886 cfg->clk_post = 60000 + 52 * ui; 887 cfg->clk_pre = 8000; 888 cfg->clk_prepare = 38000; 889 cfg->clk_settle = 95000; 890 cfg->clk_term_en = 0; 891 cfg->clk_trail = 60000; 892 cfg->clk_zero = 262000; 893 cfg->d_term_en = 0; 894 cfg->eot = 0; 895 cfg->hs_exit = 100000; 896 cfg->hs_prepare = 40000 + 4 * ui; 897 cfg->hs_zero = 105000 + 6 * ui; 898 cfg->hs_settle = 85000 + 6 * ui; 899 cfg->hs_skip = 40000; 900 901 /* 902 * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40) 903 * contains this formula as: 904 * 905 * T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui) 906 * 907 * where n = 1 for forward-direction HS mode and n = 4 for reverse- 908 * direction HS mode. There's only one setting and this function does 909 * not parameterize on anything other that ui, so this code will 910 * assumes that reverse-direction HS mode is supported and uses n = 4. 911 */ 912 cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui); 913 914 cfg->init = 100; 915 cfg->lpx = 60000; 916 cfg->ta_get = 5 * cfg->lpx; 917 cfg->ta_go = 4 * cfg->lpx; 918 cfg->ta_sure = 2 * cfg->lpx; 919 cfg->wakeup = 1000; 920 921 return 0; 922 } 923 924 static void dw_mipi_dsi2_set_hs_clk(struct dw_mipi_dsi2 *dsi2, unsigned long rate) 925 { 926 mipi_dphy_get_default_config(rate, &dsi2->mipi_dphy_cfg); 927 928 if (!dsi2->c_option) 929 rockchip_phy_set_mode(dsi2->dcphy.phy, PHY_MODE_MIPI_DPHY); 930 931 rate = rockchip_phy_set_pll(dsi2->dcphy.phy, rate); 932 dsi2->lane_hs_rate = DIV_ROUND_CLOSEST(rate, MSEC_PER_SEC); 933 } 934 935 static void dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 *dsi2) 936 { 937 dsi_write(dsi2, DSI2_SOFT_RESET, 0X0); 938 udelay(100); 939 dsi_write(dsi2, DSI2_SOFT_RESET, SYS_RSTN | PHY_RSTN | IPI_RSTN); 940 } 941 942 static void 943 dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 *dsi2, u32 mode) 944 { 945 /* 946 * select controller work in Manual mode 947 * Manual: MANUAL_MODE_EN 948 * Automatic: 0 949 */ 950 dsi_write(dsi2, MANUAL_MODE_CFG, mode); 951 } 952 953 static void dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 *dsi2) 954 { 955 u32 val = 0; 956 957 /* PPI width is fixed to 16 bits in DCPHY */ 958 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes); 959 val |= PHY_TYPE(dsi2->c_option ? CPHY : DPHY); 960 dsi_write(dsi2, DSI2_PHY_MODE_CFG, val); 961 } 962 963 static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2) 964 { 965 u32 sys_clk = SYS_CLK / USEC_PER_SEC; 966 u32 esc_clk_div; 967 u32 val = 0; 968 969 if (dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 970 val |= NON_CONTINUOUS_CLK; 971 972 /* The Escape clock ranges from 1MHz to 20MHz. */ 973 esc_clk_div = DIV_ROUND_UP(sys_clk, 10 * 2); 974 val |= PHY_LPTX_CLK_DIV(esc_clk_div); 975 976 dsi_write(dsi2, DSI2_PHY_CLK_CFG, val); 977 } 978 979 static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2) 980 { 981 struct drm_display_mode *mode = &dsi2->mode; 982 u64 pixel_clk, ipi_clk, phy_hsclk, tmp; 983 984 /* 985 * in DPHY mode, the phy_hstx_clk is exactly 1/16 the Lane high-speed 986 * data rate; In CPHY mode, the phy_hstx_clk is exactly 1/7 the trio 987 * high speed symbol rate. 988 */ 989 if (dsi2->c_option) 990 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 991 992 else 993 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 994 995 /* IPI_RATIO_MAN_CFG = PHY_HSTX_CLK / IPI_CLK */ 996 pixel_clk = mode->crtc_clock * MSEC_PER_SEC; 997 ipi_clk = pixel_clk / 4; 998 999 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, ipi_clk); 1000 dsi_write(dsi2, DSI2_PHY_IPI_RATIO_MAN_CFG, PHY_IPI_RATIO(tmp)); 1001 1002 /* SYS_RATIO_MAN_CFG = MIPI_DCPHY_HSCLK_Freq / SYS_CLK */ 1003 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, SYS_CLK); 1004 dsi_write(dsi2, DSI2_PHY_SYS_RATIO_MAN_CFG, PHY_SYS_RATIO(tmp)); 1005 } 1006 1007 static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2) 1008 { 1009 struct mipi_dphy_configure *cfg = &dsi2->mipi_dphy_cfg; 1010 unsigned long long tmp, ui; 1011 unsigned long long hstx_clk; 1012 1013 hstx_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 1014 1015 ui = ALIGN(PSEC_PER_SEC, hstx_clk); 1016 do_div(ui, hstx_clk); 1017 1018 /* PHY_LP2HS_TIME = (TLPX + THS-PREPARE + THS-ZERO) / Tphy_hstx_clk */ 1019 tmp = cfg->lpx + cfg->hs_prepare + cfg->hs_zero; 1020 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 1021 dsi_write(dsi2, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(tmp)); 1022 1023 /* PHY_HS2LP_TIME = (THS-TRAIL + THS-EXIT) / Tphy_hstx_clk */ 1024 tmp = cfg->hs_trail + cfg->hs_exit; 1025 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 1026 dsi_write(dsi2, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(tmp)); 1027 } 1028 1029 static void dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 *dsi2) 1030 { 1031 dw_mipi_dsi2_phy_mode_cfg(dsi2); 1032 dw_mipi_dsi2_phy_clk_mode_cfg(dsi2); 1033 dw_mipi_dsi2_phy_ratio_cfg(dsi2); 1034 dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(dsi2); 1035 1036 /* phy configuration 8 - 10 */ 1037 } 1038 1039 static void dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 *dsi2) 1040 { 1041 u32 val; 1042 1043 val = BTA_EN | EOTP_TX_EN; 1044 1045 if (dsi2->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 1046 val &= ~EOTP_TX_EN; 1047 1048 dsi_write(dsi2, DSI2_DSI_GENERAL_CFG, val); 1049 dsi_write(dsi2, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel)); 1050 1051 if (dsi2->scrambling_en) 1052 dsi_write(dsi2, DSI2_DSI_SCRAMBLING_CFG, SCRAMBLING_EN); 1053 } 1054 1055 static void dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 *dsi2, bool enable) 1056 { 1057 if (enable) { 1058 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x1); 1059 dsi_write(dsi2, DSI2_INT_MASK_TO, 0xf); 1060 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x1); 1061 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x1); 1062 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x1); 1063 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x1); 1064 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x1); 1065 } else { 1066 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x0); 1067 dsi_write(dsi2, DSI2_INT_MASK_TO, 0x0); 1068 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x0); 1069 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x0); 1070 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x0); 1071 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x0); 1072 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x0); 1073 }; 1074 } 1075 1076 static void mipi_dcphy_power_on(struct dw_mipi_dsi2 *dsi2) 1077 { 1078 if (!dsi2->dcphy.phy) 1079 return; 1080 1081 rockchip_phy_power_on(dsi2->dcphy.phy); 1082 } 1083 1084 static void dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 *dsi2) 1085 { 1086 if (dsi2->prepared) 1087 return; 1088 1089 dw_mipi_dsi2_host_softrst(dsi2); 1090 dsi_write(dsi2, DSI2_PWR_UP, RESET); 1091 1092 dw_mipi_dsi2_work_mode(dsi2, MANUAL_MODE_EN); 1093 dw_mipi_dsi2_phy_init(dsi2); 1094 dw_mipi_dsi2_tx_option_set(dsi2); 1095 dw_mipi_dsi2_irq_enable(dsi2, 0); 1096 mipi_dcphy_power_on(dsi2); 1097 dsi_write(dsi2, DSI2_PWR_UP, POWER_UP); 1098 dw_mipi_dsi2_set_cmd_mode(dsi2); 1099 1100 dsi2->prepared = true; 1101 1102 if (dsi2->slave) 1103 dw_mipi_dsi2_pre_enable(dsi2->slave); 1104 } 1105 1106 static int dw_mipi_dsi2_connector_prepare(struct rockchip_connector *conn, 1107 struct display_state *state) 1108 { 1109 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1110 struct connector_state *conn_state = &state->conn_state; 1111 unsigned long lane_rate; 1112 1113 memcpy(&dsi2->mode, &conn_state->mode, sizeof(struct drm_display_mode)); 1114 if (dsi2->slave) 1115 memcpy(&dsi2->slave->mode, &dsi2->mode, 1116 sizeof(struct drm_display_mode)); 1117 1118 lane_rate = dw_mipi_dsi2_get_lane_rate(dsi2); 1119 if (dsi2->dcphy.phy) 1120 dw_mipi_dsi2_set_hs_clk(dsi2, lane_rate); 1121 1122 if (dsi2->slave && dsi2->slave->dcphy.phy) 1123 dw_mipi_dsi2_set_hs_clk(dsi2->slave, lane_rate); 1124 1125 printf("final DSI-Link bandwidth: %u %s x %d\n", 1126 dsi2->lane_hs_rate, dsi2->c_option ? "Ksps" : "Kbps", 1127 dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes); 1128 1129 dw_mipi_dsi2_pre_enable(dsi2); 1130 1131 return 0; 1132 } 1133 1134 static void dw_mipi_dsi2_connector_unprepare(struct rockchip_connector *conn, 1135 struct display_state *state) 1136 { 1137 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1138 1139 dw_mipi_dsi2_post_disable(dsi2); 1140 } 1141 1142 static int dw_mipi_dsi2_connector_enable(struct rockchip_connector *conn, 1143 struct display_state *state) 1144 { 1145 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1146 1147 dw_mipi_dsi2_enable(dsi2); 1148 1149 return 0; 1150 } 1151 1152 static int dw_mipi_dsi2_connector_disable(struct rockchip_connector *conn, 1153 struct display_state *state) 1154 { 1155 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1156 1157 dw_mipi_dsi2_disable(dsi2); 1158 1159 return 0; 1160 } 1161 1162 static int dw_mipi_dsi2_connector_mode_valid(struct rockchip_connector *conn, 1163 struct display_state *state) 1164 { 1165 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1166 struct connector_state *conn_state = &state->conn_state; 1167 u8 min_pixels = dsi2->slave ? 8 : 4; 1168 struct videomode vm; 1169 1170 drm_display_mode_to_videomode(&conn_state->mode, &vm); 1171 1172 /* 1173 * the minimum region size (HSA,HBP,HACT,HFP) is 4 pixels 1174 * which is the ip known issues and limitations. 1175 */ 1176 if (!(vm.hsync_len < min_pixels || vm.hback_porch < min_pixels || 1177 vm.hfront_porch < min_pixels || vm.hactive < min_pixels)) 1178 return MODE_OK; 1179 1180 if (vm.hsync_len < min_pixels) 1181 vm.hsync_len = min_pixels; 1182 1183 if (vm.hback_porch < min_pixels) 1184 vm.hback_porch = min_pixels; 1185 1186 if (vm.hfront_porch < min_pixels) 1187 vm.hfront_porch = min_pixels; 1188 1189 if (vm.hactive < min_pixels) 1190 vm.hactive = min_pixels; 1191 1192 drm_display_mode_from_videomode(&vm, &conn_state->mode); 1193 1194 return MODE_OK; 1195 } 1196 1197 static const struct rockchip_connector_funcs dw_mipi_dsi2_connector_funcs = { 1198 .pre_init = dw_mipi_dsi2_connector_pre_init, 1199 .init = dw_mipi_dsi2_connector_init, 1200 .prepare = dw_mipi_dsi2_connector_prepare, 1201 .unprepare = dw_mipi_dsi2_connector_unprepare, 1202 .enable = dw_mipi_dsi2_connector_enable, 1203 .disable = dw_mipi_dsi2_connector_disable, 1204 .mode_valid = dw_mipi_dsi2_connector_mode_valid, 1205 }; 1206 1207 static int dw_mipi_dsi2_probe(struct udevice *dev) 1208 { 1209 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(dev); 1210 const struct dw_mipi_dsi2_plat_data *pdata = 1211 (const struct dw_mipi_dsi2_plat_data *)dev_get_driver_data(dev); 1212 struct udevice *syscon; 1213 int id, ret; 1214 1215 dsi2->base = dev_read_addr_ptr(dev); 1216 1217 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1218 &syscon); 1219 if (!ret) { 1220 dsi2->grf = syscon_get_regmap(syscon); 1221 if (!dsi2->grf) 1222 return -ENODEV; 1223 } 1224 1225 id = of_alias_get_id(ofnode_to_np(dev->node), "dsi"); 1226 if (id < 0) 1227 id = 0; 1228 1229 dsi2->dev = dev; 1230 dsi2->pdata = pdata; 1231 dsi2->id = id; 1232 dsi2->data_swap = dev_read_bool(dsi2->dev, "rockchip,data-swap"); 1233 1234 rockchip_connector_bind(&dsi2->connector, dev, id, &dw_mipi_dsi2_connector_funcs, NULL, 1235 DRM_MODE_CONNECTOR_DSI); 1236 1237 return 0; 1238 } 1239 1240 static const u32 rk3588_dsi0_grf_reg_fields[MAX_FIELDS] = { 1241 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0000, 11, 11), 1242 [GATING_EN] = GRF_REG_FIELD(0x0000, 10, 10), 1243 [IPI_SHUTDN] = GRF_REG_FIELD(0x0000, 9, 9), 1244 [IPI_COLORM] = GRF_REG_FIELD(0x0000, 8, 8), 1245 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0000, 4, 7), 1246 [IPI_FORMAT] = GRF_REG_FIELD(0x0000, 0, 3), 1247 }; 1248 1249 static const u32 rk3588_dsi1_grf_reg_fields[MAX_FIELDS] = { 1250 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0004, 11, 11), 1251 [GATING_EN] = GRF_REG_FIELD(0x0004, 10, 10), 1252 [IPI_SHUTDN] = GRF_REG_FIELD(0x0004, 9, 9), 1253 [IPI_COLORM] = GRF_REG_FIELD(0x0004, 8, 8), 1254 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0004, 4, 7), 1255 [IPI_FORMAT] = GRF_REG_FIELD(0x0004, 0, 3), 1256 }; 1257 1258 static const struct dw_mipi_dsi2_plat_data rk3588_mipi_dsi2_plat_data = { 1259 .dsi0_grf_reg_fields = rk3588_dsi0_grf_reg_fields, 1260 .dsi1_grf_reg_fields = rk3588_dsi1_grf_reg_fields, 1261 .dphy_max_bit_rate_per_lane = 4500000000ULL, 1262 .cphy_max_symbol_rate_per_lane = 2000000000ULL, 1263 }; 1264 1265 static const struct udevice_id dw_mipi_dsi2_ids[] = { 1266 { 1267 .compatible = "rockchip,rk3588-mipi-dsi2", 1268 .data = (ulong)&rk3588_mipi_dsi2_plat_data, 1269 }, 1270 {} 1271 }; 1272 1273 static ssize_t dw_mipi_dsi2_host_transfer(struct mipi_dsi_host *host, 1274 const struct mipi_dsi_msg *msg) 1275 { 1276 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1277 1278 return dw_mipi_dsi2_transfer(dsi2, msg); 1279 } 1280 1281 static int dw_mipi_dsi2_host_attach(struct mipi_dsi_host *host, 1282 struct mipi_dsi_device *device) 1283 { 1284 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1285 1286 if (device->lanes < 1 || device->lanes > 8) 1287 return -EINVAL; 1288 1289 dsi2->lanes = device->lanes; 1290 dsi2->channel = device->channel; 1291 dsi2->format = device->format; 1292 dsi2->mode_flags = device->mode_flags; 1293 1294 return 0; 1295 } 1296 1297 static const struct mipi_dsi_host_ops dw_mipi_dsi2_host_ops = { 1298 .attach = dw_mipi_dsi2_host_attach, 1299 .transfer = dw_mipi_dsi2_host_transfer, 1300 }; 1301 1302 static int dw_mipi_dsi2_bind(struct udevice *dev) 1303 { 1304 struct mipi_dsi_host *host = dev_get_platdata(dev); 1305 1306 host->dev = dev; 1307 host->ops = &dw_mipi_dsi2_host_ops; 1308 1309 return dm_scan_fdt_dev(dev); 1310 } 1311 1312 U_BOOT_DRIVER(dw_mipi_dsi2) = { 1313 .name = "dw_mipi_dsi2", 1314 .id = UCLASS_DISPLAY, 1315 .of_match = dw_mipi_dsi2_ids, 1316 .probe = dw_mipi_dsi2_probe, 1317 .bind = dw_mipi_dsi2_bind, 1318 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi2), 1319 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_host), 1320 }; 1321