1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Author: Guochun Huang <hero.huang@rock-chips.com> 7 */ 8 9 #include <drm/drm_mipi_dsi.h> 10 11 #include <config.h> 12 #include <common.h> 13 #include <errno.h> 14 #include <asm/unaligned.h> 15 #include <asm/gpio.h> 16 #include <asm/io.h> 17 #include <asm/hardware.h> 18 #include <dm/device.h> 19 #include <dm/read.h> 20 #include <dm/of_access.h> 21 #include <regmap.h> 22 #include <syscon.h> 23 #include <asm/arch-rockchip/clock.h> 24 #include <linux/iopoll.h> 25 26 #include "rockchip_display.h" 27 #include "rockchip_crtc.h" 28 #include "rockchip_connector.h" 29 #include "rockchip_panel.h" 30 #include "rockchip_phy.h" 31 32 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) 33 34 #define DSI2_PWR_UP 0x000c 35 #define RESET 0 36 #define POWER_UP BIT(0) 37 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 38 #define DSI2_SOFT_RESET 0x0010 39 #define SYS_RSTN BIT(2) 40 #define PHY_RSTN BIT(1) 41 #define IPI_RSTN BIT(0) 42 #define INT_ST_MAIN 0x0014 43 #define DSI2_MODE_CTRL 0x0018 44 #define DSI2_MODE_STATUS 0x001c 45 #define DSI2_CORE_STATUS 0x0020 46 #define PRI_RD_DATA_AVAIL BIT(26) 47 #define PRI_FIFOS_NOT_EMPTY BIT(25) 48 #define PRI_BUSY BIT(24) 49 #define CRI_RD_DATA_AVAIL BIT(18) 50 #define CRT_FIFOS_NOT_EMPTY BIT(17) 51 #define CRI_BUSY BIT(16) 52 #define IPI_FIFOS_NOT_EMPTY BIT(9) 53 #define IPI_BUSY BIT(8) 54 #define CORE_FIFOS_NOT_EMPTY BIT(1) 55 #define CORE_BUSY BIT(0) 56 #define MANUAL_MODE_CFG 0x0024 57 #define MANUAL_MODE_EN BIT(0) 58 #define DSI2_TIMEOUT_HSTX_CFG 0x0048 59 #define TO_HSTX(x) UPDATE(x, 15, 0) 60 #define DSI2_TIMEOUT_HSTXRDY_CFG 0x004c 61 #define TO_HSTXRDY(x) UPDATE(x, 15, 0) 62 #define DSI2_TIMEOUT_LPRX_CFG 0x0050 63 #define TO_LPRXRDY(x) UPDATE(x, 15, 0) 64 #define DSI2_TIMEOUT_LPTXRDY_CFG 0x0054 65 #define TO_LPTXRDY(x) UPDATE(x, 15, 0) 66 #define DSI2_TIMEOUT_LPTXTRIG_CFG 0x0058 67 #define TO_LPTXTRIG(x) UPDATE(x, 15, 0) 68 #define DSI2_TIMEOUT_LPTXULPS_CFG 0x005c 69 #define TO_LPTXULPS(x) UPDATE(x, 15, 0) 70 #define DSI2_TIMEOUT_BTA_CFG 0x60 71 #define TO_BTA(x) UPDATE(x, 15, 0) 72 73 #define DSI2_PHY_MODE_CFG 0x0100 74 #define PPI_WIDTH(x) UPDATE(x, 9, 8) 75 #define PHY_LANES(x) UPDATE(x - 1, 5, 4) 76 #define PHY_TYPE(x) UPDATE(x, 0, 0) 77 #define DSI2_PHY_CLK_CFG 0X0104 78 #define PHY_LPTX_CLK_DIV(x) UPDATE(x, 12, 8) 79 #define NON_CONTINUOUS_CLK BIT(0) 80 #define DSI2_PHY_LP2HS_MAN_CFG 0x010c 81 #define PHY_LP2HS_TIME(x) UPDATE(x, 28, 0) 82 #define DSI2_PHY_HS2LP_MAN_CFG 0x0114 83 #define PHY_HS2LP_TIME(x) UPDATE(x, 28, 0) 84 #define DSI2_PHY_MAX_RD_T_MAN_CFG 0x011c 85 #define PHY_MAX_RD_TIME(x) UPDATE(x, 26, 0) 86 #define DSI2_PHY_ESC_CMD_T_MAN_CFG 0x0124 87 #define PHY_ESC_CMD_TIME(x) UPDATE(x, 28, 0) 88 #define DSI2_PHY_ESC_BYTE_T_MAN_CFG 0x012c 89 #define PHY_ESC_BYTE_TIME(x) UPDATE(x, 28, 0) 90 91 #define DSI2_PHY_IPI_RATIO_MAN_CFG 0x0134 92 #define PHY_IPI_RATIO(x) UPDATE(x, 21, 0) 93 #define DSI2_PHY_SYS_RATIO_MAN_CFG 0x013C 94 #define PHY_SYS_RATIO(x) UPDATE(x, 16, 0) 95 96 #define DSI2_DSI_GENERAL_CFG 0x0200 97 #define BTA_EN BIT(1) 98 #define EOTP_TX_EN BIT(0) 99 #define DSI2_DSI_VCID_CFG 0x0204 100 #define TX_VCID(x) UPDATE(x, 1, 0) 101 #define DSI2_DSI_SCRAMBLING_CFG 0x0208 102 #define SCRAMBLING_SEED(x) UPDATE(x, 31, 16) 103 #define SCRAMBLING_EN BIT(0) 104 #define DSI2_DSI_VID_TX_CFG 0x020c 105 #define LPDT_DISPLAY_CMD_EN BIT(20) 106 #define BLK_VFP_HS_EN BIT(14) 107 #define BLK_VBP_HS_EN BIT(13) 108 #define BLK_VSA_HS_EN BIT(12) 109 #define BLK_HFP_HS_EN BIT(6) 110 #define BLK_HBP_HS_EN BIT(5) 111 #define BLK_HSA_HS_EN BIT(4) 112 #define VID_MODE_TYPE(x) UPDATE(x, 1, 0) 113 #define DSI2_CRI_TX_HDR 0x02c0 114 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 115 #define DSI2_CRI_TX_PLD 0x02c4 116 #define DSI2_CRI_RX_HDR 0x02c8 117 #define DSI2_CRI_RX_PLD 0x02cc 118 119 #define DSI2_IPI_COLOR_MAN_CFG 0x0300 120 #define IPI_DEPTH(x) UPDATE(x, 7, 4) 121 #define IPI_DEPTH_5_6_5_BITS 0x02 122 #define IPI_DEPTH_6_BITS 0x03 123 #define IPI_DEPTH_8_BITS 0x05 124 #define IPI_DEPTH_10_BITS 0x06 125 #define IPI_FORMAT(x) UPDATE(x, 3, 0) 126 #define IPI_FORMAT_RGB 0x0 127 #define IPI_FORMAT_DSC 0x0b 128 #define DSI2_IPI_VID_HSA_MAN_CFG 0x0304 129 #define VID_HSA_TIME(x) UPDATE(x, 29, 0) 130 #define DSI2_IPI_VID_HBP_MAN_CFG 0x030c 131 #define VID_HBP_TIME(x) UPDATE(x, 29, 0) 132 #define DSI2_IPI_VID_HACT_MAN_CFG 0x0314 133 #define VID_HACT_TIME(x) UPDATE(x, 29, 0) 134 #define DSI2_IPI_VID_HLINE_MAN_CFG 0x031c 135 #define VID_HLINE_TIME(x) UPDATE(x, 29, 0) 136 #define DSI2_IPI_VID_VSA_MAN_CFG 0x0324 137 #define VID_VSA_LINES(x) UPDATE(x, 9, 0) 138 #define DSI2_IPI_VID_VBP_MAN_CFG 0X032C 139 #define VID_VBP_LINES(x) UPDATE(x, 9, 0) 140 #define DSI2_IPI_VID_VACT_MAN_CFG 0X0334 141 #define VID_VACT_LINES(x) UPDATE(x, 13, 0) 142 #define DSI2_IPI_VID_VFP_MAN_CFG 0X033C 143 #define VID_VFP_LINES(x) UPDATE(x, 9, 0) 144 #define DSI2_IPI_PIX_PKT_CFG 0x0344 145 #define MAX_PIX_PKT(x) UPDATE(x, 15, 0) 146 147 #define DSI2_INT_ST_PHY 0x0400 148 #define DSI2_INT_MASK_PHY 0x0404 149 #define DSI2_INT_ST_TO 0x0410 150 #define DSI2_INT_MASK_TO 0x0414 151 #define DSI2_INT_ST_ACK 0x0420 152 #define DSI2_INT_MASK_ACK 0x0424 153 #define DSI2_INT_ST_IPI 0x0430 154 #define DSI2_INT_MASK_IPI 0x0434 155 #define DSI2_INT_ST_FIFO 0x0440 156 #define DSI2_INT_MASK_FIFO 0x0444 157 #define DSI2_INT_ST_PRI 0x0450 158 #define DSI2_INT_MASK_PRI 0x0454 159 #define DSI2_INT_ST_CRI 0x0460 160 #define DSI2_INT_MASK_CRI 0x0464 161 #define DSI2_INT_FORCE_CRI 0x0468 162 #define DSI2_MAX_REGISGER DSI2_INT_FORCE_CRI 163 164 #define CMD_PKT_STATUS_TIMEOUT_US 1000 165 #define MODE_STATUS_TIMEOUT_US 20000 166 #define PSEC_PER_SEC 1000000000000LL 167 #define USEC_PER_SEC 1000000L 168 #define MSEC_PER_SEC 1000L 169 170 #define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 16) | ((lsb) << 8) | (msb)) 171 172 enum vid_mode_type { 173 VID_MODE_TYPE_NON_BURST_SYNC_PULSES, 174 VID_MODE_TYPE_NON_BURST_SYNC_EVENTS, 175 VID_MODE_TYPE_BURST, 176 }; 177 178 enum mode_ctrl { 179 IDLE_MODE, 180 AUTOCALC_MODE, 181 COMMAND_MODE, 182 VIDEO_MODE, 183 DATA_STREAM_MODE, 184 VIDE_TEST_MODE, 185 DATA_STREAM_TEST_MODE, 186 }; 187 188 enum grf_reg_fields { 189 TXREQCLKHS_EN, 190 GATING_EN, 191 IPI_SHUTDN, 192 IPI_COLORM, 193 IPI_COLOR_DEPTH, 194 IPI_FORMAT, 195 MAX_FIELDS, 196 }; 197 198 enum phy_type { 199 DPHY, 200 CPHY, 201 }; 202 203 enum ppi_width { 204 PPI_WIDTH_8_BITS, 205 PPI_WIDTH_16_BITS, 206 PPI_WIDTH_32_BITS, 207 }; 208 209 struct rockchip_cmd_header { 210 u8 data_type; 211 u8 delay_ms; 212 u8 payload_length; 213 }; 214 215 struct dw_mipi_dsi2_plat_data { 216 bool dsc; 217 const u32 *dsi0_grf_reg_fields; 218 const u32 *dsi1_grf_reg_fields; 219 unsigned long long dphy_max_bit_rate_per_lane; 220 unsigned long long cphy_max_symbol_rate_per_lane; 221 }; 222 223 struct mipi_dcphy { 224 /* Non-SNPS PHY */ 225 struct rockchip_phy *phy; 226 227 u16 input_div; 228 u16 feedback_div; 229 }; 230 231 /** 232 * struct mipi_dphy_configure - MIPI D-PHY configuration set 233 * 234 * This structure is used to represent the configuration state of a 235 * MIPI D-PHY phy. 236 */ 237 struct mipi_dphy_configure { 238 unsigned int clk_miss; 239 unsigned int clk_post; 240 unsigned int clk_pre; 241 unsigned int clk_prepare; 242 unsigned int clk_settle; 243 unsigned int clk_term_en; 244 unsigned int clk_trail; 245 unsigned int clk_zero; 246 unsigned int d_term_en; 247 unsigned int eot; 248 unsigned int hs_exit; 249 unsigned int hs_prepare; 250 unsigned int hs_settle; 251 unsigned int hs_skip; 252 unsigned int hs_trail; 253 unsigned int hs_zero; 254 unsigned int init; 255 unsigned int lpx; 256 unsigned int ta_get; 257 unsigned int ta_go; 258 unsigned int ta_sure; 259 unsigned int wakeup; 260 unsigned long hs_clk_rate; 261 unsigned long lp_clk_rate; 262 unsigned char lanes; 263 }; 264 265 struct dw_mipi_dsi2 { 266 struct rockchip_connector connector; 267 struct udevice *dev; 268 void *base; 269 void *grf; 270 int id; 271 struct dw_mipi_dsi2 *master; 272 struct dw_mipi_dsi2 *slave; 273 bool prepared; 274 275 bool auto_calc_mode; 276 bool c_option; 277 bool dsc_enable; 278 bool scrambling_en; 279 unsigned int slice_width; 280 unsigned int slice_height; 281 u32 version_major; 282 u32 version_minor; 283 struct clk sys_clk; 284 285 unsigned int lane_hs_rate; /* Kbps/Ksps per lane */ 286 u32 channel; 287 u32 lanes; 288 u32 format; 289 u32 mode_flags; 290 u64 mipi_pixel_rate; 291 struct mipi_dcphy dcphy; 292 struct drm_display_mode mode; 293 bool data_swap; 294 295 struct gpio_desc te_gpio; 296 struct mipi_dsi_device *device; 297 struct mipi_dphy_configure mipi_dphy_cfg; 298 const struct dw_mipi_dsi2_plat_data *pdata; 299 struct drm_dsc_picture_parameter_set *pps; 300 }; 301 302 static inline void dsi_write(struct dw_mipi_dsi2 *dsi2, u32 reg, u32 val) 303 { 304 writel(val, dsi2->base + reg); 305 } 306 307 static inline u32 dsi_read(struct dw_mipi_dsi2 *dsi2, u32 reg) 308 { 309 return readl(dsi2->base + reg); 310 } 311 312 static inline void dsi_update_bits(struct dw_mipi_dsi2 *dsi2, 313 u32 reg, u32 mask, u32 val) 314 { 315 u32 orig, tmp; 316 317 orig = dsi_read(dsi2, reg); 318 tmp = orig & ~mask; 319 tmp |= val & mask; 320 dsi_write(dsi2, reg, tmp); 321 } 322 323 static void grf_field_write(struct dw_mipi_dsi2 *dsi2, enum grf_reg_fields index, 324 unsigned int val) 325 { 326 const u32 field = dsi2->id ? dsi2->pdata->dsi1_grf_reg_fields[index] : 327 dsi2->pdata->dsi0_grf_reg_fields[index]; 328 u16 reg; 329 u8 msb, lsb; 330 331 if (!field) 332 return; 333 334 reg = (field >> 16) & 0xffff; 335 lsb = (field >> 8) & 0xff; 336 msb = (field >> 0) & 0xff; 337 338 regmap_write(dsi2->grf, reg, GENMASK(msb, lsb) << 16 | val << lsb); 339 } 340 341 static unsigned long dw_mipi_dsi2_get_lane_rate(struct dw_mipi_dsi2 *dsi2) 342 { 343 const struct drm_display_mode *mode = &dsi2->mode; 344 u64 max_lane_rate, lane_rate; 345 unsigned int value; 346 int bpp, lanes; 347 u64 tmp; 348 349 max_lane_rate = (dsi2->c_option) ? 350 dsi2->pdata->cphy_max_symbol_rate_per_lane : 351 dsi2->pdata->dphy_max_bit_rate_per_lane; 352 353 /* 354 * optional override of the desired bandwidth 355 * High-Speed mode: Differential and terminated: 80Mbps ~ 4500 Mbps 356 */ 357 value = dev_read_u32_default(dsi2->dev, "rockchip,lane-rate", 0); 358 if (value >= 80000 && value <= 4500000) 359 return value * MSEC_PER_SEC; 360 else if (value >= 80 && value <= 4500) 361 return value * USEC_PER_SEC; 362 363 bpp = mipi_dsi_pixel_format_to_bpp(dsi2->format); 364 if (bpp < 0) 365 bpp = 24; 366 367 lanes = dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes; 368 tmp = (u64)mode->crtc_clock * 1000 * bpp; 369 do_div(tmp, lanes); 370 371 if (dsi2->c_option) 372 tmp = DIV_ROUND_CLOSEST(tmp * 100, 228); 373 374 /* set BW a little larger only in video burst mode in 375 * consideration of the protocol overhead and HS mode 376 * switching to BLLP mode, take 1 / 0.9, since Mbps must 377 * big than bandwidth of RGB 378 */ 379 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { 380 tmp *= 10; 381 do_div(tmp, 9); 382 } 383 384 if (tmp > max_lane_rate) 385 lane_rate = max_lane_rate; 386 else 387 lane_rate = tmp; 388 389 return lane_rate; 390 } 391 392 static int cri_fifos_wait_avail(struct dw_mipi_dsi2 *dsi2) 393 { 394 u32 sts, mask; 395 int ret; 396 397 mask = CRI_BUSY | CRT_FIFOS_NOT_EMPTY; 398 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 399 sts, !(sts & mask), 400 CMD_PKT_STATUS_TIMEOUT_US); 401 if (ret < 0) { 402 printf("command interface is busy: 0x%x\n", sts); 403 return ret; 404 } 405 406 return 0; 407 } 408 409 static int dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 *dsi2, 410 const struct mipi_dsi_msg *msg) 411 { 412 u8 *payload = msg->rx_buf; 413 u8 data_type; 414 u16 wc; 415 int i, j, ret, len = msg->rx_len; 416 unsigned int vrefresh = drm_mode_vrefresh(&dsi2->mode); 417 u32 val; 418 419 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 420 val, val & CRI_RD_DATA_AVAIL, 421 DIV_ROUND_UP(1000000, vrefresh)); 422 if (ret) { 423 printf("CRI has no available read data\n"); 424 return ret; 425 } 426 427 val = dsi_read(dsi2, DSI2_CRI_RX_HDR); 428 data_type = val & 0x3f; 429 430 if (mipi_dsi_packet_format_is_short(data_type)) { 431 for (i = 0; i < len && i < 2; i++) 432 payload[i] = (val >> (8 * (i + 1))) & 0xff; 433 434 return 0; 435 } 436 437 wc = (val >> 8) & 0xffff; 438 /* Receive payload */ 439 for (i = 0; i < len && i < wc; i += 4) { 440 val = dsi_read(dsi2, DSI2_CRI_RX_PLD); 441 for (j = 0; j < 4 && j + i < len && j + i < wc; j++) 442 payload[i + j] = val >> (8 * j); 443 } 444 445 return 0; 446 } 447 448 static ssize_t dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 *dsi2, 449 const struct mipi_dsi_msg *msg) 450 { 451 struct mipi_dsi_packet packet; 452 int ret; 453 int val; 454 u32 mode; 455 456 dsi_update_bits(dsi2, DSI2_DSI_VID_TX_CFG, LPDT_DISPLAY_CMD_EN, 457 msg->flags & MIPI_DSI_MSG_USE_LPM ? 458 LPDT_DISPLAY_CMD_EN : 0); 459 460 /* create a packet to the DSI protocol */ 461 ret = mipi_dsi_create_packet(&packet, msg); 462 if (ret) { 463 printf("failed to create packet: %d\n", ret); 464 return ret; 465 } 466 467 /* check cri interface is not busy */ 468 ret = cri_fifos_wait_avail(dsi2); 469 if (ret) 470 return ret; 471 472 /* Send payload */ 473 while (DIV_ROUND_UP(packet.payload_length, 4)) { 474 if (packet.payload_length < 4) { 475 /* send residu payload */ 476 val = 0; 477 memcpy(&val, packet.payload, packet.payload_length); 478 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 479 packet.payload_length = 0; 480 } else { 481 val = get_unaligned_le32(packet.payload); 482 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 483 packet.payload += 4; 484 packet.payload_length -= 4; 485 } 486 } 487 488 /* Send packet header */ 489 mode = CMD_TX_MODE(msg->flags & MIPI_DSI_MSG_USE_LPM ? 1 : 0); 490 val = get_unaligned_le32(packet.header); 491 dsi_write(dsi2, DSI2_CRI_TX_HDR, mode | val); 492 493 ret = cri_fifos_wait_avail(dsi2); 494 if (ret) 495 return ret; 496 497 if (msg->rx_len) { 498 ret = dw_mipi_dsi2_read_from_fifo(dsi2, msg); 499 if (ret < 0) 500 return ret; 501 } 502 503 if (dsi2->slave) { 504 ret = dw_mipi_dsi2_transfer(dsi2->slave, msg); 505 if (ret < 0) 506 return ret; 507 } 508 509 return msg->rx_len ? msg->rx_len : msg->tx_len; 510 } 511 512 static void dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 *dsi2) 513 { 514 u32 val, color_depth; 515 516 switch (dsi2->format) { 517 case MIPI_DSI_FMT_RGB666: 518 case MIPI_DSI_FMT_RGB666_PACKED: 519 color_depth = IPI_DEPTH_6_BITS; 520 break; 521 case MIPI_DSI_FMT_RGB565: 522 color_depth = IPI_DEPTH_5_6_5_BITS; 523 break; 524 case MIPI_DSI_FMT_RGB888: 525 default: 526 color_depth = IPI_DEPTH_8_BITS; 527 break; 528 } 529 530 val = IPI_DEPTH(color_depth) | 531 IPI_FORMAT(dsi2->dsc_enable ? IPI_FORMAT_DSC : IPI_FORMAT_RGB); 532 dsi_write(dsi2, DSI2_IPI_COLOR_MAN_CFG, val); 533 grf_field_write(dsi2, IPI_COLOR_DEPTH, color_depth); 534 535 if (dsi2->dsc_enable) 536 grf_field_write(dsi2, IPI_FORMAT, IPI_FORMAT_DSC); 537 } 538 539 static void dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 *dsi2) 540 { 541 struct drm_display_mode *mode = &dsi2->mode; 542 u32 hline, hsa, hbp, hact; 543 u64 hline_time, hsa_time, hbp_time, hact_time, tmp; 544 u64 pixel_clk, phy_hs_clk; 545 u32 vact, vsa, vfp, vbp; 546 u16 val; 547 548 if (dsi2->slave || dsi2->master) 549 val = mode->hdisplay / 2; 550 else 551 val = mode->hdisplay; 552 553 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val)); 554 555 dw_mipi_dsi2_ipi_color_coding_cfg(dsi2); 556 557 if (dsi2->auto_calc_mode) 558 return; 559 560 /* 561 * if the controller is intended to operate in data stream mode, 562 * no more steps are required. 563 */ 564 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) 565 return; 566 567 vact = mode->vdisplay; 568 vsa = mode->vsync_end - mode->vsync_start; 569 vfp = mode->vsync_start - mode->vdisplay; 570 vbp = mode->vtotal - mode->vsync_end; 571 hact = mode->hdisplay; 572 hsa = mode->hsync_end - mode->hsync_start; 573 hbp = mode->htotal - mode->hsync_end; 574 hline = mode->htotal; 575 576 pixel_clk = mode->crtc_clock * MSEC_PER_SEC; 577 578 if (dsi2->c_option) 579 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 580 else 581 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 582 583 tmp = hsa * phy_hs_clk; 584 hsa_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 585 dsi_write(dsi2, DSI2_IPI_VID_HSA_MAN_CFG, VID_HSA_TIME(hsa_time)); 586 587 tmp = hbp * phy_hs_clk; 588 hbp_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 589 dsi_write(dsi2, DSI2_IPI_VID_HBP_MAN_CFG, VID_HBP_TIME(hbp_time)); 590 591 tmp = hact * phy_hs_clk; 592 hact_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 593 dsi_write(dsi2, DSI2_IPI_VID_HACT_MAN_CFG, VID_HACT_TIME(hact_time)); 594 595 tmp = hline * phy_hs_clk; 596 hline_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 597 dsi_write(dsi2, DSI2_IPI_VID_HLINE_MAN_CFG, VID_HLINE_TIME(hline_time)); 598 599 dsi_write(dsi2, DSI2_IPI_VID_VSA_MAN_CFG, VID_VSA_LINES(vsa)); 600 dsi_write(dsi2, DSI2_IPI_VID_VBP_MAN_CFG, VID_VBP_LINES(vbp)); 601 dsi_write(dsi2, DSI2_IPI_VID_VACT_MAN_CFG, VID_VACT_LINES(vact)); 602 dsi_write(dsi2, DSI2_IPI_VID_VFP_MAN_CFG, VID_VFP_LINES(vfp)); 603 } 604 605 static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2) 606 { 607 u32 val = 0, mode; 608 int ret; 609 610 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) 611 val |= BLK_HFP_HS_EN; 612 613 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) 614 val |= BLK_HBP_HS_EN; 615 616 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HSA) 617 val |= BLK_HSA_HS_EN; 618 619 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 620 val |= VID_MODE_TYPE_BURST; 621 else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 622 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 623 else 624 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 625 626 dsi_write(dsi2, DSI2_DSI_VID_TX_CFG, val); 627 628 dsi_write(dsi2, DSI2_MODE_CTRL, VIDEO_MODE); 629 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 630 mode, mode & VIDEO_MODE, 631 MODE_STATUS_TIMEOUT_US); 632 if (ret < 0) 633 printf("failed to enter video mode\n"); 634 } 635 636 static void dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 *dsi2) 637 { 638 u32 mode; 639 int ret; 640 641 dsi_write(dsi2, DSI2_MODE_CTRL, DATA_STREAM_MODE); 642 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 643 mode, mode & DATA_STREAM_MODE, 644 MODE_STATUS_TIMEOUT_US); 645 if (ret < 0) 646 printf("failed to enter data stream mode\n"); 647 } 648 649 static void dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 *dsi2) 650 { 651 u32 mode; 652 int ret; 653 654 dsi_write(dsi2, DSI2_MODE_CTRL, COMMAND_MODE); 655 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 656 mode, mode & COMMAND_MODE, 657 MODE_STATUS_TIMEOUT_US); 658 if (ret < 0) 659 printf("failed to enter cmd mode\n"); 660 } 661 662 static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2) 663 { 664 u32 mode; 665 int ret; 666 667 dw_mipi_dsi2_ipi_set(dsi2); 668 669 if (dsi2->auto_calc_mode) { 670 dsi_write(dsi2, DSI2_MODE_CTRL, AUTOCALC_MODE); 671 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 672 mode, mode == IDLE_MODE, 673 MODE_STATUS_TIMEOUT_US); 674 if (ret < 0) 675 printf("auto calculation training failed\n"); 676 } 677 678 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO) 679 dw_mipi_dsi2_set_vid_mode(dsi2); 680 else 681 dw_mipi_dsi2_set_data_stream_mode(dsi2); 682 683 if (dsi2->slave) 684 dw_mipi_dsi2_enable(dsi2->slave); 685 } 686 687 static void dw_mipi_dsi2_disable(struct dw_mipi_dsi2 *dsi2) 688 { 689 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, 0); 690 dw_mipi_dsi2_set_cmd_mode(dsi2); 691 692 if (dsi2->slave) 693 dw_mipi_dsi2_disable(dsi2->slave); 694 } 695 696 static void dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 *dsi2) 697 { 698 if (!dsi2->prepared) 699 return; 700 701 dsi_write(dsi2, DSI2_PWR_UP, RESET); 702 703 if (dsi2->dcphy.phy) 704 rockchip_phy_power_off(dsi2->dcphy.phy); 705 706 dsi2->prepared = false; 707 708 if (dsi2->slave) 709 dw_mipi_dsi2_post_disable(dsi2->slave); 710 } 711 712 static int dw_mipi_dsi2_connector_pre_init(struct rockchip_connector *conn, 713 struct display_state *state) 714 { 715 struct connector_state *conn_state = &state->conn_state; 716 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 717 struct mipi_dsi_host *host = dev_get_platdata(dsi2->dev); 718 struct mipi_dsi_device *device; 719 char name[20]; 720 721 conn_state->type = DRM_MODE_CONNECTOR_DSI; 722 723 if (conn->bridge) { 724 device = dev_get_platdata(conn->bridge->dev); 725 if (!device) 726 return -ENODEV; 727 728 device->host = host; 729 sprintf(name, "%s.%d", host->dev->name, device->channel); 730 device_set_name(conn->bridge->dev, name); 731 mipi_dsi_attach(device); 732 } 733 734 return 0; 735 } 736 737 static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2) 738 { 739 struct udevice *dev = dsi2->device->dev; 740 struct rockchip_cmd_header *header; 741 struct drm_dsc_picture_parameter_set *pps = NULL; 742 u8 *dsc_packed_pps; 743 const void *data; 744 int len; 745 746 dsi2->c_option = dev_read_bool(dev, "phy-c-option"); 747 dsi2->scrambling_en = dev_read_bool(dev, "scrambling-enable"); 748 dsi2->dsc_enable = dsi2->pdata->dsc ? 749 dev_read_bool(dev, "compressed-data") : false; 750 751 if (dsi2->slave) { 752 dsi2->slave->c_option = dsi2->c_option; 753 dsi2->slave->scrambling_en = dsi2->scrambling_en; 754 dsi2->slave->dsc_enable = dsi2->dsc_enable; 755 } 756 757 if (!dsi2->dsc_enable) 758 return 0; 759 760 dsi2->slice_width = dev_read_u32_default(dev, "slice-width", 0); 761 dsi2->slice_height = dev_read_u32_default(dev, "slice-height", 0); 762 dsi2->version_major = dev_read_u32_default(dev, "version-major", 0); 763 dsi2->version_minor = dev_read_u32_default(dev, "version-minor", 0); 764 765 data = dev_read_prop(dev, "panel-init-sequence", &len); 766 if (!data) 767 return -EINVAL; 768 769 while (len > sizeof(*header)) { 770 header = (struct rockchip_cmd_header *)data; 771 data += sizeof(*header); 772 len -= sizeof(*header); 773 774 if (header->payload_length > len) 775 return -EINVAL; 776 777 if (header->data_type == MIPI_DSI_PICTURE_PARAMETER_SET) { 778 dsc_packed_pps = calloc(1, header->payload_length); 779 if (!dsc_packed_pps) 780 return -ENOMEM; 781 782 memcpy(dsc_packed_pps, data, header->payload_length); 783 pps = (struct drm_dsc_picture_parameter_set *)dsc_packed_pps; 784 break; 785 } 786 787 data += header->payload_length; 788 len -= header->payload_length; 789 } 790 791 if (!pps) { 792 printf("not found dsc pps definition\n"); 793 return -EINVAL; 794 } 795 796 dsi2->pps = pps; 797 798 if (dsi2->slave) { 799 u16 pic_width = be16_to_cpu(pps->pic_width) / 2; 800 801 dsi2->pps->pic_width = cpu_to_be16(pic_width); 802 printf("dsc pic_width change from %d to %d\n", pic_width * 2, pic_width); 803 } 804 805 return 0; 806 } 807 808 static int dw_mipi_dsi2_connector_init(struct rockchip_connector *conn, struct display_state *state) 809 { 810 struct connector_state *conn_state = &state->conn_state; 811 struct crtc_state *cstate = &state->crtc_state; 812 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 813 struct rockchip_phy *phy = NULL; 814 struct udevice *phy_dev; 815 struct udevice *dev; 816 int ret; 817 818 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dsi2->id); 819 dsi2->dcphy.phy = conn->phy; 820 821 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 822 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709; 823 conn_state->color_range = DRM_COLOR_YCBCR_FULL_RANGE; 824 conn_state->output_if |= 825 dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0; 826 827 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) { 828 conn_state->output_flags |= ROCKCHIP_OUTPUT_MIPI_DS_MODE; 829 conn_state->hold_mode = true; 830 } 831 832 if (dsi2->lanes > 4) { 833 ret = uclass_get_device_by_name(UCLASS_DISPLAY, 834 "dsi@fde30000", 835 &dev); 836 if (ret) 837 return ret; 838 839 dsi2->slave = dev_get_priv(dev); 840 if (!dsi2->slave) 841 return -ENODEV; 842 843 dsi2->slave->master = dsi2; 844 dsi2->lanes /= 2; 845 846 dsi2->slave->auto_calc_mode = dsi2->auto_calc_mode; 847 dsi2->slave->lanes = dsi2->lanes; 848 dsi2->slave->format = dsi2->format; 849 dsi2->slave->mode_flags = dsi2->mode_flags; 850 dsi2->slave->channel = dsi2->channel; 851 conn_state->output_flags |= 852 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; 853 if (dsi2->data_swap) 854 conn_state->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP; 855 856 conn_state->output_if |= VOP_OUTPUT_IF_MIPI1; 857 858 ret = uclass_get_device_by_phandle(UCLASS_PHY, dev, 859 "phys", &phy_dev); 860 if (ret) 861 return -ENODEV; 862 863 phy = (struct rockchip_phy *)dev_get_driver_data(phy_dev); 864 if (!phy) 865 return -ENODEV; 866 867 dsi2->slave->dcphy.phy = phy; 868 if (phy->funcs && phy->funcs->init) 869 return phy->funcs->init(phy); 870 } 871 872 dw_mipi_dsi2_get_dsc_params_from_sink(dsi2); 873 874 if (dm_gpio_is_valid(&dsi2->te_gpio)) { 875 cstate->soft_te = true; 876 conn_state->te_gpio = &dsi2->te_gpio; 877 } 878 879 if (dsi2->dsc_enable) { 880 cstate->dsc_enable = 1; 881 cstate->dsc_sink_cap.version_major = dsi2->version_major; 882 cstate->dsc_sink_cap.version_minor = dsi2->version_minor; 883 cstate->dsc_sink_cap.slice_width = dsi2->slice_width; 884 cstate->dsc_sink_cap.slice_height = dsi2->slice_height; 885 /* only can support rgb888 panel now */ 886 cstate->dsc_sink_cap.target_bits_per_pixel_x16 = 8 << 4; 887 cstate->dsc_sink_cap.native_420 = 0; 888 memcpy(&cstate->pps, dsi2->pps, sizeof(struct drm_dsc_picture_parameter_set)); 889 } 890 891 return 0; 892 } 893 894 /* 895 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived 896 * from the valid ranges specified in Section 6.9, Table 14, Page 41 897 * of the D-PHY specification (v2.1). 898 */ 899 int mipi_dphy_get_default_config(unsigned long long hs_clk_rate, 900 struct mipi_dphy_configure *cfg) 901 { 902 unsigned long long ui; 903 904 if (!cfg) 905 return -EINVAL; 906 907 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); 908 do_div(ui, hs_clk_rate); 909 910 cfg->clk_miss = 0; 911 cfg->clk_post = 60000 + 52 * ui; 912 cfg->clk_pre = 8000; 913 cfg->clk_prepare = 38000; 914 cfg->clk_settle = 95000; 915 cfg->clk_term_en = 0; 916 cfg->clk_trail = 60000; 917 cfg->clk_zero = 262000; 918 cfg->d_term_en = 0; 919 cfg->eot = 0; 920 cfg->hs_exit = 100000; 921 cfg->hs_prepare = 40000 + 4 * ui; 922 cfg->hs_zero = 105000 + 6 * ui; 923 cfg->hs_settle = 85000 + 6 * ui; 924 cfg->hs_skip = 40000; 925 926 /* 927 * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40) 928 * contains this formula as: 929 * 930 * T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui) 931 * 932 * where n = 1 for forward-direction HS mode and n = 4 for reverse- 933 * direction HS mode. There's only one setting and this function does 934 * not parameterize on anything other that ui, so this code will 935 * assumes that reverse-direction HS mode is supported and uses n = 4. 936 */ 937 cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui); 938 939 cfg->init = 100; 940 cfg->lpx = 50000; 941 cfg->ta_get = 5 * cfg->lpx; 942 cfg->ta_go = 4 * cfg->lpx; 943 cfg->ta_sure = cfg->lpx; 944 cfg->wakeup = 1000; 945 946 return 0; 947 } 948 949 static void dw_mipi_dsi2_set_hs_clk(struct dw_mipi_dsi2 *dsi2, unsigned long rate) 950 { 951 mipi_dphy_get_default_config(rate, &dsi2->mipi_dphy_cfg); 952 953 if (!dsi2->c_option) 954 rockchip_phy_set_mode(dsi2->dcphy.phy, PHY_MODE_MIPI_DPHY); 955 956 rate = rockchip_phy_set_pll(dsi2->dcphy.phy, rate); 957 dsi2->lane_hs_rate = DIV_ROUND_CLOSEST(rate, MSEC_PER_SEC); 958 } 959 960 static void dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 *dsi2) 961 { 962 dsi_write(dsi2, DSI2_SOFT_RESET, 0X0); 963 udelay(100); 964 dsi_write(dsi2, DSI2_SOFT_RESET, SYS_RSTN | PHY_RSTN | IPI_RSTN); 965 } 966 967 static void 968 dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 *dsi2, u32 mode) 969 { 970 /* 971 * select controller work in Manual mode 972 * Manual: MANUAL_MODE_EN 973 * Automatic: 0 974 */ 975 dsi_write(dsi2, MANUAL_MODE_CFG, mode); 976 } 977 978 static void dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 *dsi2) 979 { 980 u32 val = 0; 981 982 /* PPI width is fixed to 16 bits in DCPHY */ 983 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes); 984 val |= PHY_TYPE(dsi2->c_option ? CPHY : DPHY); 985 dsi_write(dsi2, DSI2_PHY_MODE_CFG, val); 986 } 987 988 static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2) 989 { 990 u32 sys_clk = clk_get_rate(&dsi2->sys_clk) / USEC_PER_SEC; 991 u32 esc_clk_div; 992 u32 val = 0; 993 994 if (dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 995 val |= NON_CONTINUOUS_CLK; 996 997 /* The Escape clock ranges from 1MHz to 20MHz. */ 998 esc_clk_div = DIV_ROUND_UP(sys_clk, 20 * 2); 999 val |= PHY_LPTX_CLK_DIV(esc_clk_div); 1000 1001 dsi_write(dsi2, DSI2_PHY_CLK_CFG, val); 1002 } 1003 1004 static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2) 1005 { 1006 u64 ipi_clk, phy_hsclk, tmp; 1007 u32 sys_clk = clk_get_rate(&dsi2->sys_clk); 1008 1009 /* 1010 * in DPHY mode, the phy_hstx_clk is exactly 1/16 the Lane high-speed 1011 * data rate; In CPHY mode, the phy_hstx_clk is exactly 1/7 the trio 1012 * high speed symbol rate. 1013 */ 1014 if (dsi2->c_option) 1015 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 1016 1017 else 1018 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 1019 1020 /* IPI_RATIO_MAN_CFG = PHY_HSTX_CLK / IPI_CLK */ 1021 ipi_clk = dsi2->mipi_pixel_rate; 1022 1023 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, ipi_clk); 1024 dsi_write(dsi2, DSI2_PHY_IPI_RATIO_MAN_CFG, PHY_IPI_RATIO(tmp)); 1025 1026 /* SYS_RATIO_MAN_CFG = MIPI_DCPHY_HSCLK_Freq / SYS_CLK */ 1027 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, sys_clk); 1028 dsi_write(dsi2, DSI2_PHY_SYS_RATIO_MAN_CFG, PHY_SYS_RATIO(tmp)); 1029 } 1030 1031 static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2) 1032 { 1033 struct mipi_dphy_configure *cfg = &dsi2->mipi_dphy_cfg; 1034 unsigned long long tmp, ui; 1035 unsigned long long hstx_clk; 1036 1037 hstx_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 1038 1039 ui = ALIGN(PSEC_PER_SEC, hstx_clk); 1040 do_div(ui, hstx_clk); 1041 1042 /* PHY_LP2HS_TIME = (TLPX + THS-PREPARE + THS-ZERO) / Tphy_hstx_clk */ 1043 tmp = cfg->lpx + cfg->hs_prepare + cfg->hs_zero; 1044 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 1045 dsi_write(dsi2, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(tmp)); 1046 1047 /* PHY_HS2LP_TIME = (THS-TRAIL + THS-EXIT) / Tphy_hstx_clk */ 1048 tmp = cfg->hs_trail + cfg->hs_exit; 1049 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 1050 dsi_write(dsi2, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(tmp)); 1051 } 1052 1053 static void dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 *dsi2) 1054 { 1055 dw_mipi_dsi2_phy_mode_cfg(dsi2); 1056 dw_mipi_dsi2_phy_clk_mode_cfg(dsi2); 1057 1058 if (dsi2->auto_calc_mode) 1059 return; 1060 1061 dw_mipi_dsi2_phy_ratio_cfg(dsi2); 1062 dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(dsi2); 1063 1064 /* phy configuration 8 - 10 */ 1065 } 1066 1067 static void dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 *dsi2) 1068 { 1069 u32 val; 1070 1071 val = BTA_EN | EOTP_TX_EN; 1072 1073 if (dsi2->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 1074 val &= ~EOTP_TX_EN; 1075 1076 dsi_write(dsi2, DSI2_DSI_GENERAL_CFG, val); 1077 dsi_write(dsi2, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel)); 1078 1079 if (dsi2->scrambling_en) 1080 dsi_write(dsi2, DSI2_DSI_SCRAMBLING_CFG, SCRAMBLING_EN); 1081 } 1082 1083 static void dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 *dsi2, bool enable) 1084 { 1085 if (enable) { 1086 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x1); 1087 dsi_write(dsi2, DSI2_INT_MASK_TO, 0xf); 1088 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x1); 1089 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x1); 1090 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x1); 1091 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x1); 1092 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x1); 1093 } else { 1094 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x0); 1095 dsi_write(dsi2, DSI2_INT_MASK_TO, 0x0); 1096 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x0); 1097 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x0); 1098 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x0); 1099 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x0); 1100 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x0); 1101 }; 1102 } 1103 1104 static void mipi_dcphy_power_on(struct dw_mipi_dsi2 *dsi2) 1105 { 1106 if (!dsi2->dcphy.phy) 1107 return; 1108 1109 rockchip_phy_power_on(dsi2->dcphy.phy); 1110 } 1111 1112 static void dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 *dsi2) 1113 { 1114 if (dsi2->prepared) 1115 return; 1116 1117 dw_mipi_dsi2_host_softrst(dsi2); 1118 dsi_write(dsi2, DSI2_PWR_UP, RESET); 1119 1120 dw_mipi_dsi2_work_mode(dsi2, dsi2->auto_calc_mode ? 0 : MANUAL_MODE_EN); 1121 dw_mipi_dsi2_phy_init(dsi2); 1122 dw_mipi_dsi2_tx_option_set(dsi2); 1123 dw_mipi_dsi2_irq_enable(dsi2, 0); 1124 mipi_dcphy_power_on(dsi2); 1125 dsi_write(dsi2, DSI2_PWR_UP, POWER_UP); 1126 dw_mipi_dsi2_set_cmd_mode(dsi2); 1127 1128 dsi2->prepared = true; 1129 1130 if (dsi2->slave) 1131 dw_mipi_dsi2_pre_enable(dsi2->slave); 1132 } 1133 1134 static void dw_mipi_dsi2_get_mipi_pixel_clk(struct dw_mipi_dsi2 *dsi2, 1135 struct crtc_state *s) 1136 { 1137 struct drm_display_mode *mode = &dsi2->mode; 1138 u8 k = dsi2->slave ? 2 : 1; 1139 1140 /* 1.When MIPI works in uncompressed mode: 1141 * (Video Timing Pixel Rate)/(4)=(MIPI Pixel ClockxK)=(dclk_out×K)=dclk_core 1142 * 2.When MIPI works in compressed mode: 1143 * MIPI Pixel Clock = cds_clk / 2 1144 * MIPI is configured as double channel display mode, K=2, otherwise K=1. 1145 */ 1146 if (dsi2->dsc_enable) { 1147 dsi2->mipi_pixel_rate = s->dsc_cds_clk_rate / 2; 1148 if (dsi2->slave) 1149 dsi2->slave->mipi_pixel_rate = dsi2->mipi_pixel_rate; 1150 1151 return; 1152 } 1153 1154 dsi2->mipi_pixel_rate = (mode->crtc_clock * MSEC_PER_SEC) / (4 * k); 1155 if (dsi2->slave) 1156 dsi2->slave->mipi_pixel_rate = dsi2->mipi_pixel_rate; 1157 } 1158 1159 static int dw_mipi_dsi2_connector_prepare(struct rockchip_connector *conn, 1160 struct display_state *state) 1161 { 1162 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1163 struct connector_state *conn_state = &state->conn_state; 1164 struct crtc_state *cstate = &state->crtc_state; 1165 unsigned long lane_rate; 1166 1167 memcpy(&dsi2->mode, &conn_state->mode, sizeof(struct drm_display_mode)); 1168 if (dsi2->slave) 1169 memcpy(&dsi2->slave->mode, &dsi2->mode, 1170 sizeof(struct drm_display_mode)); 1171 1172 dw_mipi_dsi2_get_mipi_pixel_clk(dsi2, cstate); 1173 1174 lane_rate = dw_mipi_dsi2_get_lane_rate(dsi2); 1175 if (dsi2->dcphy.phy) 1176 dw_mipi_dsi2_set_hs_clk(dsi2, lane_rate); 1177 1178 if (dsi2->slave && dsi2->slave->dcphy.phy) 1179 dw_mipi_dsi2_set_hs_clk(dsi2->slave, lane_rate); 1180 1181 printf("final DSI-Link bandwidth: %u %s x %d\n", 1182 dsi2->lane_hs_rate, dsi2->c_option ? "Ksps" : "Kbps", 1183 dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes); 1184 1185 dw_mipi_dsi2_pre_enable(dsi2); 1186 1187 return 0; 1188 } 1189 1190 static void dw_mipi_dsi2_connector_unprepare(struct rockchip_connector *conn, 1191 struct display_state *state) 1192 { 1193 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1194 1195 dw_mipi_dsi2_post_disable(dsi2); 1196 } 1197 1198 static int dw_mipi_dsi2_connector_enable(struct rockchip_connector *conn, 1199 struct display_state *state) 1200 { 1201 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1202 1203 dw_mipi_dsi2_enable(dsi2); 1204 1205 return 0; 1206 } 1207 1208 static int dw_mipi_dsi2_connector_disable(struct rockchip_connector *conn, 1209 struct display_state *state) 1210 { 1211 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1212 1213 dw_mipi_dsi2_disable(dsi2); 1214 1215 return 0; 1216 } 1217 1218 static int dw_mipi_dsi2_connector_mode_valid(struct rockchip_connector *conn, 1219 struct display_state *state) 1220 { 1221 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1222 struct connector_state *conn_state = &state->conn_state; 1223 u8 min_pixels = dsi2->slave ? 8 : 4; 1224 struct videomode vm; 1225 1226 drm_display_mode_to_videomode(&conn_state->mode, &vm); 1227 1228 /* 1229 * the minimum region size (HSA,HBP,HACT,HFP) is 4 pixels 1230 * which is the ip known issues and limitations. 1231 */ 1232 if (!(vm.hsync_len < min_pixels || vm.hback_porch < min_pixels || 1233 vm.hfront_porch < min_pixels || vm.hactive < min_pixels)) 1234 return MODE_OK; 1235 1236 if (vm.hsync_len < min_pixels) 1237 vm.hsync_len = min_pixels; 1238 1239 if (vm.hback_porch < min_pixels) 1240 vm.hback_porch = min_pixels; 1241 1242 if (vm.hfront_porch < min_pixels) 1243 vm.hfront_porch = min_pixels; 1244 1245 if (vm.hactive < min_pixels) 1246 vm.hactive = min_pixels; 1247 1248 memset(&conn_state->mode, 0, sizeof(struct drm_display_mode)); 1249 drm_display_mode_from_videomode(&vm, &conn_state->mode); 1250 conn_state->mode.vrefresh = drm_mode_vrefresh(&conn_state->mode); 1251 1252 return MODE_OK; 1253 } 1254 1255 static const struct rockchip_connector_funcs dw_mipi_dsi2_connector_funcs = { 1256 .pre_init = dw_mipi_dsi2_connector_pre_init, 1257 .init = dw_mipi_dsi2_connector_init, 1258 .prepare = dw_mipi_dsi2_connector_prepare, 1259 .unprepare = dw_mipi_dsi2_connector_unprepare, 1260 .enable = dw_mipi_dsi2_connector_enable, 1261 .disable = dw_mipi_dsi2_connector_disable, 1262 .mode_valid = dw_mipi_dsi2_connector_mode_valid, 1263 }; 1264 1265 static int dw_mipi_dsi2_probe(struct udevice *dev) 1266 { 1267 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(dev); 1268 const struct dw_mipi_dsi2_plat_data *pdata = 1269 (const struct dw_mipi_dsi2_plat_data *)dev_get_driver_data(dev); 1270 struct udevice *syscon; 1271 int id, ret; 1272 1273 dsi2->base = dev_read_addr_ptr(dev); 1274 1275 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1276 &syscon); 1277 if (!ret) { 1278 dsi2->grf = syscon_get_regmap(syscon); 1279 if (!dsi2->grf) 1280 return -ENODEV; 1281 } 1282 1283 id = of_alias_get_id(ofnode_to_np(dev->node), "dsi"); 1284 if (id < 0) 1285 id = 0; 1286 1287 ret = gpio_request_by_name(dev, "te-gpios", 0, 1288 &dsi2->te_gpio, GPIOD_IS_IN); 1289 if (ret && ret != -ENOENT) { 1290 printf("%s: Cannot get TE GPIO: %d\n", __func__, ret); 1291 return ret; 1292 } 1293 1294 ret = clk_get_by_name(dev, "sys_clk", &dsi2->sys_clk); 1295 if (ret < 0) { 1296 printf("failed to get sys_clk: %d\n", ret); 1297 return ret; 1298 } 1299 1300 dsi2->dev = dev; 1301 dsi2->pdata = pdata; 1302 dsi2->id = id; 1303 dsi2->data_swap = dev_read_bool(dsi2->dev, "rockchip,data-swap"); 1304 dsi2->auto_calc_mode = dev_read_bool(dsi2->dev, "auto-calculation-mode"); 1305 1306 rockchip_connector_bind(&dsi2->connector, dev, id, &dw_mipi_dsi2_connector_funcs, NULL, 1307 DRM_MODE_CONNECTOR_DSI); 1308 1309 return 0; 1310 } 1311 1312 static const u32 rk3576_dsi_grf_reg_fields[MAX_FIELDS] = { 1313 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0028, 1, 1), 1314 [GATING_EN] = GRF_REG_FIELD(0x0028, 0, 0), 1315 [IPI_SHUTDN] = GRF_REG_FIELD(0x0028, 3, 3), 1316 [IPI_COLORM] = GRF_REG_FIELD(0x0028, 2, 2), 1317 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0028, 8, 11), 1318 [IPI_FORMAT] = GRF_REG_FIELD(0x0028, 4, 7), 1319 }; 1320 1321 static const u32 rk3588_dsi0_grf_reg_fields[MAX_FIELDS] = { 1322 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0000, 11, 11), 1323 [GATING_EN] = GRF_REG_FIELD(0x0000, 10, 10), 1324 [IPI_SHUTDN] = GRF_REG_FIELD(0x0000, 9, 9), 1325 [IPI_COLORM] = GRF_REG_FIELD(0x0000, 8, 8), 1326 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0000, 4, 7), 1327 [IPI_FORMAT] = GRF_REG_FIELD(0x0000, 0, 3), 1328 }; 1329 1330 static const u32 rk3588_dsi1_grf_reg_fields[MAX_FIELDS] = { 1331 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0004, 11, 11), 1332 [GATING_EN] = GRF_REG_FIELD(0x0004, 10, 10), 1333 [IPI_SHUTDN] = GRF_REG_FIELD(0x0004, 9, 9), 1334 [IPI_COLORM] = GRF_REG_FIELD(0x0004, 8, 8), 1335 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0004, 4, 7), 1336 [IPI_FORMAT] = GRF_REG_FIELD(0x0004, 0, 3), 1337 }; 1338 1339 static const struct dw_mipi_dsi2_plat_data rk3576_mipi_dsi2_plat_data = { 1340 .dsc = false, 1341 .dsi0_grf_reg_fields = rk3576_dsi_grf_reg_fields, 1342 .dphy_max_bit_rate_per_lane = 2500000000ULL, 1343 .cphy_max_symbol_rate_per_lane = 1700000000ULL, 1344 }; 1345 1346 static const struct dw_mipi_dsi2_plat_data rk3588_mipi_dsi2_plat_data = { 1347 .dsc = true, 1348 .dsi0_grf_reg_fields = rk3588_dsi0_grf_reg_fields, 1349 .dsi1_grf_reg_fields = rk3588_dsi1_grf_reg_fields, 1350 .dphy_max_bit_rate_per_lane = 4500000000ULL, 1351 .cphy_max_symbol_rate_per_lane = 2000000000ULL, 1352 }; 1353 1354 static const struct udevice_id dw_mipi_dsi2_ids[] = { 1355 { 1356 .compatible = "rockchip,rk3576-mipi-dsi2", 1357 .data = (ulong)&rk3576_mipi_dsi2_plat_data, 1358 }, { 1359 .compatible = "rockchip,rk3588-mipi-dsi2", 1360 .data = (ulong)&rk3588_mipi_dsi2_plat_data, 1361 }, 1362 {} 1363 }; 1364 1365 static ssize_t dw_mipi_dsi2_host_transfer(struct mipi_dsi_host *host, 1366 const struct mipi_dsi_msg *msg) 1367 { 1368 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1369 1370 return dw_mipi_dsi2_transfer(dsi2, msg); 1371 } 1372 1373 static int dw_mipi_dsi2_host_attach(struct mipi_dsi_host *host, 1374 struct mipi_dsi_device *device) 1375 { 1376 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1377 1378 if (device->lanes < 1 || device->lanes > 8) 1379 return -EINVAL; 1380 1381 dsi2->lanes = device->lanes; 1382 dsi2->channel = device->channel; 1383 dsi2->format = device->format; 1384 dsi2->mode_flags = device->mode_flags; 1385 dsi2->device = device; 1386 1387 return 0; 1388 } 1389 1390 static const struct mipi_dsi_host_ops dw_mipi_dsi2_host_ops = { 1391 .attach = dw_mipi_dsi2_host_attach, 1392 .transfer = dw_mipi_dsi2_host_transfer, 1393 }; 1394 1395 static int dw_mipi_dsi2_bind(struct udevice *dev) 1396 { 1397 struct mipi_dsi_host *host = dev_get_platdata(dev); 1398 1399 host->dev = dev; 1400 host->ops = &dw_mipi_dsi2_host_ops; 1401 1402 return dm_scan_fdt_dev(dev); 1403 } 1404 1405 static int dw_mipi_dsi2_child_post_bind(struct udevice *dev) 1406 { 1407 struct mipi_dsi_host *host = dev_get_platdata(dev->parent); 1408 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1409 char name[20]; 1410 1411 sprintf(name, "%s.%d", host->dev->name, device->channel); 1412 device_set_name(dev, name); 1413 1414 device->dev = dev; 1415 device->host = host; 1416 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4); 1417 device->format = dev_read_u32_default(dev, "dsi,format", 1418 MIPI_DSI_FMT_RGB888); 1419 device->mode_flags = dev_read_u32_default(dev, "dsi,flags", 1420 MIPI_DSI_MODE_VIDEO | 1421 MIPI_DSI_MODE_VIDEO_BURST | 1422 MIPI_DSI_MODE_VIDEO_HBP | 1423 MIPI_DSI_MODE_LPM | 1424 MIPI_DSI_MODE_EOT_PACKET); 1425 device->channel = dev_read_u32_default(dev, "reg", 0); 1426 1427 return 0; 1428 } 1429 1430 static int dw_mipi_dsi2_child_pre_probe(struct udevice *dev) 1431 { 1432 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1433 int ret; 1434 1435 ret = mipi_dsi_attach(device); 1436 if (ret) { 1437 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret); 1438 return ret; 1439 } 1440 1441 return 0; 1442 } 1443 1444 U_BOOT_DRIVER(dw_mipi_dsi2) = { 1445 .name = "dw_mipi_dsi2", 1446 .id = UCLASS_DISPLAY, 1447 .of_match = dw_mipi_dsi2_ids, 1448 .probe = dw_mipi_dsi2_probe, 1449 .bind = dw_mipi_dsi2_bind, 1450 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi2), 1451 .per_child_platdata_auto_alloc_size = sizeof(struct mipi_dsi_device), 1452 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_host), 1453 .child_post_bind = dw_mipi_dsi2_child_post_bind, 1454 .child_pre_probe = dw_mipi_dsi2_child_pre_probe, 1455 }; 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