1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Author: Guochun Huang <hero.huang@rock-chips.com> 7 */ 8 9 #include <drm/drm_mipi_dsi.h> 10 11 #include <config.h> 12 #include <common.h> 13 #include <errno.h> 14 #include <asm/unaligned.h> 15 #include <asm/gpio.h> 16 #include <asm/io.h> 17 #include <asm/hardware.h> 18 #include <dm/device.h> 19 #include <dm/read.h> 20 #include <dm/of_access.h> 21 #include <regmap.h> 22 #include <syscon.h> 23 #include <asm/arch-rockchip/clock.h> 24 #include <linux/iopoll.h> 25 26 #include "rockchip_display.h" 27 #include "rockchip_crtc.h" 28 #include "rockchip_connector.h" 29 #include "rockchip_panel.h" 30 #include "rockchip_phy.h" 31 32 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) 33 34 #define DSI2_PWR_UP 0x000c 35 #define RESET 0 36 #define POWER_UP BIT(0) 37 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 38 #define DSI2_SOFT_RESET 0x0010 39 #define SYS_RSTN BIT(2) 40 #define PHY_RSTN BIT(1) 41 #define IPI_RSTN BIT(0) 42 #define INT_ST_MAIN 0x0014 43 #define DSI2_MODE_CTRL 0x0018 44 #define DSI2_MODE_STATUS 0x001c 45 #define DSI2_CORE_STATUS 0x0020 46 #define PRI_RD_DATA_AVAIL BIT(26) 47 #define PRI_FIFOS_NOT_EMPTY BIT(25) 48 #define PRI_BUSY BIT(24) 49 #define CRI_RD_DATA_AVAIL BIT(18) 50 #define CRT_FIFOS_NOT_EMPTY BIT(17) 51 #define CRI_BUSY BIT(16) 52 #define IPI_FIFOS_NOT_EMPTY BIT(9) 53 #define IPI_BUSY BIT(8) 54 #define CORE_FIFOS_NOT_EMPTY BIT(1) 55 #define CORE_BUSY BIT(0) 56 #define MANUAL_MODE_CFG 0x0024 57 #define MANUAL_MODE_EN BIT(0) 58 #define DSI2_TIMEOUT_HSTX_CFG 0x0048 59 #define TO_HSTX(x) UPDATE(x, 15, 0) 60 #define DSI2_TIMEOUT_HSTXRDY_CFG 0x004c 61 #define TO_HSTXRDY(x) UPDATE(x, 15, 0) 62 #define DSI2_TIMEOUT_LPRX_CFG 0x0050 63 #define TO_LPRXRDY(x) UPDATE(x, 15, 0) 64 #define DSI2_TIMEOUT_LPTXRDY_CFG 0x0054 65 #define TO_LPTXRDY(x) UPDATE(x, 15, 0) 66 #define DSI2_TIMEOUT_LPTXTRIG_CFG 0x0058 67 #define TO_LPTXTRIG(x) UPDATE(x, 15, 0) 68 #define DSI2_TIMEOUT_LPTXULPS_CFG 0x005c 69 #define TO_LPTXULPS(x) UPDATE(x, 15, 0) 70 #define DSI2_TIMEOUT_BTA_CFG 0x60 71 #define TO_BTA(x) UPDATE(x, 15, 0) 72 73 #define DSI2_PHY_MODE_CFG 0x0100 74 #define PPI_WIDTH(x) UPDATE(x, 9, 8) 75 #define PHY_LANES(x) UPDATE(x - 1, 5, 4) 76 #define PHY_TYPE(x) UPDATE(x, 0, 0) 77 #define DSI2_PHY_CLK_CFG 0X0104 78 #define PHY_LPTX_CLK_DIV(x) UPDATE(x, 12, 8) 79 #define NON_CONTINUOUS_CLK BIT(0) 80 #define DSI2_PHY_LP2HS_MAN_CFG 0x010c 81 #define PHY_LP2HS_TIME(x) UPDATE(x, 28, 0) 82 #define DSI2_PHY_HS2LP_MAN_CFG 0x0114 83 #define PHY_HS2LP_TIME(x) UPDATE(x, 28, 0) 84 #define DSI2_PHY_MAX_RD_T_MAN_CFG 0x011c 85 #define PHY_MAX_RD_TIME(x) UPDATE(x, 26, 0) 86 #define DSI2_PHY_ESC_CMD_T_MAN_CFG 0x0124 87 #define PHY_ESC_CMD_TIME(x) UPDATE(x, 28, 0) 88 #define DSI2_PHY_ESC_BYTE_T_MAN_CFG 0x012c 89 #define PHY_ESC_BYTE_TIME(x) UPDATE(x, 28, 0) 90 91 #define DSI2_PHY_IPI_RATIO_MAN_CFG 0x0134 92 #define PHY_IPI_RATIO(x) UPDATE(x, 21, 0) 93 #define DSI2_PHY_SYS_RATIO_MAN_CFG 0x013C 94 #define PHY_SYS_RATIO(x) UPDATE(x, 16, 0) 95 96 #define DSI2_DSI_GENERAL_CFG 0x0200 97 #define BTA_EN BIT(1) 98 #define EOTP_TX_EN BIT(0) 99 #define DSI2_DSI_VCID_CFG 0x0204 100 #define TX_VCID(x) UPDATE(x, 1, 0) 101 #define DSI2_DSI_SCRAMBLING_CFG 0x0208 102 #define SCRAMBLING_SEED(x) UPDATE(x, 31, 16) 103 #define SCRAMBLING_EN BIT(0) 104 #define DSI2_DSI_VID_TX_CFG 0x020c 105 #define LPDT_DISPLAY_CMD_EN BIT(20) 106 #define BLK_VFP_HS_EN BIT(14) 107 #define BLK_VBP_HS_EN BIT(13) 108 #define BLK_VSA_HS_EN BIT(12) 109 #define BLK_HFP_HS_EN BIT(6) 110 #define BLK_HBP_HS_EN BIT(5) 111 #define BLK_HSA_HS_EN BIT(4) 112 #define VID_MODE_TYPE(x) UPDATE(x, 1, 0) 113 #define DSI2_CRI_TX_HDR 0x02c0 114 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 115 #define DSI2_CRI_TX_PLD 0x02c4 116 #define DSI2_CRI_RX_HDR 0x02c8 117 #define DSI2_CRI_RX_PLD 0x02cc 118 119 #define DSI2_IPI_COLOR_MAN_CFG 0x0300 120 #define IPI_DEPTH(x) UPDATE(x, 7, 4) 121 #define IPI_DEPTH_5_6_5_BITS 0x02 122 #define IPI_DEPTH_6_BITS 0x03 123 #define IPI_DEPTH_8_BITS 0x05 124 #define IPI_DEPTH_10_BITS 0x06 125 #define IPI_FORMAT(x) UPDATE(x, 3, 0) 126 #define IPI_FORMAT_RGB 0x0 127 #define IPI_FORMAT_DSC 0x0b 128 #define DSI2_IPI_VID_HSA_MAN_CFG 0x0304 129 #define VID_HSA_TIME(x) UPDATE(x, 29, 0) 130 #define DSI2_IPI_VID_HBP_MAN_CFG 0x030c 131 #define VID_HBP_TIME(x) UPDATE(x, 29, 0) 132 #define DSI2_IPI_VID_HACT_MAN_CFG 0x0314 133 #define VID_HACT_TIME(x) UPDATE(x, 29, 0) 134 #define DSI2_IPI_VID_HLINE_MAN_CFG 0x031c 135 #define VID_HLINE_TIME(x) UPDATE(x, 29, 0) 136 #define DSI2_IPI_VID_VSA_MAN_CFG 0x0324 137 #define VID_VSA_LINES(x) UPDATE(x, 9, 0) 138 #define DSI2_IPI_VID_VBP_MAN_CFG 0X032C 139 #define VID_VBP_LINES(x) UPDATE(x, 9, 0) 140 #define DSI2_IPI_VID_VACT_MAN_CFG 0X0334 141 #define VID_VACT_LINES(x) UPDATE(x, 13, 0) 142 #define DSI2_IPI_VID_VFP_MAN_CFG 0X033C 143 #define VID_VFP_LINES(x) UPDATE(x, 9, 0) 144 #define DSI2_IPI_PIX_PKT_CFG 0x0344 145 #define MAX_PIX_PKT(x) UPDATE(x, 15, 0) 146 147 #define DSI2_INT_ST_PHY 0x0400 148 #define DSI2_INT_MASK_PHY 0x0404 149 #define DSI2_INT_ST_TO 0x0410 150 #define DSI2_INT_MASK_TO 0x0414 151 #define DSI2_INT_ST_ACK 0x0420 152 #define DSI2_INT_MASK_ACK 0x0424 153 #define DSI2_INT_ST_IPI 0x0430 154 #define DSI2_INT_MASK_IPI 0x0434 155 #define DSI2_INT_ST_FIFO 0x0440 156 #define DSI2_INT_MASK_FIFO 0x0444 157 #define DSI2_INT_ST_PRI 0x0450 158 #define DSI2_INT_MASK_PRI 0x0454 159 #define DSI2_INT_ST_CRI 0x0460 160 #define DSI2_INT_MASK_CRI 0x0464 161 #define DSI2_INT_FORCE_CRI 0x0468 162 #define DSI2_MAX_REGISGER DSI2_INT_FORCE_CRI 163 164 #define CMD_PKT_STATUS_TIMEOUT_US 1000 165 #define MODE_STATUS_TIMEOUT_US 20000 166 #define PSEC_PER_SEC 1000000000000LL 167 #define USEC_PER_SEC 1000000L 168 #define MSEC_PER_SEC 1000L 169 170 #define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 16) | ((lsb) << 8) | (msb)) 171 172 enum vid_mode_type { 173 VID_MODE_TYPE_NON_BURST_SYNC_PULSES, 174 VID_MODE_TYPE_NON_BURST_SYNC_EVENTS, 175 VID_MODE_TYPE_BURST, 176 }; 177 178 enum mode_ctrl { 179 IDLE_MODE, 180 AUTOCALC_MODE, 181 COMMAND_MODE, 182 VIDEO_MODE, 183 DATA_STREAM_MODE, 184 VIDE_TEST_MODE, 185 DATA_STREAM_TEST_MODE, 186 }; 187 188 enum grf_reg_fields { 189 TXREQCLKHS_EN, 190 GATING_EN, 191 IPI_SHUTDN, 192 IPI_COLORM, 193 IPI_COLOR_DEPTH, 194 IPI_FORMAT, 195 MAX_FIELDS, 196 }; 197 198 enum phy_type { 199 DPHY, 200 CPHY, 201 }; 202 203 enum ppi_width { 204 PPI_WIDTH_8_BITS, 205 PPI_WIDTH_16_BITS, 206 PPI_WIDTH_32_BITS, 207 }; 208 209 struct rockchip_cmd_header { 210 u8 data_type; 211 u8 delay_ms; 212 u8 payload_length; 213 }; 214 215 struct dw_mipi_dsi2_plat_data { 216 bool dsc; 217 const u32 *dsi0_grf_reg_fields; 218 const u32 *dsi1_grf_reg_fields; 219 unsigned long long dphy_max_bit_rate_per_lane; 220 unsigned long long cphy_max_symbol_rate_per_lane; 221 }; 222 223 struct mipi_dcphy { 224 /* Non-SNPS PHY */ 225 struct rockchip_phy *phy; 226 227 u16 input_div; 228 u16 feedback_div; 229 }; 230 231 /** 232 * struct mipi_dphy_configure - MIPI D-PHY configuration set 233 * 234 * This structure is used to represent the configuration state of a 235 * MIPI D-PHY phy. 236 */ 237 struct mipi_dphy_configure { 238 unsigned int clk_miss; 239 unsigned int clk_post; 240 unsigned int clk_pre; 241 unsigned int clk_prepare; 242 unsigned int clk_settle; 243 unsigned int clk_term_en; 244 unsigned int clk_trail; 245 unsigned int clk_zero; 246 unsigned int d_term_en; 247 unsigned int eot; 248 unsigned int hs_exit; 249 unsigned int hs_prepare; 250 unsigned int hs_settle; 251 unsigned int hs_skip; 252 unsigned int hs_trail; 253 unsigned int hs_zero; 254 unsigned int init; 255 unsigned int lpx; 256 unsigned int ta_get; 257 unsigned int ta_go; 258 unsigned int ta_sure; 259 unsigned int wakeup; 260 unsigned long hs_clk_rate; 261 unsigned long lp_clk_rate; 262 unsigned char lanes; 263 }; 264 265 struct dw_mipi_dsi2 { 266 struct rockchip_connector connector; 267 struct udevice *dev; 268 void *base; 269 void *grf; 270 int id; 271 struct dw_mipi_dsi2 *master; 272 struct dw_mipi_dsi2 *slave; 273 bool prepared; 274 275 bool disable_hold_mode; 276 bool auto_calc_mode; 277 bool c_option; 278 bool dsc_enable; 279 bool scrambling_en; 280 unsigned int slice_width; 281 unsigned int slice_height; 282 u32 version_major; 283 u32 version_minor; 284 struct clk sys_clk; 285 286 unsigned int lane_hs_rate; /* Kbps/Ksps per lane */ 287 u32 channel; 288 u32 lanes; 289 u32 format; 290 u32 mode_flags; 291 u64 mipi_pixel_rate; 292 struct mipi_dcphy dcphy; 293 struct drm_display_mode mode; 294 bool data_swap; 295 bool dual_channel; 296 297 struct gpio_desc te_gpio; 298 struct mipi_dsi_device *device; 299 struct mipi_dphy_configure mipi_dphy_cfg; 300 const struct dw_mipi_dsi2_plat_data *pdata; 301 struct drm_dsc_picture_parameter_set *pps; 302 }; 303 304 static inline void dsi_write(struct dw_mipi_dsi2 *dsi2, u32 reg, u32 val) 305 { 306 writel(val, dsi2->base + reg); 307 } 308 309 static inline u32 dsi_read(struct dw_mipi_dsi2 *dsi2, u32 reg) 310 { 311 return readl(dsi2->base + reg); 312 } 313 314 static inline void dsi_update_bits(struct dw_mipi_dsi2 *dsi2, 315 u32 reg, u32 mask, u32 val) 316 { 317 u32 orig, tmp; 318 319 orig = dsi_read(dsi2, reg); 320 tmp = orig & ~mask; 321 tmp |= val & mask; 322 dsi_write(dsi2, reg, tmp); 323 } 324 325 static void grf_field_write(struct dw_mipi_dsi2 *dsi2, enum grf_reg_fields index, 326 unsigned int val) 327 { 328 const u32 field = dsi2->id ? dsi2->pdata->dsi1_grf_reg_fields[index] : 329 dsi2->pdata->dsi0_grf_reg_fields[index]; 330 u16 reg; 331 u8 msb, lsb; 332 333 if (!field) 334 return; 335 336 reg = (field >> 16) & 0xffff; 337 lsb = (field >> 8) & 0xff; 338 msb = (field >> 0) & 0xff; 339 340 regmap_write(dsi2->grf, reg, GENMASK(msb, lsb) << 16 | val << lsb); 341 } 342 343 static unsigned long dw_mipi_dsi2_get_lane_rate(struct dw_mipi_dsi2 *dsi2) 344 { 345 const struct drm_display_mode *mode = &dsi2->mode; 346 u64 max_lane_rate, lane_rate; 347 unsigned int value; 348 int bpp, lanes; 349 u64 tmp; 350 351 max_lane_rate = (dsi2->c_option) ? 352 dsi2->pdata->cphy_max_symbol_rate_per_lane : 353 dsi2->pdata->dphy_max_bit_rate_per_lane; 354 355 /* 356 * optional override of the desired bandwidth 357 * High-Speed mode: Differential and terminated: 80Mbps ~ 4500 Mbps 358 */ 359 value = dev_read_u32_default(dsi2->dev, "rockchip,lane-rate", 0); 360 if (value >= 80000 && value <= 4500000) 361 return value * MSEC_PER_SEC; 362 else if (value >= 80 && value <= 4500) 363 return value * USEC_PER_SEC; 364 365 bpp = mipi_dsi_pixel_format_to_bpp(dsi2->format); 366 if (bpp < 0) 367 bpp = 24; 368 369 lanes = dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes; 370 tmp = (u64)mode->crtc_clock * 1000 * bpp; 371 do_div(tmp, lanes); 372 373 if (dsi2->c_option) 374 tmp = DIV_ROUND_CLOSEST(tmp * 100, 228); 375 376 /* set BW a little larger only in video burst mode in 377 * consideration of the protocol overhead and HS mode 378 * switching to BLLP mode, take 1 / 0.9, since Mbps must 379 * big than bandwidth of RGB 380 */ 381 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { 382 tmp *= 10; 383 do_div(tmp, 9); 384 } 385 386 if (tmp > max_lane_rate) 387 lane_rate = max_lane_rate; 388 else 389 lane_rate = tmp; 390 391 return lane_rate; 392 } 393 394 static int cri_fifos_wait_avail(struct dw_mipi_dsi2 *dsi2) 395 { 396 u32 sts, mask; 397 int ret; 398 399 mask = CRI_BUSY | CRT_FIFOS_NOT_EMPTY; 400 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 401 sts, !(sts & mask), 402 CMD_PKT_STATUS_TIMEOUT_US); 403 if (ret < 0) { 404 printf("command interface is busy: 0x%x\n", sts); 405 return ret; 406 } 407 408 return 0; 409 } 410 411 static int dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 *dsi2, 412 const struct mipi_dsi_msg *msg) 413 { 414 u8 *payload = msg->rx_buf; 415 u8 data_type; 416 u16 wc; 417 int i, j, ret, len = msg->rx_len; 418 unsigned int vrefresh = drm_mode_vrefresh(&dsi2->mode); 419 u32 val; 420 421 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 422 val, val & CRI_RD_DATA_AVAIL, 423 DIV_ROUND_UP(1000000, vrefresh)); 424 if (ret) { 425 printf("CRI has no available read data\n"); 426 return ret; 427 } 428 429 val = dsi_read(dsi2, DSI2_CRI_RX_HDR); 430 data_type = val & 0x3f; 431 432 if (mipi_dsi_packet_format_is_short(data_type)) { 433 for (i = 0; i < len && i < 2; i++) 434 payload[i] = (val >> (8 * (i + 1))) & 0xff; 435 436 return 0; 437 } 438 439 wc = (val >> 8) & 0xffff; 440 /* Receive payload */ 441 for (i = 0; i < len && i < wc; i += 4) { 442 val = dsi_read(dsi2, DSI2_CRI_RX_PLD); 443 for (j = 0; j < 4 && j + i < len && j + i < wc; j++) 444 payload[i + j] = val >> (8 * j); 445 } 446 447 return 0; 448 } 449 450 static ssize_t dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 *dsi2, 451 const struct mipi_dsi_msg *msg) 452 { 453 struct mipi_dsi_packet packet; 454 int ret; 455 int val; 456 u32 mode; 457 458 dsi_update_bits(dsi2, DSI2_DSI_VID_TX_CFG, LPDT_DISPLAY_CMD_EN, 459 msg->flags & MIPI_DSI_MSG_USE_LPM ? 460 LPDT_DISPLAY_CMD_EN : 0); 461 462 /* create a packet to the DSI protocol */ 463 ret = mipi_dsi_create_packet(&packet, msg); 464 if (ret) { 465 printf("failed to create packet: %d\n", ret); 466 return ret; 467 } 468 469 /* check cri interface is not busy */ 470 ret = cri_fifos_wait_avail(dsi2); 471 if (ret) 472 return ret; 473 474 /* Send payload */ 475 while (DIV_ROUND_UP(packet.payload_length, 4)) { 476 if (packet.payload_length < 4) { 477 /* send residu payload */ 478 val = 0; 479 memcpy(&val, packet.payload, packet.payload_length); 480 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 481 packet.payload_length = 0; 482 } else { 483 val = get_unaligned_le32(packet.payload); 484 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 485 packet.payload += 4; 486 packet.payload_length -= 4; 487 } 488 } 489 490 /* Send packet header */ 491 mode = CMD_TX_MODE(msg->flags & MIPI_DSI_MSG_USE_LPM ? 1 : 0); 492 val = get_unaligned_le32(packet.header); 493 dsi_write(dsi2, DSI2_CRI_TX_HDR, mode | val); 494 495 ret = cri_fifos_wait_avail(dsi2); 496 if (ret) 497 return ret; 498 499 if (msg->rx_len) { 500 ret = dw_mipi_dsi2_read_from_fifo(dsi2, msg); 501 if (ret < 0) 502 return ret; 503 } 504 505 if (dsi2->slave) { 506 ret = dw_mipi_dsi2_transfer(dsi2->slave, msg); 507 if (ret < 0) 508 return ret; 509 } 510 511 return msg->rx_len ? msg->rx_len : msg->tx_len; 512 } 513 514 static void dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 *dsi2) 515 { 516 u32 val, color_depth; 517 518 switch (dsi2->format) { 519 case MIPI_DSI_FMT_RGB666: 520 case MIPI_DSI_FMT_RGB666_PACKED: 521 color_depth = IPI_DEPTH_6_BITS; 522 break; 523 case MIPI_DSI_FMT_RGB565: 524 color_depth = IPI_DEPTH_5_6_5_BITS; 525 break; 526 case MIPI_DSI_FMT_RGB888: 527 default: 528 color_depth = IPI_DEPTH_8_BITS; 529 break; 530 } 531 532 val = IPI_DEPTH(color_depth) | 533 IPI_FORMAT(dsi2->dsc_enable ? IPI_FORMAT_DSC : IPI_FORMAT_RGB); 534 dsi_write(dsi2, DSI2_IPI_COLOR_MAN_CFG, val); 535 grf_field_write(dsi2, IPI_COLOR_DEPTH, color_depth); 536 537 if (dsi2->dsc_enable) 538 grf_field_write(dsi2, IPI_FORMAT, IPI_FORMAT_DSC); 539 } 540 541 static void dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 *dsi2) 542 { 543 struct drm_display_mode *mode = &dsi2->mode; 544 u32 hline, hsa, hbp, hact; 545 u64 hline_time, hsa_time, hbp_time, hact_time, tmp; 546 u64 pixel_clk, phy_hs_clk; 547 u32 vact, vsa, vfp, vbp; 548 u16 val; 549 550 if (dsi2->slave || dsi2->master) 551 val = mode->hdisplay / 2; 552 else 553 val = mode->hdisplay; 554 555 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val)); 556 557 dw_mipi_dsi2_ipi_color_coding_cfg(dsi2); 558 559 if (dsi2->auto_calc_mode) 560 return; 561 562 /* 563 * if the controller is intended to operate in data stream mode, 564 * no more steps are required. 565 */ 566 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) 567 return; 568 569 vact = mode->vdisplay; 570 vsa = mode->vsync_end - mode->vsync_start; 571 vfp = mode->vsync_start - mode->vdisplay; 572 vbp = mode->vtotal - mode->vsync_end; 573 hact = mode->hdisplay; 574 hsa = mode->hsync_end - mode->hsync_start; 575 hbp = mode->htotal - mode->hsync_end; 576 hline = mode->htotal; 577 578 pixel_clk = mode->crtc_clock * MSEC_PER_SEC; 579 580 if (dsi2->c_option) 581 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 582 else 583 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 584 585 tmp = hsa * phy_hs_clk; 586 hsa_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 587 dsi_write(dsi2, DSI2_IPI_VID_HSA_MAN_CFG, VID_HSA_TIME(hsa_time)); 588 589 tmp = hbp * phy_hs_clk; 590 hbp_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 591 dsi_write(dsi2, DSI2_IPI_VID_HBP_MAN_CFG, VID_HBP_TIME(hbp_time)); 592 593 tmp = hact * phy_hs_clk; 594 hact_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 595 dsi_write(dsi2, DSI2_IPI_VID_HACT_MAN_CFG, VID_HACT_TIME(hact_time)); 596 597 tmp = hline * phy_hs_clk; 598 hline_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 599 dsi_write(dsi2, DSI2_IPI_VID_HLINE_MAN_CFG, VID_HLINE_TIME(hline_time)); 600 601 dsi_write(dsi2, DSI2_IPI_VID_VSA_MAN_CFG, VID_VSA_LINES(vsa)); 602 dsi_write(dsi2, DSI2_IPI_VID_VBP_MAN_CFG, VID_VBP_LINES(vbp)); 603 dsi_write(dsi2, DSI2_IPI_VID_VACT_MAN_CFG, VID_VACT_LINES(vact)); 604 dsi_write(dsi2, DSI2_IPI_VID_VFP_MAN_CFG, VID_VFP_LINES(vfp)); 605 } 606 607 static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2) 608 { 609 u32 val = 0, mode; 610 int ret; 611 612 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) 613 val |= BLK_HFP_HS_EN; 614 615 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) 616 val |= BLK_HBP_HS_EN; 617 618 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HSA) 619 val |= BLK_HSA_HS_EN; 620 621 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 622 val |= VID_MODE_TYPE_BURST; 623 else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 624 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 625 else 626 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 627 628 dsi_write(dsi2, DSI2_DSI_VID_TX_CFG, val); 629 630 dsi_write(dsi2, DSI2_MODE_CTRL, VIDEO_MODE); 631 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 632 mode, mode & VIDEO_MODE, 633 MODE_STATUS_TIMEOUT_US); 634 if (ret < 0) 635 printf("failed to enter video mode\n"); 636 } 637 638 static void dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 *dsi2) 639 { 640 u32 mode; 641 int ret; 642 643 dsi_write(dsi2, DSI2_MODE_CTRL, DATA_STREAM_MODE); 644 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 645 mode, mode & DATA_STREAM_MODE, 646 MODE_STATUS_TIMEOUT_US); 647 if (ret < 0) 648 printf("failed to enter data stream mode\n"); 649 } 650 651 static void dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 *dsi2) 652 { 653 u32 mode; 654 int ret; 655 656 dsi_write(dsi2, DSI2_MODE_CTRL, COMMAND_MODE); 657 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 658 mode, mode & COMMAND_MODE, 659 MODE_STATUS_TIMEOUT_US); 660 if (ret < 0) 661 printf("failed to enter cmd mode\n"); 662 } 663 664 static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2) 665 { 666 u32 mode; 667 int ret; 668 669 dw_mipi_dsi2_ipi_set(dsi2); 670 671 if (dsi2->auto_calc_mode) { 672 dsi_write(dsi2, DSI2_MODE_CTRL, AUTOCALC_MODE); 673 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 674 mode, mode == IDLE_MODE, 675 MODE_STATUS_TIMEOUT_US); 676 if (ret < 0) 677 printf("auto calculation training failed\n"); 678 } 679 680 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO) 681 dw_mipi_dsi2_set_vid_mode(dsi2); 682 else 683 dw_mipi_dsi2_set_data_stream_mode(dsi2); 684 685 if (dsi2->slave) 686 dw_mipi_dsi2_enable(dsi2->slave); 687 } 688 689 static void dw_mipi_dsi2_disable(struct dw_mipi_dsi2 *dsi2) 690 { 691 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, 0); 692 dw_mipi_dsi2_set_cmd_mode(dsi2); 693 694 if (dsi2->slave) 695 dw_mipi_dsi2_disable(dsi2->slave); 696 } 697 698 static void dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 *dsi2) 699 { 700 if (!dsi2->prepared) 701 return; 702 703 dsi_write(dsi2, DSI2_PWR_UP, RESET); 704 705 if (dsi2->dcphy.phy) 706 rockchip_phy_power_off(dsi2->dcphy.phy); 707 708 dsi2->prepared = false; 709 710 if (dsi2->slave) 711 dw_mipi_dsi2_post_disable(dsi2->slave); 712 } 713 714 static int dw_mipi_dsi2_connector_pre_init(struct rockchip_connector *conn, 715 struct display_state *state) 716 { 717 struct connector_state *conn_state = &state->conn_state; 718 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 719 struct mipi_dsi_host *host = dev_get_platdata(dsi2->dev); 720 struct mipi_dsi_device *device; 721 char name[20]; 722 723 conn_state->type = DRM_MODE_CONNECTOR_DSI; 724 725 if (conn->bridge) { 726 device = dev_get_platdata(conn->bridge->dev); 727 if (!device) 728 return -ENODEV; 729 730 device->host = host; 731 sprintf(name, "%s.%d", host->dev->name, device->channel); 732 device_set_name(conn->bridge->dev, name); 733 mipi_dsi_attach(device); 734 } 735 736 return 0; 737 } 738 739 static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2) 740 { 741 struct udevice *dev = dsi2->device->dev; 742 struct rockchip_cmd_header *header; 743 struct drm_dsc_picture_parameter_set *pps = NULL; 744 u8 *dsc_packed_pps; 745 const void *data; 746 int len; 747 748 dsi2->c_option = dev_read_bool(dev, "phy-c-option"); 749 dsi2->scrambling_en = dev_read_bool(dev, "scrambling-enable"); 750 dsi2->dsc_enable = dsi2->pdata->dsc ? 751 dev_read_bool(dev, "compressed-data") : false; 752 753 if (dsi2->slave) { 754 dsi2->slave->c_option = dsi2->c_option; 755 dsi2->slave->scrambling_en = dsi2->scrambling_en; 756 dsi2->slave->dsc_enable = dsi2->dsc_enable; 757 } 758 759 if (!dsi2->dsc_enable) 760 return 0; 761 762 dsi2->slice_width = dev_read_u32_default(dev, "slice-width", 0); 763 dsi2->slice_height = dev_read_u32_default(dev, "slice-height", 0); 764 dsi2->version_major = dev_read_u32_default(dev, "version-major", 0); 765 dsi2->version_minor = dev_read_u32_default(dev, "version-minor", 0); 766 767 data = dev_read_prop(dev, "panel-init-sequence", &len); 768 if (!data) 769 return -EINVAL; 770 771 while (len > sizeof(*header)) { 772 header = (struct rockchip_cmd_header *)data; 773 data += sizeof(*header); 774 len -= sizeof(*header); 775 776 if (header->payload_length > len) 777 return -EINVAL; 778 779 if (header->data_type == MIPI_DSI_PICTURE_PARAMETER_SET) { 780 dsc_packed_pps = calloc(1, header->payload_length); 781 if (!dsc_packed_pps) 782 return -ENOMEM; 783 784 memcpy(dsc_packed_pps, data, header->payload_length); 785 pps = (struct drm_dsc_picture_parameter_set *)dsc_packed_pps; 786 break; 787 } 788 789 data += header->payload_length; 790 len -= header->payload_length; 791 } 792 793 if (!pps) { 794 printf("not found dsc pps definition\n"); 795 return -EINVAL; 796 } 797 798 dsi2->pps = pps; 799 800 if (dsi2->slave) { 801 u16 pic_width = be16_to_cpu(pps->pic_width) / 2; 802 803 dsi2->pps->pic_width = cpu_to_be16(pic_width); 804 printf("dsc pic_width change from %d to %d\n", pic_width * 2, pic_width); 805 } 806 807 return 0; 808 } 809 810 static int dw_mipi_dsi2_connector_init(struct rockchip_connector *conn, struct display_state *state) 811 { 812 struct connector_state *conn_state = &state->conn_state; 813 struct crtc_state *cstate = &state->crtc_state; 814 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 815 struct rockchip_phy *phy = NULL; 816 struct udevice *phy_dev; 817 struct udevice *dev; 818 int ret; 819 820 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dsi2->id); 821 dsi2->dcphy.phy = conn->phy; 822 823 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 824 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709; 825 conn_state->color_range = DRM_COLOR_YCBCR_FULL_RANGE; 826 conn_state->output_if |= 827 dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0; 828 829 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) { 830 conn_state->output_flags |= ROCKCHIP_OUTPUT_MIPI_DS_MODE; 831 conn_state->hold_mode = dsi2->disable_hold_mode ? false : true; 832 } 833 834 if (dsi2->dual_channel) { 835 ret = uclass_get_device_by_name(UCLASS_DISPLAY, 836 "dsi@fde30000", 837 &dev); 838 if (ret) 839 return ret; 840 841 dsi2->slave = dev_get_priv(dev); 842 if (!dsi2->slave) 843 return -ENODEV; 844 845 dsi2->slave->master = dsi2; 846 dsi2->lanes /= 2; 847 848 dsi2->slave->auto_calc_mode = dsi2->auto_calc_mode; 849 dsi2->slave->lanes = dsi2->lanes; 850 dsi2->slave->format = dsi2->format; 851 dsi2->slave->mode_flags = dsi2->mode_flags; 852 dsi2->slave->channel = dsi2->channel; 853 conn_state->output_flags |= 854 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; 855 if (dsi2->data_swap) 856 conn_state->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP; 857 858 conn_state->output_if |= VOP_OUTPUT_IF_MIPI1; 859 860 ret = uclass_get_device_by_phandle(UCLASS_PHY, dev, 861 "phys", &phy_dev); 862 if (ret) 863 return -ENODEV; 864 865 phy = (struct rockchip_phy *)dev_get_driver_data(phy_dev); 866 if (!phy) 867 return -ENODEV; 868 869 dsi2->slave->dcphy.phy = phy; 870 if (phy->funcs && phy->funcs->init) 871 return phy->funcs->init(phy); 872 } 873 874 dw_mipi_dsi2_get_dsc_params_from_sink(dsi2); 875 876 if (dm_gpio_is_valid(&dsi2->te_gpio)) { 877 cstate->soft_te = true; 878 conn_state->te_gpio = &dsi2->te_gpio; 879 } 880 881 if (dsi2->dsc_enable) { 882 cstate->dsc_enable = 1; 883 cstate->dsc_sink_cap.version_major = dsi2->version_major; 884 cstate->dsc_sink_cap.version_minor = dsi2->version_minor; 885 cstate->dsc_sink_cap.slice_width = dsi2->slice_width; 886 cstate->dsc_sink_cap.slice_height = dsi2->slice_height; 887 /* only can support rgb888 panel now */ 888 cstate->dsc_sink_cap.target_bits_per_pixel_x16 = 8 << 4; 889 cstate->dsc_sink_cap.native_420 = 0; 890 memcpy(&cstate->pps, dsi2->pps, sizeof(struct drm_dsc_picture_parameter_set)); 891 } 892 893 return 0; 894 } 895 896 /* 897 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived 898 * from the valid ranges specified in Section 6.9, Table 14, Page 41 899 * of the D-PHY specification (v2.1). 900 */ 901 int mipi_dphy_get_default_config(unsigned long long hs_clk_rate, 902 struct mipi_dphy_configure *cfg) 903 { 904 unsigned long long ui; 905 906 if (!cfg) 907 return -EINVAL; 908 909 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); 910 do_div(ui, hs_clk_rate); 911 912 cfg->clk_miss = 0; 913 cfg->clk_post = 60000 + 52 * ui; 914 cfg->clk_pre = 8000; 915 cfg->clk_prepare = 38000; 916 cfg->clk_settle = 95000; 917 cfg->clk_term_en = 0; 918 cfg->clk_trail = 60000; 919 cfg->clk_zero = 262000; 920 cfg->d_term_en = 0; 921 cfg->eot = 0; 922 cfg->hs_exit = 100000; 923 cfg->hs_prepare = 40000 + 4 * ui; 924 cfg->hs_zero = 105000 + 6 * ui; 925 cfg->hs_settle = 85000 + 6 * ui; 926 cfg->hs_skip = 40000; 927 928 /* 929 * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40) 930 * contains this formula as: 931 * 932 * T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui) 933 * 934 * where n = 1 for forward-direction HS mode and n = 4 for reverse- 935 * direction HS mode. There's only one setting and this function does 936 * not parameterize on anything other that ui, so this code will 937 * assumes that reverse-direction HS mode is supported and uses n = 4. 938 */ 939 cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui); 940 941 cfg->init = 100; 942 cfg->lpx = 50000; 943 cfg->ta_get = 5 * cfg->lpx; 944 cfg->ta_go = 4 * cfg->lpx; 945 cfg->ta_sure = cfg->lpx; 946 cfg->wakeup = 1000; 947 948 return 0; 949 } 950 951 static void dw_mipi_dsi2_set_hs_clk(struct dw_mipi_dsi2 *dsi2, unsigned long rate) 952 { 953 mipi_dphy_get_default_config(rate, &dsi2->mipi_dphy_cfg); 954 955 if (!dsi2->c_option) 956 rockchip_phy_set_mode(dsi2->dcphy.phy, PHY_MODE_MIPI_DPHY); 957 958 rate = rockchip_phy_set_pll(dsi2->dcphy.phy, rate); 959 dsi2->lane_hs_rate = DIV_ROUND_CLOSEST(rate, MSEC_PER_SEC); 960 } 961 962 static void dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 *dsi2) 963 { 964 dsi_write(dsi2, DSI2_SOFT_RESET, 0X0); 965 udelay(100); 966 dsi_write(dsi2, DSI2_SOFT_RESET, SYS_RSTN | PHY_RSTN | IPI_RSTN); 967 } 968 969 static void 970 dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 *dsi2, u32 mode) 971 { 972 /* 973 * select controller work in Manual mode 974 * Manual: MANUAL_MODE_EN 975 * Automatic: 0 976 */ 977 dsi_write(dsi2, MANUAL_MODE_CFG, mode); 978 } 979 980 static void dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 *dsi2) 981 { 982 u32 val = 0; 983 984 /* PPI width is fixed to 16 bits in DCPHY */ 985 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes); 986 val |= PHY_TYPE(dsi2->c_option ? CPHY : DPHY); 987 dsi_write(dsi2, DSI2_PHY_MODE_CFG, val); 988 } 989 990 static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2) 991 { 992 u32 sys_clk = clk_get_rate(&dsi2->sys_clk) / USEC_PER_SEC; 993 u32 esc_clk_div; 994 u32 val = 0; 995 996 if (dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 997 val |= NON_CONTINUOUS_CLK; 998 999 /* The Escape clock ranges from 1MHz to 20MHz. */ 1000 esc_clk_div = DIV_ROUND_UP(sys_clk, 20 * 2); 1001 val |= PHY_LPTX_CLK_DIV(esc_clk_div); 1002 1003 dsi_write(dsi2, DSI2_PHY_CLK_CFG, val); 1004 } 1005 1006 static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2) 1007 { 1008 u64 ipi_clk, phy_hsclk, tmp; 1009 u32 sys_clk = clk_get_rate(&dsi2->sys_clk); 1010 1011 /* 1012 * in DPHY mode, the phy_hstx_clk is exactly 1/16 the Lane high-speed 1013 * data rate; In CPHY mode, the phy_hstx_clk is exactly 1/7 the trio 1014 * high speed symbol rate. 1015 */ 1016 if (dsi2->c_option) 1017 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 1018 1019 else 1020 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 1021 1022 /* IPI_RATIO_MAN_CFG = PHY_HSTX_CLK / IPI_CLK */ 1023 ipi_clk = dsi2->mipi_pixel_rate; 1024 1025 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, ipi_clk); 1026 dsi_write(dsi2, DSI2_PHY_IPI_RATIO_MAN_CFG, PHY_IPI_RATIO(tmp)); 1027 1028 /* SYS_RATIO_MAN_CFG = MIPI_DCPHY_HSCLK_Freq / SYS_CLK */ 1029 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, sys_clk); 1030 dsi_write(dsi2, DSI2_PHY_SYS_RATIO_MAN_CFG, PHY_SYS_RATIO(tmp)); 1031 } 1032 1033 static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2) 1034 { 1035 struct mipi_dphy_configure *cfg = &dsi2->mipi_dphy_cfg; 1036 unsigned long long tmp, ui; 1037 unsigned long long hstx_clk; 1038 1039 hstx_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 1040 1041 ui = ALIGN(PSEC_PER_SEC, hstx_clk); 1042 do_div(ui, hstx_clk); 1043 1044 /* PHY_LP2HS_TIME = (TLPX + THS-PREPARE + THS-ZERO) / Tphy_hstx_clk */ 1045 tmp = cfg->lpx + cfg->hs_prepare + cfg->hs_zero; 1046 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 1047 dsi_write(dsi2, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(tmp)); 1048 1049 /* PHY_HS2LP_TIME = (THS-TRAIL + THS-EXIT) / Tphy_hstx_clk */ 1050 tmp = cfg->hs_trail + cfg->hs_exit; 1051 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 1052 dsi_write(dsi2, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(tmp)); 1053 } 1054 1055 static void dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 *dsi2) 1056 { 1057 dw_mipi_dsi2_phy_mode_cfg(dsi2); 1058 dw_mipi_dsi2_phy_clk_mode_cfg(dsi2); 1059 1060 if (dsi2->auto_calc_mode) 1061 return; 1062 1063 dw_mipi_dsi2_phy_ratio_cfg(dsi2); 1064 dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(dsi2); 1065 1066 /* phy configuration 8 - 10 */ 1067 } 1068 1069 static void dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 *dsi2) 1070 { 1071 u32 val; 1072 1073 val = BTA_EN | EOTP_TX_EN; 1074 1075 if (dsi2->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 1076 val &= ~EOTP_TX_EN; 1077 1078 dsi_write(dsi2, DSI2_DSI_GENERAL_CFG, val); 1079 dsi_write(dsi2, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel)); 1080 1081 if (dsi2->scrambling_en) 1082 dsi_write(dsi2, DSI2_DSI_SCRAMBLING_CFG, SCRAMBLING_EN); 1083 } 1084 1085 static void dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 *dsi2, bool enable) 1086 { 1087 if (enable) { 1088 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x1); 1089 dsi_write(dsi2, DSI2_INT_MASK_TO, 0xf); 1090 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x1); 1091 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x1); 1092 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x1); 1093 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x1); 1094 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x1); 1095 } else { 1096 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x0); 1097 dsi_write(dsi2, DSI2_INT_MASK_TO, 0x0); 1098 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x0); 1099 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x0); 1100 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x0); 1101 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x0); 1102 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x0); 1103 }; 1104 } 1105 1106 static void mipi_dcphy_power_on(struct dw_mipi_dsi2 *dsi2) 1107 { 1108 if (!dsi2->dcphy.phy) 1109 return; 1110 1111 rockchip_phy_power_on(dsi2->dcphy.phy); 1112 } 1113 1114 static void dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 *dsi2) 1115 { 1116 if (dsi2->prepared) 1117 return; 1118 1119 dw_mipi_dsi2_host_softrst(dsi2); 1120 dsi_write(dsi2, DSI2_PWR_UP, RESET); 1121 1122 dw_mipi_dsi2_work_mode(dsi2, dsi2->auto_calc_mode ? 0 : MANUAL_MODE_EN); 1123 dw_mipi_dsi2_phy_init(dsi2); 1124 dw_mipi_dsi2_tx_option_set(dsi2); 1125 dw_mipi_dsi2_irq_enable(dsi2, 0); 1126 mipi_dcphy_power_on(dsi2); 1127 dsi_write(dsi2, DSI2_PWR_UP, POWER_UP); 1128 dw_mipi_dsi2_set_cmd_mode(dsi2); 1129 1130 dsi2->prepared = true; 1131 1132 if (dsi2->slave) 1133 dw_mipi_dsi2_pre_enable(dsi2->slave); 1134 } 1135 1136 static void dw_mipi_dsi2_get_mipi_pixel_clk(struct dw_mipi_dsi2 *dsi2, 1137 struct crtc_state *s) 1138 { 1139 struct drm_display_mode *mode = &dsi2->mode; 1140 u8 k = dsi2->slave ? 2 : 1; 1141 1142 /* 1.When MIPI works in uncompressed mode: 1143 * (Video Timing Pixel Rate)/(4)=(MIPI Pixel ClockxK)=(dclk_out×K)=dclk_core 1144 * 2.When MIPI works in compressed mode: 1145 * MIPI Pixel Clock = cds_clk / 2 1146 * MIPI is configured as double channel display mode, K=2, otherwise K=1. 1147 */ 1148 if (dsi2->dsc_enable) { 1149 dsi2->mipi_pixel_rate = s->dsc_cds_clk_rate / 2; 1150 if (dsi2->slave) 1151 dsi2->slave->mipi_pixel_rate = dsi2->mipi_pixel_rate; 1152 1153 return; 1154 } 1155 1156 dsi2->mipi_pixel_rate = (mode->crtc_clock * MSEC_PER_SEC) / (4 * k); 1157 if (dsi2->slave) 1158 dsi2->slave->mipi_pixel_rate = dsi2->mipi_pixel_rate; 1159 } 1160 1161 static int dw_mipi_dsi2_connector_prepare(struct rockchip_connector *conn, 1162 struct display_state *state) 1163 { 1164 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1165 struct connector_state *conn_state = &state->conn_state; 1166 struct crtc_state *cstate = &state->crtc_state; 1167 unsigned long lane_rate; 1168 1169 memcpy(&dsi2->mode, &conn_state->mode, sizeof(struct drm_display_mode)); 1170 if (dsi2->slave) 1171 memcpy(&dsi2->slave->mode, &dsi2->mode, 1172 sizeof(struct drm_display_mode)); 1173 1174 dw_mipi_dsi2_get_mipi_pixel_clk(dsi2, cstate); 1175 1176 lane_rate = dw_mipi_dsi2_get_lane_rate(dsi2); 1177 if (dsi2->dcphy.phy) 1178 dw_mipi_dsi2_set_hs_clk(dsi2, lane_rate); 1179 1180 if (dsi2->slave && dsi2->slave->dcphy.phy) 1181 dw_mipi_dsi2_set_hs_clk(dsi2->slave, lane_rate); 1182 1183 printf("final DSI-Link bandwidth: %u %s x %d\n", 1184 dsi2->lane_hs_rate, dsi2->c_option ? "Ksps" : "Kbps", 1185 dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes); 1186 1187 dw_mipi_dsi2_pre_enable(dsi2); 1188 1189 return 0; 1190 } 1191 1192 static void dw_mipi_dsi2_connector_unprepare(struct rockchip_connector *conn, 1193 struct display_state *state) 1194 { 1195 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1196 1197 dw_mipi_dsi2_post_disable(dsi2); 1198 } 1199 1200 static int dw_mipi_dsi2_connector_enable(struct rockchip_connector *conn, 1201 struct display_state *state) 1202 { 1203 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1204 1205 dw_mipi_dsi2_enable(dsi2); 1206 1207 return 0; 1208 } 1209 1210 static int dw_mipi_dsi2_connector_disable(struct rockchip_connector *conn, 1211 struct display_state *state) 1212 { 1213 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1214 1215 dw_mipi_dsi2_disable(dsi2); 1216 1217 return 0; 1218 } 1219 1220 static int dw_mipi_dsi2_connector_mode_valid(struct rockchip_connector *conn, 1221 struct display_state *state) 1222 { 1223 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1224 struct connector_state *conn_state = &state->conn_state; 1225 u8 min_pixels = dsi2->slave ? 8 : 4; 1226 struct videomode vm; 1227 1228 drm_display_mode_to_videomode(&conn_state->mode, &vm); 1229 1230 /* 1231 * the minimum region size (HSA,HBP,HACT,HFP) is 4 pixels 1232 * which is the ip known issues and limitations. 1233 */ 1234 if (!(vm.hsync_len < min_pixels || vm.hback_porch < min_pixels || 1235 vm.hfront_porch < min_pixels || vm.hactive < min_pixels)) 1236 return MODE_OK; 1237 1238 if (vm.hsync_len < min_pixels) 1239 vm.hsync_len = min_pixels; 1240 1241 if (vm.hback_porch < min_pixels) 1242 vm.hback_porch = min_pixels; 1243 1244 if (vm.hfront_porch < min_pixels) 1245 vm.hfront_porch = min_pixels; 1246 1247 if (vm.hactive < min_pixels) 1248 vm.hactive = min_pixels; 1249 1250 memset(&conn_state->mode, 0, sizeof(struct drm_display_mode)); 1251 drm_display_mode_from_videomode(&vm, &conn_state->mode); 1252 conn_state->mode.vrefresh = drm_mode_vrefresh(&conn_state->mode); 1253 1254 return MODE_OK; 1255 } 1256 1257 static const struct rockchip_connector_funcs dw_mipi_dsi2_connector_funcs = { 1258 .pre_init = dw_mipi_dsi2_connector_pre_init, 1259 .init = dw_mipi_dsi2_connector_init, 1260 .prepare = dw_mipi_dsi2_connector_prepare, 1261 .unprepare = dw_mipi_dsi2_connector_unprepare, 1262 .enable = dw_mipi_dsi2_connector_enable, 1263 .disable = dw_mipi_dsi2_connector_disable, 1264 .mode_valid = dw_mipi_dsi2_connector_mode_valid, 1265 }; 1266 1267 static int dw_mipi_dsi2_probe(struct udevice *dev) 1268 { 1269 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(dev); 1270 const struct dw_mipi_dsi2_plat_data *pdata = 1271 (const struct dw_mipi_dsi2_plat_data *)dev_get_driver_data(dev); 1272 struct udevice *syscon; 1273 int id, ret; 1274 1275 dsi2->base = dev_read_addr_ptr(dev); 1276 1277 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1278 &syscon); 1279 if (!ret) { 1280 dsi2->grf = syscon_get_regmap(syscon); 1281 if (!dsi2->grf) 1282 return -ENODEV; 1283 } 1284 1285 id = of_alias_get_id(ofnode_to_np(dev->node), "dsi"); 1286 if (id < 0) 1287 id = 0; 1288 1289 ret = gpio_request_by_name(dev, "te-gpios", 0, 1290 &dsi2->te_gpio, GPIOD_IS_IN); 1291 if (ret && ret != -ENOENT) { 1292 printf("%s: Cannot get TE GPIO: %d\n", __func__, ret); 1293 return ret; 1294 } 1295 1296 ret = clk_get_by_name(dev, "sys_clk", &dsi2->sys_clk); 1297 if (ret < 0) { 1298 printf("failed to get sys_clk: %d\n", ret); 1299 return ret; 1300 } 1301 1302 dsi2->dev = dev; 1303 dsi2->pdata = pdata; 1304 dsi2->id = id; 1305 dsi2->dual_channel = dev_read_bool(dsi2->dev, "rockchip,dual-channel"); 1306 dsi2->data_swap = dev_read_bool(dsi2->dev, "rockchip,data-swap"); 1307 dsi2->auto_calc_mode = dev_read_bool(dsi2->dev, "auto-calculation-mode"); 1308 dsi2->disable_hold_mode = dev_read_bool(dsi2->dev, "disable-hold-mode"); 1309 1310 rockchip_connector_bind(&dsi2->connector, dev, id, &dw_mipi_dsi2_connector_funcs, NULL, 1311 DRM_MODE_CONNECTOR_DSI); 1312 1313 return 0; 1314 } 1315 1316 static const u32 rk3576_dsi_grf_reg_fields[MAX_FIELDS] = { 1317 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0028, 1, 1), 1318 [GATING_EN] = GRF_REG_FIELD(0x0028, 0, 0), 1319 [IPI_SHUTDN] = GRF_REG_FIELD(0x0028, 3, 3), 1320 [IPI_COLORM] = GRF_REG_FIELD(0x0028, 2, 2), 1321 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0028, 8, 11), 1322 [IPI_FORMAT] = GRF_REG_FIELD(0x0028, 4, 7), 1323 }; 1324 1325 static const u32 rk3588_dsi0_grf_reg_fields[MAX_FIELDS] = { 1326 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0000, 11, 11), 1327 [GATING_EN] = GRF_REG_FIELD(0x0000, 10, 10), 1328 [IPI_SHUTDN] = GRF_REG_FIELD(0x0000, 9, 9), 1329 [IPI_COLORM] = GRF_REG_FIELD(0x0000, 8, 8), 1330 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0000, 4, 7), 1331 [IPI_FORMAT] = GRF_REG_FIELD(0x0000, 0, 3), 1332 }; 1333 1334 static const u32 rk3588_dsi1_grf_reg_fields[MAX_FIELDS] = { 1335 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0004, 11, 11), 1336 [GATING_EN] = GRF_REG_FIELD(0x0004, 10, 10), 1337 [IPI_SHUTDN] = GRF_REG_FIELD(0x0004, 9, 9), 1338 [IPI_COLORM] = GRF_REG_FIELD(0x0004, 8, 8), 1339 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0004, 4, 7), 1340 [IPI_FORMAT] = GRF_REG_FIELD(0x0004, 0, 3), 1341 }; 1342 1343 static const struct dw_mipi_dsi2_plat_data rk3576_mipi_dsi2_plat_data = { 1344 .dsc = false, 1345 .dsi0_grf_reg_fields = rk3576_dsi_grf_reg_fields, 1346 .dphy_max_bit_rate_per_lane = 2500000000ULL, 1347 .cphy_max_symbol_rate_per_lane = 1700000000ULL, 1348 }; 1349 1350 static const struct dw_mipi_dsi2_plat_data rk3588_mipi_dsi2_plat_data = { 1351 .dsc = true, 1352 .dsi0_grf_reg_fields = rk3588_dsi0_grf_reg_fields, 1353 .dsi1_grf_reg_fields = rk3588_dsi1_grf_reg_fields, 1354 .dphy_max_bit_rate_per_lane = 4500000000ULL, 1355 .cphy_max_symbol_rate_per_lane = 2000000000ULL, 1356 }; 1357 1358 static const struct udevice_id dw_mipi_dsi2_ids[] = { 1359 { 1360 .compatible = "rockchip,rk3576-mipi-dsi2", 1361 .data = (ulong)&rk3576_mipi_dsi2_plat_data, 1362 }, { 1363 .compatible = "rockchip,rk3588-mipi-dsi2", 1364 .data = (ulong)&rk3588_mipi_dsi2_plat_data, 1365 }, 1366 {} 1367 }; 1368 1369 static ssize_t dw_mipi_dsi2_host_transfer(struct mipi_dsi_host *host, 1370 const struct mipi_dsi_msg *msg) 1371 { 1372 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1373 1374 return dw_mipi_dsi2_transfer(dsi2, msg); 1375 } 1376 1377 static int dw_mipi_dsi2_host_attach(struct mipi_dsi_host *host, 1378 struct mipi_dsi_device *device) 1379 { 1380 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1381 1382 if (device->lanes < 1 || device->lanes > 8) 1383 return -EINVAL; 1384 1385 dsi2->lanes = device->lanes; 1386 dsi2->channel = device->channel; 1387 dsi2->format = device->format; 1388 dsi2->mode_flags = device->mode_flags; 1389 dsi2->device = device; 1390 1391 return 0; 1392 } 1393 1394 static const struct mipi_dsi_host_ops dw_mipi_dsi2_host_ops = { 1395 .attach = dw_mipi_dsi2_host_attach, 1396 .transfer = dw_mipi_dsi2_host_transfer, 1397 }; 1398 1399 static int dw_mipi_dsi2_bind(struct udevice *dev) 1400 { 1401 struct mipi_dsi_host *host = dev_get_platdata(dev); 1402 1403 host->dev = dev; 1404 host->ops = &dw_mipi_dsi2_host_ops; 1405 1406 return dm_scan_fdt_dev(dev); 1407 } 1408 1409 static int dw_mipi_dsi2_child_post_bind(struct udevice *dev) 1410 { 1411 struct mipi_dsi_host *host = dev_get_platdata(dev->parent); 1412 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1413 char name[20]; 1414 1415 sprintf(name, "%s.%d", host->dev->name, device->channel); 1416 device_set_name(dev, name); 1417 1418 device->dev = dev; 1419 device->host = host; 1420 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4); 1421 device->format = dev_read_u32_default(dev, "dsi,format", 1422 MIPI_DSI_FMT_RGB888); 1423 device->mode_flags = dev_read_u32_default(dev, "dsi,flags", 1424 MIPI_DSI_MODE_VIDEO | 1425 MIPI_DSI_MODE_VIDEO_BURST | 1426 MIPI_DSI_MODE_VIDEO_HBP | 1427 MIPI_DSI_MODE_LPM | 1428 MIPI_DSI_MODE_EOT_PACKET); 1429 device->channel = dev_read_u32_default(dev, "reg", 0); 1430 1431 return 0; 1432 } 1433 1434 static int dw_mipi_dsi2_child_pre_probe(struct udevice *dev) 1435 { 1436 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1437 int ret; 1438 1439 ret = mipi_dsi_attach(device); 1440 if (ret) { 1441 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret); 1442 return ret; 1443 } 1444 1445 return 0; 1446 } 1447 1448 U_BOOT_DRIVER(dw_mipi_dsi2) = { 1449 .name = "dw_mipi_dsi2", 1450 .id = UCLASS_DISPLAY, 1451 .of_match = dw_mipi_dsi2_ids, 1452 .probe = dw_mipi_dsi2_probe, 1453 .bind = dw_mipi_dsi2_bind, 1454 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi2), 1455 .per_child_platdata_auto_alloc_size = sizeof(struct mipi_dsi_device), 1456 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_host), 1457 .child_post_bind = dw_mipi_dsi2_child_post_bind, 1458 .child_pre_probe = dw_mipi_dsi2_child_pre_probe, 1459 }; 1460