1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Author: Guochun Huang <hero.huang@rock-chips.com> 7 */ 8 9 #include <drm/drm_mipi_dsi.h> 10 11 #include <config.h> 12 #include <common.h> 13 #include <errno.h> 14 #include <asm/unaligned.h> 15 #include <asm/io.h> 16 #include <asm/hardware.h> 17 #include <dm/device.h> 18 #include <dm/read.h> 19 #include <dm/of_access.h> 20 #include <regmap.h> 21 #include <syscon.h> 22 #include <asm/arch-rockchip/clock.h> 23 #include <linux/iopoll.h> 24 25 #include "rockchip_display.h" 26 #include "rockchip_crtc.h" 27 #include "rockchip_connector.h" 28 #include "rockchip_panel.h" 29 #include "rockchip_phy.h" 30 31 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) 32 33 #define DSI2_PWR_UP 0x000c 34 #define RESET 0 35 #define POWER_UP BIT(0) 36 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 37 #define DSI2_SOFT_RESET 0x0010 38 #define SYS_RSTN BIT(2) 39 #define PHY_RSTN BIT(1) 40 #define IPI_RSTN BIT(0) 41 #define INT_ST_MAIN 0x0014 42 #define DSI2_MODE_CTRL 0x0018 43 #define DSI2_MODE_STATUS 0x001c 44 #define DSI2_CORE_STATUS 0x0020 45 #define PRI_RD_DATA_AVAIL BIT(26) 46 #define PRI_FIFOS_NOT_EMPTY BIT(25) 47 #define PRI_BUSY BIT(24) 48 #define CRI_RD_DATA_AVAIL BIT(18) 49 #define CRT_FIFOS_NOT_EMPTY BIT(17) 50 #define CRI_BUSY BIT(16) 51 #define IPI_FIFOS_NOT_EMPTY BIT(9) 52 #define IPI_BUSY BIT(8) 53 #define CORE_FIFOS_NOT_EMPTY BIT(1) 54 #define CORE_BUSY BIT(0) 55 #define MANUAL_MODE_CFG 0x0024 56 #define MANUAL_MODE_EN BIT(0) 57 #define DSI2_TIMEOUT_HSTX_CFG 0x0048 58 #define TO_HSTX(x) UPDATE(x, 15, 0) 59 #define DSI2_TIMEOUT_HSTXRDY_CFG 0x004c 60 #define TO_HSTXRDY(x) UPDATE(x, 15, 0) 61 #define DSI2_TIMEOUT_LPRX_CFG 0x0050 62 #define TO_LPRXRDY(x) UPDATE(x, 15, 0) 63 #define DSI2_TIMEOUT_LPTXRDY_CFG 0x0054 64 #define TO_LPTXRDY(x) UPDATE(x, 15, 0) 65 #define DSI2_TIMEOUT_LPTXTRIG_CFG 0x0058 66 #define TO_LPTXTRIG(x) UPDATE(x, 15, 0) 67 #define DSI2_TIMEOUT_LPTXULPS_CFG 0x005c 68 #define TO_LPTXULPS(x) UPDATE(x, 15, 0) 69 #define DSI2_TIMEOUT_BTA_CFG 0x60 70 #define TO_BTA(x) UPDATE(x, 15, 0) 71 72 #define DSI2_PHY_MODE_CFG 0x0100 73 #define PPI_WIDTH(x) UPDATE(x, 9, 8) 74 #define PHY_LANES(x) UPDATE(x - 1, 5, 4) 75 #define PHY_TYPE(x) UPDATE(x, 0, 0) 76 #define DSI2_PHY_CLK_CFG 0X0104 77 #define PHY_LPTX_CLK_DIV(x) UPDATE(x, 12, 8) 78 #define NON_CONTINUOUS_CLK BIT(0) 79 #define DSI2_PHY_LP2HS_MAN_CFG 0x010c 80 #define PHY_LP2HS_TIME(x) UPDATE(x, 28, 0) 81 #define DSI2_PHY_HS2LP_MAN_CFG 0x0114 82 #define PHY_HS2LP_TIME(x) UPDATE(x, 28, 0) 83 #define DSI2_PHY_MAX_RD_T_MAN_CFG 0x011c 84 #define PHY_MAX_RD_TIME(x) UPDATE(x, 26, 0) 85 #define DSI2_PHY_ESC_CMD_T_MAN_CFG 0x0124 86 #define PHY_ESC_CMD_TIME(x) UPDATE(x, 28, 0) 87 #define DSI2_PHY_ESC_BYTE_T_MAN_CFG 0x012c 88 #define PHY_ESC_BYTE_TIME(x) UPDATE(x, 28, 0) 89 90 #define DSI2_PHY_IPI_RATIO_MAN_CFG 0x0134 91 #define PHY_IPI_RATIO(x) UPDATE(x, 21, 0) 92 #define DSI2_PHY_SYS_RATIO_MAN_CFG 0x013C 93 #define PHY_SYS_RATIO(x) UPDATE(x, 16, 0) 94 95 #define DSI2_DSI_GENERAL_CFG 0x0200 96 #define BTA_EN BIT(1) 97 #define EOTP_TX_EN BIT(0) 98 #define DSI2_DSI_VCID_CFG 0x0204 99 #define TX_VCID(x) UPDATE(x, 1, 0) 100 #define DSI2_DSI_SCRAMBLING_CFG 0x0208 101 #define SCRAMBLING_SEED(x) UPDATE(x, 31, 16) 102 #define SCRAMBLING_EN BIT(0) 103 #define DSI2_DSI_VID_TX_CFG 0x020c 104 #define LPDT_DISPLAY_CMD_EN BIT(20) 105 #define BLK_VFP_HS_EN BIT(14) 106 #define BLK_VBP_HS_EN BIT(13) 107 #define BLK_VSA_HS_EN BIT(12) 108 #define BLK_HFP_HS_EN BIT(6) 109 #define BLK_HBP_HS_EN BIT(5) 110 #define BLK_HSA_HS_EN BIT(4) 111 #define VID_MODE_TYPE(x) UPDATE(x, 1, 0) 112 #define DSI2_CRI_TX_HDR 0x02c0 113 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 114 #define DSI2_CRI_TX_PLD 0x02c4 115 #define DSI2_CRI_RX_HDR 0x02c8 116 #define DSI2_CRI_RX_PLD 0x02cc 117 118 #define DSI2_IPI_COLOR_MAN_CFG 0x0300 119 #define IPI_DEPTH(x) UPDATE(x, 7, 4) 120 #define IPI_DEPTH_5_6_5_BITS 0x02 121 #define IPI_DEPTH_6_BITS 0x03 122 #define IPI_DEPTH_8_BITS 0x05 123 #define IPI_DEPTH_10_BITS 0x06 124 #define IPI_FORMAT(x) UPDATE(x, 3, 0) 125 #define IPI_FORMAT_RGB 0x0 126 #define IPI_FORMAT_DSC 0x0b 127 #define DSI2_IPI_VID_HSA_MAN_CFG 0x0304 128 #define VID_HSA_TIME(x) UPDATE(x, 29, 0) 129 #define DSI2_IPI_VID_HBP_MAN_CFG 0x030c 130 #define VID_HBP_TIME(x) UPDATE(x, 29, 0) 131 #define DSI2_IPI_VID_HACT_MAN_CFG 0x0314 132 #define VID_HACT_TIME(x) UPDATE(x, 29, 0) 133 #define DSI2_IPI_VID_HLINE_MAN_CFG 0x031c 134 #define VID_HLINE_TIME(x) UPDATE(x, 29, 0) 135 #define DSI2_IPI_VID_VSA_MAN_CFG 0x0324 136 #define VID_VSA_LINES(x) UPDATE(x, 9, 0) 137 #define DSI2_IPI_VID_VBP_MAN_CFG 0X032C 138 #define VID_VBP_LINES(x) UPDATE(x, 9, 0) 139 #define DSI2_IPI_VID_VACT_MAN_CFG 0X0334 140 #define VID_VACT_LINES(x) UPDATE(x, 13, 0) 141 #define DSI2_IPI_VID_VFP_MAN_CFG 0X033C 142 #define VID_VFP_LINES(x) UPDATE(x, 9, 0) 143 #define DSI2_IPI_PIX_PKT_CFG 0x0344 144 #define MAX_PIX_PKT(x) UPDATE(x, 15, 0) 145 146 #define DSI2_INT_ST_PHY 0x0400 147 #define DSI2_INT_MASK_PHY 0x0404 148 #define DSI2_INT_ST_TO 0x0410 149 #define DSI2_INT_MASK_TO 0x0414 150 #define DSI2_INT_ST_ACK 0x0420 151 #define DSI2_INT_MASK_ACK 0x0424 152 #define DSI2_INT_ST_IPI 0x0430 153 #define DSI2_INT_MASK_IPI 0x0434 154 #define DSI2_INT_ST_FIFO 0x0440 155 #define DSI2_INT_MASK_FIFO 0x0444 156 #define DSI2_INT_ST_PRI 0x0450 157 #define DSI2_INT_MASK_PRI 0x0454 158 #define DSI2_INT_ST_CRI 0x0460 159 #define DSI2_INT_MASK_CRI 0x0464 160 #define DSI2_INT_FORCE_CRI 0x0468 161 #define DSI2_MAX_REGISGER DSI2_INT_FORCE_CRI 162 163 #define CMD_PKT_STATUS_TIMEOUT_US 1000 164 #define MODE_STATUS_TIMEOUT_US 20000 165 #define SYS_CLK 351000L 166 #define PSEC_PER_SEC 1000000000000LL 167 #define USEC_PER_SEC 1000000L 168 #define MSEC_PER_SEC 1000L 169 170 #define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 16) | ((lsb) << 8) | (msb)) 171 172 enum vid_mode_type { 173 VID_MODE_TYPE_NON_BURST_SYNC_PULSES, 174 VID_MODE_TYPE_NON_BURST_SYNC_EVENTS, 175 VID_MODE_TYPE_BURST, 176 }; 177 178 enum mode_ctrl { 179 IDLE_MODE, 180 AUTOCALC_MODE, 181 COMMAND_MODE, 182 VIDEO_MODE, 183 DATA_STREAM_MODE, 184 VIDE_TEST_MODE, 185 DATA_STREAM_TEST_MODE, 186 }; 187 188 enum grf_reg_fields { 189 TXREQCLKHS_EN, 190 GATING_EN, 191 IPI_SHUTDN, 192 IPI_COLORM, 193 IPI_COLOR_DEPTH, 194 IPI_FORMAT, 195 MAX_FIELDS, 196 }; 197 198 enum phy_type { 199 DPHY, 200 CPHY, 201 }; 202 203 enum ppi_width { 204 PPI_WIDTH_8_BITS, 205 PPI_WIDTH_16_BITS, 206 PPI_WIDTH_32_BITS, 207 }; 208 209 struct dw_mipi_dsi2_plat_data { 210 const u32 *dsi0_grf_reg_fields; 211 const u32 *dsi1_grf_reg_fields; 212 unsigned long long dphy_max_bit_rate_per_lane; 213 unsigned long long cphy_max_symbol_rate_per_lane; 214 }; 215 216 struct mipi_dcphy { 217 /* Non-SNPS PHY */ 218 struct rockchip_phy *phy; 219 220 u16 input_div; 221 u16 feedback_div; 222 }; 223 224 /** 225 * struct mipi_dphy_configure - MIPI D-PHY configuration set 226 * 227 * This structure is used to represent the configuration state of a 228 * MIPI D-PHY phy. 229 */ 230 struct mipi_dphy_configure { 231 unsigned int clk_miss; 232 unsigned int clk_post; 233 unsigned int clk_pre; 234 unsigned int clk_prepare; 235 unsigned int clk_settle; 236 unsigned int clk_term_en; 237 unsigned int clk_trail; 238 unsigned int clk_zero; 239 unsigned int d_term_en; 240 unsigned int eot; 241 unsigned int hs_exit; 242 unsigned int hs_prepare; 243 unsigned int hs_settle; 244 unsigned int hs_skip; 245 unsigned int hs_trail; 246 unsigned int hs_zero; 247 unsigned int init; 248 unsigned int lpx; 249 unsigned int ta_get; 250 unsigned int ta_go; 251 unsigned int ta_sure; 252 unsigned int wakeup; 253 unsigned long hs_clk_rate; 254 unsigned long lp_clk_rate; 255 unsigned char lanes; 256 }; 257 258 struct dw_mipi_dsi2 { 259 struct udevice *dev; 260 void *base; 261 void *grf; 262 int id; 263 struct dw_mipi_dsi2 *master; 264 struct dw_mipi_dsi2 *slave; 265 bool prepared; 266 267 bool c_option; 268 bool dsc_enable; 269 bool scrambling_en; 270 unsigned int slice_width; 271 unsigned int slice_height; 272 u32 version_major; 273 u32 version_minor; 274 275 unsigned int lane_hs_rate; /* per lane */ 276 u32 channel; 277 u32 lanes; 278 u32 format; 279 u32 mode_flags; 280 struct mipi_dcphy dcphy; 281 struct drm_display_mode mode; 282 bool data_swap; 283 284 struct mipi_dphy_configure mipi_dphy_cfg; 285 const struct dw_mipi_dsi2_plat_data *pdata; 286 }; 287 288 static inline void dsi_write(struct dw_mipi_dsi2 *dsi2, u32 reg, u32 val) 289 { 290 writel(val, dsi2->base + reg); 291 } 292 293 static inline u32 dsi_read(struct dw_mipi_dsi2 *dsi2, u32 reg) 294 { 295 return readl(dsi2->base + reg); 296 } 297 298 static inline void dsi_update_bits(struct dw_mipi_dsi2 *dsi2, 299 u32 reg, u32 mask, u32 val) 300 { 301 u32 orig, tmp; 302 303 orig = dsi_read(dsi2, reg); 304 tmp = orig & ~mask; 305 tmp |= val & mask; 306 dsi_write(dsi2, reg, tmp); 307 } 308 309 static void grf_field_write(struct dw_mipi_dsi2 *dsi2, enum grf_reg_fields index, 310 unsigned int val) 311 { 312 const u32 field = dsi2->id ? dsi2->pdata->dsi1_grf_reg_fields[index] : 313 dsi2->pdata->dsi0_grf_reg_fields[index]; 314 u16 reg; 315 u8 msb, lsb; 316 317 if (!field) 318 return; 319 320 reg = (field >> 16) & 0xffff; 321 lsb = (field >> 8) & 0xff; 322 msb = (field >> 0) & 0xff; 323 324 regmap_write(dsi2->grf, reg, GENMASK(msb, lsb) << 16 | val << lsb); 325 } 326 327 static unsigned long dw_mipi_dsi2_get_lane_rate(struct dw_mipi_dsi2 *dsi2) 328 { 329 const struct drm_display_mode *mode = &dsi2->mode; 330 u64 max_lane_rate, lane_rate; 331 unsigned int value; 332 int bpp, lanes; 333 u64 tmp; 334 335 max_lane_rate = (dsi2->c_option) ? 336 dsi2->pdata->cphy_max_symbol_rate_per_lane : 337 dsi2->pdata->dphy_max_bit_rate_per_lane; 338 339 /* optional override of the desired bandwidth */ 340 value = dev_read_u32_default(dsi2->dev, "rockchip,lane-rate", 0); 341 if (value > 0) 342 return value * 1000 * 1000; 343 344 bpp = mipi_dsi_pixel_format_to_bpp(dsi2->format); 345 if (bpp < 0) 346 bpp = 24; 347 348 lanes = dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes; 349 tmp = (u64)mode->clock * 1000 * bpp; 350 do_div(tmp, lanes); 351 352 if (dsi2->c_option) 353 tmp = DIV_ROUND_CLOSEST(tmp * 100, 228); 354 355 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */ 356 tmp *= 10; 357 do_div(tmp, 9); 358 359 if (tmp > max_lane_rate) 360 lane_rate = max_lane_rate; 361 else 362 lane_rate = tmp; 363 364 return lane_rate; 365 } 366 367 static int cri_fifos_wait_avail(struct dw_mipi_dsi2 *dsi2) 368 { 369 u32 sts, mask; 370 int ret; 371 372 mask = CRI_BUSY | CRT_FIFOS_NOT_EMPTY; 373 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 374 sts, !(sts & mask), 375 CMD_PKT_STATUS_TIMEOUT_US); 376 if (ret < 0) { 377 printf("command interface is busy: 0x%x\n", sts); 378 return ret; 379 } 380 381 return 0; 382 } 383 384 static int dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 *dsi2, 385 const struct mipi_dsi_msg *msg) 386 { 387 u8 *payload = msg->rx_buf; 388 u8 data_type; 389 u16 wc; 390 int i, j, ret, len = msg->rx_len; 391 unsigned int vrefresh = drm_mode_vrefresh(&dsi2->mode); 392 u32 val; 393 394 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 395 val, val & CRI_RD_DATA_AVAIL, 396 DIV_ROUND_UP(1000000, vrefresh)); 397 if (ret) { 398 printf("CRI has no available read data\n"); 399 return ret; 400 } 401 402 val = dsi_read(dsi2, DSI2_CRI_RX_HDR); 403 data_type = val & 0x3f; 404 405 if (mipi_dsi_packet_format_is_short(data_type)) { 406 for (i = 0; i < len && i < 2; i++) 407 payload[i] = (val >> (8 * (i + 1))) & 0xff; 408 409 return 0; 410 } 411 412 wc = (val >> 8) & 0xffff; 413 /* Receive payload */ 414 for (i = 0; i < len && i < wc; i += 4) { 415 val = dsi_read(dsi2, DSI2_CRI_RX_PLD); 416 for (j = 0; j < 4 && j + i < len && j + i < wc; j++) 417 payload[i + j] = val >> (8 * j); 418 } 419 420 return 0; 421 } 422 423 static ssize_t dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 *dsi2, 424 const struct mipi_dsi_msg *msg) 425 { 426 struct mipi_dsi_packet packet; 427 int ret; 428 int val; 429 u32 mode; 430 431 dsi_update_bits(dsi2, DSI2_DSI_VID_TX_CFG, LPDT_DISPLAY_CMD_EN, 432 msg->flags & MIPI_DSI_MSG_USE_LPM ? 433 LPDT_DISPLAY_CMD_EN : 0); 434 435 /* create a packet to the DSI protocol */ 436 ret = mipi_dsi_create_packet(&packet, msg); 437 if (ret) { 438 printf("failed to create packet: %d\n", ret); 439 return ret; 440 } 441 442 /* check cri interface is not busy */ 443 ret = cri_fifos_wait_avail(dsi2); 444 if (ret) 445 return ret; 446 447 /* Send payload */ 448 while (DIV_ROUND_UP(packet.payload_length, 4)) { 449 if (packet.payload_length < 4) { 450 /* send residu payload */ 451 val = 0; 452 memcpy(&val, packet.payload, packet.payload_length); 453 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 454 packet.payload_length = 0; 455 } else { 456 val = get_unaligned_le32(packet.payload); 457 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 458 packet.payload += 4; 459 packet.payload_length -= 4; 460 } 461 } 462 463 /* Send packet header */ 464 mode = CMD_TX_MODE(msg->flags & MIPI_DSI_MSG_USE_LPM ? 1 : 0); 465 val = get_unaligned_le32(packet.header); 466 dsi_write(dsi2, DSI2_CRI_TX_HDR, mode | val); 467 468 ret = cri_fifos_wait_avail(dsi2); 469 if (ret) 470 return ret; 471 472 if (msg->rx_len) { 473 ret = dw_mipi_dsi2_read_from_fifo(dsi2, msg); 474 if (ret < 0) 475 return ret; 476 } 477 478 if (dsi2->slave) { 479 ret = dw_mipi_dsi2_transfer(dsi2->slave, msg); 480 if (ret < 0) 481 return ret; 482 } 483 484 return msg->rx_len ? msg->rx_len : msg->tx_len; 485 } 486 487 static void dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 *dsi2) 488 { 489 u32 val, color_depth; 490 491 switch (dsi2->format) { 492 case MIPI_DSI_FMT_RGB666: 493 case MIPI_DSI_FMT_RGB666_PACKED: 494 color_depth = IPI_DEPTH_6_BITS; 495 break; 496 case MIPI_DSI_FMT_RGB565: 497 color_depth = IPI_DEPTH_5_6_5_BITS; 498 break; 499 case MIPI_DSI_FMT_RGB888: 500 default: 501 color_depth = IPI_DEPTH_8_BITS; 502 break; 503 } 504 505 val = IPI_DEPTH(color_depth) | 506 IPI_FORMAT(dsi2->dsc_enable ? IPI_FORMAT_DSC : IPI_FORMAT_RGB); 507 dsi_write(dsi2, DSI2_IPI_COLOR_MAN_CFG, val); 508 grf_field_write(dsi2, IPI_COLOR_DEPTH, color_depth); 509 510 if (dsi2->dsc_enable) 511 grf_field_write(dsi2, IPI_FORMAT, IPI_FORMAT_DSC); 512 } 513 514 static void dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 *dsi2) 515 { 516 struct drm_display_mode *mode = &dsi2->mode; 517 u32 hline, hsa, hbp, hact; 518 u64 hline_time, hsa_time, hbp_time, hact_time, tmp; 519 u32 vact, vsa, vfp, vbp; 520 u32 pixel_clk, phy_hs_clk; 521 u16 val; 522 523 if (dsi2->slave || dsi2->master) 524 val = mode->hdisplay / 2; 525 else 526 val = mode->hdisplay; 527 528 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val)); 529 530 dw_mipi_dsi2_ipi_color_coding_cfg(dsi2); 531 532 /* 533 * if the controller is intended to operate in data stream mode, 534 * no more steps are required. 535 */ 536 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) 537 return; 538 539 vact = mode->vdisplay; 540 vsa = mode->vsync_end - mode->vsync_start; 541 vfp = mode->vsync_start - mode->vdisplay; 542 vbp = mode->vtotal - mode->vsync_end; 543 hact = mode->hdisplay; 544 hsa = mode->hsync_end - mode->hsync_start; 545 hbp = mode->htotal - mode->hsync_end; 546 hline = mode->htotal; 547 548 pixel_clk = mode->clock / 1000; 549 550 if (dsi2->c_option) 551 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate, 7); 552 else 553 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate, 16); 554 555 tmp = hsa * phy_hs_clk; 556 hsa_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 557 dsi_write(dsi2, DSI2_IPI_VID_HSA_MAN_CFG, VID_HSA_TIME(hsa_time)); 558 559 tmp = hbp * phy_hs_clk; 560 hbp_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 561 dsi_write(dsi2, DSI2_IPI_VID_HBP_MAN_CFG, VID_HBP_TIME(hbp_time)); 562 563 tmp = hact * phy_hs_clk; 564 hact_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 565 dsi_write(dsi2, DSI2_IPI_VID_HACT_MAN_CFG, VID_HACT_TIME(hact_time)); 566 567 tmp = hline * phy_hs_clk; 568 hline_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 569 dsi_write(dsi2, DSI2_IPI_VID_HLINE_MAN_CFG, VID_HLINE_TIME(hline_time)); 570 571 dsi_write(dsi2, DSI2_IPI_VID_VSA_MAN_CFG, VID_VSA_LINES(vsa)); 572 dsi_write(dsi2, DSI2_IPI_VID_VBP_MAN_CFG, VID_VBP_LINES(vbp)); 573 dsi_write(dsi2, DSI2_IPI_VID_VACT_MAN_CFG, VID_VACT_LINES(vact)); 574 dsi_write(dsi2, DSI2_IPI_VID_VFP_MAN_CFG, VID_VFP_LINES(vfp)); 575 } 576 577 static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2) 578 { 579 u32 val = 0, mode; 580 int ret; 581 582 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 583 val |= VID_MODE_TYPE_BURST; 584 else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 585 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 586 587 else 588 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 589 590 dsi_write(dsi2, DSI2_DSI_VID_TX_CFG, val); 591 592 593 dsi_write(dsi2, DSI2_MODE_CTRL, VIDEO_MODE); 594 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 595 mode, mode & VIDEO_MODE, 596 MODE_STATUS_TIMEOUT_US); 597 if (ret < 0) 598 printf("failed to enter video mode\n"); 599 } 600 601 static void dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 *dsi2) 602 { 603 u32 mode; 604 int ret; 605 606 dsi_write(dsi2, DSI2_MODE_CTRL, DATA_STREAM_MODE); 607 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 608 mode, mode & DATA_STREAM_MODE, 609 MODE_STATUS_TIMEOUT_US); 610 if (ret < 0) 611 printf("failed to enter data stream mode\n"); 612 } 613 614 static void dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 *dsi2) 615 { 616 u32 mode; 617 int ret; 618 619 dsi_write(dsi2, DSI2_MODE_CTRL, COMMAND_MODE); 620 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 621 mode, mode & COMMAND_MODE, 622 MODE_STATUS_TIMEOUT_US); 623 if (ret < 0) 624 printf("failed to enter cmd mode\n"); 625 } 626 627 static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2) 628 { 629 dw_mipi_dsi2_ipi_set(dsi2); 630 631 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO) 632 dw_mipi_dsi2_set_vid_mode(dsi2); 633 else 634 dw_mipi_dsi2_set_data_stream_mode(dsi2); 635 636 if (dsi2->slave) 637 dw_mipi_dsi2_enable(dsi2->slave); 638 } 639 640 static void dw_mipi_dsi2_disable(struct dw_mipi_dsi2 *dsi2) 641 { 642 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, 0); 643 dw_mipi_dsi2_set_cmd_mode(dsi2); 644 645 if (dsi2->slave) 646 dw_mipi_dsi2_disable(dsi2->slave); 647 } 648 649 static void dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 *dsi2) 650 { 651 if (!dsi2->prepared) 652 return; 653 654 dsi_write(dsi2, DSI2_PWR_UP, RESET); 655 656 if (dsi2->dcphy.phy) 657 rockchip_phy_power_off(dsi2->dcphy.phy); 658 659 dsi2->prepared = false; 660 661 if (dsi2->slave) 662 dw_mipi_dsi2_post_disable(dsi2->slave); 663 } 664 665 static int dw_mipi_dsi2_connector_pre_init(struct display_state *state) 666 { 667 struct connector_state *conn_state = &state->conn_state; 668 669 conn_state->type = DRM_MODE_CONNECTOR_DSI; 670 671 return 0; 672 } 673 674 static int dw_mipi_dsi2_connector_init(struct display_state *state) 675 { 676 struct connector_state *conn_state = &state->conn_state; 677 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 678 struct rockchip_phy *phy = NULL; 679 struct udevice *phy_dev; 680 struct udevice *dev; 681 int ret; 682 683 684 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dsi2->id); 685 dsi2->dcphy.phy = conn_state->phy; 686 687 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 688 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 689 conn_state->output_if |= 690 dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0; 691 692 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) { 693 conn_state->output_flags |= ROCKCHIP_OUTPUT_MIPI_DS_MODE; 694 conn_state->hold_mode = true; 695 } 696 697 if (dsi2->lanes > 4) { 698 ret = uclass_get_device_by_name(UCLASS_DISPLAY, 699 "dsi@fde30000", 700 &dev); 701 if (ret) 702 return ret; 703 704 dsi2->slave = dev_get_priv(dev); 705 if (!dsi2->slave) 706 return -ENODEV; 707 708 dsi2->slave->master = dsi2; 709 dsi2->lanes /= 2; 710 dsi2->slave->lanes = dsi2->lanes; 711 dsi2->slave->format = dsi2->format; 712 dsi2->slave->mode_flags = dsi2->mode_flags; 713 dsi2->slave->channel = dsi2->channel; 714 conn_state->output_flags |= 715 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; 716 if (dsi2->data_swap) 717 conn_state->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP; 718 719 conn_state->output_if |= VOP_OUTPUT_IF_MIPI1; 720 721 ret = uclass_get_device_by_phandle(UCLASS_PHY, dev, 722 "phys", &phy_dev); 723 if (ret) 724 return -ENODEV; 725 726 phy = (struct rockchip_phy *)dev_get_driver_data(phy_dev); 727 if (!phy) 728 return -ENODEV; 729 730 dsi2->slave->dcphy.phy = phy; 731 if (phy->funcs && phy->funcs->init) 732 return phy->funcs->init(phy); 733 } 734 735 return 0; 736 } 737 738 /* 739 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived 740 * from the valid ranges specified in Section 6.9, Table 14, Page 41 741 * of the D-PHY specification (v2.1). 742 */ 743 int mipi_dphy_get_default_config(unsigned long long hs_clk_rate, 744 struct mipi_dphy_configure *cfg) 745 { 746 unsigned long long ui; 747 748 if (!cfg) 749 return -EINVAL; 750 751 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); 752 do_div(ui, hs_clk_rate); 753 754 cfg->clk_miss = 0; 755 cfg->clk_post = 60000 + 52 * ui; 756 cfg->clk_pre = 8000; 757 cfg->clk_prepare = 38000; 758 cfg->clk_settle = 95000; 759 cfg->clk_term_en = 0; 760 cfg->clk_trail = 60000; 761 cfg->clk_zero = 262000; 762 cfg->d_term_en = 0; 763 cfg->eot = 0; 764 cfg->hs_exit = 100000; 765 cfg->hs_prepare = 40000 + 4 * ui; 766 cfg->hs_zero = 105000 + 6 * ui; 767 cfg->hs_settle = 85000 + 6 * ui; 768 cfg->hs_skip = 40000; 769 770 /* 771 * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40) 772 * contains this formula as: 773 * 774 * T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui) 775 * 776 * where n = 1 for forward-direction HS mode and n = 4 for reverse- 777 * direction HS mode. There's only one setting and this function does 778 * not parameterize on anything other that ui, so this code will 779 * assumes that reverse-direction HS mode is supported and uses n = 4. 780 */ 781 cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui); 782 783 cfg->init = 100; 784 cfg->lpx = 60000; 785 cfg->ta_get = 5 * cfg->lpx; 786 cfg->ta_go = 4 * cfg->lpx; 787 cfg->ta_sure = 2 * cfg->lpx; 788 cfg->wakeup = 1000; 789 790 return 0; 791 } 792 793 static void dw_mipi_dsi2_set_hs_clk(struct dw_mipi_dsi2 *dsi2, unsigned long rate) 794 { 795 mipi_dphy_get_default_config(rate, &dsi2->mipi_dphy_cfg); 796 797 if (!dsi2->c_option) 798 rockchip_phy_set_mode(dsi2->dcphy.phy, PHY_MODE_MIPI_DPHY); 799 800 rate = rockchip_phy_set_pll(dsi2->dcphy.phy, rate); 801 dsi2->lane_hs_rate = rate / 1000 / 1000; 802 } 803 804 static void dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 *dsi2) 805 { 806 dsi_write(dsi2, DSI2_SOFT_RESET, 0X0); 807 udelay(100); 808 dsi_write(dsi2, DSI2_SOFT_RESET, SYS_RSTN | PHY_RSTN | IPI_RSTN); 809 } 810 811 static void 812 dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 *dsi2, u32 mode) 813 { 814 /* 815 * select controller work in Manual mode 816 * Manual: MANUAL_MODE_EN 817 * Automatic: 0 818 */ 819 dsi_write(dsi2, MANUAL_MODE_CFG, mode); 820 } 821 822 static void dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 *dsi2) 823 { 824 u32 val = 0; 825 826 /* PPI width is fixed to 16 bits in DCPHY */ 827 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes); 828 val |= PHY_TYPE(dsi2->c_option ? CPHY : DPHY); 829 dsi_write(dsi2, DSI2_PHY_MODE_CFG, val); 830 } 831 832 static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2) 833 { 834 u32 sys_clk = SYS_CLK / MSEC_PER_SEC; 835 u32 esc_clk_div; 836 u32 val = 0; 837 838 if (dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 839 val |= NON_CONTINUOUS_CLK; 840 841 /* The Escape clock ranges from 1MHz to 20MHz. */ 842 esc_clk_div = DIV_ROUND_UP(sys_clk, 10 * 2); 843 val |= PHY_LPTX_CLK_DIV(esc_clk_div); 844 845 dsi_write(dsi2, DSI2_PHY_CLK_CFG, val); 846 } 847 848 static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2) 849 { 850 struct drm_display_mode *mode = &dsi2->mode; 851 u64 pixel_clk, ipi_clk, phy_hsclk, tmp; 852 853 /* 854 * in DPHY mode, the phy_hstx_clk is exactly 1/16 the Lane high-speed 855 * data rate; In CPHY mode, the phy_hstx_clk is exactly 1/7 the trio 856 * high speed symbol rate. 857 */ 858 if (dsi2->c_option) 859 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 860 861 else 862 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 863 864 /* IPI_RATIO_MAN_CFG = PHY_HSTX_CLK / IPI_CLK */ 865 pixel_clk = mode->clock; 866 ipi_clk = pixel_clk / 4; 867 868 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, ipi_clk); 869 dsi_write(dsi2, DSI2_PHY_IPI_RATIO_MAN_CFG, PHY_IPI_RATIO(tmp)); 870 871 /* 872 * SYS_RATIO_MAN_CFG = MIPI_DCPHY_HSCLK_Freq / MIPI_DCPHY_HSCLK_Freq 873 */ 874 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, SYS_CLK); 875 dsi_write(dsi2, DSI2_PHY_SYS_RATIO_MAN_CFG, PHY_SYS_RATIO(tmp)); 876 } 877 878 static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2) 879 { 880 struct mipi_dphy_configure *cfg = &dsi2->mipi_dphy_cfg; 881 unsigned long long tmp, ui; 882 unsigned long long hstx_clk; 883 884 hstx_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * USEC_PER_SEC, 16); 885 886 ui = ALIGN(PSEC_PER_SEC, hstx_clk); 887 do_div(ui, hstx_clk); 888 889 /* PHY_LP2HS_TIME = (TLPX + THS-PREPARE + THS-ZERO) / Tphy_hstx_clk */ 890 tmp = cfg->lpx + cfg->hs_prepare + cfg->hs_zero; 891 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 892 dsi_write(dsi2, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(tmp)); 893 894 /* PHY_HS2LP_TIME = (THS-TRAIL + THS-EXIT) / Tphy_hstx_clk */ 895 tmp = cfg->hs_trail + cfg->hs_exit; 896 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 897 dsi_write(dsi2, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(tmp)); 898 } 899 900 static void dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 *dsi2) 901 { 902 dw_mipi_dsi2_phy_mode_cfg(dsi2); 903 dw_mipi_dsi2_phy_clk_mode_cfg(dsi2); 904 dw_mipi_dsi2_phy_ratio_cfg(dsi2); 905 dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(dsi2); 906 907 /* phy configuration 8 - 10 */ 908 } 909 910 static void dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 *dsi2) 911 { 912 u32 val; 913 914 val = BTA_EN | EOTP_TX_EN; 915 916 if (dsi2->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 917 val &= ~EOTP_TX_EN; 918 919 dsi_write(dsi2, DSI2_DSI_GENERAL_CFG, val); 920 dsi_write(dsi2, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel)); 921 922 if (dsi2->scrambling_en) 923 dsi_write(dsi2, DSI2_DSI_SCRAMBLING_CFG, SCRAMBLING_EN); 924 925 val = 0; 926 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) 927 val |= BLK_HFP_HS_EN; 928 929 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) 930 val |= BLK_HBP_HS_EN; 931 932 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HSA) 933 val |= BLK_HSA_HS_EN; 934 935 dsi_write(dsi2, DSI2_DSI_VID_TX_CFG, val); 936 937 /* configure the maximum return packet size that periphera can send */ 938 } 939 940 static void dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 *dsi2, bool enable) 941 { 942 if (enable) { 943 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x1); 944 dsi_write(dsi2, DSI2_INT_MASK_TO, 0xf); 945 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x1); 946 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x1); 947 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x1); 948 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x1); 949 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x1); 950 } else { 951 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x0); 952 dsi_write(dsi2, DSI2_INT_MASK_TO, 0x0); 953 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x0); 954 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x0); 955 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x0); 956 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x0); 957 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x0); 958 }; 959 } 960 961 static void mipi_dcphy_power_on(struct dw_mipi_dsi2 *dsi2) 962 { 963 if (!dsi2->dcphy.phy) 964 return; 965 966 rockchip_phy_power_on(dsi2->dcphy.phy); 967 } 968 969 static void dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 *dsi2) 970 { 971 if (dsi2->prepared) 972 return; 973 974 dw_mipi_dsi2_host_softrst(dsi2); 975 dsi_write(dsi2, DSI2_PWR_UP, RESET); 976 977 dw_mipi_dsi2_work_mode(dsi2, MANUAL_MODE_EN); 978 dw_mipi_dsi2_phy_init(dsi2); 979 dw_mipi_dsi2_tx_option_set(dsi2); 980 dw_mipi_dsi2_irq_enable(dsi2, 0); 981 mipi_dcphy_power_on(dsi2); 982 dsi_write(dsi2, DSI2_PWR_UP, POWER_UP); 983 dw_mipi_dsi2_set_cmd_mode(dsi2); 984 985 dsi2->prepared = true; 986 987 if (dsi2->slave) 988 dw_mipi_dsi2_pre_enable(dsi2->slave); 989 } 990 991 static int dw_mipi_dsi2_connector_prepare(struct display_state *state) 992 { 993 struct connector_state *conn_state = &state->conn_state; 994 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 995 unsigned long lane_rate; 996 997 memcpy(&dsi2->mode, &conn_state->mode, sizeof(struct drm_display_mode)); 998 if (dsi2->slave) 999 memcpy(&dsi2->slave->mode, &dsi2->mode, 1000 sizeof(struct drm_display_mode)); 1001 1002 lane_rate = dw_mipi_dsi2_get_lane_rate(dsi2); 1003 if (dsi2->dcphy.phy) 1004 dw_mipi_dsi2_set_hs_clk(dsi2, lane_rate); 1005 1006 if (dsi2->slave && dsi2->slave->dcphy.phy) 1007 dw_mipi_dsi2_set_hs_clk(dsi2->slave, lane_rate); 1008 1009 printf("final DSI-Link bandwidth: %u %s x %d\n", 1010 dsi2->lane_hs_rate, dsi2->c_option ? "Msps" : "Mbps", 1011 dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes); 1012 1013 dw_mipi_dsi2_pre_enable(dsi2); 1014 1015 return 0; 1016 } 1017 1018 static void dw_mipi_dsi2_connector_unprepare(struct display_state *state) 1019 { 1020 struct connector_state *conn_state = &state->conn_state; 1021 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 1022 1023 dw_mipi_dsi2_post_disable(dsi2); 1024 } 1025 1026 static int dw_mipi_dsi2_connector_enable(struct display_state *state) 1027 { 1028 struct connector_state *conn_state = &state->conn_state; 1029 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 1030 1031 dw_mipi_dsi2_enable(dsi2); 1032 1033 return 0; 1034 } 1035 1036 static int dw_mipi_dsi2_connector_disable(struct display_state *state) 1037 { 1038 struct connector_state *conn_state = &state->conn_state; 1039 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 1040 1041 dw_mipi_dsi2_disable(dsi2); 1042 1043 return 0; 1044 } 1045 1046 static const struct rockchip_connector_funcs dw_mipi_dsi2_connector_funcs = { 1047 .pre_init = dw_mipi_dsi2_connector_pre_init, 1048 .init = dw_mipi_dsi2_connector_init, 1049 .prepare = dw_mipi_dsi2_connector_prepare, 1050 .unprepare = dw_mipi_dsi2_connector_unprepare, 1051 .enable = dw_mipi_dsi2_connector_enable, 1052 .disable = dw_mipi_dsi2_connector_disable, 1053 }; 1054 1055 static int dw_mipi_dsi2_probe(struct udevice *dev) 1056 { 1057 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(dev); 1058 const struct rockchip_connector *connector = 1059 (const struct rockchip_connector *)dev_get_driver_data(dev); 1060 const struct dw_mipi_dsi2_plat_data *pdata = connector->data; 1061 struct udevice *syscon; 1062 int id, ret; 1063 1064 dsi2->base = dev_read_addr_ptr(dev); 1065 1066 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1067 &syscon); 1068 if (!ret) { 1069 dsi2->grf = syscon_get_regmap(syscon); 1070 if (!dsi2->grf) 1071 return -ENODEV; 1072 } 1073 1074 id = of_alias_get_id(ofnode_to_np(dev->node), "dsi"); 1075 if (id < 0) 1076 id = 0; 1077 1078 dsi2->dev = dev; 1079 dsi2->pdata = pdata; 1080 dsi2->id = id; 1081 dsi2->data_swap = dev_read_bool(dsi2->dev, "rockchip,data-swap"); 1082 1083 return 0; 1084 } 1085 1086 static const u32 rk3588_dsi0_grf_reg_fields[MAX_FIELDS] = { 1087 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0000, 11, 11), 1088 [GATING_EN] = GRF_REG_FIELD(0x0000, 10, 10), 1089 [IPI_SHUTDN] = GRF_REG_FIELD(0x0000, 9, 9), 1090 [IPI_COLORM] = GRF_REG_FIELD(0x0000, 8, 8), 1091 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0000, 4, 7), 1092 [IPI_FORMAT] = GRF_REG_FIELD(0x0000, 0, 3), 1093 }; 1094 1095 static const u32 rk3588_dsi1_grf_reg_fields[MAX_FIELDS] = { 1096 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0004, 11, 11), 1097 [GATING_EN] = GRF_REG_FIELD(0x0004, 10, 10), 1098 [IPI_SHUTDN] = GRF_REG_FIELD(0x0004, 9, 9), 1099 [IPI_COLORM] = GRF_REG_FIELD(0x0004, 8, 8), 1100 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0004, 4, 7), 1101 [IPI_FORMAT] = GRF_REG_FIELD(0x0004, 0, 3), 1102 }; 1103 1104 static const struct dw_mipi_dsi2_plat_data rk3588_mipi_dsi2_plat_data = { 1105 .dsi0_grf_reg_fields = rk3588_dsi0_grf_reg_fields, 1106 .dsi1_grf_reg_fields = rk3588_dsi1_grf_reg_fields, 1107 .dphy_max_bit_rate_per_lane = 4500000000ULL, 1108 .cphy_max_symbol_rate_per_lane = 2000000000ULL, 1109 }; 1110 static const struct rockchip_connector rk3588_mipi_dsi2_driver_data = { 1111 .funcs = &dw_mipi_dsi2_connector_funcs, 1112 .data = &rk3588_mipi_dsi2_plat_data, 1113 }; 1114 1115 static const struct udevice_id dw_mipi_dsi2_ids[] = { 1116 { 1117 .compatible = "rockchip,rk3588-mipi-dsi2", 1118 .data = (ulong)&rk3588_mipi_dsi2_driver_data, 1119 }, 1120 {} 1121 }; 1122 1123 static ssize_t dw_mipi_dsi2_host_transfer(struct mipi_dsi_host *host, 1124 const struct mipi_dsi_msg *msg) 1125 { 1126 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1127 1128 return dw_mipi_dsi2_transfer(dsi2, msg); 1129 } 1130 1131 static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2) 1132 { 1133 struct udevice *dev = NULL; 1134 int ret; 1135 1136 ret = device_find_first_child(dsi2->dev, &dev); 1137 if (ret) 1138 return ret; 1139 1140 dsi2->c_option = dev_read_bool(dev, "phy-c-option"); 1141 dsi2->scrambling_en = dev_read_bool(dev, "scrambling-enable"); 1142 dsi2->dsc_enable = dev_read_bool(dev, "compressed-data"); 1143 1144 if (dsi2->slave) { 1145 dsi2->slave->c_option = dsi2->c_option; 1146 dsi2->slave->scrambling_en = dsi2->scrambling_en; 1147 dsi2->slave->dsc_enable = dsi2->dsc_enable; 1148 } 1149 1150 dsi2->slice_width = dev_read_u32_default(dev, "slice_width", 0); 1151 dsi2->slice_height = dev_read_u32_default(dev, "slice_height", 0); 1152 dsi2->version_major = dev_read_u32_default(dev, "version_major", 0); 1153 dsi2->version_minor = dev_read_u32_default(dev, "version_minor", 0); 1154 1155 return 0; 1156 } 1157 1158 static int dw_mipi_dsi2_host_attach(struct mipi_dsi_host *host, 1159 struct mipi_dsi_device *device) 1160 { 1161 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1162 1163 if (device->lanes < 1 || device->lanes > 8) 1164 return -EINVAL; 1165 1166 dsi2->lanes = device->lanes; 1167 dsi2->channel = device->channel; 1168 dsi2->format = device->format; 1169 dsi2->mode_flags = device->mode_flags; 1170 1171 dw_mipi_dsi2_get_dsc_params_from_sink(dsi2); 1172 1173 return 0; 1174 } 1175 1176 static const struct mipi_dsi_host_ops dw_mipi_dsi2_host_ops = { 1177 .attach = dw_mipi_dsi2_host_attach, 1178 .transfer = dw_mipi_dsi2_host_transfer, 1179 }; 1180 1181 static int dw_mipi_dsi2_bind(struct udevice *dev) 1182 { 1183 struct mipi_dsi_host *host = dev_get_platdata(dev); 1184 1185 host->dev = dev; 1186 host->ops = &dw_mipi_dsi2_host_ops; 1187 1188 return dm_scan_fdt_dev(dev); 1189 } 1190 1191 static int dw_mipi_dsi2_child_post_bind(struct udevice *dev) 1192 { 1193 struct mipi_dsi_host *host = dev_get_platdata(dev->parent); 1194 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1195 char name[20]; 1196 1197 sprintf(name, "%s.%d", host->dev->name, device->channel); 1198 device_set_name(dev, name); 1199 1200 device->dev = dev; 1201 device->host = host; 1202 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4); 1203 device->format = dev_read_u32_default(dev, "dsi,format", 1204 MIPI_DSI_FMT_RGB888); 1205 device->mode_flags = dev_read_u32_default(dev, "dsi,flags", 1206 MIPI_DSI_MODE_VIDEO | 1207 MIPI_DSI_MODE_VIDEO_BURST | 1208 MIPI_DSI_MODE_VIDEO_HBP | 1209 MIPI_DSI_MODE_LPM | 1210 MIPI_DSI_MODE_EOT_PACKET); 1211 device->channel = dev_read_u32_default(dev, "reg", 0); 1212 1213 return 0; 1214 } 1215 1216 static int dw_mipi_dsi2_child_pre_probe(struct udevice *dev) 1217 { 1218 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1219 int ret; 1220 1221 ret = mipi_dsi_attach(device); 1222 if (ret) { 1223 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret); 1224 return ret; 1225 } 1226 1227 return 0; 1228 } 1229 1230 U_BOOT_DRIVER(dw_mipi_dsi2) = { 1231 .name = "dw_mipi_dsi2", 1232 .id = UCLASS_DISPLAY, 1233 .of_match = dw_mipi_dsi2_ids, 1234 .probe = dw_mipi_dsi2_probe, 1235 .bind = dw_mipi_dsi2_bind, 1236 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi2), 1237 .per_child_platdata_auto_alloc_size = sizeof(struct mipi_dsi_device), 1238 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_host), 1239 .child_post_bind = dw_mipi_dsi2_child_post_bind, 1240 .child_pre_probe = dw_mipi_dsi2_child_pre_probe, 1241 }; 1242