1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Author: Guochun Huang <hero.huang@rock-chips.com> 7 */ 8 9 #include <drm/drm_mipi_dsi.h> 10 11 #include <config.h> 12 #include <common.h> 13 #include <errno.h> 14 #include <asm/unaligned.h> 15 #include <asm/gpio.h> 16 #include <asm/io.h> 17 #include <asm/hardware.h> 18 #include <dm/device.h> 19 #include <dm/read.h> 20 #include <dm/of_access.h> 21 #include <regmap.h> 22 #include <syscon.h> 23 #include <asm/arch-rockchip/clock.h> 24 #include <linux/iopoll.h> 25 26 #include "rockchip_display.h" 27 #include "rockchip_crtc.h" 28 #include "rockchip_connector.h" 29 #include "rockchip_panel.h" 30 #include "rockchip_phy.h" 31 32 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) 33 34 #define DSI2_PWR_UP 0x000c 35 #define RESET 0 36 #define POWER_UP BIT(0) 37 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 38 #define DSI2_SOFT_RESET 0x0010 39 #define SYS_RSTN BIT(2) 40 #define PHY_RSTN BIT(1) 41 #define IPI_RSTN BIT(0) 42 #define INT_ST_MAIN 0x0014 43 #define DSI2_MODE_CTRL 0x0018 44 #define DSI2_MODE_STATUS 0x001c 45 #define DSI2_CORE_STATUS 0x0020 46 #define PRI_RD_DATA_AVAIL BIT(26) 47 #define PRI_FIFOS_NOT_EMPTY BIT(25) 48 #define PRI_BUSY BIT(24) 49 #define CRI_RD_DATA_AVAIL BIT(18) 50 #define CRT_FIFOS_NOT_EMPTY BIT(17) 51 #define CRI_BUSY BIT(16) 52 #define IPI_FIFOS_NOT_EMPTY BIT(9) 53 #define IPI_BUSY BIT(8) 54 #define CORE_FIFOS_NOT_EMPTY BIT(1) 55 #define CORE_BUSY BIT(0) 56 #define MANUAL_MODE_CFG 0x0024 57 #define MANUAL_MODE_EN BIT(0) 58 #define DSI2_TIMEOUT_HSTX_CFG 0x0048 59 #define TO_HSTX(x) UPDATE(x, 15, 0) 60 #define DSI2_TIMEOUT_HSTXRDY_CFG 0x004c 61 #define TO_HSTXRDY(x) UPDATE(x, 15, 0) 62 #define DSI2_TIMEOUT_LPRX_CFG 0x0050 63 #define TO_LPRXRDY(x) UPDATE(x, 15, 0) 64 #define DSI2_TIMEOUT_LPTXRDY_CFG 0x0054 65 #define TO_LPTXRDY(x) UPDATE(x, 15, 0) 66 #define DSI2_TIMEOUT_LPTXTRIG_CFG 0x0058 67 #define TO_LPTXTRIG(x) UPDATE(x, 15, 0) 68 #define DSI2_TIMEOUT_LPTXULPS_CFG 0x005c 69 #define TO_LPTXULPS(x) UPDATE(x, 15, 0) 70 #define DSI2_TIMEOUT_BTA_CFG 0x60 71 #define TO_BTA(x) UPDATE(x, 15, 0) 72 73 #define DSI2_PHY_MODE_CFG 0x0100 74 #define PPI_WIDTH(x) UPDATE(x, 9, 8) 75 #define PHY_LANES(x) UPDATE(x - 1, 5, 4) 76 #define PHY_TYPE(x) UPDATE(x, 0, 0) 77 #define DSI2_PHY_CLK_CFG 0X0104 78 #define PHY_LPTX_CLK_DIV(x) UPDATE(x, 12, 8) 79 #define NON_CONTINUOUS_CLK BIT(0) 80 #define DSI2_PHY_LP2HS_MAN_CFG 0x010c 81 #define PHY_LP2HS_TIME(x) UPDATE(x, 28, 0) 82 #define DSI2_PHY_HS2LP_MAN_CFG 0x0114 83 #define PHY_HS2LP_TIME(x) UPDATE(x, 28, 0) 84 #define DSI2_PHY_MAX_RD_T_MAN_CFG 0x011c 85 #define PHY_MAX_RD_TIME(x) UPDATE(x, 26, 0) 86 #define DSI2_PHY_ESC_CMD_T_MAN_CFG 0x0124 87 #define PHY_ESC_CMD_TIME(x) UPDATE(x, 28, 0) 88 #define DSI2_PHY_ESC_BYTE_T_MAN_CFG 0x012c 89 #define PHY_ESC_BYTE_TIME(x) UPDATE(x, 28, 0) 90 91 #define DSI2_PHY_IPI_RATIO_MAN_CFG 0x0134 92 #define PHY_IPI_RATIO(x) UPDATE(x, 21, 0) 93 #define DSI2_PHY_SYS_RATIO_MAN_CFG 0x013C 94 #define PHY_SYS_RATIO(x) UPDATE(x, 16, 0) 95 96 #define DSI2_DSI_GENERAL_CFG 0x0200 97 #define BTA_EN BIT(1) 98 #define EOTP_TX_EN BIT(0) 99 #define DSI2_DSI_VCID_CFG 0x0204 100 #define TX_VCID(x) UPDATE(x, 1, 0) 101 #define DSI2_DSI_SCRAMBLING_CFG 0x0208 102 #define SCRAMBLING_SEED(x) UPDATE(x, 31, 16) 103 #define SCRAMBLING_EN BIT(0) 104 #define DSI2_DSI_VID_TX_CFG 0x020c 105 #define LPDT_DISPLAY_CMD_EN BIT(20) 106 #define BLK_VFP_HS_EN BIT(14) 107 #define BLK_VBP_HS_EN BIT(13) 108 #define BLK_VSA_HS_EN BIT(12) 109 #define BLK_HFP_HS_EN BIT(6) 110 #define BLK_HBP_HS_EN BIT(5) 111 #define BLK_HSA_HS_EN BIT(4) 112 #define VID_MODE_TYPE(x) UPDATE(x, 1, 0) 113 #define DSI2_CRI_TX_HDR 0x02c0 114 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 115 #define DSI2_CRI_TX_PLD 0x02c4 116 #define DSI2_CRI_RX_HDR 0x02c8 117 #define DSI2_CRI_RX_PLD 0x02cc 118 119 #define DSI2_IPI_COLOR_MAN_CFG 0x0300 120 #define IPI_DEPTH(x) UPDATE(x, 7, 4) 121 #define IPI_DEPTH_5_6_5_BITS 0x02 122 #define IPI_DEPTH_6_BITS 0x03 123 #define IPI_DEPTH_8_BITS 0x05 124 #define IPI_DEPTH_10_BITS 0x06 125 #define IPI_FORMAT(x) UPDATE(x, 3, 0) 126 #define IPI_FORMAT_RGB 0x0 127 #define IPI_FORMAT_DSC 0x0b 128 #define DSI2_IPI_VID_HSA_MAN_CFG 0x0304 129 #define VID_HSA_TIME(x) UPDATE(x, 29, 0) 130 #define DSI2_IPI_VID_HBP_MAN_CFG 0x030c 131 #define VID_HBP_TIME(x) UPDATE(x, 29, 0) 132 #define DSI2_IPI_VID_HACT_MAN_CFG 0x0314 133 #define VID_HACT_TIME(x) UPDATE(x, 29, 0) 134 #define DSI2_IPI_VID_HLINE_MAN_CFG 0x031c 135 #define VID_HLINE_TIME(x) UPDATE(x, 29, 0) 136 #define DSI2_IPI_VID_VSA_MAN_CFG 0x0324 137 #define VID_VSA_LINES(x) UPDATE(x, 9, 0) 138 #define DSI2_IPI_VID_VBP_MAN_CFG 0X032C 139 #define VID_VBP_LINES(x) UPDATE(x, 9, 0) 140 #define DSI2_IPI_VID_VACT_MAN_CFG 0X0334 141 #define VID_VACT_LINES(x) UPDATE(x, 13, 0) 142 #define DSI2_IPI_VID_VFP_MAN_CFG 0X033C 143 #define VID_VFP_LINES(x) UPDATE(x, 9, 0) 144 #define DSI2_IPI_PIX_PKT_CFG 0x0344 145 #define MAX_PIX_PKT(x) UPDATE(x, 15, 0) 146 147 #define DSI2_INT_ST_PHY 0x0400 148 #define DSI2_INT_MASK_PHY 0x0404 149 #define DSI2_INT_ST_TO 0x0410 150 #define DSI2_INT_MASK_TO 0x0414 151 #define DSI2_INT_ST_ACK 0x0420 152 #define DSI2_INT_MASK_ACK 0x0424 153 #define DSI2_INT_ST_IPI 0x0430 154 #define DSI2_INT_MASK_IPI 0x0434 155 #define DSI2_INT_ST_FIFO 0x0440 156 #define DSI2_INT_MASK_FIFO 0x0444 157 #define DSI2_INT_ST_PRI 0x0450 158 #define DSI2_INT_MASK_PRI 0x0454 159 #define DSI2_INT_ST_CRI 0x0460 160 #define DSI2_INT_MASK_CRI 0x0464 161 #define DSI2_INT_FORCE_CRI 0x0468 162 #define DSI2_MAX_REGISGER DSI2_INT_FORCE_CRI 163 164 #define CMD_PKT_STATUS_TIMEOUT_US 1000 165 #define MODE_STATUS_TIMEOUT_US 20000 166 #define SYS_CLK 351000000LL 167 #define PSEC_PER_SEC 1000000000000LL 168 #define USEC_PER_SEC 1000000L 169 #define MSEC_PER_SEC 1000L 170 171 #define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 16) | ((lsb) << 8) | (msb)) 172 173 enum vid_mode_type { 174 VID_MODE_TYPE_NON_BURST_SYNC_PULSES, 175 VID_MODE_TYPE_NON_BURST_SYNC_EVENTS, 176 VID_MODE_TYPE_BURST, 177 }; 178 179 enum mode_ctrl { 180 IDLE_MODE, 181 AUTOCALC_MODE, 182 COMMAND_MODE, 183 VIDEO_MODE, 184 DATA_STREAM_MODE, 185 VIDE_TEST_MODE, 186 DATA_STREAM_TEST_MODE, 187 }; 188 189 enum grf_reg_fields { 190 TXREQCLKHS_EN, 191 GATING_EN, 192 IPI_SHUTDN, 193 IPI_COLORM, 194 IPI_COLOR_DEPTH, 195 IPI_FORMAT, 196 MAX_FIELDS, 197 }; 198 199 enum phy_type { 200 DPHY, 201 CPHY, 202 }; 203 204 enum ppi_width { 205 PPI_WIDTH_8_BITS, 206 PPI_WIDTH_16_BITS, 207 PPI_WIDTH_32_BITS, 208 }; 209 210 struct rockchip_cmd_header { 211 u8 data_type; 212 u8 delay_ms; 213 u8 payload_length; 214 }; 215 216 struct dw_mipi_dsi2_plat_data { 217 const u32 *dsi0_grf_reg_fields; 218 const u32 *dsi1_grf_reg_fields; 219 unsigned long long dphy_max_bit_rate_per_lane; 220 unsigned long long cphy_max_symbol_rate_per_lane; 221 }; 222 223 struct mipi_dcphy { 224 /* Non-SNPS PHY */ 225 struct rockchip_phy *phy; 226 227 u16 input_div; 228 u16 feedback_div; 229 }; 230 231 /** 232 * struct mipi_dphy_configure - MIPI D-PHY configuration set 233 * 234 * This structure is used to represent the configuration state of a 235 * MIPI D-PHY phy. 236 */ 237 struct mipi_dphy_configure { 238 unsigned int clk_miss; 239 unsigned int clk_post; 240 unsigned int clk_pre; 241 unsigned int clk_prepare; 242 unsigned int clk_settle; 243 unsigned int clk_term_en; 244 unsigned int clk_trail; 245 unsigned int clk_zero; 246 unsigned int d_term_en; 247 unsigned int eot; 248 unsigned int hs_exit; 249 unsigned int hs_prepare; 250 unsigned int hs_settle; 251 unsigned int hs_skip; 252 unsigned int hs_trail; 253 unsigned int hs_zero; 254 unsigned int init; 255 unsigned int lpx; 256 unsigned int ta_get; 257 unsigned int ta_go; 258 unsigned int ta_sure; 259 unsigned int wakeup; 260 unsigned long hs_clk_rate; 261 unsigned long lp_clk_rate; 262 unsigned char lanes; 263 }; 264 265 struct dw_mipi_dsi2 { 266 struct rockchip_connector connector; 267 struct udevice *dev; 268 void *base; 269 void *grf; 270 int id; 271 struct dw_mipi_dsi2 *master; 272 struct dw_mipi_dsi2 *slave; 273 bool prepared; 274 275 bool c_option; 276 bool dsc_enable; 277 bool scrambling_en; 278 unsigned int slice_width; 279 unsigned int slice_height; 280 u32 version_major; 281 u32 version_minor; 282 283 unsigned int lane_hs_rate; /* Kbps/Ksps per lane */ 284 u32 channel; 285 u32 lanes; 286 u32 format; 287 u32 mode_flags; 288 struct mipi_dcphy dcphy; 289 struct drm_display_mode mode; 290 bool data_swap; 291 292 struct gpio_desc te_gpio; 293 struct mipi_dsi_device *device; 294 struct mipi_dphy_configure mipi_dphy_cfg; 295 const struct dw_mipi_dsi2_plat_data *pdata; 296 struct drm_dsc_picture_parameter_set *pps; 297 }; 298 299 static inline void dsi_write(struct dw_mipi_dsi2 *dsi2, u32 reg, u32 val) 300 { 301 writel(val, dsi2->base + reg); 302 } 303 304 static inline u32 dsi_read(struct dw_mipi_dsi2 *dsi2, u32 reg) 305 { 306 return readl(dsi2->base + reg); 307 } 308 309 static inline void dsi_update_bits(struct dw_mipi_dsi2 *dsi2, 310 u32 reg, u32 mask, u32 val) 311 { 312 u32 orig, tmp; 313 314 orig = dsi_read(dsi2, reg); 315 tmp = orig & ~mask; 316 tmp |= val & mask; 317 dsi_write(dsi2, reg, tmp); 318 } 319 320 static void grf_field_write(struct dw_mipi_dsi2 *dsi2, enum grf_reg_fields index, 321 unsigned int val) 322 { 323 const u32 field = dsi2->id ? dsi2->pdata->dsi1_grf_reg_fields[index] : 324 dsi2->pdata->dsi0_grf_reg_fields[index]; 325 u16 reg; 326 u8 msb, lsb; 327 328 if (!field) 329 return; 330 331 reg = (field >> 16) & 0xffff; 332 lsb = (field >> 8) & 0xff; 333 msb = (field >> 0) & 0xff; 334 335 regmap_write(dsi2->grf, reg, GENMASK(msb, lsb) << 16 | val << lsb); 336 } 337 338 static unsigned long dw_mipi_dsi2_get_lane_rate(struct dw_mipi_dsi2 *dsi2) 339 { 340 const struct drm_display_mode *mode = &dsi2->mode; 341 u64 max_lane_rate, lane_rate; 342 unsigned int value; 343 int bpp, lanes; 344 u64 tmp; 345 346 max_lane_rate = (dsi2->c_option) ? 347 dsi2->pdata->cphy_max_symbol_rate_per_lane : 348 dsi2->pdata->dphy_max_bit_rate_per_lane; 349 350 /* 351 * optional override of the desired bandwidth 352 * High-Speed mode: Differential and terminated: 80Mbps ~ 4500 Mbps 353 */ 354 value = dev_read_u32_default(dsi2->dev, "rockchip,lane-rate", 0); 355 if (value >= 80000 && value <= 4500000) 356 return value * MSEC_PER_SEC; 357 else if (value >= 80 && value <= 4500) 358 return value * USEC_PER_SEC; 359 360 bpp = mipi_dsi_pixel_format_to_bpp(dsi2->format); 361 if (bpp < 0) 362 bpp = 24; 363 364 lanes = dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes; 365 tmp = (u64)mode->crtc_clock * 1000 * bpp; 366 do_div(tmp, lanes); 367 368 if (dsi2->c_option) 369 tmp = DIV_ROUND_CLOSEST(tmp * 100, 228); 370 371 /* set BW a little larger only in video burst mode in 372 * consideration of the protocol overhead and HS mode 373 * switching to BLLP mode, take 1 / 0.9, since Mbps must 374 * big than bandwidth of RGB 375 */ 376 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { 377 tmp *= 10; 378 do_div(tmp, 9); 379 } 380 381 if (tmp > max_lane_rate) 382 lane_rate = max_lane_rate; 383 else 384 lane_rate = tmp; 385 386 return lane_rate; 387 } 388 389 static int cri_fifos_wait_avail(struct dw_mipi_dsi2 *dsi2) 390 { 391 u32 sts, mask; 392 int ret; 393 394 mask = CRI_BUSY | CRT_FIFOS_NOT_EMPTY; 395 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 396 sts, !(sts & mask), 397 CMD_PKT_STATUS_TIMEOUT_US); 398 if (ret < 0) { 399 printf("command interface is busy: 0x%x\n", sts); 400 return ret; 401 } 402 403 return 0; 404 } 405 406 static int dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 *dsi2, 407 const struct mipi_dsi_msg *msg) 408 { 409 u8 *payload = msg->rx_buf; 410 u8 data_type; 411 u16 wc; 412 int i, j, ret, len = msg->rx_len; 413 unsigned int vrefresh = drm_mode_vrefresh(&dsi2->mode); 414 u32 val; 415 416 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 417 val, val & CRI_RD_DATA_AVAIL, 418 DIV_ROUND_UP(1000000, vrefresh)); 419 if (ret) { 420 printf("CRI has no available read data\n"); 421 return ret; 422 } 423 424 val = dsi_read(dsi2, DSI2_CRI_RX_HDR); 425 data_type = val & 0x3f; 426 427 if (mipi_dsi_packet_format_is_short(data_type)) { 428 for (i = 0; i < len && i < 2; i++) 429 payload[i] = (val >> (8 * (i + 1))) & 0xff; 430 431 return 0; 432 } 433 434 wc = (val >> 8) & 0xffff; 435 /* Receive payload */ 436 for (i = 0; i < len && i < wc; i += 4) { 437 val = dsi_read(dsi2, DSI2_CRI_RX_PLD); 438 for (j = 0; j < 4 && j + i < len && j + i < wc; j++) 439 payload[i + j] = val >> (8 * j); 440 } 441 442 return 0; 443 } 444 445 static ssize_t dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 *dsi2, 446 const struct mipi_dsi_msg *msg) 447 { 448 struct mipi_dsi_packet packet; 449 int ret; 450 int val; 451 u32 mode; 452 453 dsi_update_bits(dsi2, DSI2_DSI_VID_TX_CFG, LPDT_DISPLAY_CMD_EN, 454 msg->flags & MIPI_DSI_MSG_USE_LPM ? 455 LPDT_DISPLAY_CMD_EN : 0); 456 457 /* create a packet to the DSI protocol */ 458 ret = mipi_dsi_create_packet(&packet, msg); 459 if (ret) { 460 printf("failed to create packet: %d\n", ret); 461 return ret; 462 } 463 464 /* check cri interface is not busy */ 465 ret = cri_fifos_wait_avail(dsi2); 466 if (ret) 467 return ret; 468 469 /* Send payload */ 470 while (DIV_ROUND_UP(packet.payload_length, 4)) { 471 if (packet.payload_length < 4) { 472 /* send residu payload */ 473 val = 0; 474 memcpy(&val, packet.payload, packet.payload_length); 475 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 476 packet.payload_length = 0; 477 } else { 478 val = get_unaligned_le32(packet.payload); 479 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 480 packet.payload += 4; 481 packet.payload_length -= 4; 482 } 483 } 484 485 /* Send packet header */ 486 mode = CMD_TX_MODE(msg->flags & MIPI_DSI_MSG_USE_LPM ? 1 : 0); 487 val = get_unaligned_le32(packet.header); 488 dsi_write(dsi2, DSI2_CRI_TX_HDR, mode | val); 489 490 ret = cri_fifos_wait_avail(dsi2); 491 if (ret) 492 return ret; 493 494 if (msg->rx_len) { 495 ret = dw_mipi_dsi2_read_from_fifo(dsi2, msg); 496 if (ret < 0) 497 return ret; 498 } 499 500 if (dsi2->slave) { 501 ret = dw_mipi_dsi2_transfer(dsi2->slave, msg); 502 if (ret < 0) 503 return ret; 504 } 505 506 return msg->rx_len ? msg->rx_len : msg->tx_len; 507 } 508 509 static void dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 *dsi2) 510 { 511 u32 val, color_depth; 512 513 switch (dsi2->format) { 514 case MIPI_DSI_FMT_RGB666: 515 case MIPI_DSI_FMT_RGB666_PACKED: 516 color_depth = IPI_DEPTH_6_BITS; 517 break; 518 case MIPI_DSI_FMT_RGB565: 519 color_depth = IPI_DEPTH_5_6_5_BITS; 520 break; 521 case MIPI_DSI_FMT_RGB888: 522 default: 523 color_depth = IPI_DEPTH_8_BITS; 524 break; 525 } 526 527 val = IPI_DEPTH(color_depth) | 528 IPI_FORMAT(dsi2->dsc_enable ? IPI_FORMAT_DSC : IPI_FORMAT_RGB); 529 dsi_write(dsi2, DSI2_IPI_COLOR_MAN_CFG, val); 530 grf_field_write(dsi2, IPI_COLOR_DEPTH, color_depth); 531 532 if (dsi2->dsc_enable) 533 grf_field_write(dsi2, IPI_FORMAT, IPI_FORMAT_DSC); 534 } 535 536 static void dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 *dsi2) 537 { 538 struct drm_display_mode *mode = &dsi2->mode; 539 u32 hline, hsa, hbp, hact; 540 u64 hline_time, hsa_time, hbp_time, hact_time, tmp; 541 u64 pixel_clk, phy_hs_clk; 542 u32 vact, vsa, vfp, vbp; 543 u16 val; 544 545 if (dsi2->slave || dsi2->master) 546 val = mode->hdisplay / 2; 547 else 548 val = mode->hdisplay; 549 550 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val)); 551 552 dw_mipi_dsi2_ipi_color_coding_cfg(dsi2); 553 554 /* 555 * if the controller is intended to operate in data stream mode, 556 * no more steps are required. 557 */ 558 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) 559 return; 560 561 vact = mode->vdisplay; 562 vsa = mode->vsync_end - mode->vsync_start; 563 vfp = mode->vsync_start - mode->vdisplay; 564 vbp = mode->vtotal - mode->vsync_end; 565 hact = mode->hdisplay; 566 hsa = mode->hsync_end - mode->hsync_start; 567 hbp = mode->htotal - mode->hsync_end; 568 hline = mode->htotal; 569 570 pixel_clk = mode->crtc_clock * MSEC_PER_SEC; 571 572 if (dsi2->c_option) 573 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 574 else 575 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 576 577 tmp = hsa * phy_hs_clk; 578 hsa_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 579 dsi_write(dsi2, DSI2_IPI_VID_HSA_MAN_CFG, VID_HSA_TIME(hsa_time)); 580 581 tmp = hbp * phy_hs_clk; 582 hbp_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 583 dsi_write(dsi2, DSI2_IPI_VID_HBP_MAN_CFG, VID_HBP_TIME(hbp_time)); 584 585 tmp = hact * phy_hs_clk; 586 hact_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 587 dsi_write(dsi2, DSI2_IPI_VID_HACT_MAN_CFG, VID_HACT_TIME(hact_time)); 588 589 tmp = hline * phy_hs_clk; 590 hline_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 591 dsi_write(dsi2, DSI2_IPI_VID_HLINE_MAN_CFG, VID_HLINE_TIME(hline_time)); 592 593 dsi_write(dsi2, DSI2_IPI_VID_VSA_MAN_CFG, VID_VSA_LINES(vsa)); 594 dsi_write(dsi2, DSI2_IPI_VID_VBP_MAN_CFG, VID_VBP_LINES(vbp)); 595 dsi_write(dsi2, DSI2_IPI_VID_VACT_MAN_CFG, VID_VACT_LINES(vact)); 596 dsi_write(dsi2, DSI2_IPI_VID_VFP_MAN_CFG, VID_VFP_LINES(vfp)); 597 } 598 599 static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2) 600 { 601 u32 val = 0, mode; 602 int ret; 603 604 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) 605 val |= BLK_HFP_HS_EN; 606 607 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) 608 val |= BLK_HBP_HS_EN; 609 610 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HSA) 611 val |= BLK_HSA_HS_EN; 612 613 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 614 val |= VID_MODE_TYPE_BURST; 615 else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 616 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 617 else 618 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 619 620 dsi_write(dsi2, DSI2_DSI_VID_TX_CFG, val); 621 622 dsi_write(dsi2, DSI2_MODE_CTRL, VIDEO_MODE); 623 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 624 mode, mode & VIDEO_MODE, 625 MODE_STATUS_TIMEOUT_US); 626 if (ret < 0) 627 printf("failed to enter video mode\n"); 628 } 629 630 static void dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 *dsi2) 631 { 632 u32 mode; 633 int ret; 634 635 dsi_write(dsi2, DSI2_MODE_CTRL, DATA_STREAM_MODE); 636 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 637 mode, mode & DATA_STREAM_MODE, 638 MODE_STATUS_TIMEOUT_US); 639 if (ret < 0) 640 printf("failed to enter data stream mode\n"); 641 } 642 643 static void dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 *dsi2) 644 { 645 u32 mode; 646 int ret; 647 648 dsi_write(dsi2, DSI2_MODE_CTRL, COMMAND_MODE); 649 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 650 mode, mode & COMMAND_MODE, 651 MODE_STATUS_TIMEOUT_US); 652 if (ret < 0) 653 printf("failed to enter cmd mode\n"); 654 } 655 656 static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2) 657 { 658 dw_mipi_dsi2_ipi_set(dsi2); 659 660 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO) 661 dw_mipi_dsi2_set_vid_mode(dsi2); 662 else 663 dw_mipi_dsi2_set_data_stream_mode(dsi2); 664 665 if (dsi2->slave) 666 dw_mipi_dsi2_enable(dsi2->slave); 667 } 668 669 static void dw_mipi_dsi2_disable(struct dw_mipi_dsi2 *dsi2) 670 { 671 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, 0); 672 dw_mipi_dsi2_set_cmd_mode(dsi2); 673 674 if (dsi2->slave) 675 dw_mipi_dsi2_disable(dsi2->slave); 676 } 677 678 static void dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 *dsi2) 679 { 680 if (!dsi2->prepared) 681 return; 682 683 dsi_write(dsi2, DSI2_PWR_UP, RESET); 684 685 if (dsi2->dcphy.phy) 686 rockchip_phy_power_off(dsi2->dcphy.phy); 687 688 dsi2->prepared = false; 689 690 if (dsi2->slave) 691 dw_mipi_dsi2_post_disable(dsi2->slave); 692 } 693 694 static int dw_mipi_dsi2_connector_pre_init(struct rockchip_connector *conn, 695 struct display_state *state) 696 { 697 struct connector_state *conn_state = &state->conn_state; 698 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 699 struct mipi_dsi_host *host = dev_get_platdata(dsi2->dev); 700 struct mipi_dsi_device *device; 701 char name[20]; 702 703 conn_state->type = DRM_MODE_CONNECTOR_DSI; 704 705 if (conn->bridge) { 706 device = dev_get_platdata(conn->bridge->dev); 707 if (!device) 708 return -ENODEV; 709 710 device->host = host; 711 sprintf(name, "%s.%d", host->dev->name, device->channel); 712 device_set_name(conn->bridge->dev, name); 713 mipi_dsi_attach(device); 714 } 715 716 return 0; 717 } 718 719 static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2) 720 { 721 struct udevice *dev = dsi2->device->dev; 722 struct rockchip_cmd_header *header; 723 struct drm_dsc_picture_parameter_set *pps = NULL; 724 u8 *dsc_packed_pps; 725 const void *data; 726 int len; 727 728 dsi2->c_option = dev_read_bool(dev, "phy-c-option"); 729 dsi2->scrambling_en = dev_read_bool(dev, "scrambling-enable"); 730 dsi2->dsc_enable = dev_read_bool(dev, "compressed-data"); 731 732 if (dsi2->slave) { 733 dsi2->slave->c_option = dsi2->c_option; 734 dsi2->slave->scrambling_en = dsi2->scrambling_en; 735 dsi2->slave->dsc_enable = dsi2->dsc_enable; 736 } 737 738 if (!dsi2->dsc_enable) 739 return 0; 740 741 dsi2->slice_width = dev_read_u32_default(dev, "slice-width", 0); 742 dsi2->slice_height = dev_read_u32_default(dev, "slice-height", 0); 743 dsi2->version_major = dev_read_u32_default(dev, "version-major", 0); 744 dsi2->version_minor = dev_read_u32_default(dev, "version-minor", 0); 745 746 data = dev_read_prop(dev, "panel-init-sequence", &len); 747 if (!data) 748 return -EINVAL; 749 750 while (len > sizeof(*header)) { 751 header = (struct rockchip_cmd_header *)data; 752 data += sizeof(*header); 753 len -= sizeof(*header); 754 755 if (header->payload_length > len) 756 return -EINVAL; 757 758 if (header->data_type == MIPI_DSI_PICTURE_PARAMETER_SET) { 759 dsc_packed_pps = calloc(1, header->payload_length); 760 if (!dsc_packed_pps) 761 return -ENOMEM; 762 763 memcpy(dsc_packed_pps, data, header->payload_length); 764 pps = (struct drm_dsc_picture_parameter_set *)dsc_packed_pps; 765 break; 766 } 767 768 data += header->payload_length; 769 len -= header->payload_length; 770 } 771 772 if (!pps) { 773 printf("not found dsc pps definition\n"); 774 return -EINVAL; 775 } 776 777 dsi2->pps = pps; 778 779 if (dsi2->slave) { 780 u16 pic_width = be16_to_cpu(pps->pic_width) / 2; 781 782 dsi2->pps->pic_width = cpu_to_be16(pic_width); 783 printf("dsc pic_width change from %d to %d\n", pic_width * 2, pic_width); 784 } 785 786 return 0; 787 } 788 789 static int dw_mipi_dsi2_connector_init(struct rockchip_connector *conn, struct display_state *state) 790 { 791 struct connector_state *conn_state = &state->conn_state; 792 struct crtc_state *cstate = &state->crtc_state; 793 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 794 struct rockchip_phy *phy = NULL; 795 struct udevice *phy_dev; 796 struct udevice *dev; 797 int ret; 798 799 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dsi2->id); 800 dsi2->dcphy.phy = conn->phy; 801 802 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 803 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 804 conn_state->output_if |= 805 dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0; 806 807 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) { 808 conn_state->output_flags |= ROCKCHIP_OUTPUT_MIPI_DS_MODE; 809 conn_state->hold_mode = true; 810 } 811 812 if (dsi2->lanes > 4) { 813 ret = uclass_get_device_by_name(UCLASS_DISPLAY, 814 "dsi@fde30000", 815 &dev); 816 if (ret) 817 return ret; 818 819 dsi2->slave = dev_get_priv(dev); 820 if (!dsi2->slave) 821 return -ENODEV; 822 823 dsi2->slave->master = dsi2; 824 dsi2->lanes /= 2; 825 dsi2->slave->lanes = dsi2->lanes; 826 dsi2->slave->format = dsi2->format; 827 dsi2->slave->mode_flags = dsi2->mode_flags; 828 dsi2->slave->channel = dsi2->channel; 829 conn_state->output_flags |= 830 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; 831 if (dsi2->data_swap) 832 conn_state->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP; 833 834 conn_state->output_if |= VOP_OUTPUT_IF_MIPI1; 835 836 ret = uclass_get_device_by_phandle(UCLASS_PHY, dev, 837 "phys", &phy_dev); 838 if (ret) 839 return -ENODEV; 840 841 phy = (struct rockchip_phy *)dev_get_driver_data(phy_dev); 842 if (!phy) 843 return -ENODEV; 844 845 dsi2->slave->dcphy.phy = phy; 846 if (phy->funcs && phy->funcs->init) 847 return phy->funcs->init(phy); 848 } 849 850 dw_mipi_dsi2_get_dsc_params_from_sink(dsi2); 851 852 if (dm_gpio_is_valid(&dsi2->te_gpio)) { 853 cstate->soft_te = true; 854 conn_state->te_gpio = &dsi2->te_gpio; 855 } 856 857 if (dsi2->dsc_enable) { 858 cstate->dsc_enable = 1; 859 cstate->dsc_sink_cap.version_major = dsi2->version_major; 860 cstate->dsc_sink_cap.version_minor = dsi2->version_minor; 861 cstate->dsc_sink_cap.slice_width = dsi2->slice_width; 862 cstate->dsc_sink_cap.slice_height = dsi2->slice_height; 863 /* only can support rgb888 panel now */ 864 cstate->dsc_sink_cap.target_bits_per_pixel_x16 = 8 << 4; 865 cstate->dsc_sink_cap.native_420 = 0; 866 memcpy(&cstate->pps, dsi2->pps, sizeof(struct drm_dsc_picture_parameter_set)); 867 } 868 869 return 0; 870 } 871 872 /* 873 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived 874 * from the valid ranges specified in Section 6.9, Table 14, Page 41 875 * of the D-PHY specification (v2.1). 876 */ 877 int mipi_dphy_get_default_config(unsigned long long hs_clk_rate, 878 struct mipi_dphy_configure *cfg) 879 { 880 unsigned long long ui; 881 882 if (!cfg) 883 return -EINVAL; 884 885 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); 886 do_div(ui, hs_clk_rate); 887 888 cfg->clk_miss = 0; 889 cfg->clk_post = 60000 + 52 * ui; 890 cfg->clk_pre = 8000; 891 cfg->clk_prepare = 38000; 892 cfg->clk_settle = 95000; 893 cfg->clk_term_en = 0; 894 cfg->clk_trail = 60000; 895 cfg->clk_zero = 262000; 896 cfg->d_term_en = 0; 897 cfg->eot = 0; 898 cfg->hs_exit = 100000; 899 cfg->hs_prepare = 40000 + 4 * ui; 900 cfg->hs_zero = 105000 + 6 * ui; 901 cfg->hs_settle = 85000 + 6 * ui; 902 cfg->hs_skip = 40000; 903 904 /* 905 * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40) 906 * contains this formula as: 907 * 908 * T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui) 909 * 910 * where n = 1 for forward-direction HS mode and n = 4 for reverse- 911 * direction HS mode. There's only one setting and this function does 912 * not parameterize on anything other that ui, so this code will 913 * assumes that reverse-direction HS mode is supported and uses n = 4. 914 */ 915 cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui); 916 917 cfg->init = 100; 918 cfg->lpx = 60000; 919 cfg->ta_get = 5 * cfg->lpx; 920 cfg->ta_go = 4 * cfg->lpx; 921 cfg->ta_sure = 2 * cfg->lpx; 922 cfg->wakeup = 1000; 923 924 return 0; 925 } 926 927 static void dw_mipi_dsi2_set_hs_clk(struct dw_mipi_dsi2 *dsi2, unsigned long rate) 928 { 929 mipi_dphy_get_default_config(rate, &dsi2->mipi_dphy_cfg); 930 931 if (!dsi2->c_option) 932 rockchip_phy_set_mode(dsi2->dcphy.phy, PHY_MODE_MIPI_DPHY); 933 934 rate = rockchip_phy_set_pll(dsi2->dcphy.phy, rate); 935 dsi2->lane_hs_rate = DIV_ROUND_CLOSEST(rate, MSEC_PER_SEC); 936 } 937 938 static void dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 *dsi2) 939 { 940 dsi_write(dsi2, DSI2_SOFT_RESET, 0X0); 941 udelay(100); 942 dsi_write(dsi2, DSI2_SOFT_RESET, SYS_RSTN | PHY_RSTN | IPI_RSTN); 943 } 944 945 static void 946 dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 *dsi2, u32 mode) 947 { 948 /* 949 * select controller work in Manual mode 950 * Manual: MANUAL_MODE_EN 951 * Automatic: 0 952 */ 953 dsi_write(dsi2, MANUAL_MODE_CFG, mode); 954 } 955 956 static void dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 *dsi2) 957 { 958 u32 val = 0; 959 960 /* PPI width is fixed to 16 bits in DCPHY */ 961 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes); 962 val |= PHY_TYPE(dsi2->c_option ? CPHY : DPHY); 963 dsi_write(dsi2, DSI2_PHY_MODE_CFG, val); 964 } 965 966 static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2) 967 { 968 u32 sys_clk = SYS_CLK / USEC_PER_SEC; 969 u32 esc_clk_div; 970 u32 val = 0; 971 972 if (dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 973 val |= NON_CONTINUOUS_CLK; 974 975 /* The Escape clock ranges from 1MHz to 20MHz. */ 976 esc_clk_div = DIV_ROUND_UP(sys_clk, 20 * 2); 977 val |= PHY_LPTX_CLK_DIV(esc_clk_div); 978 979 dsi_write(dsi2, DSI2_PHY_CLK_CFG, val); 980 } 981 982 static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2) 983 { 984 struct drm_display_mode *mode = &dsi2->mode; 985 u64 pixel_clk, ipi_clk, phy_hsclk, tmp; 986 987 /* 988 * in DPHY mode, the phy_hstx_clk is exactly 1/16 the Lane high-speed 989 * data rate; In CPHY mode, the phy_hstx_clk is exactly 1/7 the trio 990 * high speed symbol rate. 991 */ 992 if (dsi2->c_option) 993 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 994 995 else 996 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 997 998 /* IPI_RATIO_MAN_CFG = PHY_HSTX_CLK / IPI_CLK */ 999 pixel_clk = mode->crtc_clock * MSEC_PER_SEC; 1000 ipi_clk = pixel_clk / 4; 1001 1002 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, ipi_clk); 1003 dsi_write(dsi2, DSI2_PHY_IPI_RATIO_MAN_CFG, PHY_IPI_RATIO(tmp)); 1004 1005 /* SYS_RATIO_MAN_CFG = MIPI_DCPHY_HSCLK_Freq / SYS_CLK */ 1006 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, SYS_CLK); 1007 dsi_write(dsi2, DSI2_PHY_SYS_RATIO_MAN_CFG, PHY_SYS_RATIO(tmp)); 1008 } 1009 1010 static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2) 1011 { 1012 struct mipi_dphy_configure *cfg = &dsi2->mipi_dphy_cfg; 1013 unsigned long long tmp, ui; 1014 unsigned long long hstx_clk; 1015 1016 hstx_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 1017 1018 ui = ALIGN(PSEC_PER_SEC, hstx_clk); 1019 do_div(ui, hstx_clk); 1020 1021 /* PHY_LP2HS_TIME = (TLPX + THS-PREPARE + THS-ZERO) / Tphy_hstx_clk */ 1022 tmp = cfg->lpx + cfg->hs_prepare + cfg->hs_zero; 1023 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 1024 dsi_write(dsi2, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(tmp)); 1025 1026 /* PHY_HS2LP_TIME = (THS-TRAIL + THS-EXIT) / Tphy_hstx_clk */ 1027 tmp = cfg->hs_trail + cfg->hs_exit; 1028 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 1029 dsi_write(dsi2, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(tmp)); 1030 } 1031 1032 static void dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 *dsi2) 1033 { 1034 dw_mipi_dsi2_phy_mode_cfg(dsi2); 1035 dw_mipi_dsi2_phy_clk_mode_cfg(dsi2); 1036 dw_mipi_dsi2_phy_ratio_cfg(dsi2); 1037 dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(dsi2); 1038 1039 /* phy configuration 8 - 10 */ 1040 } 1041 1042 static void dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 *dsi2) 1043 { 1044 u32 val; 1045 1046 val = BTA_EN | EOTP_TX_EN; 1047 1048 if (dsi2->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 1049 val &= ~EOTP_TX_EN; 1050 1051 dsi_write(dsi2, DSI2_DSI_GENERAL_CFG, val); 1052 dsi_write(dsi2, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel)); 1053 1054 if (dsi2->scrambling_en) 1055 dsi_write(dsi2, DSI2_DSI_SCRAMBLING_CFG, SCRAMBLING_EN); 1056 } 1057 1058 static void dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 *dsi2, bool enable) 1059 { 1060 if (enable) { 1061 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x1); 1062 dsi_write(dsi2, DSI2_INT_MASK_TO, 0xf); 1063 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x1); 1064 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x1); 1065 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x1); 1066 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x1); 1067 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x1); 1068 } else { 1069 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x0); 1070 dsi_write(dsi2, DSI2_INT_MASK_TO, 0x0); 1071 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x0); 1072 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x0); 1073 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x0); 1074 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x0); 1075 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x0); 1076 }; 1077 } 1078 1079 static void mipi_dcphy_power_on(struct dw_mipi_dsi2 *dsi2) 1080 { 1081 if (!dsi2->dcphy.phy) 1082 return; 1083 1084 rockchip_phy_power_on(dsi2->dcphy.phy); 1085 } 1086 1087 static void dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 *dsi2) 1088 { 1089 if (dsi2->prepared) 1090 return; 1091 1092 dw_mipi_dsi2_host_softrst(dsi2); 1093 dsi_write(dsi2, DSI2_PWR_UP, RESET); 1094 1095 dw_mipi_dsi2_work_mode(dsi2, MANUAL_MODE_EN); 1096 dw_mipi_dsi2_phy_init(dsi2); 1097 dw_mipi_dsi2_tx_option_set(dsi2); 1098 dw_mipi_dsi2_irq_enable(dsi2, 0); 1099 mipi_dcphy_power_on(dsi2); 1100 dsi_write(dsi2, DSI2_PWR_UP, POWER_UP); 1101 dw_mipi_dsi2_set_cmd_mode(dsi2); 1102 1103 dsi2->prepared = true; 1104 1105 if (dsi2->slave) 1106 dw_mipi_dsi2_pre_enable(dsi2->slave); 1107 } 1108 1109 static int dw_mipi_dsi2_connector_prepare(struct rockchip_connector *conn, 1110 struct display_state *state) 1111 { 1112 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1113 struct connector_state *conn_state = &state->conn_state; 1114 unsigned long lane_rate; 1115 1116 memcpy(&dsi2->mode, &conn_state->mode, sizeof(struct drm_display_mode)); 1117 if (dsi2->slave) 1118 memcpy(&dsi2->slave->mode, &dsi2->mode, 1119 sizeof(struct drm_display_mode)); 1120 1121 lane_rate = dw_mipi_dsi2_get_lane_rate(dsi2); 1122 if (dsi2->dcphy.phy) 1123 dw_mipi_dsi2_set_hs_clk(dsi2, lane_rate); 1124 1125 if (dsi2->slave && dsi2->slave->dcphy.phy) 1126 dw_mipi_dsi2_set_hs_clk(dsi2->slave, lane_rate); 1127 1128 printf("final DSI-Link bandwidth: %u %s x %d\n", 1129 dsi2->lane_hs_rate, dsi2->c_option ? "Ksps" : "Kbps", 1130 dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes); 1131 1132 dw_mipi_dsi2_pre_enable(dsi2); 1133 1134 return 0; 1135 } 1136 1137 static void dw_mipi_dsi2_connector_unprepare(struct rockchip_connector *conn, 1138 struct display_state *state) 1139 { 1140 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1141 1142 dw_mipi_dsi2_post_disable(dsi2); 1143 } 1144 1145 static int dw_mipi_dsi2_connector_enable(struct rockchip_connector *conn, 1146 struct display_state *state) 1147 { 1148 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1149 1150 dw_mipi_dsi2_enable(dsi2); 1151 1152 return 0; 1153 } 1154 1155 static int dw_mipi_dsi2_connector_disable(struct rockchip_connector *conn, 1156 struct display_state *state) 1157 { 1158 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1159 1160 dw_mipi_dsi2_disable(dsi2); 1161 1162 return 0; 1163 } 1164 1165 static int dw_mipi_dsi2_connector_mode_valid(struct rockchip_connector *conn, 1166 struct display_state *state) 1167 { 1168 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev); 1169 struct connector_state *conn_state = &state->conn_state; 1170 u8 min_pixels = dsi2->slave ? 8 : 4; 1171 struct videomode vm; 1172 1173 drm_display_mode_to_videomode(&conn_state->mode, &vm); 1174 1175 /* 1176 * the minimum region size (HSA,HBP,HACT,HFP) is 4 pixels 1177 * which is the ip known issues and limitations. 1178 */ 1179 if (!(vm.hsync_len < min_pixels || vm.hback_porch < min_pixels || 1180 vm.hfront_porch < min_pixels || vm.hactive < min_pixels)) 1181 return MODE_OK; 1182 1183 if (vm.hsync_len < min_pixels) 1184 vm.hsync_len = min_pixels; 1185 1186 if (vm.hback_porch < min_pixels) 1187 vm.hback_porch = min_pixels; 1188 1189 if (vm.hfront_porch < min_pixels) 1190 vm.hfront_porch = min_pixels; 1191 1192 if (vm.hactive < min_pixels) 1193 vm.hactive = min_pixels; 1194 1195 memset(&conn_state->mode, 0, sizeof(struct drm_display_mode)); 1196 drm_display_mode_from_videomode(&vm, &conn_state->mode); 1197 conn_state->mode.vrefresh = drm_mode_vrefresh(&conn_state->mode); 1198 1199 return MODE_OK; 1200 } 1201 1202 static const struct rockchip_connector_funcs dw_mipi_dsi2_connector_funcs = { 1203 .pre_init = dw_mipi_dsi2_connector_pre_init, 1204 .init = dw_mipi_dsi2_connector_init, 1205 .prepare = dw_mipi_dsi2_connector_prepare, 1206 .unprepare = dw_mipi_dsi2_connector_unprepare, 1207 .enable = dw_mipi_dsi2_connector_enable, 1208 .disable = dw_mipi_dsi2_connector_disable, 1209 .mode_valid = dw_mipi_dsi2_connector_mode_valid, 1210 }; 1211 1212 static int dw_mipi_dsi2_probe(struct udevice *dev) 1213 { 1214 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(dev); 1215 const struct dw_mipi_dsi2_plat_data *pdata = 1216 (const struct dw_mipi_dsi2_plat_data *)dev_get_driver_data(dev); 1217 struct udevice *syscon; 1218 int id, ret; 1219 1220 dsi2->base = dev_read_addr_ptr(dev); 1221 1222 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1223 &syscon); 1224 if (!ret) { 1225 dsi2->grf = syscon_get_regmap(syscon); 1226 if (!dsi2->grf) 1227 return -ENODEV; 1228 } 1229 1230 id = of_alias_get_id(ofnode_to_np(dev->node), "dsi"); 1231 if (id < 0) 1232 id = 0; 1233 1234 ret = gpio_request_by_name(dev, "te-gpios", 0, 1235 &dsi2->te_gpio, GPIOD_IS_IN); 1236 if (ret && ret != -ENOENT) { 1237 printf("%s: Cannot get TE GPIO: %d\n", __func__, ret); 1238 return ret; 1239 } 1240 1241 dsi2->dev = dev; 1242 dsi2->pdata = pdata; 1243 dsi2->id = id; 1244 dsi2->data_swap = dev_read_bool(dsi2->dev, "rockchip,data-swap"); 1245 1246 rockchip_connector_bind(&dsi2->connector, dev, id, &dw_mipi_dsi2_connector_funcs, NULL, 1247 DRM_MODE_CONNECTOR_DSI); 1248 1249 return 0; 1250 } 1251 1252 static const u32 rk3588_dsi0_grf_reg_fields[MAX_FIELDS] = { 1253 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0000, 11, 11), 1254 [GATING_EN] = GRF_REG_FIELD(0x0000, 10, 10), 1255 [IPI_SHUTDN] = GRF_REG_FIELD(0x0000, 9, 9), 1256 [IPI_COLORM] = GRF_REG_FIELD(0x0000, 8, 8), 1257 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0000, 4, 7), 1258 [IPI_FORMAT] = GRF_REG_FIELD(0x0000, 0, 3), 1259 }; 1260 1261 static const u32 rk3588_dsi1_grf_reg_fields[MAX_FIELDS] = { 1262 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0004, 11, 11), 1263 [GATING_EN] = GRF_REG_FIELD(0x0004, 10, 10), 1264 [IPI_SHUTDN] = GRF_REG_FIELD(0x0004, 9, 9), 1265 [IPI_COLORM] = GRF_REG_FIELD(0x0004, 8, 8), 1266 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0004, 4, 7), 1267 [IPI_FORMAT] = GRF_REG_FIELD(0x0004, 0, 3), 1268 }; 1269 1270 static const struct dw_mipi_dsi2_plat_data rk3588_mipi_dsi2_plat_data = { 1271 .dsi0_grf_reg_fields = rk3588_dsi0_grf_reg_fields, 1272 .dsi1_grf_reg_fields = rk3588_dsi1_grf_reg_fields, 1273 .dphy_max_bit_rate_per_lane = 4500000000ULL, 1274 .cphy_max_symbol_rate_per_lane = 2000000000ULL, 1275 }; 1276 1277 static const struct udevice_id dw_mipi_dsi2_ids[] = { 1278 { 1279 .compatible = "rockchip,rk3588-mipi-dsi2", 1280 .data = (ulong)&rk3588_mipi_dsi2_plat_data, 1281 }, 1282 {} 1283 }; 1284 1285 static ssize_t dw_mipi_dsi2_host_transfer(struct mipi_dsi_host *host, 1286 const struct mipi_dsi_msg *msg) 1287 { 1288 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1289 1290 return dw_mipi_dsi2_transfer(dsi2, msg); 1291 } 1292 1293 static int dw_mipi_dsi2_host_attach(struct mipi_dsi_host *host, 1294 struct mipi_dsi_device *device) 1295 { 1296 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1297 1298 if (device->lanes < 1 || device->lanes > 8) 1299 return -EINVAL; 1300 1301 dsi2->lanes = device->lanes; 1302 dsi2->channel = device->channel; 1303 dsi2->format = device->format; 1304 dsi2->mode_flags = device->mode_flags; 1305 dsi2->device = device; 1306 1307 return 0; 1308 } 1309 1310 static const struct mipi_dsi_host_ops dw_mipi_dsi2_host_ops = { 1311 .attach = dw_mipi_dsi2_host_attach, 1312 .transfer = dw_mipi_dsi2_host_transfer, 1313 }; 1314 1315 static int dw_mipi_dsi2_bind(struct udevice *dev) 1316 { 1317 struct mipi_dsi_host *host = dev_get_platdata(dev); 1318 1319 host->dev = dev; 1320 host->ops = &dw_mipi_dsi2_host_ops; 1321 1322 return dm_scan_fdt_dev(dev); 1323 } 1324 1325 static int dw_mipi_dsi2_child_post_bind(struct udevice *dev) 1326 { 1327 struct mipi_dsi_host *host = dev_get_platdata(dev->parent); 1328 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1329 char name[20]; 1330 1331 sprintf(name, "%s.%d", host->dev->name, device->channel); 1332 device_set_name(dev, name); 1333 1334 device->dev = dev; 1335 device->host = host; 1336 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4); 1337 device->format = dev_read_u32_default(dev, "dsi,format", 1338 MIPI_DSI_FMT_RGB888); 1339 device->mode_flags = dev_read_u32_default(dev, "dsi,flags", 1340 MIPI_DSI_MODE_VIDEO | 1341 MIPI_DSI_MODE_VIDEO_BURST | 1342 MIPI_DSI_MODE_VIDEO_HBP | 1343 MIPI_DSI_MODE_LPM | 1344 MIPI_DSI_MODE_EOT_PACKET); 1345 device->channel = dev_read_u32_default(dev, "reg", 0); 1346 1347 return 0; 1348 } 1349 1350 static int dw_mipi_dsi2_child_pre_probe(struct udevice *dev) 1351 { 1352 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1353 int ret; 1354 1355 ret = mipi_dsi_attach(device); 1356 if (ret) { 1357 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret); 1358 return ret; 1359 } 1360 1361 return 0; 1362 } 1363 1364 U_BOOT_DRIVER(dw_mipi_dsi2) = { 1365 .name = "dw_mipi_dsi2", 1366 .id = UCLASS_DISPLAY, 1367 .of_match = dw_mipi_dsi2_ids, 1368 .probe = dw_mipi_dsi2_probe, 1369 .bind = dw_mipi_dsi2_bind, 1370 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi2), 1371 .per_child_platdata_auto_alloc_size = sizeof(struct mipi_dsi_device), 1372 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_host), 1373 .child_post_bind = dw_mipi_dsi2_child_post_bind, 1374 .child_pre_probe = dw_mipi_dsi2_child_pre_probe, 1375 }; 1376