1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Author: Guochun Huang <hero.huang@rock-chips.com> 7 */ 8 9 #include <drm/drm_mipi_dsi.h> 10 11 #include <config.h> 12 #include <common.h> 13 #include <errno.h> 14 #include <asm/unaligned.h> 15 #include <asm/io.h> 16 #include <asm/hardware.h> 17 #include <dm/device.h> 18 #include <dm/read.h> 19 #include <dm/of_access.h> 20 #include <regmap.h> 21 #include <syscon.h> 22 #include <asm/arch-rockchip/clock.h> 23 #include <linux/iopoll.h> 24 25 #include "rockchip_display.h" 26 #include "rockchip_crtc.h" 27 #include "rockchip_connector.h" 28 #include "rockchip_panel.h" 29 #include "rockchip_phy.h" 30 31 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) 32 33 #define DSI2_PWR_UP 0x000c 34 #define RESET 0 35 #define POWER_UP BIT(0) 36 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 37 #define DSI2_SOFT_RESET 0x0010 38 #define SYS_RSTN BIT(2) 39 #define PHY_RSTN BIT(1) 40 #define IPI_RSTN BIT(0) 41 #define INT_ST_MAIN 0x0014 42 #define DSI2_MODE_CTRL 0x0018 43 #define DSI2_MODE_STATUS 0x001c 44 #define DSI2_CORE_STATUS 0x0020 45 #define PRI_RD_DATA_AVAIL BIT(26) 46 #define PRI_FIFOS_NOT_EMPTY BIT(25) 47 #define PRI_BUSY BIT(24) 48 #define CRI_RD_DATA_AVAIL BIT(18) 49 #define CRT_FIFOS_NOT_EMPTY BIT(17) 50 #define CRI_BUSY BIT(16) 51 #define IPI_FIFOS_NOT_EMPTY BIT(9) 52 #define IPI_BUSY BIT(8) 53 #define CORE_FIFOS_NOT_EMPTY BIT(1) 54 #define CORE_BUSY BIT(0) 55 #define MANUAL_MODE_CFG 0x0024 56 #define MANUAL_MODE_EN BIT(0) 57 #define DSI2_TIMEOUT_HSTX_CFG 0x0048 58 #define TO_HSTX(x) UPDATE(x, 15, 0) 59 #define DSI2_TIMEOUT_HSTXRDY_CFG 0x004c 60 #define TO_HSTXRDY(x) UPDATE(x, 15, 0) 61 #define DSI2_TIMEOUT_LPRX_CFG 0x0050 62 #define TO_LPRXRDY(x) UPDATE(x, 15, 0) 63 #define DSI2_TIMEOUT_LPTXRDY_CFG 0x0054 64 #define TO_LPTXRDY(x) UPDATE(x, 15, 0) 65 #define DSI2_TIMEOUT_LPTXTRIG_CFG 0x0058 66 #define TO_LPTXTRIG(x) UPDATE(x, 15, 0) 67 #define DSI2_TIMEOUT_LPTXULPS_CFG 0x005c 68 #define TO_LPTXULPS(x) UPDATE(x, 15, 0) 69 #define DSI2_TIMEOUT_BTA_CFG 0x60 70 #define TO_BTA(x) UPDATE(x, 15, 0) 71 72 #define DSI2_PHY_MODE_CFG 0x0100 73 #define PPI_WIDTH(x) UPDATE(x, 9, 8) 74 #define PHY_LANES(x) UPDATE(x - 1, 5, 4) 75 #define PHY_TYPE(x) UPDATE(x, 0, 0) 76 #define DSI2_PHY_CLK_CFG 0X0104 77 #define PHY_LPTX_CLK_DIV(x) UPDATE(x, 12, 8) 78 #define NON_CONTINUOUS_CLK BIT(0) 79 #define DSI2_PHY_LP2HS_MAN_CFG 0x010c 80 #define PHY_LP2HS_TIME(x) UPDATE(x, 28, 0) 81 #define DSI2_PHY_HS2LP_MAN_CFG 0x0114 82 #define PHY_HS2LP_TIME(x) UPDATE(x, 28, 0) 83 #define DSI2_PHY_MAX_RD_T_MAN_CFG 0x011c 84 #define PHY_MAX_RD_TIME(x) UPDATE(x, 26, 0) 85 #define DSI2_PHY_ESC_CMD_T_MAN_CFG 0x0124 86 #define PHY_ESC_CMD_TIME(x) UPDATE(x, 28, 0) 87 #define DSI2_PHY_ESC_BYTE_T_MAN_CFG 0x012c 88 #define PHY_ESC_BYTE_TIME(x) UPDATE(x, 28, 0) 89 90 #define DSI2_PHY_IPI_RATIO_MAN_CFG 0x0134 91 #define PHY_IPI_RATIO(x) UPDATE(x, 21, 0) 92 #define DSI2_PHY_SYS_RATIO_MAN_CFG 0x013C 93 #define PHY_SYS_RATIO(x) UPDATE(x, 16, 0) 94 95 #define DSI2_DSI_GENERAL_CFG 0x0200 96 #define BTA_EN BIT(1) 97 #define EOTP_TX_EN BIT(0) 98 #define DSI2_DSI_VCID_CFG 0x0204 99 #define TX_VCID(x) UPDATE(x, 1, 0) 100 #define DSI2_DSI_SCRAMBLING_CFG 0x0208 101 #define SCRAMBLING_SEED(x) UPDATE(x, 31, 16) 102 #define SCRAMBLING_EN BIT(0) 103 #define DSI2_DSI_VID_TX_CFG 0x020c 104 #define LPDT_DISPLAY_CMD_EN BIT(20) 105 #define BLK_VFP_HS_EN BIT(14) 106 #define BLK_VBP_HS_EN BIT(13) 107 #define BLK_VSA_HS_EN BIT(12) 108 #define BLK_HFP_HS_EN BIT(6) 109 #define BLK_HBP_HS_EN BIT(5) 110 #define BLK_HSA_HS_EN BIT(4) 111 #define VID_MODE_TYPE(x) UPDATE(x, 1, 0) 112 #define DSI2_CRI_TX_HDR 0x02c0 113 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 114 #define DSI2_CRI_TX_PLD 0x02c4 115 #define DSI2_CRI_RX_HDR 0x02c8 116 #define DSI2_CRI_RX_PLD 0x02cc 117 118 #define DSI2_IPI_COLOR_MAN_CFG 0x0300 119 #define IPI_DEPTH(x) UPDATE(x, 7, 4) 120 #define IPI_DEPTH_5_6_5_BITS 0x02 121 #define IPI_DEPTH_6_BITS 0x03 122 #define IPI_DEPTH_8_BITS 0x05 123 #define IPI_DEPTH_10_BITS 0x06 124 #define IPI_FORMAT(x) UPDATE(x, 3, 0) 125 #define IPI_FORMAT_RGB 0x0 126 #define IPI_FORMAT_DSC 0x0b 127 #define DSI2_IPI_VID_HSA_MAN_CFG 0x0304 128 #define VID_HSA_TIME(x) UPDATE(x, 29, 0) 129 #define DSI2_IPI_VID_HBP_MAN_CFG 0x030c 130 #define VID_HBP_TIME(x) UPDATE(x, 29, 0) 131 #define DSI2_IPI_VID_HACT_MAN_CFG 0x0314 132 #define VID_HACT_TIME(x) UPDATE(x, 29, 0) 133 #define DSI2_IPI_VID_HLINE_MAN_CFG 0x031c 134 #define VID_HLINE_TIME(x) UPDATE(x, 29, 0) 135 #define DSI2_IPI_VID_VSA_MAN_CFG 0x0324 136 #define VID_VSA_LINES(x) UPDATE(x, 9, 0) 137 #define DSI2_IPI_VID_VBP_MAN_CFG 0X032C 138 #define VID_VBP_LINES(x) UPDATE(x, 9, 0) 139 #define DSI2_IPI_VID_VACT_MAN_CFG 0X0334 140 #define VID_VACT_LINES(x) UPDATE(x, 13, 0) 141 #define DSI2_IPI_VID_VFP_MAN_CFG 0X033C 142 #define VID_VFP_LINES(x) UPDATE(x, 9, 0) 143 #define DSI2_IPI_PIX_PKT_CFG 0x0344 144 #define MAX_PIX_PKT(x) UPDATE(x, 15, 0) 145 146 #define DSI2_INT_ST_PHY 0x0400 147 #define DSI2_INT_MASK_PHY 0x0404 148 #define DSI2_INT_ST_TO 0x0410 149 #define DSI2_INT_MASK_TO 0x0414 150 #define DSI2_INT_ST_ACK 0x0420 151 #define DSI2_INT_MASK_ACK 0x0424 152 #define DSI2_INT_ST_IPI 0x0430 153 #define DSI2_INT_MASK_IPI 0x0434 154 #define DSI2_INT_ST_FIFO 0x0440 155 #define DSI2_INT_MASK_FIFO 0x0444 156 #define DSI2_INT_ST_PRI 0x0450 157 #define DSI2_INT_MASK_PRI 0x0454 158 #define DSI2_INT_ST_CRI 0x0460 159 #define DSI2_INT_MASK_CRI 0x0464 160 #define DSI2_INT_FORCE_CRI 0x0468 161 #define DSI2_MAX_REGISGER DSI2_INT_FORCE_CRI 162 163 #define CMD_PKT_STATUS_TIMEOUT_US 1000 164 #define MODE_STATUS_TIMEOUT_US 20000 165 #define SYS_CLK 351000000LL 166 #define PSEC_PER_SEC 1000000000000LL 167 #define USEC_PER_SEC 1000000L 168 #define MSEC_PER_SEC 1000L 169 170 #define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 16) | ((lsb) << 8) | (msb)) 171 172 enum vid_mode_type { 173 VID_MODE_TYPE_NON_BURST_SYNC_PULSES, 174 VID_MODE_TYPE_NON_BURST_SYNC_EVENTS, 175 VID_MODE_TYPE_BURST, 176 }; 177 178 enum mode_ctrl { 179 IDLE_MODE, 180 AUTOCALC_MODE, 181 COMMAND_MODE, 182 VIDEO_MODE, 183 DATA_STREAM_MODE, 184 VIDE_TEST_MODE, 185 DATA_STREAM_TEST_MODE, 186 }; 187 188 enum grf_reg_fields { 189 TXREQCLKHS_EN, 190 GATING_EN, 191 IPI_SHUTDN, 192 IPI_COLORM, 193 IPI_COLOR_DEPTH, 194 IPI_FORMAT, 195 MAX_FIELDS, 196 }; 197 198 enum phy_type { 199 DPHY, 200 CPHY, 201 }; 202 203 enum ppi_width { 204 PPI_WIDTH_8_BITS, 205 PPI_WIDTH_16_BITS, 206 PPI_WIDTH_32_BITS, 207 }; 208 209 struct dw_mipi_dsi2_plat_data { 210 const u32 *dsi0_grf_reg_fields; 211 const u32 *dsi1_grf_reg_fields; 212 unsigned long long dphy_max_bit_rate_per_lane; 213 unsigned long long cphy_max_symbol_rate_per_lane; 214 }; 215 216 struct mipi_dcphy { 217 /* Non-SNPS PHY */ 218 struct rockchip_phy *phy; 219 220 u16 input_div; 221 u16 feedback_div; 222 }; 223 224 /** 225 * struct mipi_dphy_configure - MIPI D-PHY configuration set 226 * 227 * This structure is used to represent the configuration state of a 228 * MIPI D-PHY phy. 229 */ 230 struct mipi_dphy_configure { 231 unsigned int clk_miss; 232 unsigned int clk_post; 233 unsigned int clk_pre; 234 unsigned int clk_prepare; 235 unsigned int clk_settle; 236 unsigned int clk_term_en; 237 unsigned int clk_trail; 238 unsigned int clk_zero; 239 unsigned int d_term_en; 240 unsigned int eot; 241 unsigned int hs_exit; 242 unsigned int hs_prepare; 243 unsigned int hs_settle; 244 unsigned int hs_skip; 245 unsigned int hs_trail; 246 unsigned int hs_zero; 247 unsigned int init; 248 unsigned int lpx; 249 unsigned int ta_get; 250 unsigned int ta_go; 251 unsigned int ta_sure; 252 unsigned int wakeup; 253 unsigned long hs_clk_rate; 254 unsigned long lp_clk_rate; 255 unsigned char lanes; 256 }; 257 258 struct dw_mipi_dsi2 { 259 struct udevice *dev; 260 void *base; 261 void *grf; 262 int id; 263 struct dw_mipi_dsi2 *master; 264 struct dw_mipi_dsi2 *slave; 265 bool prepared; 266 267 bool c_option; 268 bool dsc_enable; 269 bool scrambling_en; 270 unsigned int slice_width; 271 unsigned int slice_height; 272 u32 version_major; 273 u32 version_minor; 274 275 unsigned int lane_hs_rate; /* Kbps/Ksps per lane */ 276 u32 channel; 277 u32 lanes; 278 u32 format; 279 u32 mode_flags; 280 struct mipi_dcphy dcphy; 281 struct drm_display_mode mode; 282 bool data_swap; 283 284 struct mipi_dphy_configure mipi_dphy_cfg; 285 const struct dw_mipi_dsi2_plat_data *pdata; 286 }; 287 288 static inline void dsi_write(struct dw_mipi_dsi2 *dsi2, u32 reg, u32 val) 289 { 290 writel(val, dsi2->base + reg); 291 } 292 293 static inline u32 dsi_read(struct dw_mipi_dsi2 *dsi2, u32 reg) 294 { 295 return readl(dsi2->base + reg); 296 } 297 298 static inline void dsi_update_bits(struct dw_mipi_dsi2 *dsi2, 299 u32 reg, u32 mask, u32 val) 300 { 301 u32 orig, tmp; 302 303 orig = dsi_read(dsi2, reg); 304 tmp = orig & ~mask; 305 tmp |= val & mask; 306 dsi_write(dsi2, reg, tmp); 307 } 308 309 static void grf_field_write(struct dw_mipi_dsi2 *dsi2, enum grf_reg_fields index, 310 unsigned int val) 311 { 312 const u32 field = dsi2->id ? dsi2->pdata->dsi1_grf_reg_fields[index] : 313 dsi2->pdata->dsi0_grf_reg_fields[index]; 314 u16 reg; 315 u8 msb, lsb; 316 317 if (!field) 318 return; 319 320 reg = (field >> 16) & 0xffff; 321 lsb = (field >> 8) & 0xff; 322 msb = (field >> 0) & 0xff; 323 324 regmap_write(dsi2->grf, reg, GENMASK(msb, lsb) << 16 | val << lsb); 325 } 326 327 static unsigned long dw_mipi_dsi2_get_lane_rate(struct dw_mipi_dsi2 *dsi2) 328 { 329 const struct drm_display_mode *mode = &dsi2->mode; 330 u64 max_lane_rate, lane_rate; 331 unsigned int value; 332 int bpp, lanes; 333 u64 tmp; 334 335 max_lane_rate = (dsi2->c_option) ? 336 dsi2->pdata->cphy_max_symbol_rate_per_lane : 337 dsi2->pdata->dphy_max_bit_rate_per_lane; 338 339 /* optional override of the desired bandwidth */ 340 value = dev_read_u32_default(dsi2->dev, "rockchip,lane-rate", 0); 341 if (value > 0) 342 return value * MSEC_PER_SEC; 343 344 bpp = mipi_dsi_pixel_format_to_bpp(dsi2->format); 345 if (bpp < 0) 346 bpp = 24; 347 348 lanes = dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes; 349 tmp = (u64)mode->clock * 1000 * bpp; 350 do_div(tmp, lanes); 351 352 if (dsi2->c_option) 353 tmp = DIV_ROUND_CLOSEST(tmp * 100, 228); 354 355 /* set BW a little larger only in video burst mode in 356 * consideration of the protocol overhead and HS mode 357 * switching to BLLP mode, take 1 / 0.9, since Mbps must 358 * big than bandwidth of RGB 359 */ 360 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { 361 tmp *= 10; 362 do_div(tmp, 9); 363 } 364 365 if (tmp > max_lane_rate) 366 lane_rate = max_lane_rate; 367 else 368 lane_rate = tmp; 369 370 return lane_rate; 371 } 372 373 static int cri_fifos_wait_avail(struct dw_mipi_dsi2 *dsi2) 374 { 375 u32 sts, mask; 376 int ret; 377 378 mask = CRI_BUSY | CRT_FIFOS_NOT_EMPTY; 379 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 380 sts, !(sts & mask), 381 CMD_PKT_STATUS_TIMEOUT_US); 382 if (ret < 0) { 383 printf("command interface is busy: 0x%x\n", sts); 384 return ret; 385 } 386 387 return 0; 388 } 389 390 static int dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 *dsi2, 391 const struct mipi_dsi_msg *msg) 392 { 393 u8 *payload = msg->rx_buf; 394 u8 data_type; 395 u16 wc; 396 int i, j, ret, len = msg->rx_len; 397 unsigned int vrefresh = drm_mode_vrefresh(&dsi2->mode); 398 u32 val; 399 400 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 401 val, val & CRI_RD_DATA_AVAIL, 402 DIV_ROUND_UP(1000000, vrefresh)); 403 if (ret) { 404 printf("CRI has no available read data\n"); 405 return ret; 406 } 407 408 val = dsi_read(dsi2, DSI2_CRI_RX_HDR); 409 data_type = val & 0x3f; 410 411 if (mipi_dsi_packet_format_is_short(data_type)) { 412 for (i = 0; i < len && i < 2; i++) 413 payload[i] = (val >> (8 * (i + 1))) & 0xff; 414 415 return 0; 416 } 417 418 wc = (val >> 8) & 0xffff; 419 /* Receive payload */ 420 for (i = 0; i < len && i < wc; i += 4) { 421 val = dsi_read(dsi2, DSI2_CRI_RX_PLD); 422 for (j = 0; j < 4 && j + i < len && j + i < wc; j++) 423 payload[i + j] = val >> (8 * j); 424 } 425 426 return 0; 427 } 428 429 static ssize_t dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 *dsi2, 430 const struct mipi_dsi_msg *msg) 431 { 432 struct mipi_dsi_packet packet; 433 int ret; 434 int val; 435 u32 mode; 436 437 dsi_update_bits(dsi2, DSI2_DSI_VID_TX_CFG, LPDT_DISPLAY_CMD_EN, 438 msg->flags & MIPI_DSI_MSG_USE_LPM ? 439 LPDT_DISPLAY_CMD_EN : 0); 440 441 /* create a packet to the DSI protocol */ 442 ret = mipi_dsi_create_packet(&packet, msg); 443 if (ret) { 444 printf("failed to create packet: %d\n", ret); 445 return ret; 446 } 447 448 /* check cri interface is not busy */ 449 ret = cri_fifos_wait_avail(dsi2); 450 if (ret) 451 return ret; 452 453 /* Send payload */ 454 while (DIV_ROUND_UP(packet.payload_length, 4)) { 455 if (packet.payload_length < 4) { 456 /* send residu payload */ 457 val = 0; 458 memcpy(&val, packet.payload, packet.payload_length); 459 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 460 packet.payload_length = 0; 461 } else { 462 val = get_unaligned_le32(packet.payload); 463 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 464 packet.payload += 4; 465 packet.payload_length -= 4; 466 } 467 } 468 469 /* Send packet header */ 470 mode = CMD_TX_MODE(msg->flags & MIPI_DSI_MSG_USE_LPM ? 1 : 0); 471 val = get_unaligned_le32(packet.header); 472 dsi_write(dsi2, DSI2_CRI_TX_HDR, mode | val); 473 474 ret = cri_fifos_wait_avail(dsi2); 475 if (ret) 476 return ret; 477 478 if (msg->rx_len) { 479 ret = dw_mipi_dsi2_read_from_fifo(dsi2, msg); 480 if (ret < 0) 481 return ret; 482 } 483 484 if (dsi2->slave) { 485 ret = dw_mipi_dsi2_transfer(dsi2->slave, msg); 486 if (ret < 0) 487 return ret; 488 } 489 490 return msg->rx_len ? msg->rx_len : msg->tx_len; 491 } 492 493 static void dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 *dsi2) 494 { 495 u32 val, color_depth; 496 497 switch (dsi2->format) { 498 case MIPI_DSI_FMT_RGB666: 499 case MIPI_DSI_FMT_RGB666_PACKED: 500 color_depth = IPI_DEPTH_6_BITS; 501 break; 502 case MIPI_DSI_FMT_RGB565: 503 color_depth = IPI_DEPTH_5_6_5_BITS; 504 break; 505 case MIPI_DSI_FMT_RGB888: 506 default: 507 color_depth = IPI_DEPTH_8_BITS; 508 break; 509 } 510 511 val = IPI_DEPTH(color_depth) | 512 IPI_FORMAT(dsi2->dsc_enable ? IPI_FORMAT_DSC : IPI_FORMAT_RGB); 513 dsi_write(dsi2, DSI2_IPI_COLOR_MAN_CFG, val); 514 grf_field_write(dsi2, IPI_COLOR_DEPTH, color_depth); 515 516 if (dsi2->dsc_enable) 517 grf_field_write(dsi2, IPI_FORMAT, IPI_FORMAT_DSC); 518 } 519 520 static void dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 *dsi2) 521 { 522 struct drm_display_mode *mode = &dsi2->mode; 523 u32 hline, hsa, hbp, hact; 524 u64 hline_time, hsa_time, hbp_time, hact_time, tmp; 525 u64 pixel_clk, phy_hs_clk; 526 u32 vact, vsa, vfp, vbp; 527 u16 val; 528 529 if (dsi2->slave || dsi2->master) 530 val = mode->hdisplay / 2; 531 else 532 val = mode->hdisplay; 533 534 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val)); 535 536 dw_mipi_dsi2_ipi_color_coding_cfg(dsi2); 537 538 /* 539 * if the controller is intended to operate in data stream mode, 540 * no more steps are required. 541 */ 542 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) 543 return; 544 545 vact = mode->vdisplay; 546 vsa = mode->vsync_end - mode->vsync_start; 547 vfp = mode->vsync_start - mode->vdisplay; 548 vbp = mode->vtotal - mode->vsync_end; 549 hact = mode->hdisplay; 550 hsa = mode->hsync_end - mode->hsync_start; 551 hbp = mode->htotal - mode->hsync_end; 552 hline = mode->htotal; 553 554 pixel_clk = mode->clock * MSEC_PER_SEC; 555 556 if (dsi2->c_option) 557 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 558 else 559 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 560 561 tmp = hsa * phy_hs_clk; 562 hsa_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 563 dsi_write(dsi2, DSI2_IPI_VID_HSA_MAN_CFG, VID_HSA_TIME(hsa_time)); 564 565 tmp = hbp * phy_hs_clk; 566 hbp_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 567 dsi_write(dsi2, DSI2_IPI_VID_HBP_MAN_CFG, VID_HBP_TIME(hbp_time)); 568 569 tmp = hact * phy_hs_clk; 570 hact_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 571 dsi_write(dsi2, DSI2_IPI_VID_HACT_MAN_CFG, VID_HACT_TIME(hact_time)); 572 573 tmp = hline * phy_hs_clk; 574 hline_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 575 dsi_write(dsi2, DSI2_IPI_VID_HLINE_MAN_CFG, VID_HLINE_TIME(hline_time)); 576 577 dsi_write(dsi2, DSI2_IPI_VID_VSA_MAN_CFG, VID_VSA_LINES(vsa)); 578 dsi_write(dsi2, DSI2_IPI_VID_VBP_MAN_CFG, VID_VBP_LINES(vbp)); 579 dsi_write(dsi2, DSI2_IPI_VID_VACT_MAN_CFG, VID_VACT_LINES(vact)); 580 dsi_write(dsi2, DSI2_IPI_VID_VFP_MAN_CFG, VID_VFP_LINES(vfp)); 581 } 582 583 static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2) 584 { 585 u32 val = 0, mode; 586 int ret; 587 588 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 589 val |= VID_MODE_TYPE_BURST; 590 else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 591 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 592 593 else 594 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 595 596 dsi_write(dsi2, DSI2_DSI_VID_TX_CFG, val); 597 598 599 dsi_write(dsi2, DSI2_MODE_CTRL, VIDEO_MODE); 600 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 601 mode, mode & VIDEO_MODE, 602 MODE_STATUS_TIMEOUT_US); 603 if (ret < 0) 604 printf("failed to enter video mode\n"); 605 } 606 607 static void dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 *dsi2) 608 { 609 u32 mode; 610 int ret; 611 612 dsi_write(dsi2, DSI2_MODE_CTRL, DATA_STREAM_MODE); 613 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 614 mode, mode & DATA_STREAM_MODE, 615 MODE_STATUS_TIMEOUT_US); 616 if (ret < 0) 617 printf("failed to enter data stream mode\n"); 618 } 619 620 static void dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 *dsi2) 621 { 622 u32 mode; 623 int ret; 624 625 dsi_write(dsi2, DSI2_MODE_CTRL, COMMAND_MODE); 626 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 627 mode, mode & COMMAND_MODE, 628 MODE_STATUS_TIMEOUT_US); 629 if (ret < 0) 630 printf("failed to enter cmd mode\n"); 631 } 632 633 static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2) 634 { 635 dw_mipi_dsi2_ipi_set(dsi2); 636 637 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO) 638 dw_mipi_dsi2_set_vid_mode(dsi2); 639 else 640 dw_mipi_dsi2_set_data_stream_mode(dsi2); 641 642 if (dsi2->slave) 643 dw_mipi_dsi2_enable(dsi2->slave); 644 } 645 646 static void dw_mipi_dsi2_disable(struct dw_mipi_dsi2 *dsi2) 647 { 648 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, 0); 649 dw_mipi_dsi2_set_cmd_mode(dsi2); 650 651 if (dsi2->slave) 652 dw_mipi_dsi2_disable(dsi2->slave); 653 } 654 655 static void dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 *dsi2) 656 { 657 if (!dsi2->prepared) 658 return; 659 660 dsi_write(dsi2, DSI2_PWR_UP, RESET); 661 662 if (dsi2->dcphy.phy) 663 rockchip_phy_power_off(dsi2->dcphy.phy); 664 665 dsi2->prepared = false; 666 667 if (dsi2->slave) 668 dw_mipi_dsi2_post_disable(dsi2->slave); 669 } 670 671 static int dw_mipi_dsi2_connector_pre_init(struct display_state *state) 672 { 673 struct connector_state *conn_state = &state->conn_state; 674 675 conn_state->type = DRM_MODE_CONNECTOR_DSI; 676 677 return 0; 678 } 679 680 static int dw_mipi_dsi2_connector_init(struct display_state *state) 681 { 682 struct connector_state *conn_state = &state->conn_state; 683 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 684 struct rockchip_phy *phy = NULL; 685 struct udevice *phy_dev; 686 struct udevice *dev; 687 int ret; 688 689 690 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dsi2->id); 691 dsi2->dcphy.phy = conn_state->phy; 692 693 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 694 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 695 conn_state->output_if |= 696 dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0; 697 698 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) { 699 conn_state->output_flags |= ROCKCHIP_OUTPUT_MIPI_DS_MODE; 700 conn_state->hold_mode = true; 701 } 702 703 if (dsi2->lanes > 4) { 704 ret = uclass_get_device_by_name(UCLASS_DISPLAY, 705 "dsi@fde30000", 706 &dev); 707 if (ret) 708 return ret; 709 710 dsi2->slave = dev_get_priv(dev); 711 if (!dsi2->slave) 712 return -ENODEV; 713 714 dsi2->slave->master = dsi2; 715 dsi2->lanes /= 2; 716 dsi2->slave->lanes = dsi2->lanes; 717 dsi2->slave->format = dsi2->format; 718 dsi2->slave->mode_flags = dsi2->mode_flags; 719 dsi2->slave->channel = dsi2->channel; 720 conn_state->output_flags |= 721 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; 722 if (dsi2->data_swap) 723 conn_state->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP; 724 725 conn_state->output_if |= VOP_OUTPUT_IF_MIPI1; 726 727 ret = uclass_get_device_by_phandle(UCLASS_PHY, dev, 728 "phys", &phy_dev); 729 if (ret) 730 return -ENODEV; 731 732 phy = (struct rockchip_phy *)dev_get_driver_data(phy_dev); 733 if (!phy) 734 return -ENODEV; 735 736 dsi2->slave->dcphy.phy = phy; 737 if (phy->funcs && phy->funcs->init) 738 return phy->funcs->init(phy); 739 } 740 741 return 0; 742 } 743 744 /* 745 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived 746 * from the valid ranges specified in Section 6.9, Table 14, Page 41 747 * of the D-PHY specification (v2.1). 748 */ 749 int mipi_dphy_get_default_config(unsigned long long hs_clk_rate, 750 struct mipi_dphy_configure *cfg) 751 { 752 unsigned long long ui; 753 754 if (!cfg) 755 return -EINVAL; 756 757 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); 758 do_div(ui, hs_clk_rate); 759 760 cfg->clk_miss = 0; 761 cfg->clk_post = 60000 + 52 * ui; 762 cfg->clk_pre = 8000; 763 cfg->clk_prepare = 38000; 764 cfg->clk_settle = 95000; 765 cfg->clk_term_en = 0; 766 cfg->clk_trail = 60000; 767 cfg->clk_zero = 262000; 768 cfg->d_term_en = 0; 769 cfg->eot = 0; 770 cfg->hs_exit = 100000; 771 cfg->hs_prepare = 40000 + 4 * ui; 772 cfg->hs_zero = 105000 + 6 * ui; 773 cfg->hs_settle = 85000 + 6 * ui; 774 cfg->hs_skip = 40000; 775 776 /* 777 * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40) 778 * contains this formula as: 779 * 780 * T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui) 781 * 782 * where n = 1 for forward-direction HS mode and n = 4 for reverse- 783 * direction HS mode. There's only one setting and this function does 784 * not parameterize on anything other that ui, so this code will 785 * assumes that reverse-direction HS mode is supported and uses n = 4. 786 */ 787 cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui); 788 789 cfg->init = 100; 790 cfg->lpx = 60000; 791 cfg->ta_get = 5 * cfg->lpx; 792 cfg->ta_go = 4 * cfg->lpx; 793 cfg->ta_sure = 2 * cfg->lpx; 794 cfg->wakeup = 1000; 795 796 return 0; 797 } 798 799 static void dw_mipi_dsi2_set_hs_clk(struct dw_mipi_dsi2 *dsi2, unsigned long rate) 800 { 801 mipi_dphy_get_default_config(rate, &dsi2->mipi_dphy_cfg); 802 803 if (!dsi2->c_option) 804 rockchip_phy_set_mode(dsi2->dcphy.phy, PHY_MODE_MIPI_DPHY); 805 806 rate = rockchip_phy_set_pll(dsi2->dcphy.phy, rate); 807 dsi2->lane_hs_rate = DIV_ROUND_CLOSEST(rate, MSEC_PER_SEC); 808 } 809 810 static void dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 *dsi2) 811 { 812 dsi_write(dsi2, DSI2_SOFT_RESET, 0X0); 813 udelay(100); 814 dsi_write(dsi2, DSI2_SOFT_RESET, SYS_RSTN | PHY_RSTN | IPI_RSTN); 815 } 816 817 static void 818 dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 *dsi2, u32 mode) 819 { 820 /* 821 * select controller work in Manual mode 822 * Manual: MANUAL_MODE_EN 823 * Automatic: 0 824 */ 825 dsi_write(dsi2, MANUAL_MODE_CFG, mode); 826 } 827 828 static void dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 *dsi2) 829 { 830 u32 val = 0; 831 832 /* PPI width is fixed to 16 bits in DCPHY */ 833 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes); 834 val |= PHY_TYPE(dsi2->c_option ? CPHY : DPHY); 835 dsi_write(dsi2, DSI2_PHY_MODE_CFG, val); 836 } 837 838 static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2) 839 { 840 u32 sys_clk = SYS_CLK / MSEC_PER_SEC; 841 u32 esc_clk_div; 842 u32 val = 0; 843 844 if (dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 845 val |= NON_CONTINUOUS_CLK; 846 847 /* The Escape clock ranges from 1MHz to 20MHz. */ 848 esc_clk_div = DIV_ROUND_UP(sys_clk, 10 * 2); 849 val |= PHY_LPTX_CLK_DIV(esc_clk_div); 850 851 dsi_write(dsi2, DSI2_PHY_CLK_CFG, val); 852 } 853 854 static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2) 855 { 856 struct drm_display_mode *mode = &dsi2->mode; 857 u64 pixel_clk, ipi_clk, phy_hsclk, tmp; 858 859 /* 860 * in DPHY mode, the phy_hstx_clk is exactly 1/16 the Lane high-speed 861 * data rate; In CPHY mode, the phy_hstx_clk is exactly 1/7 the trio 862 * high speed symbol rate. 863 */ 864 if (dsi2->c_option) 865 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 866 867 else 868 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 869 870 /* IPI_RATIO_MAN_CFG = PHY_HSTX_CLK / IPI_CLK */ 871 pixel_clk = mode->clock * MSEC_PER_SEC; 872 ipi_clk = pixel_clk / 4; 873 874 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, ipi_clk); 875 dsi_write(dsi2, DSI2_PHY_IPI_RATIO_MAN_CFG, PHY_IPI_RATIO(tmp)); 876 877 /* SYS_RATIO_MAN_CFG = MIPI_DCPHY_HSCLK_Freq / SYS_CLK */ 878 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, SYS_CLK); 879 dsi_write(dsi2, DSI2_PHY_SYS_RATIO_MAN_CFG, PHY_SYS_RATIO(tmp)); 880 } 881 882 static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2) 883 { 884 struct mipi_dphy_configure *cfg = &dsi2->mipi_dphy_cfg; 885 unsigned long long tmp, ui; 886 unsigned long long hstx_clk; 887 888 hstx_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 889 890 ui = ALIGN(PSEC_PER_SEC, hstx_clk); 891 do_div(ui, hstx_clk); 892 893 /* PHY_LP2HS_TIME = (TLPX + THS-PREPARE + THS-ZERO) / Tphy_hstx_clk */ 894 tmp = cfg->lpx + cfg->hs_prepare + cfg->hs_zero; 895 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 896 dsi_write(dsi2, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(tmp)); 897 898 /* PHY_HS2LP_TIME = (THS-TRAIL + THS-EXIT) / Tphy_hstx_clk */ 899 tmp = cfg->hs_trail + cfg->hs_exit; 900 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 901 dsi_write(dsi2, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(tmp)); 902 } 903 904 static void dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 *dsi2) 905 { 906 dw_mipi_dsi2_phy_mode_cfg(dsi2); 907 dw_mipi_dsi2_phy_clk_mode_cfg(dsi2); 908 dw_mipi_dsi2_phy_ratio_cfg(dsi2); 909 dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(dsi2); 910 911 /* phy configuration 8 - 10 */ 912 } 913 914 static void dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 *dsi2) 915 { 916 u32 val; 917 918 val = BTA_EN | EOTP_TX_EN; 919 920 if (dsi2->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 921 val &= ~EOTP_TX_EN; 922 923 dsi_write(dsi2, DSI2_DSI_GENERAL_CFG, val); 924 dsi_write(dsi2, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel)); 925 926 if (dsi2->scrambling_en) 927 dsi_write(dsi2, DSI2_DSI_SCRAMBLING_CFG, SCRAMBLING_EN); 928 929 val = 0; 930 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) 931 val |= BLK_HFP_HS_EN; 932 933 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) 934 val |= BLK_HBP_HS_EN; 935 936 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HSA) 937 val |= BLK_HSA_HS_EN; 938 939 dsi_write(dsi2, DSI2_DSI_VID_TX_CFG, val); 940 941 /* configure the maximum return packet size that periphera can send */ 942 } 943 944 static void dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 *dsi2, bool enable) 945 { 946 if (enable) { 947 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x1); 948 dsi_write(dsi2, DSI2_INT_MASK_TO, 0xf); 949 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x1); 950 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x1); 951 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x1); 952 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x1); 953 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x1); 954 } else { 955 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x0); 956 dsi_write(dsi2, DSI2_INT_MASK_TO, 0x0); 957 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x0); 958 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x0); 959 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x0); 960 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x0); 961 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x0); 962 }; 963 } 964 965 static void mipi_dcphy_power_on(struct dw_mipi_dsi2 *dsi2) 966 { 967 if (!dsi2->dcphy.phy) 968 return; 969 970 rockchip_phy_power_on(dsi2->dcphy.phy); 971 } 972 973 static void dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 *dsi2) 974 { 975 if (dsi2->prepared) 976 return; 977 978 dw_mipi_dsi2_host_softrst(dsi2); 979 dsi_write(dsi2, DSI2_PWR_UP, RESET); 980 981 dw_mipi_dsi2_work_mode(dsi2, MANUAL_MODE_EN); 982 dw_mipi_dsi2_phy_init(dsi2); 983 dw_mipi_dsi2_tx_option_set(dsi2); 984 dw_mipi_dsi2_irq_enable(dsi2, 0); 985 mipi_dcphy_power_on(dsi2); 986 dsi_write(dsi2, DSI2_PWR_UP, POWER_UP); 987 dw_mipi_dsi2_set_cmd_mode(dsi2); 988 989 dsi2->prepared = true; 990 991 if (dsi2->slave) 992 dw_mipi_dsi2_pre_enable(dsi2->slave); 993 } 994 995 static int dw_mipi_dsi2_connector_prepare(struct display_state *state) 996 { 997 struct connector_state *conn_state = &state->conn_state; 998 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 999 unsigned long lane_rate; 1000 1001 memcpy(&dsi2->mode, &conn_state->mode, sizeof(struct drm_display_mode)); 1002 if (dsi2->slave) 1003 memcpy(&dsi2->slave->mode, &dsi2->mode, 1004 sizeof(struct drm_display_mode)); 1005 1006 lane_rate = dw_mipi_dsi2_get_lane_rate(dsi2); 1007 if (dsi2->dcphy.phy) 1008 dw_mipi_dsi2_set_hs_clk(dsi2, lane_rate); 1009 1010 if (dsi2->slave && dsi2->slave->dcphy.phy) 1011 dw_mipi_dsi2_set_hs_clk(dsi2->slave, lane_rate); 1012 1013 printf("final DSI-Link bandwidth: %u %s x %d\n", 1014 dsi2->lane_hs_rate, dsi2->c_option ? "Ksps" : "Kbps", 1015 dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes); 1016 1017 dw_mipi_dsi2_pre_enable(dsi2); 1018 1019 return 0; 1020 } 1021 1022 static void dw_mipi_dsi2_connector_unprepare(struct display_state *state) 1023 { 1024 struct connector_state *conn_state = &state->conn_state; 1025 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 1026 1027 dw_mipi_dsi2_post_disable(dsi2); 1028 } 1029 1030 static int dw_mipi_dsi2_connector_enable(struct display_state *state) 1031 { 1032 struct connector_state *conn_state = &state->conn_state; 1033 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 1034 1035 dw_mipi_dsi2_enable(dsi2); 1036 1037 return 0; 1038 } 1039 1040 static int dw_mipi_dsi2_connector_disable(struct display_state *state) 1041 { 1042 struct connector_state *conn_state = &state->conn_state; 1043 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 1044 1045 dw_mipi_dsi2_disable(dsi2); 1046 1047 return 0; 1048 } 1049 1050 static const struct rockchip_connector_funcs dw_mipi_dsi2_connector_funcs = { 1051 .pre_init = dw_mipi_dsi2_connector_pre_init, 1052 .init = dw_mipi_dsi2_connector_init, 1053 .prepare = dw_mipi_dsi2_connector_prepare, 1054 .unprepare = dw_mipi_dsi2_connector_unprepare, 1055 .enable = dw_mipi_dsi2_connector_enable, 1056 .disable = dw_mipi_dsi2_connector_disable, 1057 }; 1058 1059 static int dw_mipi_dsi2_probe(struct udevice *dev) 1060 { 1061 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(dev); 1062 const struct rockchip_connector *connector = 1063 (const struct rockchip_connector *)dev_get_driver_data(dev); 1064 const struct dw_mipi_dsi2_plat_data *pdata = connector->data; 1065 struct udevice *syscon; 1066 int id, ret; 1067 1068 dsi2->base = dev_read_addr_ptr(dev); 1069 1070 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1071 &syscon); 1072 if (!ret) { 1073 dsi2->grf = syscon_get_regmap(syscon); 1074 if (!dsi2->grf) 1075 return -ENODEV; 1076 } 1077 1078 id = of_alias_get_id(ofnode_to_np(dev->node), "dsi"); 1079 if (id < 0) 1080 id = 0; 1081 1082 dsi2->dev = dev; 1083 dsi2->pdata = pdata; 1084 dsi2->id = id; 1085 dsi2->data_swap = dev_read_bool(dsi2->dev, "rockchip,data-swap"); 1086 1087 return 0; 1088 } 1089 1090 static const u32 rk3588_dsi0_grf_reg_fields[MAX_FIELDS] = { 1091 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0000, 11, 11), 1092 [GATING_EN] = GRF_REG_FIELD(0x0000, 10, 10), 1093 [IPI_SHUTDN] = GRF_REG_FIELD(0x0000, 9, 9), 1094 [IPI_COLORM] = GRF_REG_FIELD(0x0000, 8, 8), 1095 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0000, 4, 7), 1096 [IPI_FORMAT] = GRF_REG_FIELD(0x0000, 0, 3), 1097 }; 1098 1099 static const u32 rk3588_dsi1_grf_reg_fields[MAX_FIELDS] = { 1100 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0004, 11, 11), 1101 [GATING_EN] = GRF_REG_FIELD(0x0004, 10, 10), 1102 [IPI_SHUTDN] = GRF_REG_FIELD(0x0004, 9, 9), 1103 [IPI_COLORM] = GRF_REG_FIELD(0x0004, 8, 8), 1104 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0004, 4, 7), 1105 [IPI_FORMAT] = GRF_REG_FIELD(0x0004, 0, 3), 1106 }; 1107 1108 static const struct dw_mipi_dsi2_plat_data rk3588_mipi_dsi2_plat_data = { 1109 .dsi0_grf_reg_fields = rk3588_dsi0_grf_reg_fields, 1110 .dsi1_grf_reg_fields = rk3588_dsi1_grf_reg_fields, 1111 .dphy_max_bit_rate_per_lane = 4500000000ULL, 1112 .cphy_max_symbol_rate_per_lane = 2000000000ULL, 1113 }; 1114 static const struct rockchip_connector rk3588_mipi_dsi2_driver_data = { 1115 .funcs = &dw_mipi_dsi2_connector_funcs, 1116 .data = &rk3588_mipi_dsi2_plat_data, 1117 }; 1118 1119 static const struct udevice_id dw_mipi_dsi2_ids[] = { 1120 { 1121 .compatible = "rockchip,rk3588-mipi-dsi2", 1122 .data = (ulong)&rk3588_mipi_dsi2_driver_data, 1123 }, 1124 {} 1125 }; 1126 1127 static ssize_t dw_mipi_dsi2_host_transfer(struct mipi_dsi_host *host, 1128 const struct mipi_dsi_msg *msg) 1129 { 1130 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1131 1132 return dw_mipi_dsi2_transfer(dsi2, msg); 1133 } 1134 1135 static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2) 1136 { 1137 struct udevice *dev = NULL; 1138 int ret; 1139 1140 ret = device_find_first_child(dsi2->dev, &dev); 1141 if (ret) 1142 return ret; 1143 1144 dsi2->c_option = dev_read_bool(dev, "phy-c-option"); 1145 dsi2->scrambling_en = dev_read_bool(dev, "scrambling-enable"); 1146 dsi2->dsc_enable = dev_read_bool(dev, "compressed-data"); 1147 1148 if (dsi2->slave) { 1149 dsi2->slave->c_option = dsi2->c_option; 1150 dsi2->slave->scrambling_en = dsi2->scrambling_en; 1151 dsi2->slave->dsc_enable = dsi2->dsc_enable; 1152 } 1153 1154 dsi2->slice_width = dev_read_u32_default(dev, "slice_width", 0); 1155 dsi2->slice_height = dev_read_u32_default(dev, "slice_height", 0); 1156 dsi2->version_major = dev_read_u32_default(dev, "version_major", 0); 1157 dsi2->version_minor = dev_read_u32_default(dev, "version_minor", 0); 1158 1159 return 0; 1160 } 1161 1162 static int dw_mipi_dsi2_host_attach(struct mipi_dsi_host *host, 1163 struct mipi_dsi_device *device) 1164 { 1165 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1166 1167 if (device->lanes < 1 || device->lanes > 8) 1168 return -EINVAL; 1169 1170 dsi2->lanes = device->lanes; 1171 dsi2->channel = device->channel; 1172 dsi2->format = device->format; 1173 dsi2->mode_flags = device->mode_flags; 1174 1175 dw_mipi_dsi2_get_dsc_params_from_sink(dsi2); 1176 1177 return 0; 1178 } 1179 1180 static const struct mipi_dsi_host_ops dw_mipi_dsi2_host_ops = { 1181 .attach = dw_mipi_dsi2_host_attach, 1182 .transfer = dw_mipi_dsi2_host_transfer, 1183 }; 1184 1185 static int dw_mipi_dsi2_bind(struct udevice *dev) 1186 { 1187 struct mipi_dsi_host *host = dev_get_platdata(dev); 1188 1189 host->dev = dev; 1190 host->ops = &dw_mipi_dsi2_host_ops; 1191 1192 return dm_scan_fdt_dev(dev); 1193 } 1194 1195 static int dw_mipi_dsi2_child_post_bind(struct udevice *dev) 1196 { 1197 struct mipi_dsi_host *host = dev_get_platdata(dev->parent); 1198 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1199 char name[20]; 1200 1201 sprintf(name, "%s.%d", host->dev->name, device->channel); 1202 device_set_name(dev, name); 1203 1204 device->dev = dev; 1205 device->host = host; 1206 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4); 1207 device->format = dev_read_u32_default(dev, "dsi,format", 1208 MIPI_DSI_FMT_RGB888); 1209 device->mode_flags = dev_read_u32_default(dev, "dsi,flags", 1210 MIPI_DSI_MODE_VIDEO | 1211 MIPI_DSI_MODE_VIDEO_BURST | 1212 MIPI_DSI_MODE_VIDEO_HBP | 1213 MIPI_DSI_MODE_LPM | 1214 MIPI_DSI_MODE_EOT_PACKET); 1215 device->channel = dev_read_u32_default(dev, "reg", 0); 1216 1217 return 0; 1218 } 1219 1220 static int dw_mipi_dsi2_child_pre_probe(struct udevice *dev) 1221 { 1222 struct mipi_dsi_device *device = dev_get_parent_platdata(dev); 1223 int ret; 1224 1225 ret = mipi_dsi_attach(device); 1226 if (ret) { 1227 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret); 1228 return ret; 1229 } 1230 1231 return 0; 1232 } 1233 1234 U_BOOT_DRIVER(dw_mipi_dsi2) = { 1235 .name = "dw_mipi_dsi2", 1236 .id = UCLASS_DISPLAY, 1237 .of_match = dw_mipi_dsi2_ids, 1238 .probe = dw_mipi_dsi2_probe, 1239 .bind = dw_mipi_dsi2_bind, 1240 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi2), 1241 .per_child_platdata_auto_alloc_size = sizeof(struct mipi_dsi_device), 1242 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_host), 1243 .child_post_bind = dw_mipi_dsi2_child_post_bind, 1244 .child_pre_probe = dw_mipi_dsi2_child_pre_probe, 1245 }; 1246