1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Author: Guochun Huang <hero.huang@rock-chips.com> 7 */ 8 9 #include <drm/drm_mipi_dsi.h> 10 11 #include <config.h> 12 #include <common.h> 13 #include <errno.h> 14 #include <asm/unaligned.h> 15 #include <asm/io.h> 16 #include <asm/hardware.h> 17 #include <dm/device.h> 18 #include <dm/read.h> 19 #include <dm/of_access.h> 20 #include <regmap.h> 21 #include <syscon.h> 22 #include <asm/arch-rockchip/clock.h> 23 #include <linux/iopoll.h> 24 25 #include "rockchip_bridge.h" 26 #include "rockchip_display.h" 27 #include "rockchip_crtc.h" 28 #include "rockchip_connector.h" 29 #include "rockchip_panel.h" 30 #include "rockchip_phy.h" 31 32 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) 33 34 #define DSI2_PWR_UP 0x000c 35 #define RESET 0 36 #define POWER_UP BIT(0) 37 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 38 #define DSI2_SOFT_RESET 0x0010 39 #define SYS_RSTN BIT(2) 40 #define PHY_RSTN BIT(1) 41 #define IPI_RSTN BIT(0) 42 #define INT_ST_MAIN 0x0014 43 #define DSI2_MODE_CTRL 0x0018 44 #define DSI2_MODE_STATUS 0x001c 45 #define DSI2_CORE_STATUS 0x0020 46 #define PRI_RD_DATA_AVAIL BIT(26) 47 #define PRI_FIFOS_NOT_EMPTY BIT(25) 48 #define PRI_BUSY BIT(24) 49 #define CRI_RD_DATA_AVAIL BIT(18) 50 #define CRT_FIFOS_NOT_EMPTY BIT(17) 51 #define CRI_BUSY BIT(16) 52 #define IPI_FIFOS_NOT_EMPTY BIT(9) 53 #define IPI_BUSY BIT(8) 54 #define CORE_FIFOS_NOT_EMPTY BIT(1) 55 #define CORE_BUSY BIT(0) 56 #define MANUAL_MODE_CFG 0x0024 57 #define MANUAL_MODE_EN BIT(0) 58 #define DSI2_TIMEOUT_HSTX_CFG 0x0048 59 #define TO_HSTX(x) UPDATE(x, 15, 0) 60 #define DSI2_TIMEOUT_HSTXRDY_CFG 0x004c 61 #define TO_HSTXRDY(x) UPDATE(x, 15, 0) 62 #define DSI2_TIMEOUT_LPRX_CFG 0x0050 63 #define TO_LPRXRDY(x) UPDATE(x, 15, 0) 64 #define DSI2_TIMEOUT_LPTXRDY_CFG 0x0054 65 #define TO_LPTXRDY(x) UPDATE(x, 15, 0) 66 #define DSI2_TIMEOUT_LPTXTRIG_CFG 0x0058 67 #define TO_LPTXTRIG(x) UPDATE(x, 15, 0) 68 #define DSI2_TIMEOUT_LPTXULPS_CFG 0x005c 69 #define TO_LPTXULPS(x) UPDATE(x, 15, 0) 70 #define DSI2_TIMEOUT_BTA_CFG 0x60 71 #define TO_BTA(x) UPDATE(x, 15, 0) 72 73 #define DSI2_PHY_MODE_CFG 0x0100 74 #define PPI_WIDTH(x) UPDATE(x, 9, 8) 75 #define PHY_LANES(x) UPDATE(x - 1, 5, 4) 76 #define PHY_TYPE(x) UPDATE(x, 0, 0) 77 #define DSI2_PHY_CLK_CFG 0X0104 78 #define PHY_LPTX_CLK_DIV(x) UPDATE(x, 12, 8) 79 #define NON_CONTINUOUS_CLK BIT(0) 80 #define DSI2_PHY_LP2HS_MAN_CFG 0x010c 81 #define PHY_LP2HS_TIME(x) UPDATE(x, 28, 0) 82 #define DSI2_PHY_HS2LP_MAN_CFG 0x0114 83 #define PHY_HS2LP_TIME(x) UPDATE(x, 28, 0) 84 #define DSI2_PHY_MAX_RD_T_MAN_CFG 0x011c 85 #define PHY_MAX_RD_TIME(x) UPDATE(x, 26, 0) 86 #define DSI2_PHY_ESC_CMD_T_MAN_CFG 0x0124 87 #define PHY_ESC_CMD_TIME(x) UPDATE(x, 28, 0) 88 #define DSI2_PHY_ESC_BYTE_T_MAN_CFG 0x012c 89 #define PHY_ESC_BYTE_TIME(x) UPDATE(x, 28, 0) 90 91 #define DSI2_PHY_IPI_RATIO_MAN_CFG 0x0134 92 #define PHY_IPI_RATIO(x) UPDATE(x, 21, 0) 93 #define DSI2_PHY_SYS_RATIO_MAN_CFG 0x013C 94 #define PHY_SYS_RATIO(x) UPDATE(x, 16, 0) 95 96 #define DSI2_DSI_GENERAL_CFG 0x0200 97 #define BTA_EN BIT(1) 98 #define EOTP_TX_EN BIT(0) 99 #define DSI2_DSI_VCID_CFG 0x0204 100 #define TX_VCID(x) UPDATE(x, 1, 0) 101 #define DSI2_DSI_SCRAMBLING_CFG 0x0208 102 #define SCRAMBLING_SEED(x) UPDATE(x, 31, 16) 103 #define SCRAMBLING_EN BIT(0) 104 #define DSI2_DSI_VID_TX_CFG 0x020c 105 #define LPDT_DISPLAY_CMD_EN BIT(20) 106 #define BLK_VFP_HS_EN BIT(14) 107 #define BLK_VBP_HS_EN BIT(13) 108 #define BLK_VSA_HS_EN BIT(12) 109 #define BLK_HFP_HS_EN BIT(6) 110 #define BLK_HBP_HS_EN BIT(5) 111 #define BLK_HSA_HS_EN BIT(4) 112 #define VID_MODE_TYPE(x) UPDATE(x, 1, 0) 113 #define DSI2_CRI_TX_HDR 0x02c0 114 #define CMD_TX_MODE(x) UPDATE(x, 24, 24) 115 #define DSI2_CRI_TX_PLD 0x02c4 116 #define DSI2_CRI_RX_HDR 0x02c8 117 #define DSI2_CRI_RX_PLD 0x02cc 118 119 #define DSI2_IPI_COLOR_MAN_CFG 0x0300 120 #define IPI_DEPTH(x) UPDATE(x, 7, 4) 121 #define IPI_DEPTH_5_6_5_BITS 0x02 122 #define IPI_DEPTH_6_BITS 0x03 123 #define IPI_DEPTH_8_BITS 0x05 124 #define IPI_DEPTH_10_BITS 0x06 125 #define IPI_FORMAT(x) UPDATE(x, 3, 0) 126 #define IPI_FORMAT_RGB 0x0 127 #define IPI_FORMAT_DSC 0x0b 128 #define DSI2_IPI_VID_HSA_MAN_CFG 0x0304 129 #define VID_HSA_TIME(x) UPDATE(x, 29, 0) 130 #define DSI2_IPI_VID_HBP_MAN_CFG 0x030c 131 #define VID_HBP_TIME(x) UPDATE(x, 29, 0) 132 #define DSI2_IPI_VID_HACT_MAN_CFG 0x0314 133 #define VID_HACT_TIME(x) UPDATE(x, 29, 0) 134 #define DSI2_IPI_VID_HLINE_MAN_CFG 0x031c 135 #define VID_HLINE_TIME(x) UPDATE(x, 29, 0) 136 #define DSI2_IPI_VID_VSA_MAN_CFG 0x0324 137 #define VID_VSA_LINES(x) UPDATE(x, 9, 0) 138 #define DSI2_IPI_VID_VBP_MAN_CFG 0X032C 139 #define VID_VBP_LINES(x) UPDATE(x, 9, 0) 140 #define DSI2_IPI_VID_VACT_MAN_CFG 0X0334 141 #define VID_VACT_LINES(x) UPDATE(x, 13, 0) 142 #define DSI2_IPI_VID_VFP_MAN_CFG 0X033C 143 #define VID_VFP_LINES(x) UPDATE(x, 9, 0) 144 #define DSI2_IPI_PIX_PKT_CFG 0x0344 145 #define MAX_PIX_PKT(x) UPDATE(x, 15, 0) 146 147 #define DSI2_INT_ST_PHY 0x0400 148 #define DSI2_INT_MASK_PHY 0x0404 149 #define DSI2_INT_ST_TO 0x0410 150 #define DSI2_INT_MASK_TO 0x0414 151 #define DSI2_INT_ST_ACK 0x0420 152 #define DSI2_INT_MASK_ACK 0x0424 153 #define DSI2_INT_ST_IPI 0x0430 154 #define DSI2_INT_MASK_IPI 0x0434 155 #define DSI2_INT_ST_FIFO 0x0440 156 #define DSI2_INT_MASK_FIFO 0x0444 157 #define DSI2_INT_ST_PRI 0x0450 158 #define DSI2_INT_MASK_PRI 0x0454 159 #define DSI2_INT_ST_CRI 0x0460 160 #define DSI2_INT_MASK_CRI 0x0464 161 #define DSI2_INT_FORCE_CRI 0x0468 162 #define DSI2_MAX_REGISGER DSI2_INT_FORCE_CRI 163 164 #define CMD_PKT_STATUS_TIMEOUT_US 1000 165 #define MODE_STATUS_TIMEOUT_US 20000 166 #define SYS_CLK 351000000LL 167 #define PSEC_PER_SEC 1000000000000LL 168 #define USEC_PER_SEC 1000000L 169 #define MSEC_PER_SEC 1000L 170 171 #define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 16) | ((lsb) << 8) | (msb)) 172 173 enum vid_mode_type { 174 VID_MODE_TYPE_NON_BURST_SYNC_PULSES, 175 VID_MODE_TYPE_NON_BURST_SYNC_EVENTS, 176 VID_MODE_TYPE_BURST, 177 }; 178 179 enum mode_ctrl { 180 IDLE_MODE, 181 AUTOCALC_MODE, 182 COMMAND_MODE, 183 VIDEO_MODE, 184 DATA_STREAM_MODE, 185 VIDE_TEST_MODE, 186 DATA_STREAM_TEST_MODE, 187 }; 188 189 enum grf_reg_fields { 190 TXREQCLKHS_EN, 191 GATING_EN, 192 IPI_SHUTDN, 193 IPI_COLORM, 194 IPI_COLOR_DEPTH, 195 IPI_FORMAT, 196 MAX_FIELDS, 197 }; 198 199 enum phy_type { 200 DPHY, 201 CPHY, 202 }; 203 204 enum ppi_width { 205 PPI_WIDTH_8_BITS, 206 PPI_WIDTH_16_BITS, 207 PPI_WIDTH_32_BITS, 208 }; 209 210 struct rockchip_cmd_header { 211 u8 data_type; 212 u8 delay_ms; 213 u8 payload_length; 214 }; 215 216 struct dw_mipi_dsi2_plat_data { 217 const u32 *dsi0_grf_reg_fields; 218 const u32 *dsi1_grf_reg_fields; 219 unsigned long long dphy_max_bit_rate_per_lane; 220 unsigned long long cphy_max_symbol_rate_per_lane; 221 }; 222 223 struct mipi_dcphy { 224 /* Non-SNPS PHY */ 225 struct rockchip_phy *phy; 226 227 u16 input_div; 228 u16 feedback_div; 229 }; 230 231 /** 232 * struct mipi_dphy_configure - MIPI D-PHY configuration set 233 * 234 * This structure is used to represent the configuration state of a 235 * MIPI D-PHY phy. 236 */ 237 struct mipi_dphy_configure { 238 unsigned int clk_miss; 239 unsigned int clk_post; 240 unsigned int clk_pre; 241 unsigned int clk_prepare; 242 unsigned int clk_settle; 243 unsigned int clk_term_en; 244 unsigned int clk_trail; 245 unsigned int clk_zero; 246 unsigned int d_term_en; 247 unsigned int eot; 248 unsigned int hs_exit; 249 unsigned int hs_prepare; 250 unsigned int hs_settle; 251 unsigned int hs_skip; 252 unsigned int hs_trail; 253 unsigned int hs_zero; 254 unsigned int init; 255 unsigned int lpx; 256 unsigned int ta_get; 257 unsigned int ta_go; 258 unsigned int ta_sure; 259 unsigned int wakeup; 260 unsigned long hs_clk_rate; 261 unsigned long lp_clk_rate; 262 unsigned char lanes; 263 }; 264 265 struct dw_mipi_dsi2 { 266 struct udevice *dev; 267 void *base; 268 void *grf; 269 int id; 270 struct dw_mipi_dsi2 *master; 271 struct dw_mipi_dsi2 *slave; 272 bool prepared; 273 274 bool c_option; 275 bool dsc_enable; 276 bool scrambling_en; 277 unsigned int slice_width; 278 unsigned int slice_height; 279 u32 version_major; 280 u32 version_minor; 281 282 unsigned int lane_hs_rate; /* Kbps/Ksps per lane */ 283 u32 channel; 284 u32 lanes; 285 u32 format; 286 u32 mode_flags; 287 struct mipi_dcphy dcphy; 288 struct drm_display_mode mode; 289 bool data_swap; 290 291 struct mipi_dsi_device *device; 292 struct mipi_dphy_configure mipi_dphy_cfg; 293 const struct dw_mipi_dsi2_plat_data *pdata; 294 struct drm_dsc_picture_parameter_set *pps; 295 }; 296 297 static inline void dsi_write(struct dw_mipi_dsi2 *dsi2, u32 reg, u32 val) 298 { 299 writel(val, dsi2->base + reg); 300 } 301 302 static inline u32 dsi_read(struct dw_mipi_dsi2 *dsi2, u32 reg) 303 { 304 return readl(dsi2->base + reg); 305 } 306 307 static inline void dsi_update_bits(struct dw_mipi_dsi2 *dsi2, 308 u32 reg, u32 mask, u32 val) 309 { 310 u32 orig, tmp; 311 312 orig = dsi_read(dsi2, reg); 313 tmp = orig & ~mask; 314 tmp |= val & mask; 315 dsi_write(dsi2, reg, tmp); 316 } 317 318 static void grf_field_write(struct dw_mipi_dsi2 *dsi2, enum grf_reg_fields index, 319 unsigned int val) 320 { 321 const u32 field = dsi2->id ? dsi2->pdata->dsi1_grf_reg_fields[index] : 322 dsi2->pdata->dsi0_grf_reg_fields[index]; 323 u16 reg; 324 u8 msb, lsb; 325 326 if (!field) 327 return; 328 329 reg = (field >> 16) & 0xffff; 330 lsb = (field >> 8) & 0xff; 331 msb = (field >> 0) & 0xff; 332 333 regmap_write(dsi2->grf, reg, GENMASK(msb, lsb) << 16 | val << lsb); 334 } 335 336 static unsigned long dw_mipi_dsi2_get_lane_rate(struct dw_mipi_dsi2 *dsi2) 337 { 338 const struct drm_display_mode *mode = &dsi2->mode; 339 u64 max_lane_rate, lane_rate; 340 unsigned int value; 341 int bpp, lanes; 342 u64 tmp; 343 344 max_lane_rate = (dsi2->c_option) ? 345 dsi2->pdata->cphy_max_symbol_rate_per_lane : 346 dsi2->pdata->dphy_max_bit_rate_per_lane; 347 348 /* 349 * optional override of the desired bandwidth 350 * High-Speed mode: Differential and terminated: 80Mbps ~ 4500 Mbps 351 */ 352 value = dev_read_u32_default(dsi2->dev, "rockchip,lane-rate", 0); 353 if (value >= 80000 && value <= 4500000) 354 return value * MSEC_PER_SEC; 355 else if (value >= 80 && value <= 4500) 356 return value * USEC_PER_SEC; 357 358 bpp = mipi_dsi_pixel_format_to_bpp(dsi2->format); 359 if (bpp < 0) 360 bpp = 24; 361 362 lanes = dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes; 363 tmp = (u64)mode->crtc_clock * 1000 * bpp; 364 do_div(tmp, lanes); 365 366 if (dsi2->c_option) 367 tmp = DIV_ROUND_CLOSEST(tmp * 100, 228); 368 369 /* set BW a little larger only in video burst mode in 370 * consideration of the protocol overhead and HS mode 371 * switching to BLLP mode, take 1 / 0.9, since Mbps must 372 * big than bandwidth of RGB 373 */ 374 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { 375 tmp *= 10; 376 do_div(tmp, 9); 377 } 378 379 if (tmp > max_lane_rate) 380 lane_rate = max_lane_rate; 381 else 382 lane_rate = tmp; 383 384 return lane_rate; 385 } 386 387 static int cri_fifos_wait_avail(struct dw_mipi_dsi2 *dsi2) 388 { 389 u32 sts, mask; 390 int ret; 391 392 mask = CRI_BUSY | CRT_FIFOS_NOT_EMPTY; 393 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 394 sts, !(sts & mask), 395 CMD_PKT_STATUS_TIMEOUT_US); 396 if (ret < 0) { 397 printf("command interface is busy: 0x%x\n", sts); 398 return ret; 399 } 400 401 return 0; 402 } 403 404 static int dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 *dsi2, 405 const struct mipi_dsi_msg *msg) 406 { 407 u8 *payload = msg->rx_buf; 408 u8 data_type; 409 u16 wc; 410 int i, j, ret, len = msg->rx_len; 411 unsigned int vrefresh = drm_mode_vrefresh(&dsi2->mode); 412 u32 val; 413 414 ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, 415 val, val & CRI_RD_DATA_AVAIL, 416 DIV_ROUND_UP(1000000, vrefresh)); 417 if (ret) { 418 printf("CRI has no available read data\n"); 419 return ret; 420 } 421 422 val = dsi_read(dsi2, DSI2_CRI_RX_HDR); 423 data_type = val & 0x3f; 424 425 if (mipi_dsi_packet_format_is_short(data_type)) { 426 for (i = 0; i < len && i < 2; i++) 427 payload[i] = (val >> (8 * (i + 1))) & 0xff; 428 429 return 0; 430 } 431 432 wc = (val >> 8) & 0xffff; 433 /* Receive payload */ 434 for (i = 0; i < len && i < wc; i += 4) { 435 val = dsi_read(dsi2, DSI2_CRI_RX_PLD); 436 for (j = 0; j < 4 && j + i < len && j + i < wc; j++) 437 payload[i + j] = val >> (8 * j); 438 } 439 440 return 0; 441 } 442 443 static ssize_t dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 *dsi2, 444 const struct mipi_dsi_msg *msg) 445 { 446 struct mipi_dsi_packet packet; 447 int ret; 448 int val; 449 u32 mode; 450 451 dsi_update_bits(dsi2, DSI2_DSI_VID_TX_CFG, LPDT_DISPLAY_CMD_EN, 452 msg->flags & MIPI_DSI_MSG_USE_LPM ? 453 LPDT_DISPLAY_CMD_EN : 0); 454 455 /* create a packet to the DSI protocol */ 456 ret = mipi_dsi_create_packet(&packet, msg); 457 if (ret) { 458 printf("failed to create packet: %d\n", ret); 459 return ret; 460 } 461 462 /* check cri interface is not busy */ 463 ret = cri_fifos_wait_avail(dsi2); 464 if (ret) 465 return ret; 466 467 /* Send payload */ 468 while (DIV_ROUND_UP(packet.payload_length, 4)) { 469 if (packet.payload_length < 4) { 470 /* send residu payload */ 471 val = 0; 472 memcpy(&val, packet.payload, packet.payload_length); 473 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 474 packet.payload_length = 0; 475 } else { 476 val = get_unaligned_le32(packet.payload); 477 dsi_write(dsi2, DSI2_CRI_TX_PLD, val); 478 packet.payload += 4; 479 packet.payload_length -= 4; 480 } 481 } 482 483 /* Send packet header */ 484 mode = CMD_TX_MODE(msg->flags & MIPI_DSI_MSG_USE_LPM ? 1 : 0); 485 val = get_unaligned_le32(packet.header); 486 dsi_write(dsi2, DSI2_CRI_TX_HDR, mode | val); 487 488 ret = cri_fifos_wait_avail(dsi2); 489 if (ret) 490 return ret; 491 492 if (msg->rx_len) { 493 ret = dw_mipi_dsi2_read_from_fifo(dsi2, msg); 494 if (ret < 0) 495 return ret; 496 } 497 498 if (dsi2->slave) { 499 ret = dw_mipi_dsi2_transfer(dsi2->slave, msg); 500 if (ret < 0) 501 return ret; 502 } 503 504 return msg->rx_len ? msg->rx_len : msg->tx_len; 505 } 506 507 static void dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 *dsi2) 508 { 509 u32 val, color_depth; 510 511 switch (dsi2->format) { 512 case MIPI_DSI_FMT_RGB666: 513 case MIPI_DSI_FMT_RGB666_PACKED: 514 color_depth = IPI_DEPTH_6_BITS; 515 break; 516 case MIPI_DSI_FMT_RGB565: 517 color_depth = IPI_DEPTH_5_6_5_BITS; 518 break; 519 case MIPI_DSI_FMT_RGB888: 520 default: 521 color_depth = IPI_DEPTH_8_BITS; 522 break; 523 } 524 525 val = IPI_DEPTH(color_depth) | 526 IPI_FORMAT(dsi2->dsc_enable ? IPI_FORMAT_DSC : IPI_FORMAT_RGB); 527 dsi_write(dsi2, DSI2_IPI_COLOR_MAN_CFG, val); 528 grf_field_write(dsi2, IPI_COLOR_DEPTH, color_depth); 529 530 if (dsi2->dsc_enable) 531 grf_field_write(dsi2, IPI_FORMAT, IPI_FORMAT_DSC); 532 } 533 534 static void dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 *dsi2) 535 { 536 struct drm_display_mode *mode = &dsi2->mode; 537 u32 hline, hsa, hbp, hact; 538 u64 hline_time, hsa_time, hbp_time, hact_time, tmp; 539 u64 pixel_clk, phy_hs_clk; 540 u32 vact, vsa, vfp, vbp; 541 u16 val; 542 543 if (dsi2->slave || dsi2->master) 544 val = mode->hdisplay / 2; 545 else 546 val = mode->hdisplay; 547 548 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val)); 549 550 dw_mipi_dsi2_ipi_color_coding_cfg(dsi2); 551 552 /* 553 * if the controller is intended to operate in data stream mode, 554 * no more steps are required. 555 */ 556 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) 557 return; 558 559 vact = mode->vdisplay; 560 vsa = mode->vsync_end - mode->vsync_start; 561 vfp = mode->vsync_start - mode->vdisplay; 562 vbp = mode->vtotal - mode->vsync_end; 563 hact = mode->hdisplay; 564 hsa = mode->hsync_end - mode->hsync_start; 565 hbp = mode->htotal - mode->hsync_end; 566 hline = mode->htotal; 567 568 pixel_clk = mode->crtc_clock * MSEC_PER_SEC; 569 570 if (dsi2->c_option) 571 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 572 else 573 phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 574 575 tmp = hsa * phy_hs_clk; 576 hsa_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 577 dsi_write(dsi2, DSI2_IPI_VID_HSA_MAN_CFG, VID_HSA_TIME(hsa_time)); 578 579 tmp = hbp * phy_hs_clk; 580 hbp_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 581 dsi_write(dsi2, DSI2_IPI_VID_HBP_MAN_CFG, VID_HBP_TIME(hbp_time)); 582 583 tmp = hact * phy_hs_clk; 584 hact_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 585 dsi_write(dsi2, DSI2_IPI_VID_HACT_MAN_CFG, VID_HACT_TIME(hact_time)); 586 587 tmp = hline * phy_hs_clk; 588 hline_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); 589 dsi_write(dsi2, DSI2_IPI_VID_HLINE_MAN_CFG, VID_HLINE_TIME(hline_time)); 590 591 dsi_write(dsi2, DSI2_IPI_VID_VSA_MAN_CFG, VID_VSA_LINES(vsa)); 592 dsi_write(dsi2, DSI2_IPI_VID_VBP_MAN_CFG, VID_VBP_LINES(vbp)); 593 dsi_write(dsi2, DSI2_IPI_VID_VACT_MAN_CFG, VID_VACT_LINES(vact)); 594 dsi_write(dsi2, DSI2_IPI_VID_VFP_MAN_CFG, VID_VFP_LINES(vfp)); 595 } 596 597 static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2) 598 { 599 u32 val = 0, mode; 600 int ret; 601 602 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) 603 val |= BLK_HFP_HS_EN; 604 605 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) 606 val |= BLK_HBP_HS_EN; 607 608 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HSA) 609 val |= BLK_HSA_HS_EN; 610 611 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 612 val |= VID_MODE_TYPE_BURST; 613 else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 614 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 615 else 616 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 617 618 dsi_write(dsi2, DSI2_DSI_VID_TX_CFG, val); 619 620 dsi_write(dsi2, DSI2_MODE_CTRL, VIDEO_MODE); 621 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 622 mode, mode & VIDEO_MODE, 623 MODE_STATUS_TIMEOUT_US); 624 if (ret < 0) 625 printf("failed to enter video mode\n"); 626 } 627 628 static void dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 *dsi2) 629 { 630 u32 mode; 631 int ret; 632 633 dsi_write(dsi2, DSI2_MODE_CTRL, DATA_STREAM_MODE); 634 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 635 mode, mode & DATA_STREAM_MODE, 636 MODE_STATUS_TIMEOUT_US); 637 if (ret < 0) 638 printf("failed to enter data stream mode\n"); 639 } 640 641 static void dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 *dsi2) 642 { 643 u32 mode; 644 int ret; 645 646 dsi_write(dsi2, DSI2_MODE_CTRL, COMMAND_MODE); 647 ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, 648 mode, mode & COMMAND_MODE, 649 MODE_STATUS_TIMEOUT_US); 650 if (ret < 0) 651 printf("failed to enter cmd mode\n"); 652 } 653 654 static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2) 655 { 656 dw_mipi_dsi2_ipi_set(dsi2); 657 658 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO) 659 dw_mipi_dsi2_set_vid_mode(dsi2); 660 else 661 dw_mipi_dsi2_set_data_stream_mode(dsi2); 662 663 if (dsi2->slave) 664 dw_mipi_dsi2_enable(dsi2->slave); 665 } 666 667 static void dw_mipi_dsi2_disable(struct dw_mipi_dsi2 *dsi2) 668 { 669 dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, 0); 670 dw_mipi_dsi2_set_cmd_mode(dsi2); 671 672 if (dsi2->slave) 673 dw_mipi_dsi2_disable(dsi2->slave); 674 } 675 676 static void dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 *dsi2) 677 { 678 if (!dsi2->prepared) 679 return; 680 681 dsi_write(dsi2, DSI2_PWR_UP, RESET); 682 683 if (dsi2->dcphy.phy) 684 rockchip_phy_power_off(dsi2->dcphy.phy); 685 686 dsi2->prepared = false; 687 688 if (dsi2->slave) 689 dw_mipi_dsi2_post_disable(dsi2->slave); 690 } 691 692 static int dw_mipi_dsi2_connector_pre_init(struct display_state *state) 693 { 694 struct connector_state *conn_state = &state->conn_state; 695 struct panel_state *panel_state = &state->panel_state; 696 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 697 struct mipi_dsi_host *host = dev_get_platdata(dsi2->dev); 698 struct mipi_dsi_device *device; 699 char name[20]; 700 struct udevice *dev; 701 702 device = calloc(1, sizeof(struct dw_mipi_dsi2)); 703 if (!device) 704 return -ENOMEM; 705 706 conn_state->type = DRM_MODE_CONNECTOR_DSI; 707 708 if (conn_state->bridge) 709 dev = conn_state->bridge->dev; 710 else if (panel_state->panel) 711 dev = panel_state->panel->dev; 712 else 713 return -ENODEV; 714 715 device->dev = dev; 716 device->host = host; 717 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4); 718 device->channel = dev_read_u32_default(dev, "reg", 0); 719 device->format = dev_read_u32_default(dev, "dsi,format", 720 MIPI_DSI_FMT_RGB888); 721 device->mode_flags = dev_read_u32_default(dev, "dsi,flags", 722 MIPI_DSI_MODE_VIDEO | 723 MIPI_DSI_MODE_VIDEO_BURST | 724 MIPI_DSI_MODE_VIDEO_HBP | 725 MIPI_DSI_MODE_LPM | 726 MIPI_DSI_MODE_EOT_PACKET); 727 728 sprintf(name, "%s.%d", host->dev->name, device->channel); 729 device_set_name(dev, name); 730 dsi2->device = device; 731 dev->parent_platdata = device; 732 733 mipi_dsi_attach(dsi2->device); 734 735 return 0; 736 } 737 738 static int dw_mipi_dsi2_connector_init(struct display_state *state) 739 { 740 struct connector_state *conn_state = &state->conn_state; 741 struct crtc_state *cstate = &state->crtc_state; 742 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 743 struct rockchip_phy *phy = NULL; 744 struct udevice *phy_dev; 745 struct udevice *dev; 746 int ret; 747 748 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dsi2->id); 749 dsi2->dcphy.phy = conn_state->phy; 750 751 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 752 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 753 conn_state->output_if |= 754 dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0; 755 756 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) { 757 conn_state->output_flags |= ROCKCHIP_OUTPUT_MIPI_DS_MODE; 758 conn_state->hold_mode = true; 759 } 760 761 if (dsi2->lanes > 4) { 762 ret = uclass_get_device_by_name(UCLASS_DISPLAY, 763 "dsi@fde30000", 764 &dev); 765 if (ret) 766 return ret; 767 768 dsi2->slave = dev_get_priv(dev); 769 if (!dsi2->slave) 770 return -ENODEV; 771 772 dsi2->slave->master = dsi2; 773 dsi2->lanes /= 2; 774 dsi2->slave->lanes = dsi2->lanes; 775 dsi2->slave->format = dsi2->format; 776 dsi2->slave->mode_flags = dsi2->mode_flags; 777 dsi2->slave->channel = dsi2->channel; 778 conn_state->output_flags |= 779 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; 780 if (dsi2->data_swap) 781 conn_state->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP; 782 783 conn_state->output_if |= VOP_OUTPUT_IF_MIPI1; 784 785 ret = uclass_get_device_by_phandle(UCLASS_PHY, dev, 786 "phys", &phy_dev); 787 if (ret) 788 return -ENODEV; 789 790 phy = (struct rockchip_phy *)dev_get_driver_data(phy_dev); 791 if (!phy) 792 return -ENODEV; 793 794 dsi2->slave->dcphy.phy = phy; 795 if (phy->funcs && phy->funcs->init) 796 return phy->funcs->init(phy); 797 } 798 799 if (dsi2->dsc_enable) { 800 cstate->dsc_enable = 1; 801 cstate->dsc_sink_cap.version_major = dsi2->version_major; 802 cstate->dsc_sink_cap.version_minor = dsi2->version_minor; 803 cstate->dsc_sink_cap.slice_width = dsi2->slice_width; 804 cstate->dsc_sink_cap.slice_height = dsi2->slice_height; 805 /* only can support rgb888 panel now */ 806 cstate->dsc_sink_cap.target_bits_per_pixel_x16 = 8 << 4; 807 cstate->dsc_sink_cap.native_420 = 0; 808 memcpy(&cstate->pps, dsi2->pps, sizeof(struct drm_dsc_picture_parameter_set)); 809 } 810 811 return 0; 812 } 813 814 /* 815 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived 816 * from the valid ranges specified in Section 6.9, Table 14, Page 41 817 * of the D-PHY specification (v2.1). 818 */ 819 int mipi_dphy_get_default_config(unsigned long long hs_clk_rate, 820 struct mipi_dphy_configure *cfg) 821 { 822 unsigned long long ui; 823 824 if (!cfg) 825 return -EINVAL; 826 827 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); 828 do_div(ui, hs_clk_rate); 829 830 cfg->clk_miss = 0; 831 cfg->clk_post = 60000 + 52 * ui; 832 cfg->clk_pre = 8000; 833 cfg->clk_prepare = 38000; 834 cfg->clk_settle = 95000; 835 cfg->clk_term_en = 0; 836 cfg->clk_trail = 60000; 837 cfg->clk_zero = 262000; 838 cfg->d_term_en = 0; 839 cfg->eot = 0; 840 cfg->hs_exit = 100000; 841 cfg->hs_prepare = 40000 + 4 * ui; 842 cfg->hs_zero = 105000 + 6 * ui; 843 cfg->hs_settle = 85000 + 6 * ui; 844 cfg->hs_skip = 40000; 845 846 /* 847 * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40) 848 * contains this formula as: 849 * 850 * T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui) 851 * 852 * where n = 1 for forward-direction HS mode and n = 4 for reverse- 853 * direction HS mode. There's only one setting and this function does 854 * not parameterize on anything other that ui, so this code will 855 * assumes that reverse-direction HS mode is supported and uses n = 4. 856 */ 857 cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui); 858 859 cfg->init = 100; 860 cfg->lpx = 60000; 861 cfg->ta_get = 5 * cfg->lpx; 862 cfg->ta_go = 4 * cfg->lpx; 863 cfg->ta_sure = 2 * cfg->lpx; 864 cfg->wakeup = 1000; 865 866 return 0; 867 } 868 869 static void dw_mipi_dsi2_set_hs_clk(struct dw_mipi_dsi2 *dsi2, unsigned long rate) 870 { 871 mipi_dphy_get_default_config(rate, &dsi2->mipi_dphy_cfg); 872 873 if (!dsi2->c_option) 874 rockchip_phy_set_mode(dsi2->dcphy.phy, PHY_MODE_MIPI_DPHY); 875 876 rate = rockchip_phy_set_pll(dsi2->dcphy.phy, rate); 877 dsi2->lane_hs_rate = DIV_ROUND_CLOSEST(rate, MSEC_PER_SEC); 878 } 879 880 static void dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 *dsi2) 881 { 882 dsi_write(dsi2, DSI2_SOFT_RESET, 0X0); 883 udelay(100); 884 dsi_write(dsi2, DSI2_SOFT_RESET, SYS_RSTN | PHY_RSTN | IPI_RSTN); 885 } 886 887 static void 888 dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 *dsi2, u32 mode) 889 { 890 /* 891 * select controller work in Manual mode 892 * Manual: MANUAL_MODE_EN 893 * Automatic: 0 894 */ 895 dsi_write(dsi2, MANUAL_MODE_CFG, mode); 896 } 897 898 static void dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 *dsi2) 899 { 900 u32 val = 0; 901 902 /* PPI width is fixed to 16 bits in DCPHY */ 903 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes); 904 val |= PHY_TYPE(dsi2->c_option ? CPHY : DPHY); 905 dsi_write(dsi2, DSI2_PHY_MODE_CFG, val); 906 } 907 908 static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2) 909 { 910 u32 sys_clk = SYS_CLK / MSEC_PER_SEC; 911 u32 esc_clk_div; 912 u32 val = 0; 913 914 if (dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 915 val |= NON_CONTINUOUS_CLK; 916 917 /* The Escape clock ranges from 1MHz to 20MHz. */ 918 esc_clk_div = DIV_ROUND_UP(sys_clk, 10 * 2); 919 val |= PHY_LPTX_CLK_DIV(esc_clk_div); 920 921 dsi_write(dsi2, DSI2_PHY_CLK_CFG, val); 922 } 923 924 static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2) 925 { 926 struct drm_display_mode *mode = &dsi2->mode; 927 u64 pixel_clk, ipi_clk, phy_hsclk, tmp; 928 929 /* 930 * in DPHY mode, the phy_hstx_clk is exactly 1/16 the Lane high-speed 931 * data rate; In CPHY mode, the phy_hstx_clk is exactly 1/7 the trio 932 * high speed symbol rate. 933 */ 934 if (dsi2->c_option) 935 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); 936 937 else 938 phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 939 940 /* IPI_RATIO_MAN_CFG = PHY_HSTX_CLK / IPI_CLK */ 941 pixel_clk = mode->crtc_clock * MSEC_PER_SEC; 942 ipi_clk = pixel_clk / 4; 943 944 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, ipi_clk); 945 dsi_write(dsi2, DSI2_PHY_IPI_RATIO_MAN_CFG, PHY_IPI_RATIO(tmp)); 946 947 /* SYS_RATIO_MAN_CFG = MIPI_DCPHY_HSCLK_Freq / SYS_CLK */ 948 tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, SYS_CLK); 949 dsi_write(dsi2, DSI2_PHY_SYS_RATIO_MAN_CFG, PHY_SYS_RATIO(tmp)); 950 } 951 952 static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2) 953 { 954 struct mipi_dphy_configure *cfg = &dsi2->mipi_dphy_cfg; 955 unsigned long long tmp, ui; 956 unsigned long long hstx_clk; 957 958 hstx_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); 959 960 ui = ALIGN(PSEC_PER_SEC, hstx_clk); 961 do_div(ui, hstx_clk); 962 963 /* PHY_LP2HS_TIME = (TLPX + THS-PREPARE + THS-ZERO) / Tphy_hstx_clk */ 964 tmp = cfg->lpx + cfg->hs_prepare + cfg->hs_zero; 965 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 966 dsi_write(dsi2, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(tmp)); 967 968 /* PHY_HS2LP_TIME = (THS-TRAIL + THS-EXIT) / Tphy_hstx_clk */ 969 tmp = cfg->hs_trail + cfg->hs_exit; 970 tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); 971 dsi_write(dsi2, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(tmp)); 972 } 973 974 static void dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 *dsi2) 975 { 976 dw_mipi_dsi2_phy_mode_cfg(dsi2); 977 dw_mipi_dsi2_phy_clk_mode_cfg(dsi2); 978 dw_mipi_dsi2_phy_ratio_cfg(dsi2); 979 dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(dsi2); 980 981 /* phy configuration 8 - 10 */ 982 } 983 984 static void dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 *dsi2) 985 { 986 u32 val; 987 988 val = BTA_EN | EOTP_TX_EN; 989 990 if (dsi2->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 991 val &= ~EOTP_TX_EN; 992 993 dsi_write(dsi2, DSI2_DSI_GENERAL_CFG, val); 994 dsi_write(dsi2, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel)); 995 996 if (dsi2->scrambling_en) 997 dsi_write(dsi2, DSI2_DSI_SCRAMBLING_CFG, SCRAMBLING_EN); 998 } 999 1000 static void dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 *dsi2, bool enable) 1001 { 1002 if (enable) { 1003 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x1); 1004 dsi_write(dsi2, DSI2_INT_MASK_TO, 0xf); 1005 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x1); 1006 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x1); 1007 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x1); 1008 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x1); 1009 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x1); 1010 } else { 1011 dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x0); 1012 dsi_write(dsi2, DSI2_INT_MASK_TO, 0x0); 1013 dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x0); 1014 dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x0); 1015 dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x0); 1016 dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x0); 1017 dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x0); 1018 }; 1019 } 1020 1021 static void mipi_dcphy_power_on(struct dw_mipi_dsi2 *dsi2) 1022 { 1023 if (!dsi2->dcphy.phy) 1024 return; 1025 1026 rockchip_phy_power_on(dsi2->dcphy.phy); 1027 } 1028 1029 static void dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 *dsi2) 1030 { 1031 if (dsi2->prepared) 1032 return; 1033 1034 dw_mipi_dsi2_host_softrst(dsi2); 1035 dsi_write(dsi2, DSI2_PWR_UP, RESET); 1036 1037 dw_mipi_dsi2_work_mode(dsi2, MANUAL_MODE_EN); 1038 dw_mipi_dsi2_phy_init(dsi2); 1039 dw_mipi_dsi2_tx_option_set(dsi2); 1040 dw_mipi_dsi2_irq_enable(dsi2, 0); 1041 mipi_dcphy_power_on(dsi2); 1042 dsi_write(dsi2, DSI2_PWR_UP, POWER_UP); 1043 dw_mipi_dsi2_set_cmd_mode(dsi2); 1044 1045 dsi2->prepared = true; 1046 1047 if (dsi2->slave) 1048 dw_mipi_dsi2_pre_enable(dsi2->slave); 1049 } 1050 1051 static int dw_mipi_dsi2_connector_prepare(struct display_state *state) 1052 { 1053 struct connector_state *conn_state = &state->conn_state; 1054 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 1055 unsigned long lane_rate; 1056 1057 memcpy(&dsi2->mode, &conn_state->mode, sizeof(struct drm_display_mode)); 1058 if (dsi2->slave) 1059 memcpy(&dsi2->slave->mode, &dsi2->mode, 1060 sizeof(struct drm_display_mode)); 1061 1062 lane_rate = dw_mipi_dsi2_get_lane_rate(dsi2); 1063 if (dsi2->dcphy.phy) 1064 dw_mipi_dsi2_set_hs_clk(dsi2, lane_rate); 1065 1066 if (dsi2->slave && dsi2->slave->dcphy.phy) 1067 dw_mipi_dsi2_set_hs_clk(dsi2->slave, lane_rate); 1068 1069 printf("final DSI-Link bandwidth: %u %s x %d\n", 1070 dsi2->lane_hs_rate, dsi2->c_option ? "Ksps" : "Kbps", 1071 dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes); 1072 1073 dw_mipi_dsi2_pre_enable(dsi2); 1074 1075 return 0; 1076 } 1077 1078 static void dw_mipi_dsi2_connector_unprepare(struct display_state *state) 1079 { 1080 struct connector_state *conn_state = &state->conn_state; 1081 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 1082 1083 dw_mipi_dsi2_post_disable(dsi2); 1084 } 1085 1086 static int dw_mipi_dsi2_connector_enable(struct display_state *state) 1087 { 1088 struct connector_state *conn_state = &state->conn_state; 1089 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 1090 1091 dw_mipi_dsi2_enable(dsi2); 1092 1093 return 0; 1094 } 1095 1096 static int dw_mipi_dsi2_connector_disable(struct display_state *state) 1097 { 1098 struct connector_state *conn_state = &state->conn_state; 1099 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn_state->dev); 1100 1101 dw_mipi_dsi2_disable(dsi2); 1102 1103 return 0; 1104 } 1105 1106 static const struct rockchip_connector_funcs dw_mipi_dsi2_connector_funcs = { 1107 .pre_init = dw_mipi_dsi2_connector_pre_init, 1108 .init = dw_mipi_dsi2_connector_init, 1109 .prepare = dw_mipi_dsi2_connector_prepare, 1110 .unprepare = dw_mipi_dsi2_connector_unprepare, 1111 .enable = dw_mipi_dsi2_connector_enable, 1112 .disable = dw_mipi_dsi2_connector_disable, 1113 }; 1114 1115 static int dw_mipi_dsi2_probe(struct udevice *dev) 1116 { 1117 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(dev); 1118 const struct rockchip_connector *connector = 1119 (const struct rockchip_connector *)dev_get_driver_data(dev); 1120 const struct dw_mipi_dsi2_plat_data *pdata = connector->data; 1121 struct udevice *syscon; 1122 int id, ret; 1123 1124 dsi2->base = dev_read_addr_ptr(dev); 1125 1126 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1127 &syscon); 1128 if (!ret) { 1129 dsi2->grf = syscon_get_regmap(syscon); 1130 if (!dsi2->grf) 1131 return -ENODEV; 1132 } 1133 1134 id = of_alias_get_id(ofnode_to_np(dev->node), "dsi"); 1135 if (id < 0) 1136 id = 0; 1137 1138 dsi2->dev = dev; 1139 dsi2->pdata = pdata; 1140 dsi2->id = id; 1141 dsi2->data_swap = dev_read_bool(dsi2->dev, "rockchip,data-swap"); 1142 1143 return 0; 1144 } 1145 1146 static const u32 rk3588_dsi0_grf_reg_fields[MAX_FIELDS] = { 1147 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0000, 11, 11), 1148 [GATING_EN] = GRF_REG_FIELD(0x0000, 10, 10), 1149 [IPI_SHUTDN] = GRF_REG_FIELD(0x0000, 9, 9), 1150 [IPI_COLORM] = GRF_REG_FIELD(0x0000, 8, 8), 1151 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0000, 4, 7), 1152 [IPI_FORMAT] = GRF_REG_FIELD(0x0000, 0, 3), 1153 }; 1154 1155 static const u32 rk3588_dsi1_grf_reg_fields[MAX_FIELDS] = { 1156 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0004, 11, 11), 1157 [GATING_EN] = GRF_REG_FIELD(0x0004, 10, 10), 1158 [IPI_SHUTDN] = GRF_REG_FIELD(0x0004, 9, 9), 1159 [IPI_COLORM] = GRF_REG_FIELD(0x0004, 8, 8), 1160 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0004, 4, 7), 1161 [IPI_FORMAT] = GRF_REG_FIELD(0x0004, 0, 3), 1162 }; 1163 1164 static const struct dw_mipi_dsi2_plat_data rk3588_mipi_dsi2_plat_data = { 1165 .dsi0_grf_reg_fields = rk3588_dsi0_grf_reg_fields, 1166 .dsi1_grf_reg_fields = rk3588_dsi1_grf_reg_fields, 1167 .dphy_max_bit_rate_per_lane = 4500000000ULL, 1168 .cphy_max_symbol_rate_per_lane = 2000000000ULL, 1169 }; 1170 static const struct rockchip_connector rk3588_mipi_dsi2_driver_data = { 1171 .funcs = &dw_mipi_dsi2_connector_funcs, 1172 .data = &rk3588_mipi_dsi2_plat_data, 1173 }; 1174 1175 static const struct udevice_id dw_mipi_dsi2_ids[] = { 1176 { 1177 .compatible = "rockchip,rk3588-mipi-dsi2", 1178 .data = (ulong)&rk3588_mipi_dsi2_driver_data, 1179 }, 1180 {} 1181 }; 1182 1183 static ssize_t dw_mipi_dsi2_host_transfer(struct mipi_dsi_host *host, 1184 const struct mipi_dsi_msg *msg) 1185 { 1186 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1187 1188 return dw_mipi_dsi2_transfer(dsi2, msg); 1189 } 1190 1191 static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2) 1192 { 1193 struct udevice *dev = dsi2->device->dev; 1194 struct rockchip_cmd_header *header; 1195 struct drm_dsc_picture_parameter_set *pps = NULL; 1196 u8 *dsc_packed_pps; 1197 const void *data; 1198 int len; 1199 1200 dsi2->c_option = dev_read_bool(dev, "phy-c-option"); 1201 dsi2->scrambling_en = dev_read_bool(dev, "scrambling-enable"); 1202 dsi2->dsc_enable = dev_read_bool(dev, "compressed-data"); 1203 1204 if (dsi2->slave) { 1205 dsi2->slave->c_option = dsi2->c_option; 1206 dsi2->slave->scrambling_en = dsi2->scrambling_en; 1207 dsi2->slave->dsc_enable = dsi2->dsc_enable; 1208 } 1209 1210 dsi2->slice_width = dev_read_u32_default(dev, "slice-width", 0); 1211 dsi2->slice_height = dev_read_u32_default(dev, "slice-height", 0); 1212 dsi2->version_major = dev_read_u32_default(dev, "version-major", 0); 1213 dsi2->version_minor = dev_read_u32_default(dev, "version-minor", 0); 1214 1215 data = dev_read_prop(dev, "panel-init-sequence", &len); 1216 if (!data) 1217 return -EINVAL; 1218 1219 while (len > sizeof(*header)) { 1220 header = (struct rockchip_cmd_header *)data; 1221 data += sizeof(*header); 1222 len -= sizeof(*header); 1223 1224 if (header->payload_length > len) 1225 return -EINVAL; 1226 1227 if (header->data_type == MIPI_DSI_PICTURE_PARAMETER_SET) { 1228 dsc_packed_pps = calloc(1, header->payload_length); 1229 if (!dsc_packed_pps) 1230 return -ENOMEM; 1231 1232 memcpy(dsc_packed_pps, data, header->payload_length); 1233 pps = (struct drm_dsc_picture_parameter_set *)dsc_packed_pps; 1234 break; 1235 } 1236 1237 data += header->payload_length; 1238 len -= header->payload_length; 1239 } 1240 1241 dsi2->pps = pps; 1242 1243 return 0; 1244 } 1245 1246 static int dw_mipi_dsi2_host_attach(struct mipi_dsi_host *host, 1247 struct mipi_dsi_device *device) 1248 { 1249 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(host->dev); 1250 1251 if (device->lanes < 1 || device->lanes > 8) 1252 return -EINVAL; 1253 1254 dsi2->lanes = device->lanes; 1255 dsi2->channel = device->channel; 1256 dsi2->format = device->format; 1257 dsi2->mode_flags = device->mode_flags; 1258 1259 dw_mipi_dsi2_get_dsc_params_from_sink(dsi2); 1260 1261 return 0; 1262 } 1263 1264 static const struct mipi_dsi_host_ops dw_mipi_dsi2_host_ops = { 1265 .attach = dw_mipi_dsi2_host_attach, 1266 .transfer = dw_mipi_dsi2_host_transfer, 1267 }; 1268 1269 static int dw_mipi_dsi2_bind(struct udevice *dev) 1270 { 1271 struct mipi_dsi_host *host = dev_get_platdata(dev); 1272 1273 host->dev = dev; 1274 host->ops = &dw_mipi_dsi2_host_ops; 1275 1276 return dm_scan_fdt_dev(dev); 1277 } 1278 1279 U_BOOT_DRIVER(dw_mipi_dsi2) = { 1280 .name = "dw_mipi_dsi2", 1281 .id = UCLASS_DISPLAY, 1282 .of_match = dw_mipi_dsi2_ids, 1283 .probe = dw_mipi_dsi2_probe, 1284 .bind = dw_mipi_dsi2_bind, 1285 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi2), 1286 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_host), 1287 }; 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