1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2022 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 #ifndef __DW_HDMI_QP_H__ 6 #define __DW_HDMI_QP_H__ 7 /* Main Unit Registers */ 8 #define CORE_ID 0x0 9 #define VER_NUMBER 0x4 10 #define VER_TYPE 0x8 11 #define CONFIG_REG 0xc 12 #define CONFIG_CEC BIT(28) 13 #define CONFIG_AUD_UD BIT(23) 14 #define CORE_TIMESTAMP_HHMM 0x14 15 #define CORE_TIMESTAMP_MMDD 0x18 16 #define CORE_TIMESTAMP_YYYY 0x1c 17 /* Reset Manager Registers */ 18 #define GLOBAL_SWRESET_REQUEST 0x40 19 #define EARCRX_CMDC_SWINIT_P BIT(27) 20 #define AVP_DATAPATH_PACKET_AUDIO_SWINIT_P BIT(10) 21 #define GLOBAL_SWDISABLE 0x44 22 #define CEC_SWDISABLE BIT(17) 23 #define AVP_DATAPATH_PACKET_AUDIO_SWDISABLE BIT(10) 24 #define AVP_DATAPATH_VIDEO_SWDISABLE BIT(6) 25 #define RESET_MANAGER_CONFIG0 0x48 26 #define RESET_MANAGER_STATUS0 0x50 27 #define RESET_MANAGER_STATUS1 0x54 28 #define RESET_MANAGER_STATUS2 0x58 29 /* Timer Base Registers */ 30 #define TIMER_BASE_CONFIG0 0x80 31 #define TIMER_BASE_STATUS0 0x84 32 /* CMU Registers */ 33 #define CMU_CONFIG0 0xa0 34 #define CMU_CONFIG1 0xa4 35 #define CMU_CONFIG2 0xa8 36 #define CMU_CONFIG3 0xac 37 #define CMU_STATUS 0xb0 38 #define EARC_BPCLK_OFF BIT(9) 39 #define AUDCLK_OFF BIT(7) 40 #define LINKQPCLK_OFF BIT(5) 41 #define VIDQPCLK_OFF BIT(3) 42 #define IPI_CLK_OFF BIT(1) 43 #define CMU_IPI_CLK_FREQ 0xb4 44 #define CMU_VIDQPCLK_FREQ 0xb8 45 #define CMU_LINKQPCLK_FREQ 0xbc 46 #define CMU_AUDQPCLK_FREQ 0xc0 47 #define CMU_EARC_BPCLK_FREQ 0xc4 48 /* I2CM Registers */ 49 #define I2CM_SM_SCL_CONFIG0 0xe0 50 #define I2CM_FM_SCL_CONFIG0 0xe4 51 #define I2CM_CONFIG0 0xe8 52 #define I2CM_CONTROL0 0xec 53 #define I2CM_STATUS0 0xf0 54 #define I2CM_INTERFACE_CONTROL0 0xf4 55 #define I2CM_ADDR 0xff000 56 #define I2CM_SLVADDR 0xfe0 57 #define I2CM_WR_MASK 0x1e 58 #define I2CM_EXT_READ BIT(4) 59 #define I2CM_SHORT_READ BIT(3) 60 #define I2CM_FM_READ BIT(2) 61 #define I2CM_FM_WRITE BIT(1) 62 #define I2CM_FM_EN BIT(0) 63 #define I2CM_INTERFACE_CONTROL1 0xf8 64 #define I2CM_SEG_PTR 0x7f80 65 #define I2CM_SEG_ADDR 0x7f 66 #define I2CM_INTERFACE_WRDATA_0_3 0xfc 67 #define I2CM_INTERFACE_WRDATA_4_7 0x100 68 #define I2CM_INTERFACE_WRDATA_8_11 0x104 69 #define I2CM_INTERFACE_WRDATA_12_15 0x108 70 #define I2CM_INTERFACE_RDDATA_0_3 0x10c 71 #define I2CM_INTERFACE_RDDATA_4_7 0x110 72 #define I2CM_INTERFACE_RDDATA_8_11 0x114 73 #define I2CM_INTERFACE_RDDATA_12_15 0x118 74 /* SCDC Registers */ 75 #define SCDC_CONFIG0 0x140 76 #define SCDC_I2C_FM_EN BIT(12) 77 #define SCDC_UPD_FLAGS_AUTO_CLR BIT(6) 78 #define SCDC_UPD_FLAGS_POLL_EN BIT(4) 79 #define SCDC_CONTROL0 0x148 80 #define SCDC_STATUS0 0x150 81 #define STATUS_UPDATE BIT(0) 82 #define FRL_START BIT(4) 83 #define FLT_UPDATE BIT(5) 84 /* FLT Registers */ 85 #define FLT_CONFIG0 0x160 86 #define FLT_CONFIG1 0x164 87 #define FLT_CONFIG2 0x168 88 #define FLT_CONTROL0 0x170 89 /* Main Unit 2 Registers */ 90 #define MAINUNIT_STATUS0 0x180 91 /* Video Interface Registers */ 92 #define VIDEO_INTERFACE_CONFIG0 0x800 93 #define VIDEO_INTERFACE_CONFIG1 0x804 94 #define VIDEO_INTERFACE_CONFIG2 0x808 95 #define VIDEO_INTERFACE_CONTROL0 0x80c 96 #define VIDEO_INTERFACE_STATUS0 0x814 97 /* Video Packing Registers */ 98 #define VIDEO_PACKING_CONFIG0 0x81c 99 /* Audio Interface Registers */ 100 #define AUDIO_INTERFACE_CONFIG0 0x820 101 #define AUD_IF_SEL_MSK 0x3 102 #define AUD_IF_SPDIF 0x2 103 #define AUD_IF_I2S 0x1 104 #define AUD_IF_PAI 0x0 105 #define AUD_FIFO_INIT_ON_OVF_MSK BIT(2) 106 #define AUD_FIFO_INIT_ON_OVF_EN BIT(2) 107 #define I2S_LINES_EN_MSK GENMASK(7, 4) 108 #define I2S_LINES_EN(x) BIT((x) + 4) 109 #define I2S_BPCUV_RCV_MSK BIT(12) 110 #define I2S_BPCUV_RCV_EN BIT(12) 111 #define I2S_BPCUV_RCV_DIS 0 112 #define SPDIF_LINES_EN GENMASK(19, 16) 113 #define AUD_FORMAT_MSK GENMASK(26, 24) 114 #define AUD_3DOBA (0x7 << 24) 115 #define AUD_3DASP (0x6 << 24) 116 #define AUD_MSOBA (0x5 << 24) 117 #define AUD_MSASP (0x4 << 24) 118 #define AUD_HBR (0x3 << 24) 119 #define AUD_DST (0x2 << 24) 120 #define AUD_OBA (0x1 << 24) 121 #define AUD_ASP (0x0 << 24) 122 #define AUDIO_INTERFACE_CONFIG1 0x824 123 #define AUDIO_INTERFACE_CONTROL0 0x82c 124 #define AUDIO_FIFO_CLR_P BIT(0) 125 #define AUDIO_INTERFACE_STATUS0 0x834 126 /* Frame Composer Registers */ 127 #define FRAME_COMPOSER_CONFIG0 0x840 128 #define FRAME_COMPOSER_CONFIG1 0x844 129 #define FRAME_COMPOSER_CONFIG2 0x848 130 #define FRAME_COMPOSER_CONFIG3 0x84c 131 #define FRAME_COMPOSER_CONFIG4 0x850 132 #define FRAME_COMPOSER_CONFIG5 0x854 133 #define FRAME_COMPOSER_CONFIG6 0x858 134 #define FRAME_COMPOSER_CONFIG7 0x85c 135 #define FRAME_COMPOSER_CONFIG8 0x860 136 #define FRAME_COMPOSER_CONFIG9 0x864 137 #define FRAME_COMPOSER_CONTROL0 0x86c 138 /* Video Monitor Registers */ 139 #define VIDEO_MONITOR_CONFIG0 0x880 140 #define VIDEO_MONITOR_STATUS0 0x884 141 #define VIDEO_MONITOR_STATUS1 0x888 142 #define VIDEO_MONITOR_STATUS2 0x88c 143 #define VIDEO_MONITOR_STATUS3 0x890 144 #define VIDEO_MONITOR_STATUS4 0x894 145 #define VIDEO_MONITOR_STATUS5 0x898 146 #define VIDEO_MONITOR_STATUS6 0x89c 147 /* HDCP2 Logic Registers */ 148 #define HDCP2LOGIC_CONFIG0 0x8e0 149 #define HDCP2_BYPASS BIT(0) 150 #define HDCP2LOGIC_ESM_GPIO_IN 0x8e4 151 #define HDCP2LOGIC_ESM_GPIO_OUT 0x8e8 152 /* HDCP14 Registers */ 153 #define HDCP14_CONFIG0 0x900 154 #define HDCP14_CONFIG1 0x904 155 #define HDCP14_CONFIG2 0x908 156 #define HDCP14_CONFIG3 0x90c 157 #define HDCP14_KEY_SEED 0x914 158 #define HDCP14_KEY_H 0x918 159 #define HDCP14_KEY_L 0x91c 160 #define HDCP14_KEY_STATUS 0x920 161 #define HDCP14_AKSV_H 0x924 162 #define HDCP14_AKSV_L 0x928 163 #define HDCP14_AN_H 0x92c 164 #define HDCP14_AN_L 0x930 165 #define HDCP14_STATUS0 0x934 166 #define HDCP14_STATUS1 0x938 167 /* Scrambler Registers */ 168 #define SCRAMB_CONFIG0 0x960 169 /* Video Configuration Registers */ 170 #define LINK_CONFIG0 0x968 171 #define OPMODE_FRL_4LANES BIT(8) 172 #define OPMODE_DVI BIT(4) 173 #define OPMODE_FRL BIT(0) 174 /* TMDS FIFO Registers */ 175 #define TMDS_FIFO_CONFIG0 0x970 176 #define TMDS_FIFO_CONTROL0 0x974 177 /* FRL RSFEC Registers */ 178 #define FRL_RSFEC_CONFIG0 0xa20 179 #define FRL_RSFEC_STATUS0 0xa30 180 /* FRL Packetizer Registers */ 181 #define FRL_PKTZ_CONFIG0 0xa40 182 #define FRL_PKTZ_CONTROL0 0xa44 183 #define FRL_PKTZ_CONTROL1 0xa50 184 #define FRL_PKTZ_STATUS1 0xa54 185 /* Packet Scheduler Registers */ 186 #define PKTSCHED_CONFIG0 0xa80 187 #define PKTSCHED_PRQUEUE0_CONFIG0 0xa84 188 #define PKTSCHED_PRQUEUE1_CONFIG0 0xa88 189 #define PKTSCHED_PRQUEUE2_CONFIG0 0xa8c 190 #define PKTSCHED_PRQUEUE2_CONFIG1 0xa90 191 #define PKTSCHED_PRQUEUE2_CONFIG2 0xa94 192 #define PKTSCHED_PKT_CONFIG0 0xa98 193 #define PKTSCHED_PKT_CONFIG1 0xa9c 194 #define PKTSCHED_PKT_CONFIG2 0xaa0 195 #define PKTSCHED_PKT_CONFIG3 0xaa4 196 #define PKTSCHED_PKT_EN 0xaa8 197 #define PKTSCHED_DRMI_TX_EN BIT(17) 198 #define PKTSCHED_AUDI_TX_EN BIT(15) 199 #define PKTSCHED_AVI_TX_EN BIT(13) 200 #define PKTSCHED_EMP_CVTEM_TX_EN BIT(10) 201 #define PKTSCHED_AMD_TX_EN BIT(8) 202 #define PKTSCHED_GCP_TX_EN BIT(3) 203 #define PKTSCHED_AUDS_TX_EN BIT(2) 204 #define PKTSCHED_ACR_TX_EN BIT(1) 205 #define PKTSCHED_NULL_TX_EN BIT(0) 206 #define PKTSCHED_PKT_CONTROL0 0xaac 207 #define PKTSCHED_PKT_SEND 0xab0 208 #define PKTSCHED_PKT_STATUS0 0xab4 209 #define PKTSCHED_PKT_STATUS1 0xab8 210 #define PKT_NULL_CONTENTS0 0xb00 211 #define PKT_NULL_CONTENTS1 0xb04 212 #define PKT_NULL_CONTENTS2 0xb08 213 #define PKT_NULL_CONTENTS3 0xb0c 214 #define PKT_NULL_CONTENTS4 0xb10 215 #define PKT_NULL_CONTENTS5 0xb14 216 #define PKT_NULL_CONTENTS6 0xb18 217 #define PKT_NULL_CONTENTS7 0xb1c 218 #define PKT_ACP_CONTENTS0 0xb20 219 #define PKT_ACP_CONTENTS1 0xb24 220 #define PKT_ACP_CONTENTS2 0xb28 221 #define PKT_ACP_CONTENTS3 0xb2c 222 #define PKT_ACP_CONTENTS4 0xb30 223 #define PKT_ACP_CONTENTS5 0xb34 224 #define PKT_ACP_CONTENTS6 0xb38 225 #define PKT_ACP_CONTENTS7 0xb3c 226 #define PKT_ISRC1_CONTENTS0 0xb40 227 #define PKT_ISRC1_CONTENTS1 0xb44 228 #define PKT_ISRC1_CONTENTS2 0xb48 229 #define PKT_ISRC1_CONTENTS3 0xb4c 230 #define PKT_ISRC1_CONTENTS4 0xb50 231 #define PKT_ISRC1_CONTENTS5 0xb54 232 #define PKT_ISRC1_CONTENTS6 0xb58 233 #define PKT_ISRC1_CONTENTS7 0xb5c 234 #define PKT_ISRC2_CONTENTS0 0xb60 235 #define PKT_ISRC2_CONTENTS1 0xb64 236 #define PKT_ISRC2_CONTENTS2 0xb68 237 #define PKT_ISRC2_CONTENTS3 0xb6c 238 #define PKT_ISRC2_CONTENTS4 0xb70 239 #define PKT_ISRC2_CONTENTS5 0xb74 240 #define PKT_ISRC2_CONTENTS6 0xb78 241 #define PKT_ISRC2_CONTENTS7 0xb7c 242 #define PKT_GMD_CONTENTS0 0xb80 243 #define PKT_GMD_CONTENTS1 0xb84 244 #define PKT_GMD_CONTENTS2 0xb88 245 #define PKT_GMD_CONTENTS3 0xb8c 246 #define PKT_GMD_CONTENTS4 0xb90 247 #define PKT_GMD_CONTENTS5 0xb94 248 #define PKT_GMD_CONTENTS6 0xb98 249 #define PKT_GMD_CONTENTS7 0xb9c 250 #define PKT_AMD_CONTENTS0 0xba0 251 #define PKT_AMD_CONTENTS1 0xba4 252 #define PKT_AMD_CONTENTS2 0xba8 253 #define PKT_AMD_CONTENTS3 0xbac 254 #define PKT_AMD_CONTENTS4 0xbb0 255 #define PKT_AMD_CONTENTS5 0xbb4 256 #define PKT_AMD_CONTENTS6 0xbb8 257 #define PKT_AMD_CONTENTS7 0xbbc 258 #define PKT_VSI_CONTENTS0 0xbc0 259 #define PKT_VSI_CONTENTS1 0xbc4 260 #define PKT_VSI_CONTENTS2 0xbc8 261 #define PKT_VSI_CONTENTS3 0xbcc 262 #define PKT_VSI_CONTENTS4 0xbd0 263 #define PKT_VSI_CONTENTS5 0xbd4 264 #define PKT_VSI_CONTENTS6 0xbd8 265 #define PKT_VSI_CONTENTS7 0xbdc 266 #define PKT_AVI_CONTENTS0 0xbe0 267 #define HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT BIT(4) 268 #define HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR 0x04 269 #define HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR 0x08 270 #define HDMI_FC_AVICONF2_IT_CONTENT_VALID 0x80 271 #define PKT_AVI_CONTENTS1 0xbe4 272 #define PKT_AVI_CONTENTS2 0xbe8 273 #define PKT_AVI_CONTENTS3 0xbec 274 #define PKT_AVI_CONTENTS4 0xbf0 275 #define PKT_AVI_CONTENTS5 0xbf4 276 #define PKT_AVI_CONTENTS6 0xbf8 277 #define PKT_AVI_CONTENTS7 0xbfc 278 #define PKT_SPDI_CONTENTS0 0xc00 279 #define PKT_SPDI_CONTENTS1 0xc04 280 #define PKT_SPDI_CONTENTS2 0xc08 281 #define PKT_SPDI_CONTENTS3 0xc0c 282 #define PKT_SPDI_CONTENTS4 0xc10 283 #define PKT_SPDI_CONTENTS5 0xc14 284 #define PKT_SPDI_CONTENTS6 0xc18 285 #define PKT_SPDI_CONTENTS7 0xc1c 286 #define PKT_AUDI_CONTENTS0 0xc20 287 #define PKT_AUDI_CONTENTS1 0xc24 288 #define PKT_AUDI_CONTENTS2 0xc28 289 #define PKT_AUDI_CONTENTS3 0xc2c 290 #define PKT_AUDI_CONTENTS4 0xc30 291 #define PKT_AUDI_CONTENTS5 0xc34 292 #define PKT_AUDI_CONTENTS6 0xc38 293 #define PKT_AUDI_CONTENTS7 0xc3c 294 #define PKT_NVI_CONTENTS0 0xc40 295 #define PKT_NVI_CONTENTS1 0xc44 296 #define PKT_NVI_CONTENTS2 0xc48 297 #define PKT_NVI_CONTENTS3 0xc4c 298 #define PKT_NVI_CONTENTS4 0xc50 299 #define PKT_NVI_CONTENTS5 0xc54 300 #define PKT_NVI_CONTENTS6 0xc58 301 #define PKT_NVI_CONTENTS7 0xc5c 302 #define PKT_DRMI_CONTENTS0 0xc60 303 #define PKT_DRMI_CONTENTS1 0xc64 304 #define PKT_DRMI_CONTENTS2 0xc68 305 #define PKT_DRMI_CONTENTS3 0xc6c 306 #define PKT_DRMI_CONTENTS4 0xc70 307 #define PKT_DRMI_CONTENTS5 0xc74 308 #define PKT_DRMI_CONTENTS6 0xc78 309 #define PKT_DRMI_CONTENTS7 0xc7c 310 #define PKT_GHDMI1_CONTENTS0 0xc80 311 #define PKT_GHDMI1_CONTENTS1 0xc84 312 #define PKT_GHDMI1_CONTENTS2 0xc88 313 #define PKT_GHDMI1_CONTENTS3 0xc8c 314 #define PKT_GHDMI1_CONTENTS4 0xc90 315 #define PKT_GHDMI1_CONTENTS5 0xc94 316 #define PKT_GHDMI1_CONTENTS6 0xc98 317 #define PKT_GHDMI1_CONTENTS7 0xc9c 318 #define PKT_GHDMI2_CONTENTS0 0xca0 319 #define PKT_GHDMI2_CONTENTS1 0xca4 320 #define PKT_GHDMI2_CONTENTS2 0xca8 321 #define PKT_GHDMI2_CONTENTS3 0xcac 322 #define PKT_GHDMI2_CONTENTS4 0xcb0 323 #define PKT_GHDMI2_CONTENTS5 0xcb4 324 #define PKT_GHDMI2_CONTENTS6 0xcb8 325 #define PKT_GHDMI2_CONTENTS7 0xcbc 326 /* EMP Packetizer Registers */ 327 #define PKT_EMP_CONFIG0 0xce0 328 #define PKT_EMP_CONTROL0 0xcec 329 #define PKT_EMP_CONTROL1 0xcf0 330 #define PKT_EMP_CONTROL2 0xcf4 331 #define PKT_EMP_VTEM_CONTENTS0 0xd00 332 #define PKT_EMP_VTEM_CONTENTS1 0xd04 333 #define PKT_EMP_VTEM_CONTENTS2 0xd08 334 #define PKT_EMP_VTEM_CONTENTS3 0xd0c 335 #define PKT_EMP_VTEM_CONTENTS4 0xd10 336 #define PKT_EMP_VTEM_CONTENTS5 0xd14 337 #define PKT_EMP_VTEM_CONTENTS6 0xd18 338 #define PKT_EMP_VTEM_CONTENTS7 0xd1c 339 #define PKT0_EMP_CVTEM_CONTENTS0 0xd20 340 #define PKT0_EMP_CVTEM_CONTENTS1 0xd24 341 #define PKT0_EMP_CVTEM_CONTENTS2 0xd28 342 #define PKT0_EMP_CVTEM_CONTENTS3 0xd2c 343 #define PKT0_EMP_CVTEM_CONTENTS4 0xd30 344 #define PKT0_EMP_CVTEM_CONTENTS5 0xd34 345 #define PKT0_EMP_CVTEM_CONTENTS6 0xd38 346 #define PKT0_EMP_CVTEM_CONTENTS7 0xd3c 347 #define PKT1_EMP_CVTEM_CONTENTS0 0xd40 348 #define PKT1_EMP_CVTEM_CONTENTS1 0xd44 349 #define PKT1_EMP_CVTEM_CONTENTS2 0xd48 350 #define PKT1_EMP_CVTEM_CONTENTS3 0xd4c 351 #define PKT1_EMP_CVTEM_CONTENTS4 0xd50 352 #define PKT1_EMP_CVTEM_CONTENTS5 0xd54 353 #define PKT1_EMP_CVTEM_CONTENTS6 0xd58 354 #define PKT1_EMP_CVTEM_CONTENTS7 0xd5c 355 #define PKT2_EMP_CVTEM_CONTENTS0 0xd60 356 #define PKT2_EMP_CVTEM_CONTENTS1 0xd64 357 #define PKT2_EMP_CVTEM_CONTENTS2 0xd68 358 #define PKT2_EMP_CVTEM_CONTENTS3 0xd6c 359 #define PKT2_EMP_CVTEM_CONTENTS4 0xd70 360 #define PKT2_EMP_CVTEM_CONTENTS5 0xd74 361 #define PKT2_EMP_CVTEM_CONTENTS6 0xd78 362 #define PKT2_EMP_CVTEM_CONTENTS7 0xd7c 363 #define PKT3_EMP_CVTEM_CONTENTS0 0xd80 364 #define PKT3_EMP_CVTEM_CONTENTS1 0xd84 365 #define PKT3_EMP_CVTEM_CONTENTS2 0xd88 366 #define PKT3_EMP_CVTEM_CONTENTS3 0xd8c 367 #define PKT3_EMP_CVTEM_CONTENTS4 0xd90 368 #define PKT3_EMP_CVTEM_CONTENTS5 0xd94 369 #define PKT3_EMP_CVTEM_CONTENTS6 0xd98 370 #define PKT3_EMP_CVTEM_CONTENTS7 0xd9c 371 #define PKT4_EMP_CVTEM_CONTENTS0 0xda0 372 #define PKT4_EMP_CVTEM_CONTENTS1 0xda4 373 #define PKT4_EMP_CVTEM_CONTENTS2 0xda8 374 #define PKT4_EMP_CVTEM_CONTENTS3 0xdac 375 #define PKT4_EMP_CVTEM_CONTENTS4 0xdb0 376 #define PKT4_EMP_CVTEM_CONTENTS5 0xdb4 377 #define PKT4_EMP_CVTEM_CONTENTS6 0xdb8 378 #define PKT4_EMP_CVTEM_CONTENTS7 0xdbc 379 #define PKT5_EMP_CVTEM_CONTENTS0 0xdc0 380 #define PKT5_EMP_CVTEM_CONTENTS1 0xdc4 381 #define PKT5_EMP_CVTEM_CONTENTS2 0xdc8 382 #define PKT5_EMP_CVTEM_CONTENTS3 0xdcc 383 #define PKT5_EMP_CVTEM_CONTENTS4 0xdd0 384 #define PKT5_EMP_CVTEM_CONTENTS5 0xdd4 385 #define PKT5_EMP_CVTEM_CONTENTS6 0xdd8 386 #define PKT5_EMP_CVTEM_CONTENTS7 0xddc 387 /* Audio Packetizer Registers */ 388 #define AUDPKT_CONTROL0 0xe20 389 #define AUDPKT_CHSTATUS_OVR_EN_MASK BIT(0) 390 #define AUDPKT_CHSTATUS_OVR_EN BIT(0) 391 #define AUDPKT_CONTROL1 0xe24 392 #define AUDPKT_ACR_CONTROL0 0xe40 393 #define AUDPKT_ACR_N_VALUE 0xfffff 394 #define AUDPKT_ACR_CONTROL1 0xe44 395 #define AUDPKT_ACR_CTS_OVR_VAL_MSK GENMASK(23, 4) 396 #define AUDPKT_ACR_CTS_OVR_VAL(x) ((x) << 4) 397 #define AUDPKT_ACR_CTS_OVR_EN_MSK BIT(1) 398 #define AUDPKT_ACR_CTS_OVR_EN BIT(1) 399 #define AUDPKT_ACR_STATUS0 0xe4c 400 #define AUDPKT_CHSTATUS_OVR0 0xe60 401 #define AUDPKT_CHSTATUS_OVR1 0xe64 402 /* IEC60958 Byte 3: Sampleing frenuency Bits 24 to 27 */ 403 #define AUDPKT_CHSTATUS_SR_MASK GENMASK(3, 0) 404 #define AUDPKT_CHSTATUS_SR_22050 0x4 405 #define AUDPKT_CHSTATUS_SR_24000 0x6 406 #define AUDPKT_CHSTATUS_SR_32000 0x3 407 #define AUDPKT_CHSTATUS_SR_44100 0x0 408 #define AUDPKT_CHSTATUS_SR_48000 0x2 409 #define AUDPKT_CHSTATUS_SR_88200 0x8 410 #define AUDPKT_CHSTATUS_SR_96000 0xa 411 #define AUDPKT_CHSTATUS_SR_176400 0xc 412 #define AUDPKT_CHSTATUS_SR_192000 0xe 413 #define AUDPKT_CHSTATUS_SR_768000 0x9 414 #define AUDPKT_CHSTATUS_SR_NOT_INDICATED 0x1 415 /* IEC60958 Byte 4: Original Sampleing frenuency Bits 36 to 39 */ 416 #define AUDPKT_CHSTATUS_0SR_MASK GENMASK(15, 12) 417 #define AUDPKT_CHSTATUS_OSR_8000 0x6 418 #define AUDPKT_CHSTATUS_OSR_11025 0xa 419 #define AUDPKT_CHSTATUS_OSR_12000 0x2 420 #define AUDPKT_CHSTATUS_OSR_16000 0x8 421 #define AUDPKT_CHSTATUS_OSR_22050 0xb 422 #define AUDPKT_CHSTATUS_OSR_24000 0x9 423 #define AUDPKT_CHSTATUS_OSR_32000 0xc 424 #define AUDPKT_CHSTATUS_OSR_44100 0xf 425 #define AUDPKT_CHSTATUS_OSR_48000 0xd 426 #define AUDPKT_CHSTATUS_OSR_88200 0x7 427 #define AUDPKT_CHSTATUS_OSR_96000 0x5 428 #define AUDPKT_CHSTATUS_OSR_176400 0x3 429 #define AUDPKT_CHSTATUS_OSR_192000 0x1 430 #define AUDPKT_CHSTATUS_OSR_NOT_INDICATED 0x0 431 #define AUDPKT_CHSTATUS_OVR2 0xe68 432 #define AUDPKT_CHSTATUS_OVR3 0xe6c 433 #define AUDPKT_CHSTATUS_OVR4 0xe70 434 #define AUDPKT_CHSTATUS_OVR5 0xe74 435 #define AUDPKT_CHSTATUS_OVR6 0xe78 436 #define AUDPKT_CHSTATUS_OVR7 0xe7c 437 #define AUDPKT_CHSTATUS_OVR8 0xe80 438 #define AUDPKT_CHSTATUS_OVR9 0xe84 439 #define AUDPKT_CHSTATUS_OVR10 0xe88 440 #define AUDPKT_CHSTATUS_OVR11 0xe8c 441 #define AUDPKT_CHSTATUS_OVR12 0xe90 442 #define AUDPKT_CHSTATUS_OVR13 0xe94 443 #define AUDPKT_CHSTATUS_OVR14 0xe98 444 #define AUDPKT_USRDATA_OVR_MSG_GENERIC0 0xea0 445 #define AUDPKT_USRDATA_OVR_MSG_GENERIC1 0xea4 446 #define AUDPKT_USRDATA_OVR_MSG_GENERIC2 0xea8 447 #define AUDPKT_USRDATA_OVR_MSG_GENERIC3 0xeac 448 #define AUDPKT_USRDATA_OVR_MSG_GENERIC4 0xeb0 449 #define AUDPKT_USRDATA_OVR_MSG_GENERIC5 0xeb4 450 #define AUDPKT_USRDATA_OVR_MSG_GENERIC6 0xeb8 451 #define AUDPKT_USRDATA_OVR_MSG_GENERIC7 0xebc 452 #define AUDPKT_USRDATA_OVR_MSG_GENERIC8 0xec0 453 #define AUDPKT_USRDATA_OVR_MSG_GENERIC9 0xec4 454 #define AUDPKT_USRDATA_OVR_MSG_GENERIC10 0xec8 455 #define AUDPKT_USRDATA_OVR_MSG_GENERIC11 0xecc 456 #define AUDPKT_USRDATA_OVR_MSG_GENERIC12 0xed0 457 #define AUDPKT_USRDATA_OVR_MSG_GENERIC13 0xed4 458 #define AUDPKT_USRDATA_OVR_MSG_GENERIC14 0xed8 459 #define AUDPKT_USRDATA_OVR_MSG_GENERIC15 0xedc 460 #define AUDPKT_USRDATA_OVR_MSG_GENERIC16 0xee0 461 #define AUDPKT_USRDATA_OVR_MSG_GENERIC17 0xee4 462 #define AUDPKT_USRDATA_OVR_MSG_GENERIC18 0xee8 463 #define AUDPKT_USRDATA_OVR_MSG_GENERIC19 0xeec 464 #define AUDPKT_USRDATA_OVR_MSG_GENERIC20 0xef0 465 #define AUDPKT_USRDATA_OVR_MSG_GENERIC21 0xef4 466 #define AUDPKT_USRDATA_OVR_MSG_GENERIC22 0xef8 467 #define AUDPKT_USRDATA_OVR_MSG_GENERIC23 0xefc 468 #define AUDPKT_USRDATA_OVR_MSG_GENERIC24 0xf00 469 #define AUDPKT_USRDATA_OVR_MSG_GENERIC25 0xf04 470 #define AUDPKT_USRDATA_OVR_MSG_GENERIC26 0xf08 471 #define AUDPKT_USRDATA_OVR_MSG_GENERIC27 0xf0c 472 #define AUDPKT_USRDATA_OVR_MSG_GENERIC28 0xf10 473 #define AUDPKT_USRDATA_OVR_MSG_GENERIC29 0xf14 474 #define AUDPKT_USRDATA_OVR_MSG_GENERIC30 0xf18 475 #define AUDPKT_USRDATA_OVR_MSG_GENERIC31 0xf1c 476 #define AUDPKT_USRDATA_OVR_MSG_GENERIC32 0xf20 477 #define AUDPKT_VBIT_OVR0 0xf24 478 /* CEC Registers */ 479 #define CEC_TX_CONTROL 0x1000 480 #define CEC_STATUS 0x1004 481 #define CEC_CONFIG 0x1008 482 #define CEC_ADDR 0x100c 483 #define CEC_TX_COUNT 0x1020 484 #define CEC_TX_DATA3_0 0x1024 485 #define CEC_TX_DATA7_4 0x1028 486 #define CEC_TX_DATA11_8 0x102c 487 #define CEC_TX_DATA15_12 0x1030 488 #define CEC_RX_COUNT_STATUS 0x1040 489 #define CEC_RX_DATA3_0 0x1044 490 #define CEC_RX_DATA7_4 0x1048 491 #define CEC_RX_DATA11_8 0x104c 492 #define CEC_RX_DATA15_12 0x1050 493 #define CEC_LOCK_CONTROL 0x1054 494 #define CEC_RXQUAL_BITTIME_CONFIG 0x1060 495 #define CEC_RX_BITTIME_CONFIG 0x1064 496 #define CEC_TX_BITTIME_CONFIG 0x1068 497 /* eARC RX CMDC Registers */ 498 #define EARCRX_CMDC_CONFIG0 0x1800 499 #define EARCRX_XACTREAD_STOP_CFG BIT(26) 500 #define EARCRX_XACTREAD_RETRY_CFG BIT(25) 501 #define EARCRX_CMDC_DSCVR_EARCVALID0_TO_DISC1 BIT(24) 502 #define EARCRX_CMDC_XACT_RESTART_EN BIT(18) 503 #define EARCRX_CMDC_CONFIG1 0x1804 504 #define EARCRX_CMDC_CONTROL 0x1808 505 #define EARCRX_CMDC_HEARTBEAT_LOSS_EN BIT(4) 506 #define EARCRX_CMDC_DISCOVERY_EN BIT(3) 507 #define EARCRX_CONNECTOR_HPD BIT(1) 508 #define EARCRX_CMDC_WHITELIST0_CONFIG 0x180c 509 #define EARCRX_CMDC_WHITELIST1_CONFIG 0x1810 510 #define EARCRX_CMDC_WHITELIST2_CONFIG 0x1814 511 #define EARCRX_CMDC_WHITELIST3_CONFIG 0x1818 512 #define EARCRX_CMDC_STATUS 0x181c 513 #define EARCRX_CMDC_XACT_INFO 0x1820 514 #define EARCRX_CMDC_XACT_ACTION 0x1824 515 #define EARCRX_CMDC_HEARTBEAT_RXSTAT_SE 0x1828 516 #define EARCRX_CMDC_HEARTBEAT_STATUS 0x182c 517 #define EARCRX_CMDC_XACT_WR0 0x1840 518 #define EARCRX_CMDC_XACT_WR1 0x1844 519 #define EARCRX_CMDC_XACT_WR2 0x1848 520 #define EARCRX_CMDC_XACT_WR3 0x184c 521 #define EARCRX_CMDC_XACT_WR4 0x1850 522 #define EARCRX_CMDC_XACT_WR5 0x1854 523 #define EARCRX_CMDC_XACT_WR6 0x1858 524 #define EARCRX_CMDC_XACT_WR7 0x185c 525 #define EARCRX_CMDC_XACT_WR8 0x1860 526 #define EARCRX_CMDC_XACT_WR9 0x1864 527 #define EARCRX_CMDC_XACT_WR10 0x1868 528 #define EARCRX_CMDC_XACT_WR11 0x186c 529 #define EARCRX_CMDC_XACT_WR12 0x1870 530 #define EARCRX_CMDC_XACT_WR13 0x1874 531 #define EARCRX_CMDC_XACT_WR14 0x1878 532 #define EARCRX_CMDC_XACT_WR15 0x187c 533 #define EARCRX_CMDC_XACT_WR16 0x1880 534 #define EARCRX_CMDC_XACT_WR17 0x1884 535 #define EARCRX_CMDC_XACT_WR18 0x1888 536 #define EARCRX_CMDC_XACT_WR19 0x188c 537 #define EARCRX_CMDC_XACT_WR20 0x1890 538 #define EARCRX_CMDC_XACT_WR21 0x1894 539 #define EARCRX_CMDC_XACT_WR22 0x1898 540 #define EARCRX_CMDC_XACT_WR23 0x189c 541 #define EARCRX_CMDC_XACT_WR24 0x18a0 542 #define EARCRX_CMDC_XACT_WR25 0x18a4 543 #define EARCRX_CMDC_XACT_WR26 0x18a8 544 #define EARCRX_CMDC_XACT_WR27 0x18ac 545 #define EARCRX_CMDC_XACT_WR28 0x18b0 546 #define EARCRX_CMDC_XACT_WR29 0x18b4 547 #define EARCRX_CMDC_XACT_WR30 0x18b8 548 #define EARCRX_CMDC_XACT_WR31 0x18bc 549 #define EARCRX_CMDC_XACT_WR32 0x18c0 550 #define EARCRX_CMDC_XACT_WR33 0x18c4 551 #define EARCRX_CMDC_XACT_WR34 0x18c8 552 #define EARCRX_CMDC_XACT_WR35 0x18cc 553 #define EARCRX_CMDC_XACT_WR36 0x18d0 554 #define EARCRX_CMDC_XACT_WR37 0x18d4 555 #define EARCRX_CMDC_XACT_WR38 0x18d8 556 #define EARCRX_CMDC_XACT_WR39 0x18dc 557 #define EARCRX_CMDC_XACT_WR40 0x18e0 558 #define EARCRX_CMDC_XACT_WR41 0x18e4 559 #define EARCRX_CMDC_XACT_WR42 0x18e8 560 #define EARCRX_CMDC_XACT_WR43 0x18ec 561 #define EARCRX_CMDC_XACT_WR44 0x18f0 562 #define EARCRX_CMDC_XACT_WR45 0x18f4 563 #define EARCRX_CMDC_XACT_WR46 0x18f8 564 #define EARCRX_CMDC_XACT_WR47 0x18fc 565 #define EARCRX_CMDC_XACT_WR48 0x1900 566 #define EARCRX_CMDC_XACT_WR49 0x1904 567 #define EARCRX_CMDC_XACT_WR50 0x1908 568 #define EARCRX_CMDC_XACT_WR51 0x190c 569 #define EARCRX_CMDC_XACT_WR52 0x1910 570 #define EARCRX_CMDC_XACT_WR53 0x1914 571 #define EARCRX_CMDC_XACT_WR54 0x1918 572 #define EARCRX_CMDC_XACT_WR55 0x191c 573 #define EARCRX_CMDC_XACT_WR56 0x1920 574 #define EARCRX_CMDC_XACT_WR57 0x1924 575 #define EARCRX_CMDC_XACT_WR58 0x1928 576 #define EARCRX_CMDC_XACT_WR59 0x192c 577 #define EARCRX_CMDC_XACT_WR60 0x1930 578 #define EARCRX_CMDC_XACT_WR61 0x1934 579 #define EARCRX_CMDC_XACT_WR62 0x1938 580 #define EARCRX_CMDC_XACT_WR63 0x193c 581 #define EARCRX_CMDC_XACT_WR64 0x1940 582 #define EARCRX_CMDC_XACT_RD0 0x1960 583 #define EARCRX_CMDC_XACT_RD1 0x1964 584 #define EARCRX_CMDC_XACT_RD2 0x1968 585 #define EARCRX_CMDC_XACT_RD3 0x196c 586 #define EARCRX_CMDC_XACT_RD4 0x1970 587 #define EARCRX_CMDC_XACT_RD5 0x1974 588 #define EARCRX_CMDC_XACT_RD6 0x1978 589 #define EARCRX_CMDC_XACT_RD7 0x197c 590 #define EARCRX_CMDC_XACT_RD8 0x1980 591 #define EARCRX_CMDC_XACT_RD9 0x1984 592 #define EARCRX_CMDC_XACT_RD10 0x1988 593 #define EARCRX_CMDC_XACT_RD11 0x198c 594 #define EARCRX_CMDC_XACT_RD12 0x1990 595 #define EARCRX_CMDC_XACT_RD13 0x1994 596 #define EARCRX_CMDC_XACT_RD14 0x1998 597 #define EARCRX_CMDC_XACT_RD15 0x199c 598 #define EARCRX_CMDC_XACT_RD16 0x19a0 599 #define EARCRX_CMDC_XACT_RD17 0x19a4 600 #define EARCRX_CMDC_XACT_RD18 0x19a8 601 #define EARCRX_CMDC_XACT_RD19 0x19ac 602 #define EARCRX_CMDC_XACT_RD20 0x19b0 603 #define EARCRX_CMDC_XACT_RD21 0x19b4 604 #define EARCRX_CMDC_XACT_RD22 0x19b8 605 #define EARCRX_CMDC_XACT_RD23 0x19bc 606 #define EARCRX_CMDC_XACT_RD24 0x19c0 607 #define EARCRX_CMDC_XACT_RD25 0x19c4 608 #define EARCRX_CMDC_XACT_RD26 0x19c8 609 #define EARCRX_CMDC_XACT_RD27 0x19cc 610 #define EARCRX_CMDC_XACT_RD28 0x19d0 611 #define EARCRX_CMDC_XACT_RD29 0x19d4 612 #define EARCRX_CMDC_XACT_RD30 0x19d8 613 #define EARCRX_CMDC_XACT_RD31 0x19dc 614 #define EARCRX_CMDC_XACT_RD32 0x19e0 615 #define EARCRX_CMDC_XACT_RD33 0x19e4 616 #define EARCRX_CMDC_XACT_RD34 0x19e8 617 #define EARCRX_CMDC_XACT_RD35 0x19ec 618 #define EARCRX_CMDC_XACT_RD36 0x19f0 619 #define EARCRX_CMDC_XACT_RD37 0x19f4 620 #define EARCRX_CMDC_XACT_RD38 0x19f8 621 #define EARCRX_CMDC_XACT_RD39 0x19fc 622 #define EARCRX_CMDC_XACT_RD40 0x1a00 623 #define EARCRX_CMDC_XACT_RD41 0x1a04 624 #define EARCRX_CMDC_XACT_RD42 0x1a08 625 #define EARCRX_CMDC_XACT_RD43 0x1a0c 626 #define EARCRX_CMDC_XACT_RD44 0x1a10 627 #define EARCRX_CMDC_XACT_RD45 0x1a14 628 #define EARCRX_CMDC_XACT_RD46 0x1a18 629 #define EARCRX_CMDC_XACT_RD47 0x1a1c 630 #define EARCRX_CMDC_XACT_RD48 0x1a20 631 #define EARCRX_CMDC_XACT_RD49 0x1a24 632 #define EARCRX_CMDC_XACT_RD50 0x1a28 633 #define EARCRX_CMDC_XACT_RD51 0x1a2c 634 #define EARCRX_CMDC_XACT_RD52 0x1a30 635 #define EARCRX_CMDC_XACT_RD53 0x1a34 636 #define EARCRX_CMDC_XACT_RD54 0x1a38 637 #define EARCRX_CMDC_XACT_RD55 0x1a3c 638 #define EARCRX_CMDC_XACT_RD56 0x1a40 639 #define EARCRX_CMDC_XACT_RD57 0x1a44 640 #define EARCRX_CMDC_XACT_RD58 0x1a48 641 #define EARCRX_CMDC_XACT_RD59 0x1a4c 642 #define EARCRX_CMDC_XACT_RD60 0x1a50 643 #define EARCRX_CMDC_XACT_RD61 0x1a54 644 #define EARCRX_CMDC_XACT_RD62 0x1a58 645 #define EARCRX_CMDC_XACT_RD63 0x1a5c 646 #define EARCRX_CMDC_XACT_RD64 0x1a60 647 #define EARCRX_CMDC_SYNC_CONFIG 0x1b00 648 /* eARC RX DMAC Registers */ 649 #define EARCRX_DMAC_PHY_CONTROL 0x1c00 650 #define EARCRX_DMAC_CONFIG 0x1c08 651 #define EARCRX_DMAC_CONTROL0 0x1c0c 652 #define EARCRX_DMAC_AUDIO_EN BIT(1) 653 #define EARCRX_DMAC_EN BIT(0) 654 #define EARCRX_DMAC_CONTROL1 0x1c10 655 #define EARCRX_DMAC_STATUS 0x1c14 656 #define EARCRX_DMAC_CHSTATUS0 0x1c18 657 #define EARCRX_DMAC_CHSTATUS1 0x1c1c 658 #define EARCRX_DMAC_CHSTATUS2 0x1c20 659 #define EARCRX_DMAC_CHSTATUS3 0x1c24 660 #define EARCRX_DMAC_CHSTATUS4 0x1c28 661 #define EARCRX_DMAC_CHSTATUS5 0x1c2c 662 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC0 0x1c30 663 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC1 0x1c34 664 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC2 0x1c38 665 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC3 0x1c3c 666 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC4 0x1c40 667 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC5 0x1c44 668 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC6 0x1c48 669 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC7 0x1c4c 670 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC8 0x1c50 671 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC9 0x1c54 672 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC10 0x1c58 673 #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC11 0x1c5c 674 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT0 0x1c60 675 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT1 0x1c64 676 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT2 0x1c68 677 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT3 0x1c6c 678 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT4 0x1c70 679 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT5 0x1c74 680 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT6 0x1c78 681 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT7 0x1c7c 682 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT8 0x1c80 683 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT9 0x1c84 684 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT10 0x1c88 685 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT11 0x1c8c 686 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT0 0x1c90 687 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT1 0x1c94 688 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT2 0x1c98 689 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT3 0x1c9c 690 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT4 0x1ca0 691 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT5 0x1ca4 692 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT6 0x1ca8 693 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT7 0x1cac 694 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT8 0x1cb0 695 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT9 0x1cb4 696 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT10 0x1cb8 697 #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT11 0x1cbc 698 #define EARCRX_DMAC_USRDATA_MSG_GENERIC0 0x1cc0 699 #define EARCRX_DMAC_USRDATA_MSG_GENERIC1 0x1cc4 700 #define EARCRX_DMAC_USRDATA_MSG_GENERIC2 0x1cc8 701 #define EARCRX_DMAC_USRDATA_MSG_GENERIC3 0x1ccc 702 #define EARCRX_DMAC_USRDATA_MSG_GENERIC4 0x1cd0 703 #define EARCRX_DMAC_USRDATA_MSG_GENERIC5 0x1cd4 704 #define EARCRX_DMAC_USRDATA_MSG_GENERIC6 0x1cd8 705 #define EARCRX_DMAC_USRDATA_MSG_GENERIC7 0x1cdc 706 #define EARCRX_DMAC_USRDATA_MSG_GENERIC8 0x1ce0 707 #define EARCRX_DMAC_USRDATA_MSG_GENERIC9 0x1ce4 708 #define EARCRX_DMAC_USRDATA_MSG_GENERIC10 0x1ce8 709 #define EARCRX_DMAC_USRDATA_MSG_GENERIC11 0x1cec 710 #define EARCRX_DMAC_USRDATA_MSG_GENERIC12 0x1cf0 711 #define EARCRX_DMAC_USRDATA_MSG_GENERIC13 0x1cf4 712 #define EARCRX_DMAC_USRDATA_MSG_GENERIC14 0x1cf8 713 #define EARCRX_DMAC_USRDATA_MSG_GENERIC15 0x1cfc 714 #define EARCRX_DMAC_USRDATA_MSG_GENERIC16 0x1d00 715 #define EARCRX_DMAC_USRDATA_MSG_GENERIC17 0x1d04 716 #define EARCRX_DMAC_USRDATA_MSG_GENERIC18 0x1d08 717 #define EARCRX_DMAC_USRDATA_MSG_GENERIC19 0x1d0c 718 #define EARCRX_DMAC_USRDATA_MSG_GENERIC20 0x1d10 719 #define EARCRX_DMAC_USRDATA_MSG_GENERIC21 0x1d14 720 #define EARCRX_DMAC_USRDATA_MSG_GENERIC22 0x1d18 721 #define EARCRX_DMAC_USRDATA_MSG_GENERIC23 0x1d1c 722 #define EARCRX_DMAC_USRDATA_MSG_GENERIC24 0x1d20 723 #define EARCRX_DMAC_USRDATA_MSG_GENERIC25 0x1d24 724 #define EARCRX_DMAC_USRDATA_MSG_GENERIC26 0x1d28 725 #define EARCRX_DMAC_USRDATA_MSG_GENERIC27 0x1d2c 726 #define EARCRX_DMAC_USRDATA_MSG_GENERIC28 0x1d30 727 #define EARCRX_DMAC_USRDATA_MSG_GENERIC29 0x1d34 728 #define EARCRX_DMAC_USRDATA_MSG_GENERIC30 0x1d38 729 #define EARCRX_DMAC_USRDATA_MSG_GENERIC31 0x1d3c 730 #define EARCRX_DMAC_USRDATA_MSG_GENERIC32 0x1d40 731 #define EARCRX_DMAC_CHSTATUS_STREAMER0 0x1d44 732 #define EARCRX_DMAC_CHSTATUS_STREAMER1 0x1d48 733 #define EARCRX_DMAC_CHSTATUS_STREAMER2 0x1d4c 734 #define EARCRX_DMAC_CHSTATUS_STREAMER3 0x1d50 735 #define EARCRX_DMAC_CHSTATUS_STREAMER4 0x1d54 736 #define EARCRX_DMAC_CHSTATUS_STREAMER5 0x1d58 737 #define EARCRX_DMAC_CHSTATUS_STREAMER6 0x1d5c 738 #define EARCRX_DMAC_CHSTATUS_STREAMER7 0x1d60 739 #define EARCRX_DMAC_CHSTATUS_STREAMER8 0x1d64 740 #define EARCRX_DMAC_CHSTATUS_STREAMER9 0x1d68 741 #define EARCRX_DMAC_CHSTATUS_STREAMER10 0x1d6c 742 #define EARCRX_DMAC_CHSTATUS_STREAMER11 0x1d70 743 #define EARCRX_DMAC_CHSTATUS_STREAMER12 0x1d74 744 #define EARCRX_DMAC_CHSTATUS_STREAMER13 0x1d78 745 #define EARCRX_DMAC_CHSTATUS_STREAMER14 0x1d7c 746 #define EARCRX_DMAC_USRDATA_STREAMER0 0x1d80 747 /* Main Unit Interrupt Registers */ 748 #define MAIN_INTVEC_INDEX 0x3000 749 #define MAINUNIT_0_INT_STATUS 0x3010 750 #define MAINUNIT_0_INT_MASK_N 0x3014 751 #define MAINUNIT_0_INT_CLEAR 0x3018 752 #define MAINUNIT_0_INT_FORCE 0x301c 753 #define MAINUNIT_1_INT_STATUS 0x3020 754 #define FLT_EXIT_TO_LTSL_IRQ BIT(22) 755 #define FLT_EXIT_TO_LTS4_IRQ BIT(21) 756 #define FLT_EXIT_TO_LTSP_IRQ BIT(20) 757 #define SCDC_NACK_RCVD_IRQ BIT(12) 758 #define SCDC_RR_REPLY_STOP_IRQ BIT(11) 759 #define SCDC_UPD_FLAGS_CLR_IRQ BIT(10) 760 #define SCDC_UPD_FLAGS_CHG_IRQ BIT(9) 761 #define SCDC_UPD_FLAGS_RD_IRQ BIT(8) 762 #define I2CM_NACK_RCVD_IRQ BIT(2) 763 #define I2CM_READ_REQUEST_IRQ BIT(1) 764 #define I2CM_OP_DONE_IRQ BIT(0) 765 #define MAINUNIT_1_INT_MASK_N 0x3024 766 #define I2CM_NACK_RCVD_MASK_N BIT(2) 767 #define I2CM_READ_REQUEST_MASK_N BIT(1) 768 #define I2CM_OP_DONE_MASK_N BIT(0) 769 #define MAINUNIT_1_INT_CLEAR 0x3028 770 #define I2CM_NACK_RCVD_CLEAR BIT(2) 771 #define I2CM_READ_REQUEST_CLEAR BIT(1) 772 #define I2CM_OP_DONE_CLEAR BIT(0) 773 #define MAINUNIT_1_INT_FORCE 0x302c 774 /* AVPUNIT Interrupt Registers */ 775 #define AVP_INTVEC_INDEX 0x3800 776 #define AVP_0_INT_STATUS 0x3810 777 #define AVP_0_INT_MASK_N 0x3814 778 #define AVP_0_INT_CLEAR 0x3818 779 #define AVP_0_INT_FORCE 0x381c 780 #define AVP_1_INT_STATUS 0x3820 781 #define AVP_1_INT_MASK_N 0x3824 782 #define HDCP14_AUTH_CHG_MASK_N BIT(6) 783 #define AVP_1_INT_CLEAR 0x3828 784 #define AVP_1_INT_FORCE 0x382c 785 #define AVP_2_INT_STATUS 0x3830 786 #define AVP_2_INT_MASK_N 0x3834 787 #define AVP_2_INT_CLEAR 0x3838 788 #define AVP_2_INT_FORCE 0x383c 789 #define AVP_3_INT_STATUS 0x3840 790 #define AVP_3_INT_MASK_N 0x3844 791 #define AVP_3_INT_CLEAR 0x3848 792 #define AVP_3_INT_FORCE 0x384c 793 #define AVP_4_INT_STATUS 0x3850 794 #define AVP_4_INT_MASK_N 0x3854 795 #define AVP_4_INT_CLEAR 0x3858 796 #define AVP_4_INT_FORCE 0x385c 797 #define AVP_5_INT_STATUS 0x3860 798 #define AVP_5_INT_MASK_N 0x3864 799 #define AVP_5_INT_CLEAR 0x3868 800 #define AVP_5_INT_FORCE 0x386c 801 #define AVP_6_INT_STATUS 0x3870 802 #define AVP_6_INT_MASK_N 0x3874 803 #define AVP_6_INT_CLEAR 0x3878 804 #define AVP_6_INT_FORCE 0x387c 805 /* CEC Interrupt Registers */ 806 #define CEC_INT_STATUS 0x4000 807 #define CEC_INT_MASK_N 0x4004 808 #define CEC_INT_CLEAR 0x4008 809 #define CEC_INT_FORCE 0x400c 810 /* eARC RX Interrupt Registers */ 811 #define EARCRX_INTVEC_INDEX 0x4800 812 #define EARCRX_0_INT_STATUS 0x4810 813 #define EARCRX_CMDC_DISCOVERY_TIMEOUT_IRQ BIT(9) 814 #define EARCRX_CMDC_DISCOVERY_DONE_IRQ BIT(8) 815 #define EARCRX_0_INT_MASK_N 0x4814 816 #define EARCRX_0_INT_CLEAR 0x4818 817 #define EARCRX_0_INT_FORCE 0x481c 818 #define EARCRX_1_INT_STATUS 0x4820 819 #define EARCRX_1_INT_MASK_N 0x4824 820 #define EARCRX_1_INT_CLEAR 0x4828 821 #define EARCRX_1_INT_FORCE 0x482c 822 823 /* SCDC Registers */ 824 #define SCDC_SINK_VERSION 0x01 825 #define SCDC_SOURCE_VERSION 0x02 826 827 #define SCDC_UPDATE_0 0x10 828 #define SCDC_READ_REQUEST_TEST BIT(2) 829 #define SCDC_CED_UPDATE BIT(1) 830 #define SCDC_STATUS_UPDATE BIT(0) 831 #define SCDC_UPDATE_1 0x11 832 833 #define SCDC_TMDS_CONFIG 0x20 834 #define SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 BIT(1) 835 #define SCDC_TMDS_BIT_CLOCK_RATIO_BY_10 (0 << 1) 836 #define SCDC_SCRAMBLING_ENABLE BIT(0) 837 #define SCDC_SCRAMBLER_STATUS 0x21 838 #define SCDC_SCRAMBLING_STATUS BIT(0) 839 840 #define SCDC_CONFIG_0 0x30 841 #define SCDC_READ_REQUEST_ENABLE BIT(0) 842 843 #define SCDC_STATUS_FLAGS_0 0x40 844 #define SCDC_CH2_LOCK BIT(3) 845 #define SCDC_CH1_LOCK BIT(2) 846 #define SCDC_CH0_LOCK BIT(1) 847 #define SCDC_CH_LOCK_MASK (SCDC_CH2_LOCK | SCDC_CH1_LOCK | SCDC_CH0_LOCK) 848 #define SCDC_CLOCK_DETECT BIT(0) 849 #define SCDC_STATUS_FLAGS_1 0x41 850 851 #define SCDC_ERR_DET_0_L 0x50 852 #define SCDC_ERR_DET_0_H 0x51 853 #define SCDC_ERR_DET_1_L 0x52 854 #define SCDC_ERR_DET_1_H 0x53 855 #define SCDC_ERR_DET_2_L 0x54 856 #define SCDC_ERR_DET_2_H 0x55 857 #define SCDC_CHANNEL_VALID BIT(7) 858 #define SCDC_ERR_DET_CHECKSUM 0x56 859 860 #define SCDC_TEST_CONFIG_0 0xc0 861 #define SCDC_TEST_READ_REQUEST BIT(7) 862 #define SCDC_TEST_READ_REQUEST_DELAY(x) ((x) & 0x7f) 863 864 #define SCDC_MANUFACTURER_IEEE_OUI 0xd0 865 #define SCDC_MANUFACTURER_IEEE_OUI_SIZE 3 866 #define SCDC_DEVICE_ID 0xd3 867 #define SCDC_DEVICE_ID_SIZE 8 868 #define SCDC_DEVICE_HARDWARE_REVISION 0xdb 869 #define SCDC_DEVICE_HARDWARE_REVISION_MAJOR(x) (((x) >> 4) & 0xf) 870 #define SCDC_DEVICE_HARDWARE_REVISION_MINOR(x) (((x) >> 0) & 0xf) 871 #define SCDC_DEVICE_SOFTWARE_MAJOR_REVISION 0xdc 872 #define SCDC_DEVICE_SOFTWARE_MINOR_REVISION 0xdd 873 874 #define SCDC_MANUFACTURER_SPECIFIC 0xde 875 #define SCDC_MANUFACTURER_SPECIFIC_SIZE 34 876 877 enum v4l2_ycbcr_encoding { 878 /* 879 * Mapping of V4L2_YCBCR_ENC_DEFAULT to actual encodings for the 880 * various colorspaces: 881 * 882 * V4L2_COLORSPACE_SMPTE170M, V4L2_COLORSPACE_470_SYSTEM_M, 883 * V4L2_COLORSPACE_470_SYSTEM_BG, V4L2_COLORSPACE_ADOBERGB and 884 * V4L2_COLORSPACE_JPEG: V4L2_YCBCR_ENC_601 885 * 886 * V4L2_COLORSPACE_REC709 and V4L2_COLORSPACE_DCI_P3: V4L2_YCBCR_ENC_709 887 * 888 * V4L2_COLORSPACE_SRGB: V4L2_YCBCR_ENC_SYCC 889 * 890 * V4L2_COLORSPACE_BT2020: V4L2_YCBCR_ENC_BT2020 891 * 892 * V4L2_COLORSPACE_SMPTE240M: V4L2_YCBCR_ENC_SMPTE240M 893 */ 894 V4L2_YCBCR_ENC_DEFAULT = 0, 895 896 /* ITU-R 601 -- SDTV */ 897 V4L2_YCBCR_ENC_601 = 1, 898 899 /* Rec. 709 -- HDTV */ 900 V4L2_YCBCR_ENC_709 = 2, 901 902 /* ITU-R 601/EN 61966-2-4 Extended Gamut -- SDTV */ 903 V4L2_YCBCR_ENC_XV601 = 3, 904 905 /* Rec. 709/EN 61966-2-4 Extended Gamut -- HDTV */ 906 V4L2_YCBCR_ENC_XV709 = 4, 907 908 /* sYCC (Y'CbCr encoding of sRGB) */ 909 V4L2_YCBCR_ENC_SYCC = 5, 910 911 /* BT.2020 Non-constant Luminance Y'CbCr */ 912 V4L2_YCBCR_ENC_BT2020 = 6, 913 914 /* BT.2020 Constant Luminance Y'CbcCrc */ 915 V4L2_YCBCR_ENC_BT2020_CONST_LUM = 7, 916 917 /* SMPTE 240M -- Obsolete HDTV */ 918 V4L2_YCBCR_ENC_SMPTE240M = 8, 919 }; 920 921 enum drm_connector_status { 922 connector_status_disconnected = 0, 923 connector_status_connected = 1, 924 }; 925 926 void rk3588_set_grf_cfg(void *data); 927 void dw_hdmi_qp_set_iomux(void *data); 928 struct dw_hdmi_link_config *dw_hdmi_rockchip_get_link_cfg(void *data); 929 void dw_hdmi_qp_selete_output(struct hdmi_edid_data *edid_data, 930 struct connector_state *conn_state, 931 unsigned int *bus_format, 932 struct overscan *overscan, 933 enum dw_hdmi_devtype dev_type, 934 bool output_bus_format_rgb, 935 void *data, struct display_state *state); 936 937 #endif /* __DW_HDMI_QP_H__ */ 938