1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd 4 * Author: Algea Cao <algea.cao@rock-chips.com> 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <syscon.h> 10 #include <asm/arch-rockchip/clock.h> 11 #include <asm/arch/vendor.h> 12 #include <edid.h> 13 #include <dm/device.h> 14 #include <dm/of_access.h> 15 #include <dm/ofnode.h> 16 #include <dm/read.h> 17 #include <linux/hdmi.h> 18 #include <linux/media-bus-format.h> 19 #include <linux/dw_hdmi.h> 20 #include <asm/io.h> 21 #include "rockchip_display.h" 22 #include "rockchip_crtc.h" 23 #include "rockchip_connector.h" 24 #include "dw_hdmi_qp.h" 25 #include "rockchip_phy.h" 26 27 enum frl_mask { 28 FRL_3GBPS_3LANE = 1, 29 FRL_6GBPS_3LANE, 30 FRL_6GBPS_4LANE, 31 FRL_8GBPS_4LANE, 32 FRL_10GBPS_4LANE, 33 FRL_12GBPS_4LANE, 34 }; 35 36 #define DDC_CI_ADDR 0x37 37 #define DDC_SEGMENT_ADDR 0x30 38 39 #define HDMI_EDID_LEN 512 40 41 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ 42 #define SCDC_MIN_SOURCE_VERSION 0x1 43 44 #define HDMI14_MAX_TMDSCLK 340000000 45 46 struct hdmi_vmode { 47 bool mdataenablepolarity; 48 49 unsigned int mpixelclock; 50 unsigned int mpixelrepetitioninput; 51 unsigned int mpixelrepetitionoutput; 52 unsigned int mtmdsclock; 53 }; 54 55 struct hdmi_data_info { 56 unsigned int enc_in_bus_format; 57 unsigned int enc_out_bus_format; 58 unsigned int enc_in_encoding; 59 unsigned int enc_out_encoding; 60 unsigned int quant_range; 61 unsigned int pix_repet_factor; 62 struct hdmi_vmode video_mode; 63 }; 64 65 struct dw_hdmi_phy_data { 66 enum dw_hdmi_phy_type type; 67 const char *name; 68 unsigned int gen; 69 bool has_svsret; 70 int (*configure)(struct dw_hdmi *hdmi, 71 const struct dw_hdmi_plat_data *pdata, 72 unsigned long mpixelclock); 73 }; 74 75 struct dw_hdmi_i2c { 76 u8 slave_reg; 77 bool is_regaddr; 78 bool is_segment; 79 80 unsigned int scl_high_ns; 81 unsigned int scl_low_ns; 82 }; 83 84 struct dw_hdmi_qp { 85 enum dw_hdmi_devtype dev_type; 86 unsigned int version; 87 struct hdmi_data_info hdmi_data; 88 struct hdmi_edid_data edid_data; 89 const struct dw_hdmi_plat_data *plat_data; 90 struct ddc_adapter adap; 91 92 int vic; 93 int id; 94 95 unsigned long bus_format; 96 bool cable_plugin; 97 bool sink_is_hdmi; 98 bool sink_has_audio; 99 void *regs; 100 void *rk_hdmi; 101 struct dw_hdmi_i2c *i2c; 102 103 struct { 104 const struct dw_hdmi_qp_phy_ops *ops; 105 const char *name; 106 void *data; 107 bool enabled; 108 } phy; 109 110 struct drm_display_mode previous_mode; 111 112 unsigned int sample_rate; 113 unsigned int audio_cts; 114 unsigned int audio_n; 115 bool audio_enable; 116 bool scramble_low_rates; 117 118 void (*write)(struct dw_hdmi_qp *hdmi, u32 val, int offset); 119 u8 (*read)(struct dw_hdmi_qp *hdmi, int offset); 120 121 bool hdcp1x_enable; 122 bool output_bus_format_rgb; 123 }; 124 125 static inline void hdmi_writel(struct dw_hdmi_qp *hdmi, u32 val, int offset) 126 { 127 writel(val, hdmi->regs + offset); 128 } 129 130 static inline u32 hdmi_readl(struct dw_hdmi_qp *hdmi, int offset) 131 { 132 return readl(hdmi->regs + offset); 133 } 134 135 static void 136 hdmi_modb(struct dw_hdmi_qp *hdmi, u32 data, u32 mask, unsigned int reg) 137 { 138 u32 val = hdmi_readl(hdmi, reg) & ~mask; 139 140 val |= data & mask; 141 hdmi_writel(hdmi, val, reg); 142 } 143 144 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 145 { 146 switch (bus_format) { 147 case MEDIA_BUS_FMT_RGB888_1X24: 148 case MEDIA_BUS_FMT_RGB101010_1X30: 149 case MEDIA_BUS_FMT_RGB121212_1X36: 150 case MEDIA_BUS_FMT_RGB161616_1X48: 151 return true; 152 153 default: 154 return false; 155 } 156 } 157 158 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 159 { 160 switch (bus_format) { 161 case MEDIA_BUS_FMT_YUV8_1X24: 162 case MEDIA_BUS_FMT_YUV10_1X30: 163 case MEDIA_BUS_FMT_YUV12_1X36: 164 case MEDIA_BUS_FMT_YUV16_1X48: 165 return true; 166 167 default: 168 return false; 169 } 170 } 171 172 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 173 { 174 switch (bus_format) { 175 case MEDIA_BUS_FMT_UYVY8_1X16: 176 case MEDIA_BUS_FMT_UYVY10_1X20: 177 case MEDIA_BUS_FMT_UYVY12_1X24: 178 return true; 179 180 default: 181 return false; 182 } 183 } 184 185 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 186 { 187 switch (bus_format) { 188 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 189 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 190 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 191 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 192 return true; 193 194 default: 195 return false; 196 } 197 } 198 199 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 200 { 201 switch (bus_format) { 202 case MEDIA_BUS_FMT_RGB888_1X24: 203 case MEDIA_BUS_FMT_YUV8_1X24: 204 case MEDIA_BUS_FMT_UYVY8_1X16: 205 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 206 return 8; 207 208 case MEDIA_BUS_FMT_RGB101010_1X30: 209 case MEDIA_BUS_FMT_YUV10_1X30: 210 case MEDIA_BUS_FMT_UYVY10_1X20: 211 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 212 return 10; 213 214 case MEDIA_BUS_FMT_RGB121212_1X36: 215 case MEDIA_BUS_FMT_YUV12_1X36: 216 case MEDIA_BUS_FMT_UYVY12_1X24: 217 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 218 return 12; 219 220 case MEDIA_BUS_FMT_RGB161616_1X48: 221 case MEDIA_BUS_FMT_YUV16_1X48: 222 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 223 return 16; 224 225 default: 226 return 0; 227 } 228 } 229 230 static bool drm_scdc_set_scrambling(struct ddc_adapter *adapter, bool enable) 231 { 232 u8 config; 233 int ret; 234 235 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 236 if (ret < 0) { 237 debug("Failed to read TMDS config: %d\n", ret); 238 return false; 239 } 240 241 if (enable) 242 config |= SCDC_SCRAMBLING_ENABLE; 243 else 244 config &= ~SCDC_SCRAMBLING_ENABLE; 245 246 ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config); 247 if (ret < 0) { 248 debug("Failed to enable scrambling: %d\n", ret); 249 return false; 250 } 251 252 return true; 253 } 254 255 static bool 256 drm_scdc_set_high_tmds_clock_ratio(struct ddc_adapter *adapter, bool set) 257 { 258 u8 config; 259 int ret; 260 261 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 262 if (ret < 0) { 263 debug("Failed to read TMDS config: %d\n", ret); 264 return false; 265 } 266 267 if (set) 268 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 269 else 270 config &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 271 272 ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config); 273 if (ret < 0) { 274 debug("Failed to set TMDS clock ratio: %d\n", ret); 275 return false; 276 } 277 278 /* 279 * The spec says that a source should wait minimum 1ms and maximum 280 * 100ms after writing the TMDS config for clock ratio. Lets allow a 281 * wait of up to 2ms here. 282 */ 283 udelay(2000); 284 return true; 285 } 286 287 static void dw_hdmi_i2c_init(struct dw_hdmi_qp *hdmi) 288 { 289 /* Software reset */ 290 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 291 292 hdmi_writel(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0); 293 294 hdmi_modb(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0); 295 296 /* Clear DONE and ERROR interrupts */ 297 hdmi_writel(hdmi, I2CM_OP_DONE_CLEAR | I2CM_NACK_RCVD_CLEAR, 298 MAINUNIT_1_INT_CLEAR); 299 } 300 301 static int dw_hdmi_i2c_read(struct dw_hdmi_qp *hdmi, 302 unsigned char *buf, unsigned int length) 303 { 304 struct dw_hdmi_i2c *i2c = hdmi->i2c; 305 int i = 20; 306 u32 intr = 0; 307 308 if (!i2c->is_regaddr) { 309 printf("set read register address to 0\n"); 310 i2c->slave_reg = 0x00; 311 i2c->is_regaddr = true; 312 } 313 314 while (length--) { 315 hdmi_modb(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, 316 I2CM_INTERFACE_CONTROL0); 317 318 hdmi_modb(hdmi, I2CM_FM_READ, I2CM_WR_MASK, 319 I2CM_INTERFACE_CONTROL0); 320 321 while (i--) { 322 udelay(1000); 323 intr = hdmi_readl(hdmi, MAINUNIT_1_INT_STATUS) & 324 (I2CM_OP_DONE_IRQ | I2CM_READ_REQUEST_IRQ | 325 I2CM_NACK_RCVD_IRQ); 326 if (intr) { 327 hdmi_writel(hdmi, intr, MAINUNIT_1_INT_CLEAR); 328 break; 329 } 330 } 331 332 if (!i) { 333 printf("i2c read time out!\n"); 334 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 335 return -EAGAIN; 336 } 337 338 /* Check for error condition on the bus */ 339 if (intr & I2CM_NACK_RCVD_IRQ) { 340 printf("i2c read err!\n"); 341 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 342 return -EIO; 343 } 344 345 *buf++ = hdmi_readl(hdmi, I2CM_INTERFACE_RDDATA_0_3) & 0xff; 346 hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); 347 i = 20; 348 } 349 i2c->is_segment = false; 350 351 return 0; 352 } 353 354 static int dw_hdmi_i2c_write(struct dw_hdmi_qp *hdmi, 355 unsigned char *buf, unsigned int length) 356 { 357 struct dw_hdmi_i2c *i2c = hdmi->i2c; 358 int i = 20; 359 u32 intr = 0; 360 361 if (!i2c->is_regaddr) { 362 /* Use the first write byte as register address */ 363 i2c->slave_reg = buf[0]; 364 length--; 365 buf++; 366 i2c->is_regaddr = true; 367 } 368 369 while (length--) { 370 hdmi_writel(hdmi, *buf++, I2CM_INTERFACE_WRDATA_0_3); 371 hdmi_modb(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, 372 I2CM_INTERFACE_CONTROL0); 373 hdmi_modb(hdmi, I2CM_FM_WRITE, I2CM_WR_MASK, 374 I2CM_INTERFACE_CONTROL0); 375 376 while (i--) { 377 udelay(1000); 378 intr = hdmi_readl(hdmi, MAINUNIT_1_INT_STATUS) & 379 (I2CM_OP_DONE_IRQ | I2CM_READ_REQUEST_IRQ | 380 I2CM_NACK_RCVD_IRQ); 381 if (intr) { 382 hdmi_writel(hdmi, intr, MAINUNIT_1_INT_CLEAR); 383 break; 384 } 385 } 386 387 if (!i) { 388 printf("i2c write time out!\n"); 389 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 390 return -EAGAIN; 391 } 392 393 /* Check for error condition on the bus */ 394 if (intr & I2CM_NACK_RCVD_IRQ) { 395 printf("i2c write nack!\n"); 396 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 397 return -EIO; 398 } 399 hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); 400 i = 20; 401 } 402 403 return 0; 404 } 405 406 static int dw_hdmi_i2c_xfer(struct ddc_adapter *adap, 407 struct i2c_msg *msgs, int num) 408 { 409 struct dw_hdmi_qp *hdmi = container_of(adap, struct dw_hdmi_qp, adap); 410 struct dw_hdmi_i2c *i2c = hdmi->i2c; 411 u8 addr = msgs[0].addr; 412 int i, ret = 0; 413 414 debug("i2c xfer: num: %d, addr: %#x\n", num, addr); 415 416 for (i = 0; i < num; i++) { 417 if (msgs[i].len == 0) { 418 printf("unsupported transfer %d/%d, no data\n", 419 i + 1, num); 420 return -EOPNOTSUPP; 421 } 422 } 423 424 /* Unmute DONE and ERROR interrupts */ 425 hdmi_modb(hdmi, I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, 426 I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, 427 MAINUNIT_1_INT_MASK_N); 428 429 /* Set slave device address taken from the first I2C message */ 430 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1) 431 addr = DDC_ADDR; 432 433 hdmi_modb(hdmi, addr << 5, I2CM_SLVADDR, I2CM_INTERFACE_CONTROL0); 434 435 /* Set slave device register address on transfer */ 436 i2c->is_regaddr = false; 437 438 /* Set segment pointer for I2C extended read mode operation */ 439 i2c->is_segment = false; 440 441 for (i = 0; i < num; i++) { 442 debug("xfer: num: %d/%d, len: %d, flags: %#x\n", 443 i + 1, num, msgs[i].len, msgs[i].flags); 444 445 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 446 i2c->is_segment = true; 447 hdmi_modb(hdmi, DDC_SEGMENT_ADDR, I2CM_SEG_ADDR, 448 I2CM_INTERFACE_CONTROL1); 449 hdmi_modb(hdmi, *msgs[i].buf, I2CM_SEG_PTR, 450 I2CM_INTERFACE_CONTROL1); 451 } else { 452 if (msgs[i].flags & I2C_M_RD) 453 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 454 msgs[i].len); 455 else 456 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 457 msgs[i].len); 458 } 459 if (ret < 0) 460 break; 461 } 462 463 if (!ret) 464 ret = num; 465 466 /* Mute DONE and ERROR interrupts */ 467 hdmi_modb(hdmi, 0, I2CM_OP_DONE_MASK_N | I2CM_NACK_RCVD_MASK_N, 468 MAINUNIT_1_INT_MASK_N); 469 470 return ret; 471 } 472 473 static int dw_hdmi_detect_phy(struct dw_hdmi_qp *hdmi) 474 { 475 /* Vendor PHYs require support from the glue layer. */ 476 if (!hdmi->plat_data->qp_phy_ops || !hdmi->plat_data->phy_name) { 477 dev_err(hdmi->dev, 478 "Vendor HDMI PHY not supported by glue layer\n"); 479 return -ENODEV; 480 } 481 482 hdmi->phy.ops = hdmi->plat_data->qp_phy_ops; 483 hdmi->phy.data = hdmi->plat_data->phy_data; 484 hdmi->phy.name = hdmi->plat_data->phy_name; 485 486 return 0; 487 } 488 489 static unsigned int 490 hdmi_get_tmdsclock(struct dw_hdmi_qp *hdmi, unsigned long mpixelclock) 491 { 492 unsigned int tmdsclock = mpixelclock; 493 unsigned int depth = 494 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 495 496 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 497 switch (depth) { 498 case 16: 499 tmdsclock = mpixelclock * 2; 500 break; 501 case 12: 502 tmdsclock = mpixelclock * 3 / 2; 503 break; 504 case 10: 505 tmdsclock = mpixelclock * 5 / 4; 506 break; 507 default: 508 break; 509 } 510 } 511 512 return tmdsclock; 513 } 514 515 static void hdmi_config_AVI(struct dw_hdmi_qp *hdmi, struct drm_display_mode *mode) 516 { 517 struct hdmi_avi_infoframe frame; 518 u32 val, i, j; 519 u8 buff[17]; 520 bool is_hdmi2 = false; 521 enum hdmi_quantization_range rgb_quant_range = 522 hdmi->hdmi_data.quant_range; 523 524 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) || 525 hdmi->edid_data.display_info.hdmi.scdc.supported) 526 is_hdmi2 = true; 527 /* Initialise info frame from DRM mode */ 528 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2); 529 530 /* 531 * Ignore monitor selectable quantization, use quantization set 532 * by the user 533 */ 534 drm_hdmi_avi_infoframe_quant_range(&frame, mode, rgb_quant_range, 535 true); 536 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 537 frame.colorspace = HDMI_COLORSPACE_YUV444; 538 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 539 frame.colorspace = HDMI_COLORSPACE_YUV422; 540 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 541 frame.colorspace = HDMI_COLORSPACE_YUV420; 542 else 543 frame.colorspace = HDMI_COLORSPACE_RGB; 544 545 /* Set up colorimetry */ 546 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 547 switch (hdmi->hdmi_data.enc_out_encoding) { 548 case V4L2_YCBCR_ENC_601: 549 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 550 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 551 else 552 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 553 frame.extended_colorimetry = 554 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 555 break; 556 case V4L2_YCBCR_ENC_709: 557 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 558 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 559 else 560 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 561 frame.extended_colorimetry = 562 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 563 break; 564 default: /* Carries no data */ 565 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 566 frame.extended_colorimetry = 567 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 568 break; 569 } 570 } 571 572 frame.scan_mode = HDMI_SCAN_MODE_NONE; 573 frame.video_code = hdmi->vic; 574 575 hdmi_avi_infoframe_pack_only(&frame, buff, 17); 576 577 /* 578 * The Designware IP uses a different byte format from standard 579 * AVI info frames, though generally the bits are in the correct 580 * bytes. 581 */ 582 583 val = (frame.version << 8) | (frame.length << 16); 584 hdmi_writel(hdmi, val, PKT_AVI_CONTENTS0); 585 586 for (i = 0; i < 4; i++) { 587 for (j = 0; j < 4; j++) { 588 if (i * 4 + j >= 14) 589 break; 590 if (!j) 591 val = buff[i * 4 + j + 3]; 592 val |= buff[i * 4 + j + 3] << (8 * j); 593 } 594 595 hdmi_writel(hdmi, val, PKT_AVI_CONTENTS1 + i * 4); 596 } 597 598 hdmi_modb(hdmi, 0, PKTSCHED_AVI_FIELDRATE, PKTSCHED_PKT_CONFIG1); 599 600 hdmi_modb(hdmi, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, 601 PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, 602 PKTSCHED_PKT_EN); 603 } 604 605 static void hdmi_config_CVTEM(struct dw_hdmi_qp *hdmi, 606 struct dw_hdmi_link_config *link_cfg) 607 { 608 u8 ds_type = 0; 609 u8 sync = 1; 610 u8 vfr = 1; 611 u8 afr = 0; 612 u8 new = 1; 613 u8 end = 0; 614 u8 data_set_length = 136; 615 u8 hb1[6] = { 0x80, 0, 0, 0, 0, 0x40 }; 616 u8 *pps_body; 617 u32 val, i, reg; 618 struct drm_display_mode *mode = &hdmi->previous_mode; 619 int hsync, hfront, hback; 620 621 hdmi_modb(hdmi, 0, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_PKT_EN); 622 623 if (!link_cfg->dsc_mode) { 624 printf("don't use dsc mode\n"); 625 return; 626 } 627 628 pps_body = link_cfg->pps_payload; 629 630 hsync = mode->hsync_end - mode->hsync_start; 631 hback = mode->htotal - mode->hsync_end; 632 hfront = mode->hsync_start - mode->hdisplay; 633 634 for (i = 0; i < 6; i++) { 635 val = i << 16 | hb1[i] << 8; 636 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS0 + i * 0x20); 637 } 638 639 val = new << 7 | end << 6 | ds_type << 4 | afr << 3 | 640 vfr << 2 | sync << 1; 641 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS1); 642 643 val = data_set_length << 16 | pps_body[0] << 24; 644 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS2); 645 646 reg = PKT0_EMP_CVTEM_CONTENTS3; 647 for (i = 1; i < 125; i++) { 648 if (reg == PKT1_EMP_CVTEM_CONTENTS0 || 649 reg == PKT2_EMP_CVTEM_CONTENTS0 || 650 reg == PKT3_EMP_CVTEM_CONTENTS0 || 651 reg == PKT4_EMP_CVTEM_CONTENTS0 || 652 reg == PKT5_EMP_CVTEM_CONTENTS0) { 653 reg += 4; 654 i--; 655 continue; 656 } 657 if (i % 4 == 1) 658 val = pps_body[i]; 659 if (i % 4 == 2) 660 val |= pps_body[i] << 8; 661 if (i % 4 == 3) 662 val |= pps_body[i] << 16; 663 if (!(i % 4)) { 664 val |= pps_body[i] << 24; 665 hdmi_writel(hdmi, val, reg); 666 reg += 4; 667 } 668 } 669 670 val = (hfront & 0xff) << 24 | pps_body[127] << 16 | 671 pps_body[126] << 8 | pps_body[125]; 672 hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS6); 673 674 val = (hback & 0xff) << 24 | ((hsync >> 8) & 0xff) << 16 | 675 (hsync & 0xff) << 8 | ((hfront >> 8) & 0xff); 676 hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS7); 677 678 val = link_cfg->hcactive << 8 | ((hback >> 8) & 0xff); 679 hdmi_writel(hdmi, val, PKT5_EMP_CVTEM_CONTENTS1); 680 681 for (i = PKT5_EMP_CVTEM_CONTENTS2; i <= PKT5_EMP_CVTEM_CONTENTS7; i += 4) 682 hdmi_writel(hdmi, 0, i); 683 684 hdmi_modb(hdmi, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_EMP_CVTEM_TX_EN, 685 PKTSCHED_PKT_EN); 686 } 687 688 static int hdmi_set_frl_mask(int frl_rate) 689 { 690 switch (frl_rate) { 691 case 48: 692 return FRL_12GBPS_4LANE; 693 case 40: 694 return FRL_10GBPS_4LANE; 695 case 32: 696 return FRL_8GBPS_4LANE; 697 case 24: 698 return FRL_6GBPS_4LANE; 699 case 18: 700 return FRL_6GBPS_3LANE; 701 case 9: 702 return FRL_3GBPS_3LANE; 703 } 704 705 return 0; 706 } 707 708 static int hdmi_start_flt(struct dw_hdmi_qp *hdmi, u8 rate) 709 { 710 u8 val; 711 u32 value; 712 u8 ffe_lv = 0; 713 int i = 0; 714 bool ltsp = false; 715 716 hdmi_modb(hdmi, BIT(6), BIT(6), 0x44); 717 /* FLT_READY & FFE_LEVELS read */ 718 for (i = 0; i < 20; i++) { 719 drm_scdc_readb(&hdmi->adap, SCDC_STATUS_FLAGS_0, &val); 720 if (val & BIT(6)) 721 break; 722 mdelay(20); 723 } 724 725 if (i == 20) { 726 dev_err(hdmi->dev, "sink flt isn't ready\n"); 727 return -EINVAL; 728 } 729 730 /* max ffe level 3 */ 731 val = 0 << 4 | hdmi_set_frl_mask(rate); 732 drm_scdc_writeb(&hdmi->adap, 0x31, val); 733 734 /* select FRL_RATE & FFE_LEVELS */ 735 hdmi_writel(hdmi, ffe_lv, FLT_CONFIG0); 736 737 while (1) { 738 mdelay(4); 739 drm_scdc_readb(&hdmi->adap, 0x10, &val); 740 741 if (!(val & 0x30)) 742 continue; 743 744 if (val & BIT(5)) { 745 u8 reg_val, ln0, ln1, ln2, ln3; 746 747 drm_scdc_readb(&hdmi->adap, 0x41, ®_val); 748 ln0 = reg_val & 0xf; 749 ln1 = (reg_val >> 4) & 0xf; 750 751 drm_scdc_readb(&hdmi->adap, 0x42, ®_val); 752 ln2 = reg_val & 0xf; 753 ln3 = (reg_val >> 4) & 0xf; 754 755 if (!ln0 && !ln1 && !ln2 && !ln3) { 756 printf("ltsp!\n"); 757 ltsp = true; 758 hdmi_writel(hdmi, 0, FLT_CONFIG1); 759 } else if ((ln0 == 0xf) | (ln1 == 0xf) | (ln2 == 0xf) | (ln3 == 0xf)) { 760 printf("lts4!\n"); 761 break; 762 } else if ((ln0 == 0xe) | (ln1 == 0xe) | (ln2 == 0xe) | (ln3 == 0xe)) { 763 printf("ffe!\n"); 764 break; 765 } else { 766 value = (ln3 << 16) | (ln2 << 12) | (ln1 << 8) | (ln0 << 4) | 0xf; 767 hdmi_writel(hdmi, value, FLT_CONFIG1); 768 } 769 } 770 771 drm_scdc_writeb(&hdmi->adap, 0x10, val); 772 773 if ((val & BIT(4)) && ltsp) { 774 printf("flt success\n"); 775 break; 776 } 777 } 778 779 hdmi_modb(hdmi, 0, BIT(6), 0x44); 780 return 0; 781 } 782 783 #define HDMI_MODE_FRL_MASK BIT(30) 784 785 static void hdmi_set_op_mode(struct dw_hdmi_qp *hdmi, 786 struct dw_hdmi_link_config *link_cfg, 787 bool scdc_support) 788 { 789 int frl_rate; 790 int i; 791 792 hdmi_writel(hdmi, 0, FLT_CONFIG0); 793 if (scdc_support) 794 drm_scdc_writeb(&hdmi->adap, 0x31, 0); 795 mdelay(200); 796 if (!link_cfg->frl_mode) { 797 printf("dw hdmi qp use tmds mode\n"); 798 hdmi_modb(hdmi, 0, OPMODE_FRL, LINK_CONFIG0); 799 hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0); 800 return; 801 } 802 803 if (link_cfg->frl_lanes == 4) 804 hdmi_modb(hdmi, OPMODE_FRL_4LANES, OPMODE_FRL_4LANES, 805 LINK_CONFIG0); 806 else 807 hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0); 808 809 hdmi_modb(hdmi, 1, OPMODE_FRL, LINK_CONFIG0); 810 811 frl_rate = link_cfg->frl_lanes * link_cfg->rate_per_lane; 812 hdmi_start_flt(hdmi, frl_rate); 813 814 for (i = 0; i < 50; i++) { 815 hdmi_modb(hdmi, PKTSCHED_NULL_TX_EN, PKTSCHED_NULL_TX_EN, PKTSCHED_PKT_EN); 816 mdelay(1); 817 hdmi_modb(hdmi, 0, PKTSCHED_NULL_TX_EN, PKTSCHED_PKT_EN); 818 } 819 } 820 821 static int dw_hdmi_setup(struct dw_hdmi_qp *hdmi, 822 struct drm_display_mode *mode, 823 struct display_state *state) 824 { 825 int ret; 826 void *data = hdmi->plat_data->phy_data; 827 struct dw_hdmi_link_config *link_cfg; 828 struct drm_hdmi_info *hdmi_info = &hdmi->edid_data.display_info.hdmi; 829 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 830 u8 bytes = 0; 831 832 if (!hdmi->vic) 833 printf("Non-CEA mode used in HDMI\n"); 834 else 835 printf("CEA mode used vic=%d\n", hdmi->vic); 836 837 vmode->mpixelclock = mode->clock * 1000; 838 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock); 839 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 840 vmode->mtmdsclock /= 2; 841 printf("mtmdsclock:%d\n", vmode->mtmdsclock); 842 843 if (hdmi->plat_data->get_enc_out_encoding) 844 hdmi->hdmi_data.enc_out_encoding = 845 hdmi->plat_data->get_enc_out_encoding(data); 846 else if (hdmi->vic == 6 || hdmi->vic == 7 || 847 hdmi->vic == 21 || hdmi->vic == 22 || 848 hdmi->vic == 2 || hdmi->vic == 3 || 849 hdmi->vic == 17 || hdmi->vic == 18) 850 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 851 else 852 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 853 854 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 855 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1; 856 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1; 857 } else { 858 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 859 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 860 } 861 862 /* TOFIX: Get input encoding from plat data or fallback to none */ 863 if (hdmi->plat_data->get_enc_in_encoding) 864 hdmi->hdmi_data.enc_in_encoding = 865 hdmi->plat_data->get_enc_in_encoding(data); 866 else if (hdmi->plat_data->input_bus_encoding) 867 hdmi->hdmi_data.enc_in_encoding = 868 hdmi->plat_data->input_bus_encoding; 869 else 870 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 871 872 if (hdmi->plat_data->get_quant_range) 873 hdmi->hdmi_data.quant_range = 874 hdmi->plat_data->get_quant_range(data); 875 else 876 hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 877 878 /* 879 * According to the dw-hdmi specification 6.4.2 880 * vp_pr_cd[3:0]: 881 * 0000b: No pixel repetition (pixel sent only once) 882 * 0001b: Pixel sent two times (pixel repeated once) 883 */ 884 hdmi->hdmi_data.pix_repet_factor = 885 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0; 886 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 887 888 /* HDMI Initialization Step B.2 */ 889 ret = hdmi->phy.ops->init(hdmi->rk_hdmi, state); 890 if (ret) 891 return ret; 892 hdmi->phy.enabled = true; 893 894 rk3588_set_grf_cfg(hdmi->rk_hdmi); 895 link_cfg = dw_hdmi_rockchip_get_link_cfg(hdmi->rk_hdmi); 896 897 /* not for DVI mode */ 898 if (hdmi->sink_is_hdmi) { 899 printf("%s HDMI mode\n", __func__); 900 hdmi_modb(hdmi, 0, OPMODE_DVI, LINK_CONFIG0); 901 hdmi_modb(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0); 902 if (!link_cfg->frl_mode) { 903 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK) { 904 drm_scdc_readb(&hdmi->adap, SCDC_SINK_VERSION, &bytes); 905 drm_scdc_writeb(&hdmi->adap, SCDC_SOURCE_VERSION, 906 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); 907 drm_scdc_set_high_tmds_clock_ratio(&hdmi->adap, 1); 908 drm_scdc_set_scrambling(&hdmi->adap, 1); 909 hdmi_writel(hdmi, 1, SCRAMB_CONFIG0); 910 } else { 911 if (hdmi_info->scdc.supported) { 912 drm_scdc_set_high_tmds_clock_ratio(&hdmi->adap, 0); 913 drm_scdc_set_scrambling(&hdmi->adap, 0); 914 } 915 hdmi_writel(hdmi, 0, SCRAMB_CONFIG0); 916 } 917 } 918 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 919 hdmi_config_AVI(hdmi, mode); 920 hdmi_config_CVTEM(hdmi, link_cfg); 921 hdmi_set_op_mode(hdmi, link_cfg, hdmi_info->scdc.supported); 922 } else { 923 hdmi_modb(hdmi, OPMODE_DVI, OPMODE_DVI, LINK_CONFIG0); 924 printf("%s DVI mode\n", __func__); 925 } 926 927 return 0; 928 } 929 930 int dw_hdmi_detect_hotplug(struct dw_hdmi_qp *hdmi, 931 struct display_state *state) 932 { 933 struct connector_state *conn_state = &state->conn_state; 934 int ret; 935 936 ret = hdmi->phy.ops->read_hpd(hdmi->rk_hdmi); 937 if (ret || state->force_output) { 938 if (!hdmi->id) 939 conn_state->output_if |= VOP_OUTPUT_IF_HDMI0; 940 else 941 conn_state->output_if |= VOP_OUTPUT_IF_HDMI1; 942 } 943 944 return ret; 945 } 946 947 int rockchip_dw_hdmi_qp_pre_init(struct display_state *state) 948 { 949 struct connector_state *conn_state = &state->conn_state; 950 951 conn_state->type = DRM_MODE_CONNECTOR_HDMIA; 952 953 return 0; 954 } 955 956 int rockchip_dw_hdmi_qp_init(struct display_state *state) 957 { 958 struct connector_state *conn_state = &state->conn_state; 959 const struct rockchip_connector *connector = conn_state->connector; 960 const struct dw_hdmi_plat_data *pdata = connector->data; 961 void *rk_hdmi = dev_get_priv(conn_state->dev); 962 struct dw_hdmi_qp *hdmi; 963 struct drm_display_mode *mode_buf; 964 ofnode hdmi_node = conn_state->node; 965 struct device_node *ddc_node; 966 967 hdmi = malloc(sizeof(struct dw_hdmi_qp)); 968 if (!hdmi) 969 return -ENOMEM; 970 971 memset(hdmi, 0, sizeof(struct dw_hdmi_qp)); 972 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 973 if (!mode_buf) 974 return -ENOMEM; 975 976 hdmi->rk_hdmi = rk_hdmi; 977 hdmi->id = of_alias_get_id(ofnode_to_np(hdmi_node), "hdmi"); 978 if (hdmi->id < 0) 979 hdmi->id = 0; 980 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, hdmi->id); 981 982 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 983 984 hdmi->regs = dev_read_addr_ptr(conn_state->dev); 985 986 ddc_node = of_parse_phandle(ofnode_to_np(hdmi_node), "ddc-i2c-bus", 0); 987 if (ddc_node) { 988 uclass_get_device_by_ofnode(UCLASS_I2C, np_to_ofnode(ddc_node), 989 &hdmi->adap.i2c_bus); 990 if (hdmi->adap.i2c_bus) 991 hdmi->adap.ops = i2c_get_ops(hdmi->adap.i2c_bus); 992 } 993 994 hdmi->i2c = malloc(sizeof(struct dw_hdmi_i2c)); 995 if (!hdmi->i2c) 996 return -ENOMEM; 997 hdmi->adap.ddc_xfer = dw_hdmi_i2c_xfer; 998 999 /* 1000 * Read high and low time from device tree. If not available use 1001 * the default timing scl clock rate is about 99.6KHz. 1002 */ 1003 hdmi->i2c->scl_high_ns = 1004 ofnode_read_s32_default(hdmi_node, 1005 "ddc-i2c-scl-high-time-ns", 4708); 1006 hdmi->i2c->scl_low_ns = 1007 ofnode_read_s32_default(hdmi_node, 1008 "ddc-i2c-scl-low-time-ns", 4916); 1009 1010 dw_hdmi_i2c_init(hdmi); 1011 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1012 1013 hdmi->dev_type = pdata->dev_type; 1014 hdmi->plat_data = pdata; 1015 hdmi->edid_data.mode_buf = mode_buf; 1016 1017 conn_state->private = hdmi; 1018 1019 dw_hdmi_detect_phy(hdmi); 1020 hdmi_writel(hdmi, 0, MAINUNIT_0_INT_MASK_N); 1021 hdmi_writel(hdmi, 0, MAINUNIT_1_INT_MASK_N); 1022 hdmi_writel(hdmi, 428571429, TIMER_BASE_CONFIG0); 1023 1024 dw_hdmi_qp_set_iomux(hdmi->rk_hdmi); 1025 1026 return 0; 1027 } 1028 1029 void rockchip_dw_hdmi_qp_deinit(struct display_state *state) 1030 { 1031 struct connector_state *conn_state = &state->conn_state; 1032 struct dw_hdmi_qp *hdmi = conn_state->private; 1033 1034 if (hdmi->i2c) 1035 free(hdmi->i2c); 1036 if (hdmi->edid_data.mode_buf) 1037 free(hdmi->edid_data.mode_buf); 1038 if (hdmi) 1039 free(hdmi); 1040 } 1041 1042 int rockchip_dw_hdmi_qp_prepare(struct display_state *state) 1043 { 1044 return 0; 1045 } 1046 1047 static void dw_hdmi_disable(struct dw_hdmi_qp *hdmi, struct display_state *state) 1048 { 1049 if (hdmi->phy.enabled) { 1050 hdmi->phy.ops->disable(hdmi->rk_hdmi, state); 1051 hdmi->phy.enabled = false; 1052 } 1053 } 1054 1055 int rockchip_dw_hdmi_qp_enable(struct display_state *state) 1056 { 1057 struct connector_state *conn_state = &state->conn_state; 1058 struct drm_display_mode *mode = &conn_state->mode; 1059 struct dw_hdmi_qp *hdmi = conn_state->private; 1060 1061 if (!hdmi) 1062 return -EFAULT; 1063 1064 /* Store the display mode for plugin/DKMS poweron events */ 1065 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 1066 1067 dw_hdmi_setup(hdmi, mode, state); 1068 1069 return 0; 1070 } 1071 1072 int rockchip_dw_hdmi_qp_disable(struct display_state *state) 1073 { 1074 struct connector_state *conn_state = &state->conn_state; 1075 struct dw_hdmi_qp *hdmi = conn_state->private; 1076 1077 dw_hdmi_disable(hdmi, state); 1078 return 0; 1079 } 1080 1081 int rockchip_dw_hdmi_qp_get_timing(struct display_state *state) 1082 { 1083 int ret, i; 1084 struct connector_state *conn_state = &state->conn_state; 1085 struct drm_display_mode *mode = &conn_state->mode; 1086 struct dw_hdmi_qp *hdmi = conn_state->private; 1087 struct edid *edid = (struct edid *)conn_state->edid; 1088 unsigned int bus_format; 1089 unsigned long enc_out_encoding; 1090 struct overscan *overscan = &conn_state->overscan; 1091 const u8 def_modes_vic[6] = {4, 16, 2, 17, 31, 19}; 1092 1093 if (!hdmi) 1094 return -EFAULT; 1095 1096 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 1097 if (!ret) { 1098 hdmi->sink_is_hdmi = 1099 drm_detect_hdmi_monitor(edid); 1100 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 1101 ret = drm_add_edid_modes(&hdmi->edid_data, conn_state->edid); 1102 } 1103 if (ret < 0) { 1104 hdmi->sink_is_hdmi = true; 1105 hdmi->sink_has_audio = true; 1106 do_cea_modes(&hdmi->edid_data, def_modes_vic, 1107 sizeof(def_modes_vic)); 1108 hdmi->edid_data.preferred_mode = &hdmi->edid_data.mode_buf[0]; 1109 printf("failed to get edid\n"); 1110 } 1111 drm_rk_filter_whitelist(&hdmi->edid_data); 1112 if (hdmi->phy.ops->mode_valid) 1113 hdmi->phy.ops->mode_valid(hdmi->rk_hdmi, state); 1114 drm_mode_max_resolution_filter(&hdmi->edid_data, 1115 &state->crtc_state.max_output); 1116 if (!drm_mode_prune_invalid(&hdmi->edid_data)) { 1117 printf("can't find valid hdmi mode\n"); 1118 return -EINVAL; 1119 } 1120 1121 for (i = 0; i < hdmi->edid_data.modes; i++) 1122 hdmi->edid_data.mode_buf[i].vrefresh = 1123 drm_mode_vrefresh(&hdmi->edid_data.mode_buf[i]); 1124 1125 drm_mode_sort(&hdmi->edid_data); 1126 dw_hdmi_qp_selete_output(&hdmi->edid_data, conn_state, &bus_format, 1127 overscan, hdmi->dev_type, 1128 hdmi->output_bus_format_rgb, hdmi->rk_hdmi, 1129 state); 1130 1131 *mode = *hdmi->edid_data.preferred_mode; 1132 hdmi->vic = drm_match_cea_mode(mode); 1133 1134 printf("mode:%dx%d bus_format:0x%x\n", mode->hdisplay, mode->vdisplay, bus_format); 1135 conn_state->bus_format = bus_format; 1136 hdmi->hdmi_data.enc_in_bus_format = bus_format; 1137 hdmi->hdmi_data.enc_out_bus_format = bus_format; 1138 1139 switch (bus_format) { 1140 case MEDIA_BUS_FMT_UYVY10_1X20: 1141 conn_state->bus_format = MEDIA_BUS_FMT_YUV10_1X30; 1142 hdmi->hdmi_data.enc_in_bus_format = 1143 MEDIA_BUS_FMT_YUV10_1X30; 1144 break; 1145 case MEDIA_BUS_FMT_UYVY8_1X16: 1146 conn_state->bus_format = MEDIA_BUS_FMT_YUV8_1X24; 1147 hdmi->hdmi_data.enc_in_bus_format = 1148 MEDIA_BUS_FMT_YUV8_1X24; 1149 break; 1150 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1151 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1152 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420; 1153 break; 1154 } 1155 1156 if (hdmi->vic == 6 || hdmi->vic == 7 || hdmi->vic == 21 || 1157 hdmi->vic == 22 || hdmi->vic == 2 || hdmi->vic == 3 || 1158 hdmi->vic == 17 || hdmi->vic == 18) 1159 enc_out_encoding = V4L2_YCBCR_ENC_601; 1160 else 1161 enc_out_encoding = V4L2_YCBCR_ENC_709; 1162 1163 if (enc_out_encoding == V4L2_YCBCR_ENC_BT2020) 1164 conn_state->color_space = V4L2_COLORSPACE_BT2020; 1165 else if (bus_format == MEDIA_BUS_FMT_RGB888_1X24 || 1166 bus_format == MEDIA_BUS_FMT_RGB101010_1X30) 1167 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 1168 else if (enc_out_encoding == V4L2_YCBCR_ENC_709) 1169 conn_state->color_space = V4L2_COLORSPACE_REC709; 1170 else 1171 conn_state->color_space = V4L2_COLORSPACE_SMPTE170M; 1172 1173 return 0; 1174 } 1175 1176 int rockchip_dw_hdmi_qp_detect(struct display_state *state) 1177 { 1178 int ret; 1179 struct connector_state *conn_state = &state->conn_state; 1180 struct dw_hdmi_qp *hdmi = conn_state->private; 1181 1182 if (!hdmi) 1183 return -EFAULT; 1184 1185 ret = dw_hdmi_detect_hotplug(hdmi, state); 1186 1187 return ret; 1188 } 1189 1190 int rockchip_dw_hdmi_qp_get_edid(struct display_state *state) 1191 { 1192 int ret; 1193 struct connector_state *conn_state = &state->conn_state; 1194 struct dw_hdmi_qp *hdmi = conn_state->private; 1195 1196 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 1197 1198 return ret; 1199 } 1200