1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd 4 * Author: Algea Cao <algea.cao@rock-chips.com> 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <syscon.h> 10 #include <asm/arch-rockchip/clock.h> 11 #include <asm/arch/vendor.h> 12 #include <edid.h> 13 #include <dm/device.h> 14 #include <dm/of_access.h> 15 #include <dm/ofnode.h> 16 #include <dm/read.h> 17 #include <linux/hdmi.h> 18 #include <linux/media-bus-format.h> 19 #include <linux/dw_hdmi.h> 20 #include <asm/io.h> 21 #include "rockchip_bridge.h" 22 #include "rockchip_display.h" 23 #include "rockchip_crtc.h" 24 #include "rockchip_connector.h" 25 #include "dw_hdmi_qp.h" 26 #include "rockchip_phy.h" 27 28 enum frl_mask { 29 FRL_3GBPS_3LANE = 1, 30 FRL_6GBPS_3LANE, 31 FRL_6GBPS_4LANE, 32 FRL_8GBPS_4LANE, 33 FRL_10GBPS_4LANE, 34 FRL_12GBPS_4LANE, 35 }; 36 37 #define DDC_CI_ADDR 0x37 38 #define DDC_SEGMENT_ADDR 0x30 39 40 #define HDMI_EDID_LEN 512 41 #define HDMI_EDID_BLOCK_LEN 128 42 43 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ 44 #define SCDC_MIN_SOURCE_VERSION 0x1 45 46 #define HDMI14_MAX_TMDSCLK 340000000 47 48 struct hdmi_vmode { 49 bool mdataenablepolarity; 50 51 unsigned int mpixelclock; 52 unsigned int mpixelrepetitioninput; 53 unsigned int mpixelrepetitionoutput; 54 unsigned int mtmdsclock; 55 }; 56 57 struct hdmi_data_info { 58 unsigned int enc_in_bus_format; 59 unsigned int enc_out_bus_format; 60 unsigned int enc_in_encoding; 61 unsigned int enc_out_encoding; 62 unsigned int quant_range; 63 unsigned int pix_repet_factor; 64 struct hdmi_vmode video_mode; 65 }; 66 67 struct dw_hdmi_phy_data { 68 enum dw_hdmi_phy_type type; 69 const char *name; 70 unsigned int gen; 71 bool has_svsret; 72 int (*configure)(struct dw_hdmi *hdmi, 73 const struct dw_hdmi_plat_data *pdata, 74 unsigned long mpixelclock); 75 }; 76 77 struct dw_hdmi_i2c { 78 u8 slave_reg; 79 bool is_regaddr; 80 bool is_segment; 81 82 unsigned int scl_high_ns; 83 unsigned int scl_low_ns; 84 }; 85 86 struct dw_hdmi_qp { 87 enum dw_hdmi_devtype dev_type; 88 unsigned int version; 89 struct hdmi_data_info hdmi_data; 90 struct hdmi_edid_data edid_data; 91 const struct dw_hdmi_plat_data *plat_data; 92 struct ddc_adapter adap; 93 94 int vic; 95 int id; 96 97 unsigned long bus_format; 98 bool cable_plugin; 99 bool sink_is_hdmi; 100 bool sink_has_audio; 101 void *regs; 102 void *rk_hdmi; 103 struct dw_hdmi_i2c *i2c; 104 105 struct { 106 const struct dw_hdmi_qp_phy_ops *ops; 107 const char *name; 108 void *data; 109 bool enabled; 110 } phy; 111 112 struct drm_display_mode previous_mode; 113 114 unsigned int sample_rate; 115 unsigned int audio_cts; 116 unsigned int audio_n; 117 bool audio_enable; 118 bool scramble_low_rates; 119 120 void (*write)(struct dw_hdmi_qp *hdmi, u32 val, int offset); 121 u8 (*read)(struct dw_hdmi_qp *hdmi, int offset); 122 123 bool hdcp1x_enable; 124 bool output_bus_format_rgb; 125 }; 126 127 static inline void hdmi_writel(struct dw_hdmi_qp *hdmi, u32 val, int offset) 128 { 129 writel(val, hdmi->regs + offset); 130 } 131 132 static inline u32 hdmi_readl(struct dw_hdmi_qp *hdmi, int offset) 133 { 134 return readl(hdmi->regs + offset); 135 } 136 137 static void 138 hdmi_modb(struct dw_hdmi_qp *hdmi, u32 data, u32 mask, unsigned int reg) 139 { 140 u32 val = hdmi_readl(hdmi, reg) & ~mask; 141 142 val |= data & mask; 143 hdmi_writel(hdmi, val, reg); 144 } 145 146 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 147 { 148 switch (bus_format) { 149 case MEDIA_BUS_FMT_RGB888_1X24: 150 case MEDIA_BUS_FMT_RGB101010_1X30: 151 case MEDIA_BUS_FMT_RGB121212_1X36: 152 case MEDIA_BUS_FMT_RGB161616_1X48: 153 return true; 154 155 default: 156 return false; 157 } 158 } 159 160 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 161 { 162 switch (bus_format) { 163 case MEDIA_BUS_FMT_YUV8_1X24: 164 case MEDIA_BUS_FMT_YUV10_1X30: 165 case MEDIA_BUS_FMT_YUV12_1X36: 166 case MEDIA_BUS_FMT_YUV16_1X48: 167 return true; 168 169 default: 170 return false; 171 } 172 } 173 174 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 175 { 176 switch (bus_format) { 177 case MEDIA_BUS_FMT_UYVY8_1X16: 178 case MEDIA_BUS_FMT_UYVY10_1X20: 179 case MEDIA_BUS_FMT_UYVY12_1X24: 180 case MEDIA_BUS_FMT_YUYV8_1X16: 181 case MEDIA_BUS_FMT_YUYV10_1X20: 182 case MEDIA_BUS_FMT_YUYV12_1X24: 183 return true; 184 185 default: 186 return false; 187 } 188 } 189 190 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 191 { 192 switch (bus_format) { 193 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 194 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 195 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 196 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 197 return true; 198 199 default: 200 return false; 201 } 202 } 203 204 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 205 { 206 switch (bus_format) { 207 case MEDIA_BUS_FMT_RGB888_1X24: 208 case MEDIA_BUS_FMT_YUV8_1X24: 209 case MEDIA_BUS_FMT_UYVY8_1X16: 210 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 211 return 8; 212 213 case MEDIA_BUS_FMT_RGB101010_1X30: 214 case MEDIA_BUS_FMT_YUV10_1X30: 215 case MEDIA_BUS_FMT_UYVY10_1X20: 216 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 217 return 10; 218 219 case MEDIA_BUS_FMT_RGB121212_1X36: 220 case MEDIA_BUS_FMT_YUV12_1X36: 221 case MEDIA_BUS_FMT_UYVY12_1X24: 222 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 223 return 12; 224 225 case MEDIA_BUS_FMT_RGB161616_1X48: 226 case MEDIA_BUS_FMT_YUV16_1X48: 227 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 228 return 16; 229 230 default: 231 return 0; 232 } 233 } 234 235 static bool drm_scdc_set_scrambling(struct ddc_adapter *adapter, bool enable) 236 { 237 u8 config; 238 int ret; 239 240 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 241 if (ret < 0) { 242 debug("Failed to read TMDS config: %d\n", ret); 243 return false; 244 } 245 246 if (enable) 247 config |= SCDC_SCRAMBLING_ENABLE; 248 else 249 config &= ~SCDC_SCRAMBLING_ENABLE; 250 251 ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config); 252 if (ret < 0) { 253 debug("Failed to enable scrambling: %d\n", ret); 254 return false; 255 } 256 257 return true; 258 } 259 260 static bool 261 drm_scdc_set_high_tmds_clock_ratio(struct ddc_adapter *adapter, bool set) 262 { 263 u8 config; 264 int ret; 265 266 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 267 if (ret < 0) { 268 debug("Failed to read TMDS config: %d\n", ret); 269 return false; 270 } 271 272 if (set) 273 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 274 else 275 config &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 276 277 ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config); 278 if (ret < 0) { 279 debug("Failed to set TMDS clock ratio: %d\n", ret); 280 return false; 281 } 282 283 /* 284 * The spec says that a source should wait minimum 1ms and maximum 285 * 100ms after writing the TMDS config for clock ratio. Lets allow a 286 * wait of up to 2ms here. 287 */ 288 udelay(2000); 289 return true; 290 } 291 292 static void dw_hdmi_i2c_init(struct dw_hdmi_qp *hdmi) 293 { 294 /* Software reset */ 295 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 296 297 hdmi_writel(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0); 298 299 hdmi_modb(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0); 300 301 /* Clear DONE and ERROR interrupts */ 302 hdmi_writel(hdmi, I2CM_OP_DONE_CLEAR | I2CM_NACK_RCVD_CLEAR, 303 MAINUNIT_1_INT_CLEAR); 304 } 305 306 static int dw_hdmi_i2c_read(struct dw_hdmi_qp *hdmi, 307 unsigned char *buf, unsigned int length) 308 { 309 struct dw_hdmi_i2c *i2c = hdmi->i2c; 310 int i = 20, retry; 311 u32 intr = 0; 312 bool read_edid = false; 313 314 if (!i2c->is_regaddr) { 315 printf("set read register address to 0\n"); 316 i2c->slave_reg = 0x00; 317 i2c->is_regaddr = true; 318 } 319 320 /* edid reads are in 128 bytes. scdc reads are in 1 byte */ 321 if (length == HDMI_EDID_BLOCK_LEN) 322 read_edid = true; 323 324 while (length > 0) { 325 retry = 100; 326 hdmi_modb(hdmi, i2c->slave_reg << 12, I2CM_ADDR, 327 I2CM_INTERFACE_CONTROL0); 328 329 if (read_edid) { 330 hdmi_modb(hdmi, I2CM_16BYTES, I2CM_NBYTES_MASK, 331 I2CM_INTERFACE_CONTROL0); 332 i2c->slave_reg += 16; 333 length -= 16; 334 } else { 335 hdmi_modb(hdmi, I2CM_1BYTES, I2CM_NBYTES_MASK, 336 I2CM_INTERFACE_CONTROL0); 337 i2c->slave_reg++; 338 length--; 339 } 340 341 while (retry > 0) { 342 if (!hdmi->phy.ops->read_hpd(hdmi->rk_hdmi)) { 343 debug("hdmi disconnect, stop ddc read\n"); 344 return -EPERM; 345 } 346 347 i = 20; 348 hdmi_modb(hdmi, I2CM_FM_READ, I2CM_WR_MASK, 349 I2CM_INTERFACE_CONTROL0); 350 351 while (i--) { 352 udelay(1000); 353 intr = hdmi_readl(hdmi, MAINUNIT_1_INT_STATUS); 354 intr &= (I2CM_OP_DONE_IRQ | 355 I2CM_READ_REQUEST_IRQ | 356 I2CM_NACK_RCVD_IRQ); 357 if (intr) { 358 hdmi_writel(hdmi, intr, 359 MAINUNIT_1_INT_CLEAR); 360 break; 361 } 362 } 363 364 if (!i) { 365 printf("i2c read time out!\n"); 366 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 367 retry -= 10; 368 continue; 369 } 370 371 /* Check for error condition on the bus */ 372 if (intr & I2CM_NACK_RCVD_IRQ) { 373 printf("i2c read err!\n"); 374 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 375 retry--; 376 mdelay(10); 377 continue; 378 } 379 380 /* read success */ 381 break; 382 } 383 384 if (retry <= 0) { 385 printf("ddc read failed offset:0x%x\n", i2c->slave_reg); 386 return -EIO; 387 } 388 389 if (read_edid) { 390 u8 reg_offset, val_offset, i; 391 u32 val, reg; 392 393 for (i = 0; i < 16; i++) { 394 reg_offset = i / 4; 395 val_offset = (i % 4) * 8; 396 reg = I2CM_INTERFACE_RDDATA_0_3 + 4 * 397 reg_offset; 398 val = hdmi_readl(hdmi, reg); 399 *buf++ = (val & (0xff << val_offset)) >> 400 val_offset; 401 debug("i2c read done! 0x%02x\n", 402 (val & (0xff << val_offset)) >> 403 val_offset); 404 } 405 } else { 406 *buf++ = hdmi_readl(hdmi, I2CM_INTERFACE_RDDATA_0_3) & 407 0xff; 408 debug("i2c read done! 0x%02x\n", 409 hdmi_readl(hdmi, I2CM_INTERFACE_RDDATA_0_3)); 410 } 411 412 hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); 413 } 414 i2c->is_segment = false; 415 416 return 0; 417 } 418 419 static int dw_hdmi_i2c_write(struct dw_hdmi_qp *hdmi, 420 unsigned char *buf, unsigned int length) 421 { 422 struct dw_hdmi_i2c *i2c = hdmi->i2c; 423 int i = 20, retry; 424 u32 intr = 0; 425 426 if (!i2c->is_regaddr) { 427 /* Use the first write byte as register address */ 428 i2c->slave_reg = buf[0]; 429 length--; 430 buf++; 431 i2c->is_regaddr = true; 432 } 433 434 while (length--) { 435 retry = 100; 436 437 while (retry > 0) { 438 if (!hdmi->phy.ops->read_hpd(hdmi->rk_hdmi)) { 439 debug("hdmi disconnect, stop ddc read\n"); 440 return -EPERM; 441 } 442 443 i = 20; 444 hdmi_writel(hdmi, *buf++, I2CM_INTERFACE_WRDATA_0_3); 445 hdmi_modb(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, 446 I2CM_INTERFACE_CONTROL0); 447 hdmi_modb(hdmi, I2CM_FM_WRITE, I2CM_WR_MASK, 448 I2CM_INTERFACE_CONTROL0); 449 450 while (i--) { 451 udelay(1000); 452 intr = hdmi_readl(hdmi, MAINUNIT_1_INT_STATUS); 453 intr &= (I2CM_OP_DONE_IRQ | 454 I2CM_READ_REQUEST_IRQ | 455 I2CM_NACK_RCVD_IRQ); 456 if (intr) { 457 hdmi_writel(hdmi, intr, 458 MAINUNIT_1_INT_CLEAR); 459 break; 460 } 461 } 462 463 if (!i) { 464 printf("i2c write time out!\n"); 465 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 466 retry -= 10; 467 continue; 468 } 469 470 /* Check for error condition on the bus */ 471 if (intr & I2CM_NACK_RCVD_IRQ) { 472 printf("i2c write nack!\n"); 473 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 474 retry--; 475 mdelay(10); 476 continue; 477 } 478 /* write success */ 479 break; 480 } 481 hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); 482 if (retry <= 0) { 483 printf("ddc write failed\n"); 484 return -EIO; 485 } 486 } 487 488 return 0; 489 } 490 491 static int dw_hdmi_i2c_xfer(struct ddc_adapter *adap, 492 struct i2c_msg *msgs, int num) 493 { 494 struct dw_hdmi_qp *hdmi = container_of(adap, struct dw_hdmi_qp, adap); 495 struct dw_hdmi_i2c *i2c = hdmi->i2c; 496 u8 addr = msgs[0].addr; 497 int i, ret = 0; 498 499 debug("i2c xfer: num: %d, addr: %#x\n", num, addr); 500 501 for (i = 0; i < num; i++) { 502 if (msgs[i].len == 0) { 503 printf("unsupported transfer %d/%d, no data\n", 504 i + 1, num); 505 return -EOPNOTSUPP; 506 } 507 } 508 509 /* Unmute DONE and ERROR interrupts */ 510 hdmi_modb(hdmi, I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, 511 I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, 512 MAINUNIT_1_INT_MASK_N); 513 514 /* Set slave device address taken from the first I2C message */ 515 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1) 516 addr = DDC_ADDR; 517 518 hdmi_modb(hdmi, addr << 5, I2CM_SLVADDR, I2CM_INTERFACE_CONTROL0); 519 520 /* Set slave device register address on transfer */ 521 i2c->is_regaddr = false; 522 523 /* Set segment pointer for I2C extended read mode operation */ 524 i2c->is_segment = false; 525 526 for (i = 0; i < num; i++) { 527 debug("xfer: num: %d/%d, len: %d, flags: %#x\n", 528 i + 1, num, msgs[i].len, msgs[i].flags); 529 530 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 531 i2c->is_segment = true; 532 hdmi_modb(hdmi, DDC_SEGMENT_ADDR, I2CM_SEG_ADDR, 533 I2CM_INTERFACE_CONTROL1); 534 hdmi_modb(hdmi, *msgs[i].buf, I2CM_SEG_PTR, 535 I2CM_INTERFACE_CONTROL1); 536 } else { 537 if (msgs[i].flags & I2C_M_RD) 538 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 539 msgs[i].len); 540 else 541 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 542 msgs[i].len); 543 } 544 if (ret < 0) 545 break; 546 } 547 548 if (!ret) 549 ret = num; 550 551 /* Mute DONE and ERROR interrupts */ 552 hdmi_modb(hdmi, 0, I2CM_OP_DONE_MASK_N | I2CM_NACK_RCVD_MASK_N, 553 MAINUNIT_1_INT_MASK_N); 554 555 return ret; 556 } 557 558 static int dw_hdmi_detect_phy(struct dw_hdmi_qp *hdmi) 559 { 560 /* Vendor PHYs require support from the glue layer. */ 561 if (!hdmi->plat_data->qp_phy_ops || !hdmi->plat_data->phy_name) { 562 dev_err(hdmi->dev, 563 "Vendor HDMI PHY not supported by glue layer\n"); 564 return -ENODEV; 565 } 566 567 hdmi->phy.ops = hdmi->plat_data->qp_phy_ops; 568 hdmi->phy.data = hdmi->plat_data->phy_data; 569 hdmi->phy.name = hdmi->plat_data->phy_name; 570 571 return 0; 572 } 573 574 static unsigned int 575 hdmi_get_tmdsclock(struct dw_hdmi_qp *hdmi, unsigned long mpixelclock) 576 { 577 unsigned int tmdsclock = mpixelclock; 578 unsigned int depth = 579 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 580 581 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 582 switch (depth) { 583 case 16: 584 tmdsclock = mpixelclock * 2; 585 break; 586 case 12: 587 tmdsclock = mpixelclock * 3 / 2; 588 break; 589 case 10: 590 tmdsclock = mpixelclock * 5 / 4; 591 break; 592 default: 593 break; 594 } 595 } 596 597 return tmdsclock; 598 } 599 600 static void hdmi_infoframe_set_checksum(u8 *ptr, int size) 601 { 602 u8 csum = 0; 603 int i; 604 605 ptr[3] = 0; 606 /* compute checksum */ 607 for (i = 0; i < size; i++) 608 csum += ptr[i]; 609 610 ptr[3] = 256 - csum; 611 } 612 613 static bool is_hdmi2_sink(struct dw_hdmi_qp *hdmi) 614 { 615 return hdmi->edid_data.display_info.hdmi.scdc.supported || 616 hdmi->edid_data.display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; 617 } 618 619 static void hdmi_config_AVI(struct dw_hdmi_qp *hdmi, struct drm_display_mode *mode) 620 { 621 struct hdmi_avi_infoframe frame; 622 u32 val, i, j; 623 u8 buff[17]; 624 bool is_hdmi2 = false; 625 enum hdmi_quantization_range rgb_quant_range = 626 hdmi->hdmi_data.quant_range; 627 628 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) || 629 hdmi->edid_data.display_info.hdmi.scdc.supported) 630 is_hdmi2 = true; 631 /* Initialise info frame from DRM mode */ 632 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2); 633 634 /* 635 * Ignore monitor selectable quantization, use quantization set 636 * by the user 637 */ 638 drm_hdmi_avi_infoframe_quant_range(&frame, mode, rgb_quant_range, 639 true, is_hdmi2); 640 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 641 frame.colorspace = HDMI_COLORSPACE_YUV444; 642 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 643 frame.colorspace = HDMI_COLORSPACE_YUV422; 644 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 645 frame.colorspace = HDMI_COLORSPACE_YUV420; 646 else 647 frame.colorspace = HDMI_COLORSPACE_RGB; 648 649 /* Set up colorimetry and quant range */ 650 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 651 switch (hdmi->hdmi_data.enc_out_encoding) { 652 case V4L2_YCBCR_ENC_601: 653 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 654 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 655 else 656 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 657 frame.extended_colorimetry = 658 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 659 break; 660 case V4L2_YCBCR_ENC_709: 661 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 662 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 663 else 664 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 665 frame.extended_colorimetry = 666 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 667 break; 668 case V4L2_YCBCR_ENC_BT2020: 669 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_BT2020) 670 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 671 else 672 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 673 frame.extended_colorimetry = 674 HDMI_EXTENDED_COLORIMETRY_BT2020; 675 break; 676 default: /* Carries no data */ 677 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 678 frame.extended_colorimetry = 679 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 680 break; 681 } 682 683 frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 684 } else { 685 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_BT2020) { 686 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 687 frame.extended_colorimetry = 688 HDMI_EXTENDED_COLORIMETRY_BT2020; 689 } else { 690 frame.colorimetry = HDMI_COLORIMETRY_NONE; 691 frame.extended_colorimetry = 692 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 693 } 694 695 if (is_hdmi2_sink(hdmi) && 696 frame.quantization_range == HDMI_QUANTIZATION_RANGE_FULL) 697 frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_FULL; 698 else 699 frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 700 } 701 702 frame.scan_mode = HDMI_SCAN_MODE_NONE; 703 704 hdmi_avi_infoframe_pack_only(&frame, buff, 17); 705 706 /* mode which vic >= 128 must use avi version 3 */ 707 if (hdmi->vic >= 128) { 708 frame.version = 3; 709 buff[1] = frame.version; 710 buff[4] &= 0x1f; 711 buff[4] |= ((frame.colorspace & 0x7) << 5); 712 buff[7] = hdmi->vic; 713 hdmi_infoframe_set_checksum(buff, 17); 714 } 715 716 /* 717 * The Designware IP uses a different byte format from standard 718 * AVI info frames, though generally the bits are in the correct 719 * bytes. 720 */ 721 722 val = (frame.version << 8) | (frame.length << 16); 723 hdmi_writel(hdmi, val, PKT_AVI_CONTENTS0); 724 725 for (i = 0; i < 4; i++) { 726 for (j = 0; j < 4; j++) { 727 if (i * 4 + j >= 14) 728 break; 729 if (!j) 730 val = buff[i * 4 + j + 3]; 731 val |= buff[i * 4 + j + 3] << (8 * j); 732 } 733 734 hdmi_writel(hdmi, val, PKT_AVI_CONTENTS1 + i * 4); 735 } 736 737 hdmi_modb(hdmi, 0, PKTSCHED_AVI_FIELDRATE, PKTSCHED_PKT_CONFIG1); 738 739 hdmi_modb(hdmi, PKTSCHED_AVI_TX_EN, PKTSCHED_AVI_TX_EN, 740 PKTSCHED_PKT_EN); 741 } 742 743 #define VSI_PKT_TYPE 0x81 744 #define VSI_PKT_VERSION 1 745 #define HDMI_FORUM_OUI 0xc45dd8 746 #define ALLM_MODE BIT(1) 747 #define HDMI_FORUM_LEN 9 748 749 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi_qp *hdmi, 750 struct drm_display_mode *mode) 751 { 752 struct hdmi_vendor_infoframe frame; 753 struct dw_hdmi_link_config *link_cfg = NULL; 754 u8 buffer[10]; 755 u32 val; 756 ssize_t err; 757 int i, reg; 758 759 link_cfg = dw_hdmi_rockchip_get_link_cfg(hdmi->rk_hdmi); 760 761 hdmi_modb(hdmi, 0, PKTSCHED_VSI_TX_EN, PKTSCHED_PKT_EN); 762 763 for (i = 0; i <= 7; i++) 764 hdmi_writel(hdmi, 0, PKT_VSI_CONTENTS0 + i * 4); 765 766 if (link_cfg->allm_en) { 767 buffer[0] = VSI_PKT_TYPE; 768 buffer[1] = VSI_PKT_VERSION; 769 buffer[2] = 5; 770 buffer[4] = HDMI_FORUM_OUI & 0xff; 771 buffer[5] = (HDMI_FORUM_OUI >> 8) & 0xff; 772 buffer[6] = (HDMI_FORUM_OUI >> 16) & 0xff; 773 buffer[7] = VSI_PKT_VERSION; 774 buffer[8] = ALLM_MODE; 775 776 hdmi_infoframe_set_checksum(buffer, HDMI_FORUM_LEN); 777 778 err = 9; 779 } else { 780 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode); 781 if (err < 0) 782 /* 783 * Going into that statement does not means vendor infoframe 784 * fails. It just informed us that vendor infoframe is not 785 * needed for the selected mode. Only 4k or stereoscopic 3D 786 * mode requires vendor infoframe. So just simply return. 787 */ 788 return; 789 790 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 791 if (err < 0) { 792 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 793 err); 794 return; 795 } 796 } 797 798 /* vsi header */ 799 val = (buffer[2] << 16) | (buffer[1] << 8) | buffer[0]; 800 hdmi_writel(hdmi, val, PKT_VSI_CONTENTS0); 801 802 reg = PKT_VSI_CONTENTS1; 803 for (i = 3; i < err; i++) { 804 if (i % 4 == 3) 805 val = buffer[i]; 806 if (i % 4 == 0) 807 val |= buffer[i] << 8; 808 if (i % 4 == 1) 809 val |= buffer[i] << 16; 810 if (i % 4 == 2) 811 val |= buffer[i] << 24; 812 813 if ((i % 4 == 2) || (i == (err - 1))) { 814 hdmi_writel(hdmi, val, reg); 815 reg += 4; 816 } 817 } 818 819 hdmi_writel(hdmi, 0, PKT_VSI_CONTENTS7); 820 821 hdmi_modb(hdmi, 0, PKTSCHED_VSI_FIELDRATE, PKTSCHED_PKT_CONFIG1); 822 hdmi_modb(hdmi, PKTSCHED_VSI_TX_EN, PKTSCHED_VSI_TX_EN, 823 PKTSCHED_PKT_EN); 824 } 825 826 static void hdmi_config_CVTEM(struct dw_hdmi_qp *hdmi, 827 struct dw_hdmi_link_config *link_cfg) 828 { 829 u8 ds_type = 0; 830 u8 sync = 1; 831 u8 vfr = 1; 832 u8 afr = 0; 833 u8 new = 1; 834 u8 end = 0; 835 u8 data_set_length = 136; 836 u8 hb1[6] = { 0x80, 0, 0, 0, 0, 0x40 }; 837 u8 *pps_body; 838 u32 val, i, reg; 839 struct drm_display_mode *mode = &hdmi->previous_mode; 840 int hsync, hfront, hback; 841 842 hdmi_modb(hdmi, 0, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_PKT_EN); 843 844 if (!link_cfg->dsc_mode) { 845 printf("don't use dsc mode\n"); 846 return; 847 } 848 849 pps_body = link_cfg->pps_payload; 850 851 hsync = mode->hsync_end - mode->hsync_start; 852 hback = mode->htotal - mode->hsync_end; 853 hfront = mode->hsync_start - mode->hdisplay; 854 855 for (i = 0; i < 6; i++) { 856 val = i << 16 | hb1[i] << 8; 857 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS0 + i * 0x20); 858 } 859 860 val = new << 7 | end << 6 | ds_type << 4 | afr << 3 | 861 vfr << 2 | sync << 1; 862 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS1); 863 864 val = data_set_length << 16 | pps_body[0] << 24; 865 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS2); 866 867 reg = PKT0_EMP_CVTEM_CONTENTS3; 868 for (i = 1; i < 125; i++) { 869 if (reg == PKT1_EMP_CVTEM_CONTENTS0 || 870 reg == PKT2_EMP_CVTEM_CONTENTS0 || 871 reg == PKT3_EMP_CVTEM_CONTENTS0 || 872 reg == PKT4_EMP_CVTEM_CONTENTS0 || 873 reg == PKT5_EMP_CVTEM_CONTENTS0) { 874 reg += 4; 875 i--; 876 continue; 877 } 878 if (i % 4 == 1) 879 val = pps_body[i]; 880 if (i % 4 == 2) 881 val |= pps_body[i] << 8; 882 if (i % 4 == 3) 883 val |= pps_body[i] << 16; 884 if (!(i % 4)) { 885 val |= pps_body[i] << 24; 886 hdmi_writel(hdmi, val, reg); 887 reg += 4; 888 } 889 } 890 891 val = (hfront & 0xff) << 24 | pps_body[127] << 16 | 892 pps_body[126] << 8 | pps_body[125]; 893 hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS6); 894 895 val = (hback & 0xff) << 24 | ((hsync >> 8) & 0xff) << 16 | 896 (hsync & 0xff) << 8 | ((hfront >> 8) & 0xff); 897 hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS7); 898 899 val = link_cfg->hcactive << 8 | ((hback >> 8) & 0xff); 900 hdmi_writel(hdmi, val, PKT5_EMP_CVTEM_CONTENTS1); 901 902 for (i = PKT5_EMP_CVTEM_CONTENTS2; i <= PKT5_EMP_CVTEM_CONTENTS7; i += 4) 903 hdmi_writel(hdmi, 0, i); 904 905 hdmi_modb(hdmi, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_EMP_CVTEM_TX_EN, 906 PKTSCHED_PKT_EN); 907 } 908 909 static int hdmi_set_frl_mask(int frl_rate) 910 { 911 switch (frl_rate) { 912 case 48: 913 return FRL_12GBPS_4LANE; 914 case 40: 915 return FRL_10GBPS_4LANE; 916 case 32: 917 return FRL_8GBPS_4LANE; 918 case 24: 919 return FRL_6GBPS_4LANE; 920 case 18: 921 return FRL_6GBPS_3LANE; 922 case 9: 923 return FRL_3GBPS_3LANE; 924 } 925 926 return 0; 927 } 928 929 static int hdmi_start_flt(struct dw_hdmi_qp *hdmi, u8 rate) 930 { 931 u8 val; 932 u32 value; 933 u8 ffe_lv = 0; 934 int i = 0; 935 bool ltsp = false; 936 937 hdmi_modb(hdmi, AVP_DATAPATH_VIDEO_SWDISABLE, 938 AVP_DATAPATH_VIDEO_SWDISABLE, GLOBAL_SWDISABLE); 939 940 hdmi_writel(hdmi, AVP_DATAPATH_SWINIT_P, GLOBAL_SWRESET_REQUEST); 941 942 /* clear flt flags */ 943 drm_scdc_writeb(&hdmi->adap, 0x10, 0xff); 944 945 /* FLT_READY & FFE_LEVELS read */ 946 for (i = 0; i < 20; i++) { 947 drm_scdc_readb(&hdmi->adap, SCDC_STATUS_FLAGS_0, &val); 948 if (val & BIT(6)) 949 break; 950 mdelay(20); 951 } 952 953 if (i == 20) { 954 printf("sink flt isn't ready\n"); 955 return -EINVAL; 956 } 957 958 /* max ffe level 3 */ 959 val = 0 << 4 | hdmi_set_frl_mask(rate); 960 drm_scdc_writeb(&hdmi->adap, 0x31, val); 961 /* select FRL_RATE & FFE_LEVELS */ 962 hdmi_writel(hdmi, ffe_lv, FLT_CONFIG0); 963 964 i = 500; 965 while (i--) { 966 mdelay(4); 967 drm_scdc_readb(&hdmi->adap, 0x10, &val); 968 969 if (!(val & 0x30)) 970 continue; 971 972 if (val & BIT(5)) { 973 u8 reg_val, ln0, ln1, ln2, ln3; 974 975 drm_scdc_readb(&hdmi->adap, 0x41, ®_val); 976 ln0 = reg_val & 0xf; 977 ln1 = (reg_val >> 4) & 0xf; 978 979 drm_scdc_readb(&hdmi->adap, 0x42, ®_val); 980 ln2 = reg_val & 0xf; 981 ln3 = (reg_val >> 4) & 0xf; 982 983 if (!ln0 && !ln1 && !ln2 && !ln3) { 984 printf("goto ltsp\n"); 985 ltsp = true; 986 hdmi_writel(hdmi, 0, FLT_CONFIG1); 987 } else if ((ln0 == 0xf) | (ln1 == 0xf) | (ln2 == 0xf) | (ln3 == 0xf)) { 988 printf("goto lts4\n"); 989 break; 990 } else if ((ln0 == 0xe) | (ln1 == 0xe) | (ln2 == 0xe) | (ln3 == 0xe)) { 991 printf("goto ffe\n"); 992 break; 993 } else { 994 value = (ln3 << 16) | (ln2 << 12) | (ln1 << 8) | (ln0 << 4) | 0xf; 995 hdmi_writel(hdmi, value, FLT_CONFIG1); 996 } 997 } 998 999 drm_scdc_writeb(&hdmi->adap, 0x10, val); 1000 1001 if ((val & BIT(4)) && ltsp) { 1002 hdmi_modb(hdmi, 0, AVP_DATAPATH_VIDEO_SWDISABLE, GLOBAL_SWDISABLE); 1003 printf("flt success\n"); 1004 break; 1005 } 1006 } 1007 1008 if (i < 0) { 1009 printf("flt time out\n"); 1010 return -ETIMEDOUT; 1011 } 1012 1013 return 0; 1014 } 1015 1016 #define HDMI_MODE_FRL_MASK BIT(30) 1017 1018 static void hdmi_set_op_mode(struct dw_hdmi_qp *hdmi, 1019 struct dw_hdmi_link_config *link_cfg, 1020 struct display_state *state, 1021 struct rockchip_connector *conn) 1022 { 1023 int frl_rate; 1024 int i, ret; 1025 1026 if (!link_cfg->frl_mode) { 1027 printf("dw hdmi qp use tmds mode\n"); 1028 hdmi_modb(hdmi, 0, OPMODE_FRL, LINK_CONFIG0); 1029 hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0); 1030 hdmi->phy.ops->init(conn, hdmi->rk_hdmi, state); 1031 hdmi->phy.enabled = true; 1032 return; 1033 } 1034 1035 if (link_cfg->frl_lanes == 4) 1036 hdmi_modb(hdmi, OPMODE_FRL_4LANES, OPMODE_FRL_4LANES, 1037 LINK_CONFIG0); 1038 else 1039 hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0); 1040 1041 hdmi_modb(hdmi, 1, OPMODE_FRL, LINK_CONFIG0); 1042 1043 frl_rate = link_cfg->frl_lanes * link_cfg->rate_per_lane; 1044 hdmi->phy.ops->init(conn, hdmi->rk_hdmi, state); 1045 hdmi->phy.enabled = true; 1046 1047 mdelay(200); 1048 ret = hdmi_start_flt(hdmi, frl_rate); 1049 if (ret) { 1050 hdmi_writel(hdmi, 0, FLT_CONFIG0); 1051 drm_scdc_writeb(&hdmi->adap, 0x31, 0); 1052 hdmi_modb(hdmi, 0, AVP_DATAPATH_VIDEO_SWDISABLE, GLOBAL_SWDISABLE); 1053 return; 1054 } 1055 1056 for (i = 0; i < 200; i++) { 1057 hdmi_modb(hdmi, PKTSCHED_NULL_TX_EN, PKTSCHED_NULL_TX_EN, PKTSCHED_PKT_EN); 1058 udelay(50); 1059 hdmi_modb(hdmi, 0, PKTSCHED_NULL_TX_EN, PKTSCHED_PKT_EN); 1060 udelay(50); 1061 } 1062 } 1063 1064 static int dw_hdmi_setup(struct dw_hdmi_qp *hdmi, 1065 struct rockchip_connector *conn, 1066 struct drm_display_mode *mode, 1067 struct display_state *state) 1068 { 1069 int ret; 1070 void *data = hdmi->plat_data->phy_data; 1071 struct dw_hdmi_link_config *link_cfg; 1072 struct drm_hdmi_info *hdmi_info = &hdmi->edid_data.display_info.hdmi; 1073 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1074 u8 bytes = 0; 1075 1076 if (!hdmi->vic) 1077 printf("Non-CEA mode used in HDMI\n"); 1078 else 1079 printf("CEA mode used vic=%d\n", hdmi->vic); 1080 1081 vmode->mpixelclock = mode->clock * 1000; 1082 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock); 1083 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1084 vmode->mtmdsclock /= 2; 1085 printf("mtmdsclock:%d\n", vmode->mtmdsclock); 1086 1087 if (hdmi->plat_data->get_enc_out_encoding) 1088 hdmi->hdmi_data.enc_out_encoding = 1089 hdmi->plat_data->get_enc_out_encoding(data); 1090 else if (hdmi->vic == 6 || hdmi->vic == 7 || 1091 hdmi->vic == 21 || hdmi->vic == 22 || 1092 hdmi->vic == 2 || hdmi->vic == 3 || 1093 hdmi->vic == 17 || hdmi->vic == 18) 1094 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 1095 else 1096 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 1097 1098 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1099 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1; 1100 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1; 1101 } else { 1102 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 1103 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 1104 } 1105 1106 /* TOFIX: Get input encoding from plat data or fallback to none */ 1107 if (hdmi->plat_data->get_enc_in_encoding) 1108 hdmi->hdmi_data.enc_in_encoding = 1109 hdmi->plat_data->get_enc_in_encoding(data); 1110 else if (hdmi->plat_data->input_bus_encoding) 1111 hdmi->hdmi_data.enc_in_encoding = 1112 hdmi->plat_data->input_bus_encoding; 1113 else 1114 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 1115 1116 if (hdmi->plat_data->get_quant_range) 1117 hdmi->hdmi_data.quant_range = 1118 hdmi->plat_data->get_quant_range(data); 1119 else 1120 hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 1121 1122 /* 1123 * According to the dw-hdmi specification 6.4.2 1124 * vp_pr_cd[3:0]: 1125 * 0000b: No pixel repetition (pixel sent only once) 1126 * 0001b: Pixel sent two times (pixel repeated once) 1127 */ 1128 hdmi->hdmi_data.pix_repet_factor = 1129 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0; 1130 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 1131 1132 /* HDMI Initialization Step B.2 */ 1133 hdmi->phy.ops->set_pll(conn, hdmi->rk_hdmi, state); 1134 1135 /* Mark yuv422 10bit */ 1136 if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_YUYV10_1X20) 1137 hdmi_writel(hdmi, BIT(20), VIDEO_INTERFACE_CONFIG0); 1138 dw_hdmi_qp_set_grf_cfg(hdmi->rk_hdmi); 1139 link_cfg = dw_hdmi_rockchip_get_link_cfg(hdmi->rk_hdmi); 1140 1141 /* not for DVI mode */ 1142 if (hdmi->sink_is_hdmi) { 1143 printf("%s HDMI mode\n", __func__); 1144 hdmi_modb(hdmi, 0, OPMODE_DVI, LINK_CONFIG0); 1145 hdmi_modb(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0); 1146 hdmi_modb(hdmi, KEEPOUT_REKEY_ALWAYS, KEEPOUT_REKEY_CFG, FRAME_COMPOSER_CONFIG9); 1147 hdmi_writel(hdmi, 0, FLT_CONFIG0); 1148 if (hdmi_info->scdc.supported) 1149 drm_scdc_writeb(&hdmi->adap, 0x31, 0); 1150 if (!link_cfg->frl_mode) { 1151 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK) { 1152 drm_scdc_readb(&hdmi->adap, SCDC_SINK_VERSION, &bytes); 1153 drm_scdc_writeb(&hdmi->adap, SCDC_SOURCE_VERSION, 1154 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); 1155 drm_scdc_set_high_tmds_clock_ratio(&hdmi->adap, 1); 1156 drm_scdc_set_scrambling(&hdmi->adap, 1); 1157 hdmi_writel(hdmi, 1, SCRAMB_CONFIG0); 1158 mdelay(100); 1159 } else { 1160 if (hdmi_info->scdc.supported) { 1161 drm_scdc_set_high_tmds_clock_ratio(&hdmi->adap, 0); 1162 drm_scdc_set_scrambling(&hdmi->adap, 0); 1163 } 1164 hdmi_writel(hdmi, 0, SCRAMB_CONFIG0); 1165 } 1166 } 1167 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 1168 hdmi_config_AVI(hdmi, mode); 1169 hdmi_config_vendor_specific_infoframe(hdmi, mode); 1170 hdmi_config_CVTEM(hdmi, link_cfg); 1171 hdmi_set_op_mode(hdmi, link_cfg, state, conn); 1172 /* clear avmute */ 1173 mdelay(50); 1174 hdmi_writel(hdmi, 2, PKTSCHED_PKT_CONTROL0); 1175 hdmi_modb(hdmi, PKTSCHED_GCP_TX_EN, PKTSCHED_GCP_TX_EN, 1176 PKTSCHED_PKT_EN); 1177 } else { 1178 hdmi_modb(hdmi, OPMODE_DVI, OPMODE_DVI, LINK_CONFIG0); 1179 ret = hdmi->phy.ops->init(conn, hdmi->rk_hdmi, state); 1180 if (ret) 1181 return ret; 1182 hdmi->phy.enabled = true; 1183 printf("%s DVI mode\n", __func__); 1184 } 1185 1186 /* Mark uboot hdmi is enabled */ 1187 hdmi_writel(hdmi, BIT(21), VIDEO_INTERFACE_CONFIG0); 1188 1189 return 0; 1190 } 1191 1192 int dw_hdmi_detect_hotplug(struct dw_hdmi_qp *hdmi, 1193 struct display_state *state) 1194 { 1195 struct connector_state *conn_state = &state->conn_state; 1196 struct rockchip_connector *conn = conn_state->connector; 1197 int ret; 1198 1199 ret = hdmi->phy.ops->read_hpd(hdmi->rk_hdmi); 1200 if (!ret) { 1201 if (conn->bridge) 1202 ret = rockchip_bridge_detect(conn->bridge); 1203 } 1204 1205 if (ret || state->force_output) { 1206 if (!hdmi->id) 1207 conn_state->output_if |= VOP_OUTPUT_IF_HDMI0; 1208 else 1209 conn_state->output_if |= VOP_OUTPUT_IF_HDMI1; 1210 } 1211 1212 return ret; 1213 } 1214 1215 int rockchip_dw_hdmi_qp_init(struct rockchip_connector *conn, struct display_state *state) 1216 { 1217 struct connector_state *conn_state = &state->conn_state; 1218 const struct dw_hdmi_plat_data *pdata = 1219 (const struct dw_hdmi_plat_data *)dev_get_driver_data(conn->dev); 1220 void *rk_hdmi = dev_get_priv(conn->dev); 1221 struct dw_hdmi_qp *hdmi; 1222 struct drm_display_mode *mode_buf; 1223 ofnode hdmi_node = conn->dev->node; 1224 struct device_node *ddc_node; 1225 1226 hdmi = malloc(sizeof(struct dw_hdmi_qp)); 1227 if (!hdmi) 1228 return -ENOMEM; 1229 1230 memset(hdmi, 0, sizeof(struct dw_hdmi_qp)); 1231 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 1232 if (!mode_buf) 1233 return -ENOMEM; 1234 1235 hdmi->rk_hdmi = rk_hdmi; 1236 hdmi->id = of_alias_get_id(ofnode_to_np(hdmi_node), "hdmi"); 1237 if (hdmi->id < 0) 1238 hdmi->id = 0; 1239 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, hdmi->id); 1240 1241 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 1242 1243 hdmi->regs = dev_read_addr_ptr(conn->dev); 1244 1245 ddc_node = of_parse_phandle(ofnode_to_np(hdmi_node), "ddc-i2c-bus", 0); 1246 if (ddc_node) { 1247 uclass_get_device_by_ofnode(UCLASS_I2C, np_to_ofnode(ddc_node), 1248 &hdmi->adap.i2c_bus); 1249 if (hdmi->adap.i2c_bus) 1250 hdmi->adap.ops = i2c_get_ops(hdmi->adap.i2c_bus); 1251 } 1252 1253 hdmi->i2c = malloc(sizeof(struct dw_hdmi_i2c)); 1254 if (!hdmi->i2c) 1255 return -ENOMEM; 1256 hdmi->adap.ddc_xfer = dw_hdmi_i2c_xfer; 1257 1258 /* 1259 * Read high and low time from device tree. If not available use 1260 * the default timing scl clock rate is about 99.6KHz. 1261 */ 1262 hdmi->i2c->scl_high_ns = 1263 ofnode_read_s32_default(hdmi_node, 1264 "ddc-i2c-scl-high-time-ns", 4708); 1265 hdmi->i2c->scl_low_ns = 1266 ofnode_read_s32_default(hdmi_node, 1267 "ddc-i2c-scl-low-time-ns", 4916); 1268 1269 dw_hdmi_i2c_init(hdmi); 1270 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1271 1272 hdmi->dev_type = pdata->dev_type; 1273 hdmi->plat_data = pdata; 1274 hdmi->edid_data.mode_buf = mode_buf; 1275 1276 conn->data = hdmi; 1277 1278 dw_hdmi_detect_phy(hdmi); 1279 hdmi_writel(hdmi, 0, MAINUNIT_0_INT_MASK_N); 1280 hdmi_writel(hdmi, 0, MAINUNIT_1_INT_MASK_N); 1281 hdmi_writel(hdmi, 428571429, TIMER_BASE_CONFIG0); 1282 1283 dw_hdmi_qp_io_path_init(hdmi->rk_hdmi); 1284 1285 return 0; 1286 } 1287 1288 void rockchip_dw_hdmi_qp_deinit(struct rockchip_connector *conn, struct display_state *state) 1289 { 1290 struct dw_hdmi_qp *hdmi = conn->data; 1291 1292 if (hdmi->i2c) 1293 free(hdmi->i2c); 1294 if (hdmi->edid_data.mode_buf) 1295 free(hdmi->edid_data.mode_buf); 1296 if (hdmi) 1297 free(hdmi); 1298 } 1299 1300 static void rockchip_dw_hdmi_qp_config_output(struct rockchip_connector *conn, 1301 struct display_state *state) 1302 { 1303 struct connector_state *conn_state = &state->conn_state; 1304 struct drm_display_mode *mode = &conn_state->mode; 1305 struct dw_hdmi_qp *hdmi = conn->data; 1306 unsigned int bus_format; 1307 unsigned long enc_out_encoding; 1308 struct overscan *overscan = &conn_state->overscan; 1309 1310 dw_hdmi_qp_select_output(&hdmi->edid_data, conn, &bus_format, 1311 overscan, hdmi->dev_type, 1312 hdmi->output_bus_format_rgb, hdmi->rk_hdmi, 1313 state); 1314 1315 *mode = *hdmi->edid_data.preferred_mode; 1316 hdmi->vic = drm_match_cea_mode(mode); 1317 1318 printf("mode:%dx%d bus_format:0x%x\n", mode->hdisplay, mode->vdisplay, bus_format); 1319 conn_state->bus_format = bus_format; 1320 hdmi->hdmi_data.enc_in_bus_format = bus_format; 1321 hdmi->hdmi_data.enc_out_bus_format = bus_format; 1322 1323 switch (bus_format) { 1324 case MEDIA_BUS_FMT_YUYV10_1X20: 1325 conn_state->bus_format = MEDIA_BUS_FMT_YUYV10_1X20; 1326 hdmi->hdmi_data.enc_in_bus_format = 1327 MEDIA_BUS_FMT_YUYV10_1X20; 1328 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV422; 1329 break; 1330 case MEDIA_BUS_FMT_YUYV8_1X16: 1331 conn_state->bus_format = MEDIA_BUS_FMT_YUYV8_1X16; 1332 hdmi->hdmi_data.enc_in_bus_format = 1333 MEDIA_BUS_FMT_YUYV8_1X16; 1334 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV422; 1335 break; 1336 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1337 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1338 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420; 1339 break; 1340 } 1341 1342 if (hdmi->vic == 6 || hdmi->vic == 7 || hdmi->vic == 21 || 1343 hdmi->vic == 22 || hdmi->vic == 2 || hdmi->vic == 3 || 1344 hdmi->vic == 17 || hdmi->vic == 18) 1345 enc_out_encoding = V4L2_YCBCR_ENC_601; 1346 else 1347 enc_out_encoding = V4L2_YCBCR_ENC_709; 1348 1349 if (enc_out_encoding == V4L2_YCBCR_ENC_BT2020) 1350 conn_state->color_encoding = DRM_COLOR_YCBCR_BT2020; 1351 else if (bus_format == MEDIA_BUS_FMT_RGB888_1X24 || 1352 bus_format == MEDIA_BUS_FMT_RGB101010_1X30) 1353 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709; 1354 else if (enc_out_encoding == V4L2_YCBCR_ENC_709) 1355 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709; 1356 else 1357 conn_state->color_encoding = DRM_COLOR_YCBCR_BT601; 1358 1359 if (bus_format == MEDIA_BUS_FMT_RGB888_1X24 || 1360 bus_format == MEDIA_BUS_FMT_RGB101010_1X30) 1361 conn_state->color_range = hdmi->hdmi_data.quant_range == 1362 HDMI_QUANTIZATION_RANGE_LIMITED ? 1363 DRM_COLOR_YCBCR_LIMITED_RANGE : 1364 DRM_COLOR_YCBCR_FULL_RANGE; 1365 else 1366 conn_state->color_range = hdmi->hdmi_data.quant_range == 1367 HDMI_QUANTIZATION_RANGE_FULL ? 1368 DRM_COLOR_YCBCR_FULL_RANGE : 1369 DRM_COLOR_YCBCR_LIMITED_RANGE; 1370 } 1371 1372 int rockchip_dw_hdmi_qp_prepare(struct rockchip_connector *conn, struct display_state *state) 1373 { 1374 struct connector_state *conn_state = &state->conn_state; 1375 struct drm_display_mode *mode = &conn_state->mode; 1376 struct dw_hdmi_qp *hdmi = conn->data; 1377 1378 if (!hdmi->edid_data.preferred_mode && conn->bridge) { 1379 drm_add_hdmi_modes(&hdmi->edid_data, mode); 1380 drm_mode_sort(&hdmi->edid_data); 1381 hdmi->sink_is_hdmi = true; 1382 hdmi->sink_has_audio = true; 1383 rockchip_dw_hdmi_qp_config_output(conn, state); 1384 } 1385 1386 return 0; 1387 } 1388 1389 int rockchip_dw_hdmi_qp_check(struct rockchip_connector *conn, struct display_state *state) 1390 { 1391 struct crtc_state *cstate = &state->crtc_state; 1392 struct rockchip_crtc *crtc = cstate->crtc; 1393 struct dw_hdmi_qp *hdmi = conn->data; 1394 1395 /* clear hdmi uboot logo on flag */ 1396 if (crtc->splice_mode && cstate->crtc_id == 1) 1397 hdmi_writel(hdmi, 0, I2CM_INTERFACE_CONTROL0); 1398 1399 return 0; 1400 } 1401 1402 static void dw_hdmi_disable(struct rockchip_connector *conn, struct dw_hdmi_qp *hdmi, 1403 struct display_state *state) 1404 { 1405 if (hdmi->phy.enabled) { 1406 hdmi->phy.ops->disable(conn, hdmi->rk_hdmi, state); 1407 hdmi->phy.enabled = false; 1408 } 1409 } 1410 1411 int rockchip_dw_hdmi_qp_enable(struct rockchip_connector *conn, struct display_state *state) 1412 { 1413 struct connector_state *conn_state = &state->conn_state; 1414 struct drm_display_mode *mode = &conn_state->mode; 1415 struct dw_hdmi_qp *hdmi = conn->data; 1416 1417 if (!hdmi) 1418 return -EFAULT; 1419 1420 /* Store the display mode for plugin/DKMS poweron events */ 1421 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 1422 1423 dw_hdmi_setup(hdmi, conn, mode, state); 1424 1425 return 0; 1426 } 1427 1428 int rockchip_dw_hdmi_qp_disable(struct rockchip_connector *conn, struct display_state *state) 1429 { 1430 struct dw_hdmi_qp *hdmi = conn->data; 1431 1432 dw_hdmi_disable(conn, hdmi, state); 1433 return 0; 1434 } 1435 1436 static void rockchip_dw_hdmi_qp_mode_valid(struct dw_hdmi_qp *hdmi) 1437 { 1438 struct hdmi_edid_data *edid_data = &hdmi->edid_data; 1439 int i; 1440 bool enable_gpio = dw_hdmi_qp_check_enable_gpio(hdmi->rk_hdmi); 1441 1442 for (i = 0; i < edid_data->modes; i++) { 1443 if (edid_data->mode_buf[i].invalid) 1444 continue; 1445 1446 if (edid_data->mode_buf[i].clock <= 25000) 1447 edid_data->mode_buf[i].invalid = true; 1448 1449 if (edid_data->mode_buf[i].clock > 600000 && !enable_gpio) 1450 edid_data->mode_buf[i].invalid = true; 1451 } 1452 } 1453 1454 static int _rockchip_dw_hdmi_qp_get_timing(struct rockchip_connector *conn, 1455 struct display_state *state, int edid_status) 1456 { 1457 int i; 1458 struct connector_state *conn_state = &state->conn_state; 1459 struct dw_hdmi_qp *hdmi = conn->data; 1460 struct edid *edid = (struct edid *)conn_state->edid; 1461 const u8 def_modes_vic[6] = {4, 16, 2, 17, 31, 19}; 1462 1463 if (!hdmi) 1464 return -EFAULT; 1465 1466 if (!edid_status) { 1467 hdmi->sink_is_hdmi = 1468 drm_detect_hdmi_monitor(edid); 1469 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 1470 edid_status = drm_add_edid_modes(&hdmi->edid_data, conn_state->edid); 1471 } 1472 if (edid_status < 0) { 1473 hdmi->sink_is_hdmi = true; 1474 hdmi->sink_has_audio = true; 1475 do_cea_modes(&hdmi->edid_data, def_modes_vic, 1476 sizeof(def_modes_vic)); 1477 hdmi->edid_data.preferred_mode = &hdmi->edid_data.mode_buf[0]; 1478 printf("failed to get edid\n"); 1479 } 1480 drm_rk_filter_whitelist(&hdmi->edid_data); 1481 rockchip_dw_hdmi_qp_mode_valid(hdmi); 1482 drm_mode_max_resolution_filter(&hdmi->edid_data, 1483 &state->crtc_state.max_output); 1484 if (!drm_mode_prune_invalid(&hdmi->edid_data)) { 1485 printf("can't find valid hdmi mode\n"); 1486 return -EINVAL; 1487 } 1488 1489 for (i = 0; i < hdmi->edid_data.modes; i++) 1490 hdmi->edid_data.mode_buf[i].vrefresh = 1491 drm_mode_vrefresh(&hdmi->edid_data.mode_buf[i]); 1492 1493 drm_mode_sort(&hdmi->edid_data); 1494 1495 rockchip_dw_hdmi_qp_config_output(conn, state); 1496 1497 return 0; 1498 } 1499 1500 int rockchip_dw_hdmi_qp_get_timing(struct rockchip_connector *conn, struct display_state *state) 1501 { 1502 struct connector_state *conn_state = &state->conn_state; 1503 struct dw_hdmi_qp *hdmi = conn->data; 1504 int ret; 1505 1506 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 1507 1508 if (conn_state->secondary) 1509 _rockchip_dw_hdmi_qp_get_timing(conn_state->secondary, state, ret); 1510 1511 return _rockchip_dw_hdmi_qp_get_timing(conn, state, ret); 1512 } 1513 1514 1515 int rockchip_dw_hdmi_qp_detect(struct rockchip_connector *conn, struct display_state *state) 1516 { 1517 int ret; 1518 struct dw_hdmi_qp *hdmi = conn->data; 1519 1520 if (!hdmi) 1521 return -EFAULT; 1522 1523 ret = dw_hdmi_detect_hotplug(hdmi, state); 1524 1525 return ret; 1526 } 1527 1528 int rockchip_dw_hdmi_qp_get_edid(struct rockchip_connector *conn, struct display_state *state) 1529 { 1530 int ret; 1531 struct connector_state *conn_state = &state->conn_state; 1532 struct dw_hdmi_qp *hdmi = conn->data; 1533 1534 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 1535 1536 return ret; 1537 } 1538