1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd 4 * Author: Algea Cao <algea.cao@rock-chips.com> 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <syscon.h> 10 #include <asm/arch-rockchip/clock.h> 11 #include <asm/arch/vendor.h> 12 #include <edid.h> 13 #include <dm/device.h> 14 #include <dm/of_access.h> 15 #include <dm/ofnode.h> 16 #include <dm/read.h> 17 #include <linux/hdmi.h> 18 #include <linux/media-bus-format.h> 19 #include <linux/dw_hdmi.h> 20 #include <asm/io.h> 21 #include "rockchip_bridge.h" 22 #include "rockchip_display.h" 23 #include "rockchip_crtc.h" 24 #include "rockchip_connector.h" 25 #include "dw_hdmi_qp.h" 26 #include "rockchip_phy.h" 27 28 enum frl_mask { 29 FRL_3GBPS_3LANE = 1, 30 FRL_6GBPS_3LANE, 31 FRL_6GBPS_4LANE, 32 FRL_8GBPS_4LANE, 33 FRL_10GBPS_4LANE, 34 FRL_12GBPS_4LANE, 35 }; 36 37 #define DDC_CI_ADDR 0x37 38 #define DDC_SEGMENT_ADDR 0x30 39 40 #define HDMI_EDID_LEN 512 41 42 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ 43 #define SCDC_MIN_SOURCE_VERSION 0x1 44 45 #define HDMI14_MAX_TMDSCLK 340000000 46 47 struct hdmi_vmode { 48 bool mdataenablepolarity; 49 50 unsigned int mpixelclock; 51 unsigned int mpixelrepetitioninput; 52 unsigned int mpixelrepetitionoutput; 53 unsigned int mtmdsclock; 54 }; 55 56 struct hdmi_data_info { 57 unsigned int enc_in_bus_format; 58 unsigned int enc_out_bus_format; 59 unsigned int enc_in_encoding; 60 unsigned int enc_out_encoding; 61 unsigned int quant_range; 62 unsigned int pix_repet_factor; 63 struct hdmi_vmode video_mode; 64 }; 65 66 struct dw_hdmi_phy_data { 67 enum dw_hdmi_phy_type type; 68 const char *name; 69 unsigned int gen; 70 bool has_svsret; 71 int (*configure)(struct dw_hdmi *hdmi, 72 const struct dw_hdmi_plat_data *pdata, 73 unsigned long mpixelclock); 74 }; 75 76 struct dw_hdmi_i2c { 77 u8 slave_reg; 78 bool is_regaddr; 79 bool is_segment; 80 81 unsigned int scl_high_ns; 82 unsigned int scl_low_ns; 83 }; 84 85 struct dw_hdmi_qp { 86 enum dw_hdmi_devtype dev_type; 87 unsigned int version; 88 struct hdmi_data_info hdmi_data; 89 struct hdmi_edid_data edid_data; 90 const struct dw_hdmi_plat_data *plat_data; 91 struct ddc_adapter adap; 92 93 int vic; 94 int id; 95 96 unsigned long bus_format; 97 bool cable_plugin; 98 bool sink_is_hdmi; 99 bool sink_has_audio; 100 void *regs; 101 void *rk_hdmi; 102 struct dw_hdmi_i2c *i2c; 103 104 struct { 105 const struct dw_hdmi_qp_phy_ops *ops; 106 const char *name; 107 void *data; 108 bool enabled; 109 } phy; 110 111 struct drm_display_mode previous_mode; 112 113 unsigned int sample_rate; 114 unsigned int audio_cts; 115 unsigned int audio_n; 116 bool audio_enable; 117 bool scramble_low_rates; 118 119 void (*write)(struct dw_hdmi_qp *hdmi, u32 val, int offset); 120 u8 (*read)(struct dw_hdmi_qp *hdmi, int offset); 121 122 bool hdcp1x_enable; 123 bool output_bus_format_rgb; 124 }; 125 126 static inline void hdmi_writel(struct dw_hdmi_qp *hdmi, u32 val, int offset) 127 { 128 writel(val, hdmi->regs + offset); 129 } 130 131 static inline u32 hdmi_readl(struct dw_hdmi_qp *hdmi, int offset) 132 { 133 return readl(hdmi->regs + offset); 134 } 135 136 static void 137 hdmi_modb(struct dw_hdmi_qp *hdmi, u32 data, u32 mask, unsigned int reg) 138 { 139 u32 val = hdmi_readl(hdmi, reg) & ~mask; 140 141 val |= data & mask; 142 hdmi_writel(hdmi, val, reg); 143 } 144 145 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 146 { 147 switch (bus_format) { 148 case MEDIA_BUS_FMT_RGB888_1X24: 149 case MEDIA_BUS_FMT_RGB101010_1X30: 150 case MEDIA_BUS_FMT_RGB121212_1X36: 151 case MEDIA_BUS_FMT_RGB161616_1X48: 152 return true; 153 154 default: 155 return false; 156 } 157 } 158 159 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 160 { 161 switch (bus_format) { 162 case MEDIA_BUS_FMT_YUV8_1X24: 163 case MEDIA_BUS_FMT_YUV10_1X30: 164 case MEDIA_BUS_FMT_YUV12_1X36: 165 case MEDIA_BUS_FMT_YUV16_1X48: 166 return true; 167 168 default: 169 return false; 170 } 171 } 172 173 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 174 { 175 switch (bus_format) { 176 case MEDIA_BUS_FMT_UYVY8_1X16: 177 case MEDIA_BUS_FMT_UYVY10_1X20: 178 case MEDIA_BUS_FMT_UYVY12_1X24: 179 case MEDIA_BUS_FMT_YUYV8_1X16: 180 case MEDIA_BUS_FMT_YUYV10_1X20: 181 case MEDIA_BUS_FMT_YUYV12_1X24: 182 return true; 183 184 default: 185 return false; 186 } 187 } 188 189 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 190 { 191 switch (bus_format) { 192 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 193 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 194 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 195 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 196 return true; 197 198 default: 199 return false; 200 } 201 } 202 203 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 204 { 205 switch (bus_format) { 206 case MEDIA_BUS_FMT_RGB888_1X24: 207 case MEDIA_BUS_FMT_YUV8_1X24: 208 case MEDIA_BUS_FMT_UYVY8_1X16: 209 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 210 return 8; 211 212 case MEDIA_BUS_FMT_RGB101010_1X30: 213 case MEDIA_BUS_FMT_YUV10_1X30: 214 case MEDIA_BUS_FMT_UYVY10_1X20: 215 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 216 return 10; 217 218 case MEDIA_BUS_FMT_RGB121212_1X36: 219 case MEDIA_BUS_FMT_YUV12_1X36: 220 case MEDIA_BUS_FMT_UYVY12_1X24: 221 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 222 return 12; 223 224 case MEDIA_BUS_FMT_RGB161616_1X48: 225 case MEDIA_BUS_FMT_YUV16_1X48: 226 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 227 return 16; 228 229 default: 230 return 0; 231 } 232 } 233 234 static bool drm_scdc_set_scrambling(struct ddc_adapter *adapter, bool enable) 235 { 236 u8 config; 237 int ret; 238 239 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 240 if (ret < 0) { 241 debug("Failed to read TMDS config: %d\n", ret); 242 return false; 243 } 244 245 if (enable) 246 config |= SCDC_SCRAMBLING_ENABLE; 247 else 248 config &= ~SCDC_SCRAMBLING_ENABLE; 249 250 ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config); 251 if (ret < 0) { 252 debug("Failed to enable scrambling: %d\n", ret); 253 return false; 254 } 255 256 return true; 257 } 258 259 static bool 260 drm_scdc_set_high_tmds_clock_ratio(struct ddc_adapter *adapter, bool set) 261 { 262 u8 config; 263 int ret; 264 265 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 266 if (ret < 0) { 267 debug("Failed to read TMDS config: %d\n", ret); 268 return false; 269 } 270 271 if (set) 272 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 273 else 274 config &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 275 276 ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config); 277 if (ret < 0) { 278 debug("Failed to set TMDS clock ratio: %d\n", ret); 279 return false; 280 } 281 282 /* 283 * The spec says that a source should wait minimum 1ms and maximum 284 * 100ms after writing the TMDS config for clock ratio. Lets allow a 285 * wait of up to 2ms here. 286 */ 287 udelay(2000); 288 return true; 289 } 290 291 static void dw_hdmi_i2c_init(struct dw_hdmi_qp *hdmi) 292 { 293 /* Software reset */ 294 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 295 296 hdmi_writel(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0); 297 298 hdmi_modb(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0); 299 300 /* Clear DONE and ERROR interrupts */ 301 hdmi_writel(hdmi, I2CM_OP_DONE_CLEAR | I2CM_NACK_RCVD_CLEAR, 302 MAINUNIT_1_INT_CLEAR); 303 } 304 305 static int dw_hdmi_i2c_read(struct dw_hdmi_qp *hdmi, 306 unsigned char *buf, unsigned int length) 307 { 308 struct dw_hdmi_i2c *i2c = hdmi->i2c; 309 int i = 20; 310 u32 intr = 0; 311 312 if (!i2c->is_regaddr) { 313 printf("set read register address to 0\n"); 314 i2c->slave_reg = 0x00; 315 i2c->is_regaddr = true; 316 } 317 318 while (length--) { 319 hdmi_modb(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, 320 I2CM_INTERFACE_CONTROL0); 321 322 hdmi_modb(hdmi, I2CM_FM_READ, I2CM_WR_MASK, 323 I2CM_INTERFACE_CONTROL0); 324 325 while (i--) { 326 udelay(1000); 327 intr = hdmi_readl(hdmi, MAINUNIT_1_INT_STATUS) & 328 (I2CM_OP_DONE_IRQ | I2CM_READ_REQUEST_IRQ | 329 I2CM_NACK_RCVD_IRQ); 330 if (intr) { 331 hdmi_writel(hdmi, intr, MAINUNIT_1_INT_CLEAR); 332 break; 333 } 334 } 335 336 if (!i) { 337 printf("i2c read time out!\n"); 338 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 339 return -EAGAIN; 340 } 341 342 /* Check for error condition on the bus */ 343 if (intr & I2CM_NACK_RCVD_IRQ) { 344 printf("i2c read err!\n"); 345 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 346 return -EIO; 347 } 348 349 *buf++ = hdmi_readl(hdmi, I2CM_INTERFACE_RDDATA_0_3) & 0xff; 350 hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); 351 i = 20; 352 } 353 i2c->is_segment = false; 354 355 return 0; 356 } 357 358 static int dw_hdmi_i2c_write(struct dw_hdmi_qp *hdmi, 359 unsigned char *buf, unsigned int length) 360 { 361 struct dw_hdmi_i2c *i2c = hdmi->i2c; 362 int i = 20; 363 u32 intr = 0; 364 365 if (!i2c->is_regaddr) { 366 /* Use the first write byte as register address */ 367 i2c->slave_reg = buf[0]; 368 length--; 369 buf++; 370 i2c->is_regaddr = true; 371 } 372 373 while (length--) { 374 hdmi_writel(hdmi, *buf++, I2CM_INTERFACE_WRDATA_0_3); 375 hdmi_modb(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, 376 I2CM_INTERFACE_CONTROL0); 377 hdmi_modb(hdmi, I2CM_FM_WRITE, I2CM_WR_MASK, 378 I2CM_INTERFACE_CONTROL0); 379 380 while (i--) { 381 udelay(1000); 382 intr = hdmi_readl(hdmi, MAINUNIT_1_INT_STATUS) & 383 (I2CM_OP_DONE_IRQ | I2CM_READ_REQUEST_IRQ | 384 I2CM_NACK_RCVD_IRQ); 385 if (intr) { 386 hdmi_writel(hdmi, intr, MAINUNIT_1_INT_CLEAR); 387 break; 388 } 389 } 390 391 if (!i) { 392 printf("i2c write time out!\n"); 393 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 394 return -EAGAIN; 395 } 396 397 /* Check for error condition on the bus */ 398 if (intr & I2CM_NACK_RCVD_IRQ) { 399 printf("i2c write nack!\n"); 400 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 401 return -EIO; 402 } 403 hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); 404 i = 20; 405 } 406 407 return 0; 408 } 409 410 static int dw_hdmi_i2c_xfer(struct ddc_adapter *adap, 411 struct i2c_msg *msgs, int num) 412 { 413 struct dw_hdmi_qp *hdmi = container_of(adap, struct dw_hdmi_qp, adap); 414 struct dw_hdmi_i2c *i2c = hdmi->i2c; 415 u8 addr = msgs[0].addr; 416 int i, ret = 0; 417 418 debug("i2c xfer: num: %d, addr: %#x\n", num, addr); 419 420 for (i = 0; i < num; i++) { 421 if (msgs[i].len == 0) { 422 printf("unsupported transfer %d/%d, no data\n", 423 i + 1, num); 424 return -EOPNOTSUPP; 425 } 426 } 427 428 /* Unmute DONE and ERROR interrupts */ 429 hdmi_modb(hdmi, I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, 430 I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, 431 MAINUNIT_1_INT_MASK_N); 432 433 /* Set slave device address taken from the first I2C message */ 434 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1) 435 addr = DDC_ADDR; 436 437 hdmi_modb(hdmi, addr << 5, I2CM_SLVADDR, I2CM_INTERFACE_CONTROL0); 438 439 /* Set slave device register address on transfer */ 440 i2c->is_regaddr = false; 441 442 /* Set segment pointer for I2C extended read mode operation */ 443 i2c->is_segment = false; 444 445 for (i = 0; i < num; i++) { 446 debug("xfer: num: %d/%d, len: %d, flags: %#x\n", 447 i + 1, num, msgs[i].len, msgs[i].flags); 448 449 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 450 i2c->is_segment = true; 451 hdmi_modb(hdmi, DDC_SEGMENT_ADDR, I2CM_SEG_ADDR, 452 I2CM_INTERFACE_CONTROL1); 453 hdmi_modb(hdmi, *msgs[i].buf, I2CM_SEG_PTR, 454 I2CM_INTERFACE_CONTROL1); 455 } else { 456 if (msgs[i].flags & I2C_M_RD) 457 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 458 msgs[i].len); 459 else 460 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 461 msgs[i].len); 462 } 463 if (ret < 0) 464 break; 465 } 466 467 if (!ret) 468 ret = num; 469 470 /* Mute DONE and ERROR interrupts */ 471 hdmi_modb(hdmi, 0, I2CM_OP_DONE_MASK_N | I2CM_NACK_RCVD_MASK_N, 472 MAINUNIT_1_INT_MASK_N); 473 474 return ret; 475 } 476 477 static int dw_hdmi_detect_phy(struct dw_hdmi_qp *hdmi) 478 { 479 /* Vendor PHYs require support from the glue layer. */ 480 if (!hdmi->plat_data->qp_phy_ops || !hdmi->plat_data->phy_name) { 481 dev_err(hdmi->dev, 482 "Vendor HDMI PHY not supported by glue layer\n"); 483 return -ENODEV; 484 } 485 486 hdmi->phy.ops = hdmi->plat_data->qp_phy_ops; 487 hdmi->phy.data = hdmi->plat_data->phy_data; 488 hdmi->phy.name = hdmi->plat_data->phy_name; 489 490 return 0; 491 } 492 493 static unsigned int 494 hdmi_get_tmdsclock(struct dw_hdmi_qp *hdmi, unsigned long mpixelclock) 495 { 496 unsigned int tmdsclock = mpixelclock; 497 unsigned int depth = 498 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 499 500 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 501 switch (depth) { 502 case 16: 503 tmdsclock = mpixelclock * 2; 504 break; 505 case 12: 506 tmdsclock = mpixelclock * 3 / 2; 507 break; 508 case 10: 509 tmdsclock = mpixelclock * 5 / 4; 510 break; 511 default: 512 break; 513 } 514 } 515 516 return tmdsclock; 517 } 518 519 static void hdmi_infoframe_set_checksum(u8 *ptr, int size) 520 { 521 u8 csum = 0; 522 int i; 523 524 ptr[3] = 0; 525 /* compute checksum */ 526 for (i = 0; i < size; i++) 527 csum += ptr[i]; 528 529 ptr[3] = 256 - csum; 530 } 531 532 static bool is_hdmi2_sink(struct dw_hdmi_qp *hdmi) 533 { 534 return hdmi->edid_data.display_info.hdmi.scdc.supported || 535 hdmi->edid_data.display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; 536 } 537 538 static void hdmi_config_AVI(struct dw_hdmi_qp *hdmi, struct drm_display_mode *mode) 539 { 540 struct hdmi_avi_infoframe frame; 541 u32 val, i, j; 542 u8 buff[17]; 543 bool is_hdmi2 = false; 544 enum hdmi_quantization_range rgb_quant_range = 545 hdmi->hdmi_data.quant_range; 546 547 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) || 548 hdmi->edid_data.display_info.hdmi.scdc.supported) 549 is_hdmi2 = true; 550 /* Initialise info frame from DRM mode */ 551 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2); 552 553 /* 554 * Ignore monitor selectable quantization, use quantization set 555 * by the user 556 */ 557 drm_hdmi_avi_infoframe_quant_range(&frame, mode, rgb_quant_range, 558 true); 559 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 560 frame.colorspace = HDMI_COLORSPACE_YUV444; 561 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 562 frame.colorspace = HDMI_COLORSPACE_YUV422; 563 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 564 frame.colorspace = HDMI_COLORSPACE_YUV420; 565 else 566 frame.colorspace = HDMI_COLORSPACE_RGB; 567 568 /* Set up colorimetry and quant range */ 569 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 570 switch (hdmi->hdmi_data.enc_out_encoding) { 571 case V4L2_YCBCR_ENC_601: 572 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 573 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 574 else 575 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 576 frame.extended_colorimetry = 577 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 578 break; 579 case V4L2_YCBCR_ENC_709: 580 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 581 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 582 else 583 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 584 frame.extended_colorimetry = 585 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 586 break; 587 case V4L2_YCBCR_ENC_BT2020: 588 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_BT2020) 589 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 590 else 591 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 592 frame.extended_colorimetry = 593 HDMI_EXTENDED_COLORIMETRY_BT2020; 594 break; 595 default: /* Carries no data */ 596 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 597 frame.extended_colorimetry = 598 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 599 break; 600 } 601 602 frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 603 } else { 604 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_BT2020) { 605 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 606 frame.extended_colorimetry = 607 HDMI_EXTENDED_COLORIMETRY_BT2020; 608 } else { 609 frame.colorimetry = HDMI_COLORIMETRY_NONE; 610 frame.extended_colorimetry = 611 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 612 } 613 614 if (is_hdmi2_sink(hdmi) && 615 frame.quantization_range == HDMI_QUANTIZATION_RANGE_FULL) 616 frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_FULL; 617 else 618 frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 619 } 620 621 frame.scan_mode = HDMI_SCAN_MODE_NONE; 622 623 hdmi_avi_infoframe_pack_only(&frame, buff, 17); 624 625 /* mode which vic >= 128 must use avi version 3 */ 626 if (hdmi->vic >= 128) { 627 frame.version = 3; 628 buff[1] = frame.version; 629 buff[4] &= 0x1f; 630 buff[4] |= ((frame.colorspace & 0x7) << 5); 631 buff[7] = hdmi->vic; 632 hdmi_infoframe_set_checksum(buff, 17); 633 } 634 635 /* 636 * The Designware IP uses a different byte format from standard 637 * AVI info frames, though generally the bits are in the correct 638 * bytes. 639 */ 640 641 val = (frame.version << 8) | (frame.length << 16); 642 hdmi_writel(hdmi, val, PKT_AVI_CONTENTS0); 643 644 for (i = 0; i < 4; i++) { 645 for (j = 0; j < 4; j++) { 646 if (i * 4 + j >= 14) 647 break; 648 if (!j) 649 val = buff[i * 4 + j + 3]; 650 val |= buff[i * 4 + j + 3] << (8 * j); 651 } 652 653 hdmi_writel(hdmi, val, PKT_AVI_CONTENTS1 + i * 4); 654 } 655 656 hdmi_modb(hdmi, 0, PKTSCHED_AVI_FIELDRATE, PKTSCHED_PKT_CONFIG1); 657 658 hdmi_modb(hdmi, PKTSCHED_AVI_TX_EN, PKTSCHED_AVI_TX_EN, 659 PKTSCHED_PKT_EN); 660 } 661 662 #define VSI_PKT_TYPE 0x81 663 #define VSI_PKT_VERSION 1 664 #define HDMI_FORUM_OUI 0xc45dd8 665 #define ALLM_MODE BIT(1) 666 #define HDMI_FORUM_LEN 9 667 668 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi_qp *hdmi, 669 struct drm_display_mode *mode) 670 { 671 struct hdmi_vendor_infoframe frame; 672 struct dw_hdmi_link_config *link_cfg = NULL; 673 u8 buffer[10]; 674 u32 val; 675 ssize_t err; 676 int i, reg; 677 678 link_cfg = dw_hdmi_rockchip_get_link_cfg(hdmi->rk_hdmi); 679 680 hdmi_modb(hdmi, 0, PKTSCHED_VSI_TX_EN, PKTSCHED_PKT_EN); 681 682 for (i = 0; i <= 7; i++) 683 hdmi_writel(hdmi, 0, PKT_VSI_CONTENTS0 + i * 4); 684 685 if (link_cfg->allm_en) { 686 buffer[0] = VSI_PKT_TYPE; 687 buffer[1] = VSI_PKT_VERSION; 688 buffer[2] = 5; 689 buffer[4] = HDMI_FORUM_OUI & 0xff; 690 buffer[5] = (HDMI_FORUM_OUI >> 8) & 0xff; 691 buffer[6] = (HDMI_FORUM_OUI >> 16) & 0xff; 692 buffer[7] = VSI_PKT_VERSION; 693 buffer[8] = ALLM_MODE; 694 695 hdmi_infoframe_set_checksum(buffer, HDMI_FORUM_LEN); 696 697 err = 9; 698 } else { 699 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode); 700 if (err < 0) 701 /* 702 * Going into that statement does not means vendor infoframe 703 * fails. It just informed us that vendor infoframe is not 704 * needed for the selected mode. Only 4k or stereoscopic 3D 705 * mode requires vendor infoframe. So just simply return. 706 */ 707 return; 708 709 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 710 if (err < 0) { 711 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 712 err); 713 return; 714 } 715 } 716 717 /* vsi header */ 718 val = (buffer[2] << 16) | (buffer[1] << 8) | buffer[0]; 719 hdmi_writel(hdmi, val, PKT_VSI_CONTENTS0); 720 721 reg = PKT_VSI_CONTENTS1; 722 for (i = 3; i < err; i++) { 723 if (i % 4 == 3) 724 val = buffer[i]; 725 if (i % 4 == 0) 726 val |= buffer[i] << 8; 727 if (i % 4 == 1) 728 val |= buffer[i] << 16; 729 if (i % 4 == 2) 730 val |= buffer[i] << 24; 731 732 if ((i % 4 == 2) || (i == (err - 1))) { 733 hdmi_writel(hdmi, val, reg); 734 reg += 4; 735 } 736 } 737 738 hdmi_writel(hdmi, 0, PKT_VSI_CONTENTS7); 739 740 hdmi_modb(hdmi, 0, PKTSCHED_VSI_FIELDRATE, PKTSCHED_PKT_CONFIG1); 741 hdmi_modb(hdmi, PKTSCHED_VSI_TX_EN, PKTSCHED_VSI_TX_EN, 742 PKTSCHED_PKT_EN); 743 } 744 745 static void hdmi_config_CVTEM(struct dw_hdmi_qp *hdmi, 746 struct dw_hdmi_link_config *link_cfg) 747 { 748 u8 ds_type = 0; 749 u8 sync = 1; 750 u8 vfr = 1; 751 u8 afr = 0; 752 u8 new = 1; 753 u8 end = 0; 754 u8 data_set_length = 136; 755 u8 hb1[6] = { 0x80, 0, 0, 0, 0, 0x40 }; 756 u8 *pps_body; 757 u32 val, i, reg; 758 struct drm_display_mode *mode = &hdmi->previous_mode; 759 int hsync, hfront, hback; 760 761 hdmi_modb(hdmi, 0, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_PKT_EN); 762 763 if (!link_cfg->dsc_mode) { 764 printf("don't use dsc mode\n"); 765 return; 766 } 767 768 pps_body = link_cfg->pps_payload; 769 770 hsync = mode->hsync_end - mode->hsync_start; 771 hback = mode->htotal - mode->hsync_end; 772 hfront = mode->hsync_start - mode->hdisplay; 773 774 for (i = 0; i < 6; i++) { 775 val = i << 16 | hb1[i] << 8; 776 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS0 + i * 0x20); 777 } 778 779 val = new << 7 | end << 6 | ds_type << 4 | afr << 3 | 780 vfr << 2 | sync << 1; 781 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS1); 782 783 val = data_set_length << 16 | pps_body[0] << 24; 784 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS2); 785 786 reg = PKT0_EMP_CVTEM_CONTENTS3; 787 for (i = 1; i < 125; i++) { 788 if (reg == PKT1_EMP_CVTEM_CONTENTS0 || 789 reg == PKT2_EMP_CVTEM_CONTENTS0 || 790 reg == PKT3_EMP_CVTEM_CONTENTS0 || 791 reg == PKT4_EMP_CVTEM_CONTENTS0 || 792 reg == PKT5_EMP_CVTEM_CONTENTS0) { 793 reg += 4; 794 i--; 795 continue; 796 } 797 if (i % 4 == 1) 798 val = pps_body[i]; 799 if (i % 4 == 2) 800 val |= pps_body[i] << 8; 801 if (i % 4 == 3) 802 val |= pps_body[i] << 16; 803 if (!(i % 4)) { 804 val |= pps_body[i] << 24; 805 hdmi_writel(hdmi, val, reg); 806 reg += 4; 807 } 808 } 809 810 val = (hfront & 0xff) << 24 | pps_body[127] << 16 | 811 pps_body[126] << 8 | pps_body[125]; 812 hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS6); 813 814 val = (hback & 0xff) << 24 | ((hsync >> 8) & 0xff) << 16 | 815 (hsync & 0xff) << 8 | ((hfront >> 8) & 0xff); 816 hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS7); 817 818 val = link_cfg->hcactive << 8 | ((hback >> 8) & 0xff); 819 hdmi_writel(hdmi, val, PKT5_EMP_CVTEM_CONTENTS1); 820 821 for (i = PKT5_EMP_CVTEM_CONTENTS2; i <= PKT5_EMP_CVTEM_CONTENTS7; i += 4) 822 hdmi_writel(hdmi, 0, i); 823 824 hdmi_modb(hdmi, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_EMP_CVTEM_TX_EN, 825 PKTSCHED_PKT_EN); 826 } 827 828 static int hdmi_set_frl_mask(int frl_rate) 829 { 830 switch (frl_rate) { 831 case 48: 832 return FRL_12GBPS_4LANE; 833 case 40: 834 return FRL_10GBPS_4LANE; 835 case 32: 836 return FRL_8GBPS_4LANE; 837 case 24: 838 return FRL_6GBPS_4LANE; 839 case 18: 840 return FRL_6GBPS_3LANE; 841 case 9: 842 return FRL_3GBPS_3LANE; 843 } 844 845 return 0; 846 } 847 848 static int hdmi_start_flt(struct dw_hdmi_qp *hdmi, u8 rate) 849 { 850 u8 val; 851 u32 value; 852 u8 ffe_lv = 0; 853 int i = 0; 854 bool ltsp = false; 855 856 hdmi_modb(hdmi, AVP_DATAPATH_VIDEO_SWDISABLE, 857 AVP_DATAPATH_VIDEO_SWDISABLE, GLOBAL_SWDISABLE); 858 859 hdmi_writel(hdmi, AVP_DATAPATH_SWINIT_P, GLOBAL_SWRESET_REQUEST); 860 861 /* clear flt flags */ 862 drm_scdc_writeb(&hdmi->adap, 0x10, 0xff); 863 864 /* FLT_READY & FFE_LEVELS read */ 865 for (i = 0; i < 20; i++) { 866 drm_scdc_readb(&hdmi->adap, SCDC_STATUS_FLAGS_0, &val); 867 if (val & BIT(6)) 868 break; 869 mdelay(20); 870 } 871 872 if (i == 20) { 873 printf("sink flt isn't ready\n"); 874 return -EINVAL; 875 } 876 877 /* max ffe level 3 */ 878 val = 0 << 4 | hdmi_set_frl_mask(rate); 879 drm_scdc_writeb(&hdmi->adap, 0x31, val); 880 /* select FRL_RATE & FFE_LEVELS */ 881 hdmi_writel(hdmi, ffe_lv, FLT_CONFIG0); 882 883 i = 500; 884 while (i--) { 885 mdelay(4); 886 drm_scdc_readb(&hdmi->adap, 0x10, &val); 887 888 if (!(val & 0x30)) 889 continue; 890 891 if (val & BIT(5)) { 892 u8 reg_val, ln0, ln1, ln2, ln3; 893 894 drm_scdc_readb(&hdmi->adap, 0x41, ®_val); 895 ln0 = reg_val & 0xf; 896 ln1 = (reg_val >> 4) & 0xf; 897 898 drm_scdc_readb(&hdmi->adap, 0x42, ®_val); 899 ln2 = reg_val & 0xf; 900 ln3 = (reg_val >> 4) & 0xf; 901 902 if (!ln0 && !ln1 && !ln2 && !ln3) { 903 printf("goto ltsp\n"); 904 ltsp = true; 905 hdmi_writel(hdmi, 0, FLT_CONFIG1); 906 } else if ((ln0 == 0xf) | (ln1 == 0xf) | (ln2 == 0xf) | (ln3 == 0xf)) { 907 printf("goto lts4\n"); 908 break; 909 } else if ((ln0 == 0xe) | (ln1 == 0xe) | (ln2 == 0xe) | (ln3 == 0xe)) { 910 printf("goto ffe\n"); 911 break; 912 } else { 913 value = (ln3 << 16) | (ln2 << 12) | (ln1 << 8) | (ln0 << 4) | 0xf; 914 hdmi_writel(hdmi, value, FLT_CONFIG1); 915 } 916 } 917 918 drm_scdc_writeb(&hdmi->adap, 0x10, val); 919 920 if ((val & BIT(4)) && ltsp) { 921 hdmi_modb(hdmi, 0, AVP_DATAPATH_VIDEO_SWDISABLE, GLOBAL_SWDISABLE); 922 printf("flt success\n"); 923 break; 924 } 925 } 926 927 if (i < 0) { 928 printf("flt time out\n"); 929 return -ETIMEDOUT; 930 } 931 932 return 0; 933 } 934 935 #define HDMI_MODE_FRL_MASK BIT(30) 936 937 static void hdmi_set_op_mode(struct dw_hdmi_qp *hdmi, 938 struct dw_hdmi_link_config *link_cfg, 939 struct display_state *state, 940 struct rockchip_connector *conn) 941 { 942 int frl_rate; 943 int i, ret; 944 945 if (!link_cfg->frl_mode) { 946 printf("dw hdmi qp use tmds mode\n"); 947 hdmi_modb(hdmi, 0, OPMODE_FRL, LINK_CONFIG0); 948 hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0); 949 hdmi->phy.ops->init(conn, hdmi->rk_hdmi, state); 950 hdmi->phy.enabled = true; 951 return; 952 } 953 954 if (link_cfg->frl_lanes == 4) 955 hdmi_modb(hdmi, OPMODE_FRL_4LANES, OPMODE_FRL_4LANES, 956 LINK_CONFIG0); 957 else 958 hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0); 959 960 hdmi_modb(hdmi, 1, OPMODE_FRL, LINK_CONFIG0); 961 962 frl_rate = link_cfg->frl_lanes * link_cfg->rate_per_lane; 963 hdmi->phy.ops->init(conn, hdmi->rk_hdmi, state); 964 hdmi->phy.enabled = true; 965 966 mdelay(200); 967 ret = hdmi_start_flt(hdmi, frl_rate); 968 if (ret) { 969 hdmi_writel(hdmi, 0, FLT_CONFIG0); 970 drm_scdc_writeb(&hdmi->adap, 0x31, 0); 971 hdmi_modb(hdmi, 0, AVP_DATAPATH_VIDEO_SWDISABLE, GLOBAL_SWDISABLE); 972 return; 973 } 974 975 for (i = 0; i < 200; i++) { 976 hdmi_modb(hdmi, PKTSCHED_NULL_TX_EN, PKTSCHED_NULL_TX_EN, PKTSCHED_PKT_EN); 977 udelay(50); 978 hdmi_modb(hdmi, 0, PKTSCHED_NULL_TX_EN, PKTSCHED_PKT_EN); 979 udelay(50); 980 } 981 } 982 983 static int dw_hdmi_setup(struct dw_hdmi_qp *hdmi, 984 struct rockchip_connector *conn, 985 struct drm_display_mode *mode, 986 struct display_state *state) 987 { 988 int ret; 989 void *data = hdmi->plat_data->phy_data; 990 struct dw_hdmi_link_config *link_cfg; 991 struct drm_hdmi_info *hdmi_info = &hdmi->edid_data.display_info.hdmi; 992 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 993 u8 bytes = 0; 994 995 if (!hdmi->vic) 996 printf("Non-CEA mode used in HDMI\n"); 997 else 998 printf("CEA mode used vic=%d\n", hdmi->vic); 999 1000 vmode->mpixelclock = mode->clock * 1000; 1001 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock); 1002 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1003 vmode->mtmdsclock /= 2; 1004 printf("mtmdsclock:%d\n", vmode->mtmdsclock); 1005 1006 if (hdmi->plat_data->get_enc_out_encoding) 1007 hdmi->hdmi_data.enc_out_encoding = 1008 hdmi->plat_data->get_enc_out_encoding(data); 1009 else if (hdmi->vic == 6 || hdmi->vic == 7 || 1010 hdmi->vic == 21 || hdmi->vic == 22 || 1011 hdmi->vic == 2 || hdmi->vic == 3 || 1012 hdmi->vic == 17 || hdmi->vic == 18) 1013 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 1014 else 1015 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 1016 1017 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1018 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1; 1019 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1; 1020 } else { 1021 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 1022 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 1023 } 1024 1025 /* TOFIX: Get input encoding from plat data or fallback to none */ 1026 if (hdmi->plat_data->get_enc_in_encoding) 1027 hdmi->hdmi_data.enc_in_encoding = 1028 hdmi->plat_data->get_enc_in_encoding(data); 1029 else if (hdmi->plat_data->input_bus_encoding) 1030 hdmi->hdmi_data.enc_in_encoding = 1031 hdmi->plat_data->input_bus_encoding; 1032 else 1033 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 1034 1035 if (hdmi->plat_data->get_quant_range) 1036 hdmi->hdmi_data.quant_range = 1037 hdmi->plat_data->get_quant_range(data); 1038 else 1039 hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 1040 1041 /* 1042 * According to the dw-hdmi specification 6.4.2 1043 * vp_pr_cd[3:0]: 1044 * 0000b: No pixel repetition (pixel sent only once) 1045 * 0001b: Pixel sent two times (pixel repeated once) 1046 */ 1047 hdmi->hdmi_data.pix_repet_factor = 1048 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0; 1049 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 1050 1051 /* HDMI Initialization Step B.2 */ 1052 hdmi->phy.ops->set_pll(conn, hdmi->rk_hdmi, state); 1053 1054 /* Mark yuv422 10bit */ 1055 if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_YUYV10_1X20) 1056 hdmi_writel(hdmi, BIT(20), VIDEO_INTERFACE_CONFIG0); 1057 rk3588_set_grf_cfg(hdmi->rk_hdmi); 1058 link_cfg = dw_hdmi_rockchip_get_link_cfg(hdmi->rk_hdmi); 1059 1060 /* not for DVI mode */ 1061 if (hdmi->sink_is_hdmi) { 1062 printf("%s HDMI mode\n", __func__); 1063 hdmi_modb(hdmi, 0, OPMODE_DVI, LINK_CONFIG0); 1064 hdmi_modb(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0); 1065 hdmi_modb(hdmi, KEEPOUT_REKEY_ALWAYS, KEEPOUT_REKEY_CFG, FRAME_COMPOSER_CONFIG9); 1066 hdmi_writel(hdmi, 0, FLT_CONFIG0); 1067 if (hdmi_info->scdc.supported) 1068 drm_scdc_writeb(&hdmi->adap, 0x31, 0); 1069 if (!link_cfg->frl_mode) { 1070 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK) { 1071 drm_scdc_readb(&hdmi->adap, SCDC_SINK_VERSION, &bytes); 1072 drm_scdc_writeb(&hdmi->adap, SCDC_SOURCE_VERSION, 1073 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); 1074 drm_scdc_set_high_tmds_clock_ratio(&hdmi->adap, 1); 1075 drm_scdc_set_scrambling(&hdmi->adap, 1); 1076 hdmi_writel(hdmi, 1, SCRAMB_CONFIG0); 1077 mdelay(100); 1078 } else { 1079 if (hdmi_info->scdc.supported) { 1080 drm_scdc_set_high_tmds_clock_ratio(&hdmi->adap, 0); 1081 drm_scdc_set_scrambling(&hdmi->adap, 0); 1082 } 1083 hdmi_writel(hdmi, 0, SCRAMB_CONFIG0); 1084 } 1085 } 1086 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 1087 hdmi_config_AVI(hdmi, mode); 1088 hdmi_config_vendor_specific_infoframe(hdmi, mode); 1089 hdmi_config_CVTEM(hdmi, link_cfg); 1090 hdmi_set_op_mode(hdmi, link_cfg, state, conn); 1091 /* clear avmute */ 1092 mdelay(50); 1093 hdmi_writel(hdmi, 2, PKTSCHED_PKT_CONTROL0); 1094 hdmi_modb(hdmi, PKTSCHED_GCP_TX_EN, PKTSCHED_GCP_TX_EN, 1095 PKTSCHED_PKT_EN); 1096 } else { 1097 hdmi_modb(hdmi, OPMODE_DVI, OPMODE_DVI, LINK_CONFIG0); 1098 ret = hdmi->phy.ops->init(conn, hdmi->rk_hdmi, state); 1099 if (ret) 1100 return ret; 1101 hdmi->phy.enabled = true; 1102 printf("%s DVI mode\n", __func__); 1103 } 1104 1105 /* Mark uboot hdmi is enabled */ 1106 hdmi_writel(hdmi, BIT(21), VIDEO_INTERFACE_CONFIG0); 1107 1108 return 0; 1109 } 1110 1111 int dw_hdmi_detect_hotplug(struct dw_hdmi_qp *hdmi, 1112 struct display_state *state) 1113 { 1114 struct connector_state *conn_state = &state->conn_state; 1115 struct rockchip_connector *conn = conn_state->connector; 1116 int ret; 1117 1118 ret = hdmi->phy.ops->read_hpd(hdmi->rk_hdmi); 1119 if (!ret) { 1120 if (conn->bridge) 1121 ret = rockchip_bridge_detect(conn->bridge); 1122 } 1123 1124 if (ret || state->force_output) { 1125 if (!hdmi->id) 1126 conn_state->output_if |= VOP_OUTPUT_IF_HDMI0; 1127 else 1128 conn_state->output_if |= VOP_OUTPUT_IF_HDMI1; 1129 } 1130 1131 return ret; 1132 } 1133 1134 int rockchip_dw_hdmi_qp_init(struct rockchip_connector *conn, struct display_state *state) 1135 { 1136 struct connector_state *conn_state = &state->conn_state; 1137 const struct dw_hdmi_plat_data *pdata = 1138 (const struct dw_hdmi_plat_data *)dev_get_driver_data(conn->dev); 1139 void *rk_hdmi = dev_get_priv(conn->dev); 1140 struct dw_hdmi_qp *hdmi; 1141 struct drm_display_mode *mode_buf; 1142 ofnode hdmi_node = conn->dev->node; 1143 struct device_node *ddc_node; 1144 1145 hdmi = malloc(sizeof(struct dw_hdmi_qp)); 1146 if (!hdmi) 1147 return -ENOMEM; 1148 1149 memset(hdmi, 0, sizeof(struct dw_hdmi_qp)); 1150 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 1151 if (!mode_buf) 1152 return -ENOMEM; 1153 1154 hdmi->rk_hdmi = rk_hdmi; 1155 hdmi->id = of_alias_get_id(ofnode_to_np(hdmi_node), "hdmi"); 1156 if (hdmi->id < 0) 1157 hdmi->id = 0; 1158 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, hdmi->id); 1159 1160 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 1161 1162 hdmi->regs = dev_read_addr_ptr(conn->dev); 1163 1164 ddc_node = of_parse_phandle(ofnode_to_np(hdmi_node), "ddc-i2c-bus", 0); 1165 if (ddc_node) { 1166 uclass_get_device_by_ofnode(UCLASS_I2C, np_to_ofnode(ddc_node), 1167 &hdmi->adap.i2c_bus); 1168 if (hdmi->adap.i2c_bus) 1169 hdmi->adap.ops = i2c_get_ops(hdmi->adap.i2c_bus); 1170 } 1171 1172 hdmi->i2c = malloc(sizeof(struct dw_hdmi_i2c)); 1173 if (!hdmi->i2c) 1174 return -ENOMEM; 1175 hdmi->adap.ddc_xfer = dw_hdmi_i2c_xfer; 1176 1177 /* 1178 * Read high and low time from device tree. If not available use 1179 * the default timing scl clock rate is about 99.6KHz. 1180 */ 1181 hdmi->i2c->scl_high_ns = 1182 ofnode_read_s32_default(hdmi_node, 1183 "ddc-i2c-scl-high-time-ns", 4708); 1184 hdmi->i2c->scl_low_ns = 1185 ofnode_read_s32_default(hdmi_node, 1186 "ddc-i2c-scl-low-time-ns", 4916); 1187 1188 dw_hdmi_i2c_init(hdmi); 1189 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1190 1191 hdmi->dev_type = pdata->dev_type; 1192 hdmi->plat_data = pdata; 1193 hdmi->edid_data.mode_buf = mode_buf; 1194 1195 conn->data = hdmi; 1196 1197 dw_hdmi_detect_phy(hdmi); 1198 hdmi_writel(hdmi, 0, MAINUNIT_0_INT_MASK_N); 1199 hdmi_writel(hdmi, 0, MAINUNIT_1_INT_MASK_N); 1200 hdmi_writel(hdmi, 428571429, TIMER_BASE_CONFIG0); 1201 1202 dw_hdmi_qp_set_iomux(hdmi->rk_hdmi); 1203 1204 return 0; 1205 } 1206 1207 void rockchip_dw_hdmi_qp_deinit(struct rockchip_connector *conn, struct display_state *state) 1208 { 1209 struct dw_hdmi_qp *hdmi = conn->data; 1210 1211 if (hdmi->i2c) 1212 free(hdmi->i2c); 1213 if (hdmi->edid_data.mode_buf) 1214 free(hdmi->edid_data.mode_buf); 1215 if (hdmi) 1216 free(hdmi); 1217 } 1218 1219 static void rockchip_dw_hdmi_qp_config_output(struct rockchip_connector *conn, 1220 struct display_state *state) 1221 { 1222 struct connector_state *conn_state = &state->conn_state; 1223 struct drm_display_mode *mode = &conn_state->mode; 1224 struct dw_hdmi_qp *hdmi = conn->data; 1225 unsigned int bus_format; 1226 unsigned long enc_out_encoding; 1227 struct overscan *overscan = &conn_state->overscan; 1228 1229 dw_hdmi_qp_selete_output(&hdmi->edid_data, conn, &bus_format, 1230 overscan, hdmi->dev_type, 1231 hdmi->output_bus_format_rgb, hdmi->rk_hdmi, 1232 state); 1233 1234 *mode = *hdmi->edid_data.preferred_mode; 1235 hdmi->vic = drm_match_cea_mode(mode); 1236 1237 printf("mode:%dx%d bus_format:0x%x\n", mode->hdisplay, mode->vdisplay, bus_format); 1238 conn_state->bus_format = bus_format; 1239 hdmi->hdmi_data.enc_in_bus_format = bus_format; 1240 hdmi->hdmi_data.enc_out_bus_format = bus_format; 1241 1242 switch (bus_format) { 1243 case MEDIA_BUS_FMT_YUYV10_1X20: 1244 conn_state->bus_format = MEDIA_BUS_FMT_YUYV10_1X20; 1245 hdmi->hdmi_data.enc_in_bus_format = 1246 MEDIA_BUS_FMT_YUYV10_1X20; 1247 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV422; 1248 break; 1249 case MEDIA_BUS_FMT_YUYV8_1X16: 1250 conn_state->bus_format = MEDIA_BUS_FMT_YUYV8_1X16; 1251 hdmi->hdmi_data.enc_in_bus_format = 1252 MEDIA_BUS_FMT_YUYV8_1X16; 1253 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV422; 1254 break; 1255 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1256 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1257 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420; 1258 break; 1259 } 1260 1261 if (hdmi->vic == 6 || hdmi->vic == 7 || hdmi->vic == 21 || 1262 hdmi->vic == 22 || hdmi->vic == 2 || hdmi->vic == 3 || 1263 hdmi->vic == 17 || hdmi->vic == 18) 1264 enc_out_encoding = V4L2_YCBCR_ENC_601; 1265 else 1266 enc_out_encoding = V4L2_YCBCR_ENC_709; 1267 1268 if (enc_out_encoding == V4L2_YCBCR_ENC_BT2020) 1269 conn_state->color_space = V4L2_COLORSPACE_BT2020; 1270 else if (bus_format == MEDIA_BUS_FMT_RGB888_1X24 || 1271 bus_format == MEDIA_BUS_FMT_RGB101010_1X30) 1272 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 1273 else if (enc_out_encoding == V4L2_YCBCR_ENC_709) 1274 conn_state->color_space = V4L2_COLORSPACE_REC709; 1275 else 1276 conn_state->color_space = V4L2_COLORSPACE_SMPTE170M; 1277 } 1278 1279 int rockchip_dw_hdmi_qp_prepare(struct rockchip_connector *conn, struct display_state *state) 1280 { 1281 struct connector_state *conn_state = &state->conn_state; 1282 struct drm_display_mode *mode = &conn_state->mode; 1283 struct dw_hdmi_qp *hdmi = conn->data; 1284 1285 if (!hdmi->edid_data.preferred_mode && conn->bridge) { 1286 drm_add_hdmi_modes(&hdmi->edid_data, mode); 1287 drm_mode_sort(&hdmi->edid_data); 1288 hdmi->sink_is_hdmi = true; 1289 hdmi->sink_has_audio = true; 1290 rockchip_dw_hdmi_qp_config_output(conn, state); 1291 } 1292 1293 return 0; 1294 } 1295 1296 int rockchip_dw_hdmi_qp_check(struct rockchip_connector *conn, struct display_state *state) 1297 { 1298 struct crtc_state *cstate = &state->crtc_state; 1299 struct rockchip_crtc *crtc = cstate->crtc; 1300 struct dw_hdmi_qp *hdmi = conn->data; 1301 1302 /* clear hdmi uboot logo on flag */ 1303 if (crtc->splice_mode && cstate->crtc_id == 1) 1304 hdmi_writel(hdmi, 0, I2CM_INTERFACE_CONTROL0); 1305 1306 return 0; 1307 } 1308 1309 static void dw_hdmi_disable(struct rockchip_connector *conn, struct dw_hdmi_qp *hdmi, 1310 struct display_state *state) 1311 { 1312 if (hdmi->phy.enabled) { 1313 hdmi->phy.ops->disable(conn, hdmi->rk_hdmi, state); 1314 hdmi->phy.enabled = false; 1315 } 1316 } 1317 1318 int rockchip_dw_hdmi_qp_enable(struct rockchip_connector *conn, struct display_state *state) 1319 { 1320 struct connector_state *conn_state = &state->conn_state; 1321 struct drm_display_mode *mode = &conn_state->mode; 1322 struct dw_hdmi_qp *hdmi = conn->data; 1323 1324 if (!hdmi) 1325 return -EFAULT; 1326 1327 /* Store the display mode for plugin/DKMS poweron events */ 1328 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 1329 1330 dw_hdmi_setup(hdmi, conn, mode, state); 1331 1332 return 0; 1333 } 1334 1335 int rockchip_dw_hdmi_qp_disable(struct rockchip_connector *conn, struct display_state *state) 1336 { 1337 struct dw_hdmi_qp *hdmi = conn->data; 1338 1339 dw_hdmi_disable(conn, hdmi, state); 1340 return 0; 1341 } 1342 1343 static void rockchip_dw_hdmi_qp_mode_valid(struct dw_hdmi_qp *hdmi) 1344 { 1345 struct hdmi_edid_data *edid_data = &hdmi->edid_data; 1346 int i; 1347 bool enable_gpio = dw_hdmi_qp_check_enable_gpio(hdmi->rk_hdmi); 1348 1349 for (i = 0; i < edid_data->modes; i++) { 1350 if (edid_data->mode_buf[i].invalid) 1351 continue; 1352 1353 if (edid_data->mode_buf[i].clock <= 25000) 1354 edid_data->mode_buf[i].invalid = true; 1355 1356 if (edid_data->mode_buf[i].clock > 600000 && !enable_gpio) 1357 edid_data->mode_buf[i].invalid = true; 1358 } 1359 } 1360 1361 static int _rockchip_dw_hdmi_qp_get_timing(struct rockchip_connector *conn, 1362 struct display_state *state, int edid_status) 1363 { 1364 int i; 1365 struct connector_state *conn_state = &state->conn_state; 1366 struct dw_hdmi_qp *hdmi = conn->data; 1367 struct edid *edid = (struct edid *)conn_state->edid; 1368 const u8 def_modes_vic[6] = {4, 16, 2, 17, 31, 19}; 1369 1370 if (!hdmi) 1371 return -EFAULT; 1372 1373 if (!edid_status) { 1374 hdmi->sink_is_hdmi = 1375 drm_detect_hdmi_monitor(edid); 1376 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 1377 edid_status = drm_add_edid_modes(&hdmi->edid_data, conn_state->edid); 1378 } 1379 if (edid_status < 0) { 1380 hdmi->sink_is_hdmi = true; 1381 hdmi->sink_has_audio = true; 1382 do_cea_modes(&hdmi->edid_data, def_modes_vic, 1383 sizeof(def_modes_vic)); 1384 hdmi->edid_data.preferred_mode = &hdmi->edid_data.mode_buf[0]; 1385 printf("failed to get edid\n"); 1386 } 1387 drm_rk_filter_whitelist(&hdmi->edid_data); 1388 rockchip_dw_hdmi_qp_mode_valid(hdmi); 1389 drm_mode_max_resolution_filter(&hdmi->edid_data, 1390 &state->crtc_state.max_output); 1391 if (!drm_mode_prune_invalid(&hdmi->edid_data)) { 1392 printf("can't find valid hdmi mode\n"); 1393 return -EINVAL; 1394 } 1395 1396 for (i = 0; i < hdmi->edid_data.modes; i++) 1397 hdmi->edid_data.mode_buf[i].vrefresh = 1398 drm_mode_vrefresh(&hdmi->edid_data.mode_buf[i]); 1399 1400 drm_mode_sort(&hdmi->edid_data); 1401 1402 rockchip_dw_hdmi_qp_config_output(conn, state); 1403 1404 return 0; 1405 } 1406 1407 int rockchip_dw_hdmi_qp_get_timing(struct rockchip_connector *conn, struct display_state *state) 1408 { 1409 struct connector_state *conn_state = &state->conn_state; 1410 struct dw_hdmi_qp *hdmi = conn->data; 1411 int ret; 1412 1413 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 1414 1415 if (conn_state->secondary) 1416 _rockchip_dw_hdmi_qp_get_timing(conn_state->secondary, state, ret); 1417 1418 return _rockchip_dw_hdmi_qp_get_timing(conn, state, ret); 1419 } 1420 1421 1422 int rockchip_dw_hdmi_qp_detect(struct rockchip_connector *conn, struct display_state *state) 1423 { 1424 int ret; 1425 struct dw_hdmi_qp *hdmi = conn->data; 1426 1427 if (!hdmi) 1428 return -EFAULT; 1429 1430 ret = dw_hdmi_detect_hotplug(hdmi, state); 1431 1432 return ret; 1433 } 1434 1435 int rockchip_dw_hdmi_qp_get_edid(struct rockchip_connector *conn, struct display_state *state) 1436 { 1437 int ret; 1438 struct connector_state *conn_state = &state->conn_state; 1439 struct dw_hdmi_qp *hdmi = conn->data; 1440 1441 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 1442 1443 return ret; 1444 } 1445