1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd 4 * Author: Algea Cao <algea.cao@rock-chips.com> 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <syscon.h> 10 #include <asm/arch-rockchip/clock.h> 11 #include <asm/arch/vendor.h> 12 #include <edid.h> 13 #include <dm/device.h> 14 #include <dm/of_access.h> 15 #include <dm/ofnode.h> 16 #include <dm/read.h> 17 #include <linux/hdmi.h> 18 #include <linux/media-bus-format.h> 19 #include <linux/dw_hdmi.h> 20 #include <asm/io.h> 21 #include "rockchip_display.h" 22 #include "rockchip_crtc.h" 23 #include "rockchip_connector.h" 24 #include "dw_hdmi_qp.h" 25 #include "rockchip_phy.h" 26 27 enum frl_mask { 28 FRL_3GBPS_3LANE = 1, 29 FRL_6GBPS_3LANE, 30 FRL_6GBPS_4LANE, 31 FRL_8GBPS_4LANE, 32 FRL_10GBPS_4LANE, 33 FRL_12GBPS_4LANE, 34 }; 35 36 #define DDC_CI_ADDR 0x37 37 #define DDC_SEGMENT_ADDR 0x30 38 39 #define HDMI_EDID_LEN 512 40 41 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ 42 #define SCDC_MIN_SOURCE_VERSION 0x1 43 44 #define HDMI14_MAX_TMDSCLK 340000000 45 46 struct hdmi_vmode { 47 bool mdataenablepolarity; 48 49 unsigned int mpixelclock; 50 unsigned int mpixelrepetitioninput; 51 unsigned int mpixelrepetitionoutput; 52 unsigned int mtmdsclock; 53 }; 54 55 struct hdmi_data_info { 56 unsigned int enc_in_bus_format; 57 unsigned int enc_out_bus_format; 58 unsigned int enc_in_encoding; 59 unsigned int enc_out_encoding; 60 unsigned int quant_range; 61 unsigned int pix_repet_factor; 62 struct hdmi_vmode video_mode; 63 }; 64 65 struct dw_hdmi_phy_data { 66 enum dw_hdmi_phy_type type; 67 const char *name; 68 unsigned int gen; 69 bool has_svsret; 70 int (*configure)(struct dw_hdmi *hdmi, 71 const struct dw_hdmi_plat_data *pdata, 72 unsigned long mpixelclock); 73 }; 74 75 struct dw_hdmi_i2c { 76 u8 slave_reg; 77 bool is_regaddr; 78 bool is_segment; 79 80 unsigned int scl_high_ns; 81 unsigned int scl_low_ns; 82 }; 83 84 struct dw_hdmi_qp { 85 enum dw_hdmi_devtype dev_type; 86 unsigned int version; 87 struct hdmi_data_info hdmi_data; 88 struct hdmi_edid_data edid_data; 89 const struct dw_hdmi_plat_data *plat_data; 90 struct ddc_adapter adap; 91 92 int vic; 93 int id; 94 95 unsigned long bus_format; 96 bool cable_plugin; 97 bool sink_is_hdmi; 98 bool sink_has_audio; 99 void *regs; 100 void *rk_hdmi; 101 struct dw_hdmi_i2c *i2c; 102 103 struct { 104 const struct dw_hdmi_qp_phy_ops *ops; 105 const char *name; 106 void *data; 107 bool enabled; 108 } phy; 109 110 struct drm_display_mode previous_mode; 111 112 unsigned int sample_rate; 113 unsigned int audio_cts; 114 unsigned int audio_n; 115 bool audio_enable; 116 bool scramble_low_rates; 117 118 void (*write)(struct dw_hdmi_qp *hdmi, u32 val, int offset); 119 u8 (*read)(struct dw_hdmi_qp *hdmi, int offset); 120 121 bool hdcp1x_enable; 122 bool output_bus_format_rgb; 123 }; 124 125 static inline void hdmi_writel(struct dw_hdmi_qp *hdmi, u32 val, int offset) 126 { 127 writel(val, hdmi->regs + offset); 128 } 129 130 static inline u32 hdmi_readl(struct dw_hdmi_qp *hdmi, int offset) 131 { 132 return readl(hdmi->regs + offset); 133 } 134 135 static void 136 hdmi_modb(struct dw_hdmi_qp *hdmi, u32 data, u32 mask, unsigned int reg) 137 { 138 u32 val = hdmi_readl(hdmi, reg) & ~mask; 139 140 val |= data & mask; 141 hdmi_writel(hdmi, val, reg); 142 } 143 144 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 145 { 146 switch (bus_format) { 147 case MEDIA_BUS_FMT_RGB888_1X24: 148 case MEDIA_BUS_FMT_RGB101010_1X30: 149 case MEDIA_BUS_FMT_RGB121212_1X36: 150 case MEDIA_BUS_FMT_RGB161616_1X48: 151 return true; 152 153 default: 154 return false; 155 } 156 } 157 158 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 159 { 160 switch (bus_format) { 161 case MEDIA_BUS_FMT_YUV8_1X24: 162 case MEDIA_BUS_FMT_YUV10_1X30: 163 case MEDIA_BUS_FMT_YUV12_1X36: 164 case MEDIA_BUS_FMT_YUV16_1X48: 165 return true; 166 167 default: 168 return false; 169 } 170 } 171 172 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 173 { 174 switch (bus_format) { 175 case MEDIA_BUS_FMT_UYVY8_1X16: 176 case MEDIA_BUS_FMT_UYVY10_1X20: 177 case MEDIA_BUS_FMT_UYVY12_1X24: 178 return true; 179 180 default: 181 return false; 182 } 183 } 184 185 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 186 { 187 switch (bus_format) { 188 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 189 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 190 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 191 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 192 return true; 193 194 default: 195 return false; 196 } 197 } 198 199 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 200 { 201 switch (bus_format) { 202 case MEDIA_BUS_FMT_RGB888_1X24: 203 case MEDIA_BUS_FMT_YUV8_1X24: 204 case MEDIA_BUS_FMT_UYVY8_1X16: 205 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 206 return 8; 207 208 case MEDIA_BUS_FMT_RGB101010_1X30: 209 case MEDIA_BUS_FMT_YUV10_1X30: 210 case MEDIA_BUS_FMT_UYVY10_1X20: 211 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 212 return 10; 213 214 case MEDIA_BUS_FMT_RGB121212_1X36: 215 case MEDIA_BUS_FMT_YUV12_1X36: 216 case MEDIA_BUS_FMT_UYVY12_1X24: 217 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 218 return 12; 219 220 case MEDIA_BUS_FMT_RGB161616_1X48: 221 case MEDIA_BUS_FMT_YUV16_1X48: 222 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 223 return 16; 224 225 default: 226 return 0; 227 } 228 } 229 230 static bool drm_scdc_set_scrambling(struct ddc_adapter *adapter, bool enable) 231 { 232 u8 config; 233 int ret; 234 235 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 236 if (ret < 0) { 237 debug("Failed to read TMDS config: %d\n", ret); 238 return false; 239 } 240 241 if (enable) 242 config |= SCDC_SCRAMBLING_ENABLE; 243 else 244 config &= ~SCDC_SCRAMBLING_ENABLE; 245 246 ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config); 247 if (ret < 0) { 248 debug("Failed to enable scrambling: %d\n", ret); 249 return false; 250 } 251 252 return true; 253 } 254 255 static bool 256 drm_scdc_set_high_tmds_clock_ratio(struct ddc_adapter *adapter, bool set) 257 { 258 u8 config; 259 int ret; 260 261 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 262 if (ret < 0) { 263 debug("Failed to read TMDS config: %d\n", ret); 264 return false; 265 } 266 267 if (set) 268 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 269 else 270 config &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 271 272 ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config); 273 if (ret < 0) { 274 debug("Failed to set TMDS clock ratio: %d\n", ret); 275 return false; 276 } 277 278 /* 279 * The spec says that a source should wait minimum 1ms and maximum 280 * 100ms after writing the TMDS config for clock ratio. Lets allow a 281 * wait of up to 2ms here. 282 */ 283 udelay(2000); 284 return true; 285 } 286 287 static void dw_hdmi_i2c_init(struct dw_hdmi_qp *hdmi) 288 { 289 /* Software reset */ 290 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 291 292 hdmi_writel(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0); 293 294 hdmi_modb(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0); 295 296 /* Clear DONE and ERROR interrupts */ 297 hdmi_writel(hdmi, I2CM_OP_DONE_CLEAR | I2CM_NACK_RCVD_CLEAR, 298 MAINUNIT_1_INT_CLEAR); 299 } 300 301 static int dw_hdmi_i2c_read(struct dw_hdmi_qp *hdmi, 302 unsigned char *buf, unsigned int length) 303 { 304 struct dw_hdmi_i2c *i2c = hdmi->i2c; 305 int i = 20; 306 u32 intr = 0; 307 308 if (!i2c->is_regaddr) { 309 printf("set read register address to 0\n"); 310 i2c->slave_reg = 0x00; 311 i2c->is_regaddr = true; 312 } 313 314 while (length--) { 315 hdmi_modb(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, 316 I2CM_INTERFACE_CONTROL0); 317 318 hdmi_modb(hdmi, I2CM_FM_READ, I2CM_WR_MASK, 319 I2CM_INTERFACE_CONTROL0); 320 321 while (i--) { 322 udelay(1000); 323 intr = hdmi_readl(hdmi, MAINUNIT_1_INT_STATUS) & 324 (I2CM_OP_DONE_IRQ | I2CM_READ_REQUEST_IRQ | 325 I2CM_NACK_RCVD_IRQ); 326 if (intr) { 327 hdmi_writel(hdmi, intr, MAINUNIT_1_INT_CLEAR); 328 break; 329 } 330 } 331 332 if (!i) { 333 printf("i2c read time out!\n"); 334 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 335 return -EAGAIN; 336 } 337 338 /* Check for error condition on the bus */ 339 if (intr & I2CM_NACK_RCVD_IRQ) { 340 printf("i2c read err!\n"); 341 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 342 return -EIO; 343 } 344 345 *buf++ = hdmi_readl(hdmi, I2CM_INTERFACE_RDDATA_0_3) & 0xff; 346 hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); 347 i = 20; 348 } 349 i2c->is_segment = false; 350 351 return 0; 352 } 353 354 static int dw_hdmi_i2c_write(struct dw_hdmi_qp *hdmi, 355 unsigned char *buf, unsigned int length) 356 { 357 struct dw_hdmi_i2c *i2c = hdmi->i2c; 358 int i = 20; 359 u32 intr = 0; 360 361 if (!i2c->is_regaddr) { 362 /* Use the first write byte as register address */ 363 i2c->slave_reg = buf[0]; 364 length--; 365 buf++; 366 i2c->is_regaddr = true; 367 } 368 369 while (length--) { 370 hdmi_writel(hdmi, *buf++, I2CM_INTERFACE_WRDATA_0_3); 371 hdmi_modb(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, 372 I2CM_INTERFACE_CONTROL0); 373 hdmi_modb(hdmi, I2CM_FM_WRITE, I2CM_WR_MASK, 374 I2CM_INTERFACE_CONTROL0); 375 376 while (i--) { 377 udelay(1000); 378 intr = hdmi_readl(hdmi, MAINUNIT_1_INT_STATUS) & 379 (I2CM_OP_DONE_IRQ | I2CM_READ_REQUEST_IRQ | 380 I2CM_NACK_RCVD_IRQ); 381 if (intr) { 382 hdmi_writel(hdmi, intr, MAINUNIT_1_INT_CLEAR); 383 break; 384 } 385 } 386 387 if (!i) { 388 printf("i2c write time out!\n"); 389 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 390 return -EAGAIN; 391 } 392 393 /* Check for error condition on the bus */ 394 if (intr & I2CM_NACK_RCVD_IRQ) { 395 printf("i2c write nack!\n"); 396 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 397 return -EIO; 398 } 399 hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); 400 i = 20; 401 } 402 403 return 0; 404 } 405 406 static int dw_hdmi_i2c_xfer(struct ddc_adapter *adap, 407 struct i2c_msg *msgs, int num) 408 { 409 struct dw_hdmi_qp *hdmi = container_of(adap, struct dw_hdmi_qp, adap); 410 struct dw_hdmi_i2c *i2c = hdmi->i2c; 411 u8 addr = msgs[0].addr; 412 int i, ret = 0; 413 414 debug("i2c xfer: num: %d, addr: %#x\n", num, addr); 415 416 for (i = 0; i < num; i++) { 417 if (msgs[i].len == 0) { 418 printf("unsupported transfer %d/%d, no data\n", 419 i + 1, num); 420 return -EOPNOTSUPP; 421 } 422 } 423 424 /* Unmute DONE and ERROR interrupts */ 425 hdmi_modb(hdmi, I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, 426 I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, 427 MAINUNIT_1_INT_MASK_N); 428 429 /* Set slave device address taken from the first I2C message */ 430 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1) 431 addr = DDC_ADDR; 432 433 hdmi_modb(hdmi, addr << 5, I2CM_SLVADDR, I2CM_INTERFACE_CONTROL0); 434 435 /* Set slave device register address on transfer */ 436 i2c->is_regaddr = false; 437 438 /* Set segment pointer for I2C extended read mode operation */ 439 i2c->is_segment = false; 440 441 for (i = 0; i < num; i++) { 442 debug("xfer: num: %d/%d, len: %d, flags: %#x\n", 443 i + 1, num, msgs[i].len, msgs[i].flags); 444 445 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 446 i2c->is_segment = true; 447 hdmi_modb(hdmi, DDC_SEGMENT_ADDR, I2CM_SEG_ADDR, 448 I2CM_INTERFACE_CONTROL1); 449 hdmi_modb(hdmi, *msgs[i].buf, I2CM_SEG_PTR, 450 I2CM_INTERFACE_CONTROL1); 451 } else { 452 if (msgs[i].flags & I2C_M_RD) 453 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 454 msgs[i].len); 455 else 456 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 457 msgs[i].len); 458 } 459 if (ret < 0) 460 break; 461 } 462 463 if (!ret) 464 ret = num; 465 466 /* Mute DONE and ERROR interrupts */ 467 hdmi_modb(hdmi, 0, I2CM_OP_DONE_MASK_N | I2CM_NACK_RCVD_MASK_N, 468 MAINUNIT_1_INT_MASK_N); 469 470 return ret; 471 } 472 473 static int dw_hdmi_detect_phy(struct dw_hdmi_qp *hdmi) 474 { 475 /* Vendor PHYs require support from the glue layer. */ 476 if (!hdmi->plat_data->qp_phy_ops || !hdmi->plat_data->phy_name) { 477 dev_err(hdmi->dev, 478 "Vendor HDMI PHY not supported by glue layer\n"); 479 return -ENODEV; 480 } 481 482 hdmi->phy.ops = hdmi->plat_data->qp_phy_ops; 483 hdmi->phy.data = hdmi->plat_data->phy_data; 484 hdmi->phy.name = hdmi->plat_data->phy_name; 485 486 return 0; 487 } 488 489 static unsigned int 490 hdmi_get_tmdsclock(struct dw_hdmi_qp *hdmi, unsigned long mpixelclock) 491 { 492 unsigned int tmdsclock = mpixelclock; 493 unsigned int depth = 494 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 495 496 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 497 switch (depth) { 498 case 16: 499 tmdsclock = mpixelclock * 2; 500 break; 501 case 12: 502 tmdsclock = mpixelclock * 3 / 2; 503 break; 504 case 10: 505 tmdsclock = mpixelclock * 5 / 4; 506 break; 507 default: 508 break; 509 } 510 } 511 512 return tmdsclock; 513 } 514 515 static void hdmi_infoframe_set_checksum(u8 *ptr, int size) 516 { 517 u8 csum = 0; 518 int i; 519 520 ptr[3] = 0; 521 /* compute checksum */ 522 for (i = 0; i < size; i++) 523 csum += ptr[i]; 524 525 ptr[3] = 256 - csum; 526 } 527 528 static bool is_hdmi2_sink(struct dw_hdmi_qp *hdmi) 529 { 530 return hdmi->edid_data.display_info.hdmi.scdc.supported || 531 hdmi->edid_data.display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; 532 } 533 534 static void hdmi_config_AVI(struct dw_hdmi_qp *hdmi, struct drm_display_mode *mode) 535 { 536 struct hdmi_avi_infoframe frame; 537 u32 val, i, j; 538 u8 buff[17]; 539 bool is_hdmi2 = false; 540 enum hdmi_quantization_range rgb_quant_range = 541 hdmi->hdmi_data.quant_range; 542 543 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) || 544 hdmi->edid_data.display_info.hdmi.scdc.supported) 545 is_hdmi2 = true; 546 /* Initialise info frame from DRM mode */ 547 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2); 548 549 /* 550 * Ignore monitor selectable quantization, use quantization set 551 * by the user 552 */ 553 drm_hdmi_avi_infoframe_quant_range(&frame, mode, rgb_quant_range, 554 true); 555 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 556 frame.colorspace = HDMI_COLORSPACE_YUV444; 557 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 558 frame.colorspace = HDMI_COLORSPACE_YUV422; 559 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 560 frame.colorspace = HDMI_COLORSPACE_YUV420; 561 else 562 frame.colorspace = HDMI_COLORSPACE_RGB; 563 564 /* Set up colorimetry and quant range */ 565 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 566 switch (hdmi->hdmi_data.enc_out_encoding) { 567 case V4L2_YCBCR_ENC_601: 568 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 569 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 570 else 571 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 572 frame.extended_colorimetry = 573 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 574 break; 575 case V4L2_YCBCR_ENC_709: 576 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 577 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 578 else 579 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 580 frame.extended_colorimetry = 581 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 582 break; 583 case V4L2_YCBCR_ENC_BT2020: 584 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_BT2020) 585 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 586 else 587 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 588 frame.extended_colorimetry = 589 HDMI_EXTENDED_COLORIMETRY_BT2020; 590 break; 591 default: /* Carries no data */ 592 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 593 frame.extended_colorimetry = 594 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 595 break; 596 } 597 598 frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 599 } else { 600 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_BT2020) { 601 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 602 frame.extended_colorimetry = 603 HDMI_EXTENDED_COLORIMETRY_BT2020; 604 } else { 605 frame.colorimetry = HDMI_COLORIMETRY_NONE; 606 frame.extended_colorimetry = 607 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 608 } 609 610 if (is_hdmi2_sink(hdmi) && 611 frame.quantization_range == HDMI_QUANTIZATION_RANGE_FULL) 612 frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_FULL; 613 else 614 frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 615 } 616 617 frame.scan_mode = HDMI_SCAN_MODE_NONE; 618 619 hdmi_avi_infoframe_pack_only(&frame, buff, 17); 620 621 /* mode which vic >= 128 must use avi version 3 */ 622 if (hdmi->vic >= 128) { 623 frame.version = 3; 624 buff[1] = frame.version; 625 buff[4] &= 0x1f; 626 buff[4] |= ((frame.colorspace & 0x7) << 5); 627 buff[7] = hdmi->vic; 628 hdmi_infoframe_set_checksum(buff, 17); 629 } 630 631 /* 632 * The Designware IP uses a different byte format from standard 633 * AVI info frames, though generally the bits are in the correct 634 * bytes. 635 */ 636 637 val = (frame.version << 8) | (frame.length << 16); 638 hdmi_writel(hdmi, val, PKT_AVI_CONTENTS0); 639 640 for (i = 0; i < 4; i++) { 641 for (j = 0; j < 4; j++) { 642 if (i * 4 + j >= 14) 643 break; 644 if (!j) 645 val = buff[i * 4 + j + 3]; 646 val |= buff[i * 4 + j + 3] << (8 * j); 647 } 648 649 hdmi_writel(hdmi, val, PKT_AVI_CONTENTS1 + i * 4); 650 } 651 652 hdmi_modb(hdmi, 0, PKTSCHED_AVI_FIELDRATE, PKTSCHED_PKT_CONFIG1); 653 654 hdmi_modb(hdmi, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, 655 PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, 656 PKTSCHED_PKT_EN); 657 } 658 659 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi_qp *hdmi, 660 struct drm_display_mode *mode) 661 { 662 struct hdmi_vendor_infoframe frame; 663 u8 buffer[10]; 664 u32 val; 665 ssize_t err; 666 int i, reg; 667 668 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode); 669 if (err < 0) 670 /* 671 * Going into that statement does not means vendor infoframe 672 * fails. It just informed us that vendor infoframe is not 673 * needed for the selected mode. Only 4k or stereoscopic 3D 674 * mode requires vendor infoframe. So just simply return. 675 */ 676 return; 677 678 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 679 if (err < 0) { 680 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 681 err); 682 return; 683 } 684 685 /* vsi header */ 686 val = (buffer[2] << 16) | (buffer[1] << 8) | buffer[0]; 687 hdmi_writel(hdmi, val, PKT_VSI_CONTENTS0); 688 689 reg = PKT_VSI_CONTENTS1; 690 for (i = 3; i < err; i++) { 691 if (i % 4 == 3) 692 val = buffer[i]; 693 if (i % 4 == 0) 694 val |= buffer[i] << 8; 695 if (i % 4 == 1) 696 val |= buffer[i] << 16; 697 if (i % 4 == 2) 698 val |= buffer[i] << 24; 699 700 if ((i % 4 == 2) || (i == (err - 1))) { 701 hdmi_writel(hdmi, val, reg); 702 reg += 4; 703 } 704 } 705 706 hdmi_writel(hdmi, 0, PKT_VSI_CONTENTS7); 707 hdmi_modb(hdmi, PKTSCHED_VSI_TX_EN, PKTSCHED_VSI_TX_EN, 708 PKTSCHED_PKT_EN); 709 } 710 711 static void hdmi_config_CVTEM(struct dw_hdmi_qp *hdmi, 712 struct dw_hdmi_link_config *link_cfg) 713 { 714 u8 ds_type = 0; 715 u8 sync = 1; 716 u8 vfr = 1; 717 u8 afr = 0; 718 u8 new = 1; 719 u8 end = 0; 720 u8 data_set_length = 136; 721 u8 hb1[6] = { 0x80, 0, 0, 0, 0, 0x40 }; 722 u8 *pps_body; 723 u32 val, i, reg; 724 struct drm_display_mode *mode = &hdmi->previous_mode; 725 int hsync, hfront, hback; 726 727 hdmi_modb(hdmi, 0, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_PKT_EN); 728 729 if (!link_cfg->dsc_mode) { 730 printf("don't use dsc mode\n"); 731 return; 732 } 733 734 pps_body = link_cfg->pps_payload; 735 736 hsync = mode->hsync_end - mode->hsync_start; 737 hback = mode->htotal - mode->hsync_end; 738 hfront = mode->hsync_start - mode->hdisplay; 739 740 for (i = 0; i < 6; i++) { 741 val = i << 16 | hb1[i] << 8; 742 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS0 + i * 0x20); 743 } 744 745 val = new << 7 | end << 6 | ds_type << 4 | afr << 3 | 746 vfr << 2 | sync << 1; 747 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS1); 748 749 val = data_set_length << 16 | pps_body[0] << 24; 750 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS2); 751 752 reg = PKT0_EMP_CVTEM_CONTENTS3; 753 for (i = 1; i < 125; i++) { 754 if (reg == PKT1_EMP_CVTEM_CONTENTS0 || 755 reg == PKT2_EMP_CVTEM_CONTENTS0 || 756 reg == PKT3_EMP_CVTEM_CONTENTS0 || 757 reg == PKT4_EMP_CVTEM_CONTENTS0 || 758 reg == PKT5_EMP_CVTEM_CONTENTS0) { 759 reg += 4; 760 i--; 761 continue; 762 } 763 if (i % 4 == 1) 764 val = pps_body[i]; 765 if (i % 4 == 2) 766 val |= pps_body[i] << 8; 767 if (i % 4 == 3) 768 val |= pps_body[i] << 16; 769 if (!(i % 4)) { 770 val |= pps_body[i] << 24; 771 hdmi_writel(hdmi, val, reg); 772 reg += 4; 773 } 774 } 775 776 val = (hfront & 0xff) << 24 | pps_body[127] << 16 | 777 pps_body[126] << 8 | pps_body[125]; 778 hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS6); 779 780 val = (hback & 0xff) << 24 | ((hsync >> 8) & 0xff) << 16 | 781 (hsync & 0xff) << 8 | ((hfront >> 8) & 0xff); 782 hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS7); 783 784 val = link_cfg->hcactive << 8 | ((hback >> 8) & 0xff); 785 hdmi_writel(hdmi, val, PKT5_EMP_CVTEM_CONTENTS1); 786 787 for (i = PKT5_EMP_CVTEM_CONTENTS2; i <= PKT5_EMP_CVTEM_CONTENTS7; i += 4) 788 hdmi_writel(hdmi, 0, i); 789 790 hdmi_modb(hdmi, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_EMP_CVTEM_TX_EN, 791 PKTSCHED_PKT_EN); 792 } 793 794 static int hdmi_set_frl_mask(int frl_rate) 795 { 796 switch (frl_rate) { 797 case 48: 798 return FRL_12GBPS_4LANE; 799 case 40: 800 return FRL_10GBPS_4LANE; 801 case 32: 802 return FRL_8GBPS_4LANE; 803 case 24: 804 return FRL_6GBPS_4LANE; 805 case 18: 806 return FRL_6GBPS_3LANE; 807 case 9: 808 return FRL_3GBPS_3LANE; 809 } 810 811 return 0; 812 } 813 814 static int hdmi_start_flt(struct dw_hdmi_qp *hdmi, u8 rate) 815 { 816 u8 val; 817 u32 value; 818 u8 ffe_lv = 0; 819 int i = 0; 820 bool ltsp = false; 821 822 hdmi_modb(hdmi, AVP_DATAPATH_VIDEO_SWDISABLE, 823 AVP_DATAPATH_VIDEO_SWDISABLE, GLOBAL_SWDISABLE); 824 825 /* clear flt flags */ 826 drm_scdc_writeb(&hdmi->adap, 0x10, 0xff); 827 828 /* FLT_READY & FFE_LEVELS read */ 829 for (i = 0; i < 20; i++) { 830 drm_scdc_readb(&hdmi->adap, SCDC_STATUS_FLAGS_0, &val); 831 if (val & BIT(6)) 832 break; 833 mdelay(20); 834 } 835 836 if (i == 20) { 837 printf("sink flt isn't ready\n"); 838 return -EINVAL; 839 } 840 841 /* max ffe level 3 */ 842 val = 0 << 4 | hdmi_set_frl_mask(rate); 843 drm_scdc_writeb(&hdmi->adap, 0x31, val); 844 /* select FRL_RATE & FFE_LEVELS */ 845 hdmi_writel(hdmi, ffe_lv, FLT_CONFIG0); 846 847 i = 500; 848 while (i--) { 849 mdelay(4); 850 drm_scdc_readb(&hdmi->adap, 0x10, &val); 851 852 if (!(val & 0x30)) 853 continue; 854 855 if (val & BIT(5)) { 856 u8 reg_val, ln0, ln1, ln2, ln3; 857 858 drm_scdc_readb(&hdmi->adap, 0x41, ®_val); 859 ln0 = reg_val & 0xf; 860 ln1 = (reg_val >> 4) & 0xf; 861 862 drm_scdc_readb(&hdmi->adap, 0x42, ®_val); 863 ln2 = reg_val & 0xf; 864 ln3 = (reg_val >> 4) & 0xf; 865 866 if (!ln0 && !ln1 && !ln2 && !ln3) { 867 printf("goto ltsp\n"); 868 ltsp = true; 869 hdmi_writel(hdmi, 0, FLT_CONFIG1); 870 } else if ((ln0 == 0xf) | (ln1 == 0xf) | (ln2 == 0xf) | (ln3 == 0xf)) { 871 printf("goto lts4\n"); 872 break; 873 } else if ((ln0 == 0xe) | (ln1 == 0xe) | (ln2 == 0xe) | (ln3 == 0xe)) { 874 printf("goto ffe\n"); 875 break; 876 } else { 877 value = (ln3 << 16) | (ln2 << 12) | (ln1 << 8) | (ln0 << 4) | 0xf; 878 hdmi_writel(hdmi, value, FLT_CONFIG1); 879 } 880 } 881 882 drm_scdc_writeb(&hdmi->adap, 0x10, val); 883 884 if ((val & BIT(4)) && ltsp) { 885 hdmi_modb(hdmi, 0, AVP_DATAPATH_VIDEO_SWDISABLE, GLOBAL_SWDISABLE); 886 printf("flt success\n"); 887 break; 888 } 889 } 890 891 if (i < 0) { 892 printf("flt time out\n"); 893 return -ETIMEDOUT; 894 } 895 896 return 0; 897 } 898 899 #define HDMI_MODE_FRL_MASK BIT(30) 900 901 static void hdmi_set_op_mode(struct dw_hdmi_qp *hdmi, 902 struct dw_hdmi_link_config *link_cfg, 903 bool scdc_support) 904 { 905 int frl_rate; 906 int i; 907 908 hdmi_writel(hdmi, 0, FLT_CONFIG0); 909 if (scdc_support) 910 drm_scdc_writeb(&hdmi->adap, 0x31, 0); 911 mdelay(200); 912 if (!link_cfg->frl_mode) { 913 printf("dw hdmi qp use tmds mode\n"); 914 hdmi_modb(hdmi, 0, OPMODE_FRL, LINK_CONFIG0); 915 hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0); 916 return; 917 } 918 919 if (link_cfg->frl_lanes == 4) 920 hdmi_modb(hdmi, OPMODE_FRL_4LANES, OPMODE_FRL_4LANES, 921 LINK_CONFIG0); 922 else 923 hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0); 924 925 hdmi_modb(hdmi, 1, OPMODE_FRL, LINK_CONFIG0); 926 927 frl_rate = link_cfg->frl_lanes * link_cfg->rate_per_lane; 928 hdmi_start_flt(hdmi, frl_rate); 929 930 for (i = 0; i < 200; i++) { 931 hdmi_modb(hdmi, PKTSCHED_NULL_TX_EN, PKTSCHED_NULL_TX_EN, PKTSCHED_PKT_EN); 932 udelay(50); 933 hdmi_modb(hdmi, 0, PKTSCHED_NULL_TX_EN, PKTSCHED_PKT_EN); 934 udelay(50); 935 } 936 } 937 938 static int dw_hdmi_setup(struct dw_hdmi_qp *hdmi, 939 struct drm_display_mode *mode, 940 struct display_state *state) 941 { 942 int ret; 943 void *data = hdmi->plat_data->phy_data; 944 struct dw_hdmi_link_config *link_cfg; 945 struct drm_hdmi_info *hdmi_info = &hdmi->edid_data.display_info.hdmi; 946 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 947 u8 bytes = 0; 948 949 if (!hdmi->vic) 950 printf("Non-CEA mode used in HDMI\n"); 951 else 952 printf("CEA mode used vic=%d\n", hdmi->vic); 953 954 vmode->mpixelclock = mode->clock * 1000; 955 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock); 956 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 957 vmode->mtmdsclock /= 2; 958 printf("mtmdsclock:%d\n", vmode->mtmdsclock); 959 960 if (hdmi->plat_data->get_enc_out_encoding) 961 hdmi->hdmi_data.enc_out_encoding = 962 hdmi->plat_data->get_enc_out_encoding(data); 963 else if (hdmi->vic == 6 || hdmi->vic == 7 || 964 hdmi->vic == 21 || hdmi->vic == 22 || 965 hdmi->vic == 2 || hdmi->vic == 3 || 966 hdmi->vic == 17 || hdmi->vic == 18) 967 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 968 else 969 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 970 971 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 972 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1; 973 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1; 974 } else { 975 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 976 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 977 } 978 979 /* TOFIX: Get input encoding from plat data or fallback to none */ 980 if (hdmi->plat_data->get_enc_in_encoding) 981 hdmi->hdmi_data.enc_in_encoding = 982 hdmi->plat_data->get_enc_in_encoding(data); 983 else if (hdmi->plat_data->input_bus_encoding) 984 hdmi->hdmi_data.enc_in_encoding = 985 hdmi->plat_data->input_bus_encoding; 986 else 987 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 988 989 if (hdmi->plat_data->get_quant_range) 990 hdmi->hdmi_data.quant_range = 991 hdmi->plat_data->get_quant_range(data); 992 else 993 hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 994 995 /* 996 * According to the dw-hdmi specification 6.4.2 997 * vp_pr_cd[3:0]: 998 * 0000b: No pixel repetition (pixel sent only once) 999 * 0001b: Pixel sent two times (pixel repeated once) 1000 */ 1001 hdmi->hdmi_data.pix_repet_factor = 1002 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0; 1003 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 1004 1005 /* HDMI Initialization Step B.2 */ 1006 ret = hdmi->phy.ops->init(hdmi->rk_hdmi, state); 1007 if (ret) 1008 return ret; 1009 hdmi->phy.enabled = true; 1010 1011 rk3588_set_grf_cfg(hdmi->rk_hdmi); 1012 link_cfg = dw_hdmi_rockchip_get_link_cfg(hdmi->rk_hdmi); 1013 1014 /* not for DVI mode */ 1015 if (hdmi->sink_is_hdmi) { 1016 printf("%s HDMI mode\n", __func__); 1017 hdmi_modb(hdmi, 0, OPMODE_DVI, LINK_CONFIG0); 1018 hdmi_modb(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0); 1019 if (!link_cfg->frl_mode) { 1020 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK) { 1021 drm_scdc_readb(&hdmi->adap, SCDC_SINK_VERSION, &bytes); 1022 drm_scdc_writeb(&hdmi->adap, SCDC_SOURCE_VERSION, 1023 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); 1024 drm_scdc_set_high_tmds_clock_ratio(&hdmi->adap, 1); 1025 drm_scdc_set_scrambling(&hdmi->adap, 1); 1026 hdmi_writel(hdmi, 1, SCRAMB_CONFIG0); 1027 } else { 1028 if (hdmi_info->scdc.supported) { 1029 drm_scdc_set_high_tmds_clock_ratio(&hdmi->adap, 0); 1030 drm_scdc_set_scrambling(&hdmi->adap, 0); 1031 } 1032 hdmi_writel(hdmi, 0, SCRAMB_CONFIG0); 1033 } 1034 } 1035 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 1036 hdmi_config_AVI(hdmi, mode); 1037 hdmi_config_vendor_specific_infoframe(hdmi, mode); 1038 hdmi_config_CVTEM(hdmi, link_cfg); 1039 hdmi_set_op_mode(hdmi, link_cfg, hdmi_info->scdc.supported); 1040 } else { 1041 hdmi_modb(hdmi, OPMODE_DVI, OPMODE_DVI, LINK_CONFIG0); 1042 printf("%s DVI mode\n", __func__); 1043 } 1044 1045 return 0; 1046 } 1047 1048 int dw_hdmi_detect_hotplug(struct dw_hdmi_qp *hdmi, 1049 struct display_state *state) 1050 { 1051 struct connector_state *conn_state = &state->conn_state; 1052 int ret; 1053 1054 ret = hdmi->phy.ops->read_hpd(hdmi->rk_hdmi); 1055 if (ret || state->force_output) { 1056 if (!hdmi->id) 1057 conn_state->output_if |= VOP_OUTPUT_IF_HDMI0; 1058 else 1059 conn_state->output_if |= VOP_OUTPUT_IF_HDMI1; 1060 } 1061 1062 return ret; 1063 } 1064 1065 int rockchip_dw_hdmi_qp_pre_init(struct display_state *state) 1066 { 1067 struct connector_state *conn_state = &state->conn_state; 1068 1069 conn_state->type = DRM_MODE_CONNECTOR_HDMIA; 1070 1071 return 0; 1072 } 1073 1074 int rockchip_dw_hdmi_qp_init(struct display_state *state) 1075 { 1076 struct connector_state *conn_state = &state->conn_state; 1077 const struct rockchip_connector *connector = conn_state->connector; 1078 const struct dw_hdmi_plat_data *pdata = connector->data; 1079 void *rk_hdmi = dev_get_priv(conn_state->dev); 1080 struct dw_hdmi_qp *hdmi; 1081 struct drm_display_mode *mode_buf; 1082 ofnode hdmi_node = conn_state->node; 1083 struct device_node *ddc_node; 1084 1085 hdmi = malloc(sizeof(struct dw_hdmi_qp)); 1086 if (!hdmi) 1087 return -ENOMEM; 1088 1089 memset(hdmi, 0, sizeof(struct dw_hdmi_qp)); 1090 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 1091 if (!mode_buf) 1092 return -ENOMEM; 1093 1094 hdmi->rk_hdmi = rk_hdmi; 1095 hdmi->id = of_alias_get_id(ofnode_to_np(hdmi_node), "hdmi"); 1096 if (hdmi->id < 0) 1097 hdmi->id = 0; 1098 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, hdmi->id); 1099 1100 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 1101 1102 hdmi->regs = dev_read_addr_ptr(conn_state->dev); 1103 1104 ddc_node = of_parse_phandle(ofnode_to_np(hdmi_node), "ddc-i2c-bus", 0); 1105 if (ddc_node) { 1106 uclass_get_device_by_ofnode(UCLASS_I2C, np_to_ofnode(ddc_node), 1107 &hdmi->adap.i2c_bus); 1108 if (hdmi->adap.i2c_bus) 1109 hdmi->adap.ops = i2c_get_ops(hdmi->adap.i2c_bus); 1110 } 1111 1112 hdmi->i2c = malloc(sizeof(struct dw_hdmi_i2c)); 1113 if (!hdmi->i2c) 1114 return -ENOMEM; 1115 hdmi->adap.ddc_xfer = dw_hdmi_i2c_xfer; 1116 1117 /* 1118 * Read high and low time from device tree. If not available use 1119 * the default timing scl clock rate is about 99.6KHz. 1120 */ 1121 hdmi->i2c->scl_high_ns = 1122 ofnode_read_s32_default(hdmi_node, 1123 "ddc-i2c-scl-high-time-ns", 4708); 1124 hdmi->i2c->scl_low_ns = 1125 ofnode_read_s32_default(hdmi_node, 1126 "ddc-i2c-scl-low-time-ns", 4916); 1127 1128 dw_hdmi_i2c_init(hdmi); 1129 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1130 1131 hdmi->dev_type = pdata->dev_type; 1132 hdmi->plat_data = pdata; 1133 hdmi->edid_data.mode_buf = mode_buf; 1134 1135 conn_state->private = hdmi; 1136 1137 dw_hdmi_detect_phy(hdmi); 1138 hdmi_writel(hdmi, 0, MAINUNIT_0_INT_MASK_N); 1139 hdmi_writel(hdmi, 0, MAINUNIT_1_INT_MASK_N); 1140 hdmi_writel(hdmi, 428571429, TIMER_BASE_CONFIG0); 1141 1142 dw_hdmi_qp_set_iomux(hdmi->rk_hdmi); 1143 1144 return 0; 1145 } 1146 1147 void rockchip_dw_hdmi_qp_deinit(struct display_state *state) 1148 { 1149 struct connector_state *conn_state = &state->conn_state; 1150 struct dw_hdmi_qp *hdmi = conn_state->private; 1151 1152 if (hdmi->i2c) 1153 free(hdmi->i2c); 1154 if (hdmi->edid_data.mode_buf) 1155 free(hdmi->edid_data.mode_buf); 1156 if (hdmi) 1157 free(hdmi); 1158 } 1159 1160 int rockchip_dw_hdmi_qp_prepare(struct display_state *state) 1161 { 1162 return 0; 1163 } 1164 1165 static void dw_hdmi_disable(struct dw_hdmi_qp *hdmi, struct display_state *state) 1166 { 1167 if (hdmi->phy.enabled) { 1168 hdmi->phy.ops->disable(hdmi->rk_hdmi, state); 1169 hdmi->phy.enabled = false; 1170 } 1171 } 1172 1173 int rockchip_dw_hdmi_qp_enable(struct display_state *state) 1174 { 1175 struct connector_state *conn_state = &state->conn_state; 1176 struct drm_display_mode *mode = &conn_state->mode; 1177 struct dw_hdmi_qp *hdmi = conn_state->private; 1178 1179 if (!hdmi) 1180 return -EFAULT; 1181 1182 /* Store the display mode for plugin/DKMS poweron events */ 1183 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 1184 1185 dw_hdmi_setup(hdmi, mode, state); 1186 1187 return 0; 1188 } 1189 1190 int rockchip_dw_hdmi_qp_disable(struct display_state *state) 1191 { 1192 struct connector_state *conn_state = &state->conn_state; 1193 struct dw_hdmi_qp *hdmi = conn_state->private; 1194 1195 dw_hdmi_disable(hdmi, state); 1196 return 0; 1197 } 1198 1199 int rockchip_dw_hdmi_qp_get_timing(struct display_state *state) 1200 { 1201 int ret, i; 1202 struct connector_state *conn_state = &state->conn_state; 1203 struct drm_display_mode *mode = &conn_state->mode; 1204 struct dw_hdmi_qp *hdmi = conn_state->private; 1205 struct edid *edid = (struct edid *)conn_state->edid; 1206 unsigned int bus_format; 1207 unsigned long enc_out_encoding; 1208 struct overscan *overscan = &conn_state->overscan; 1209 const u8 def_modes_vic[6] = {4, 16, 2, 17, 31, 19}; 1210 1211 if (!hdmi) 1212 return -EFAULT; 1213 1214 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 1215 if (!ret) { 1216 hdmi->sink_is_hdmi = 1217 drm_detect_hdmi_monitor(edid); 1218 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 1219 ret = drm_add_edid_modes(&hdmi->edid_data, conn_state->edid); 1220 } 1221 if (ret < 0) { 1222 hdmi->sink_is_hdmi = true; 1223 hdmi->sink_has_audio = true; 1224 do_cea_modes(&hdmi->edid_data, def_modes_vic, 1225 sizeof(def_modes_vic)); 1226 hdmi->edid_data.preferred_mode = &hdmi->edid_data.mode_buf[0]; 1227 printf("failed to get edid\n"); 1228 } 1229 drm_rk_filter_whitelist(&hdmi->edid_data); 1230 if (hdmi->phy.ops->mode_valid) 1231 hdmi->phy.ops->mode_valid(hdmi->rk_hdmi, state); 1232 drm_mode_max_resolution_filter(&hdmi->edid_data, 1233 &state->crtc_state.max_output); 1234 if (!drm_mode_prune_invalid(&hdmi->edid_data)) { 1235 printf("can't find valid hdmi mode\n"); 1236 return -EINVAL; 1237 } 1238 1239 for (i = 0; i < hdmi->edid_data.modes; i++) 1240 hdmi->edid_data.mode_buf[i].vrefresh = 1241 drm_mode_vrefresh(&hdmi->edid_data.mode_buf[i]); 1242 1243 drm_mode_sort(&hdmi->edid_data); 1244 dw_hdmi_qp_selete_output(&hdmi->edid_data, conn_state, &bus_format, 1245 overscan, hdmi->dev_type, 1246 hdmi->output_bus_format_rgb, hdmi->rk_hdmi, 1247 state); 1248 1249 *mode = *hdmi->edid_data.preferred_mode; 1250 hdmi->vic = drm_match_cea_mode(mode); 1251 1252 printf("mode:%dx%d bus_format:0x%x\n", mode->hdisplay, mode->vdisplay, bus_format); 1253 conn_state->bus_format = bus_format; 1254 hdmi->hdmi_data.enc_in_bus_format = bus_format; 1255 hdmi->hdmi_data.enc_out_bus_format = bus_format; 1256 1257 switch (bus_format) { 1258 case MEDIA_BUS_FMT_UYVY10_1X20: 1259 conn_state->bus_format = MEDIA_BUS_FMT_YUV10_1X30; 1260 hdmi->hdmi_data.enc_in_bus_format = 1261 MEDIA_BUS_FMT_YUV10_1X30; 1262 break; 1263 case MEDIA_BUS_FMT_UYVY8_1X16: 1264 conn_state->bus_format = MEDIA_BUS_FMT_YUV8_1X24; 1265 hdmi->hdmi_data.enc_in_bus_format = 1266 MEDIA_BUS_FMT_YUV8_1X24; 1267 break; 1268 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1269 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1270 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420; 1271 break; 1272 } 1273 1274 if (hdmi->vic == 6 || hdmi->vic == 7 || hdmi->vic == 21 || 1275 hdmi->vic == 22 || hdmi->vic == 2 || hdmi->vic == 3 || 1276 hdmi->vic == 17 || hdmi->vic == 18) 1277 enc_out_encoding = V4L2_YCBCR_ENC_601; 1278 else 1279 enc_out_encoding = V4L2_YCBCR_ENC_709; 1280 1281 if (enc_out_encoding == V4L2_YCBCR_ENC_BT2020) 1282 conn_state->color_space = V4L2_COLORSPACE_BT2020; 1283 else if (bus_format == MEDIA_BUS_FMT_RGB888_1X24 || 1284 bus_format == MEDIA_BUS_FMT_RGB101010_1X30) 1285 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 1286 else if (enc_out_encoding == V4L2_YCBCR_ENC_709) 1287 conn_state->color_space = V4L2_COLORSPACE_REC709; 1288 else 1289 conn_state->color_space = V4L2_COLORSPACE_SMPTE170M; 1290 1291 return 0; 1292 } 1293 1294 int rockchip_dw_hdmi_qp_detect(struct display_state *state) 1295 { 1296 int ret; 1297 struct connector_state *conn_state = &state->conn_state; 1298 struct dw_hdmi_qp *hdmi = conn_state->private; 1299 1300 if (!hdmi) 1301 return -EFAULT; 1302 1303 ret = dw_hdmi_detect_hotplug(hdmi, state); 1304 1305 return ret; 1306 } 1307 1308 int rockchip_dw_hdmi_qp_get_edid(struct display_state *state) 1309 { 1310 int ret; 1311 struct connector_state *conn_state = &state->conn_state; 1312 struct dw_hdmi_qp *hdmi = conn_state->private; 1313 1314 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 1315 1316 return ret; 1317 } 1318