1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd 4 * Author: Algea Cao <algea.cao@rock-chips.com> 5 */ 6 7 #include <common.h> 8 #include <malloc.h> 9 #include <syscon.h> 10 #include <asm/arch-rockchip/clock.h> 11 #include <asm/arch/vendor.h> 12 #include <edid.h> 13 #include <dm/device.h> 14 #include <dm/of_access.h> 15 #include <dm/ofnode.h> 16 #include <dm/read.h> 17 #include <linux/hdmi.h> 18 #include <linux/media-bus-format.h> 19 #include <linux/dw_hdmi.h> 20 #include <asm/io.h> 21 #include "rockchip_display.h" 22 #include "rockchip_crtc.h" 23 #include "rockchip_connector.h" 24 #include "dw_hdmi_qp.h" 25 #include "rockchip_phy.h" 26 27 enum frl_mask { 28 FRL_3GBPS_3LANE = 1, 29 FRL_6GBPS_3LANE, 30 FRL_6GBPS_4LANE, 31 FRL_8GBPS_4LANE, 32 FRL_10GBPS_4LANE, 33 FRL_12GBPS_4LANE, 34 }; 35 36 #define DDC_CI_ADDR 0x37 37 #define DDC_SEGMENT_ADDR 0x30 38 39 #define HDMI_EDID_LEN 512 40 41 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ 42 #define SCDC_MIN_SOURCE_VERSION 0x1 43 44 #define HDMI14_MAX_TMDSCLK 340000000 45 46 struct hdmi_vmode { 47 bool mdataenablepolarity; 48 49 unsigned int mpixelclock; 50 unsigned int mpixelrepetitioninput; 51 unsigned int mpixelrepetitionoutput; 52 unsigned int mtmdsclock; 53 }; 54 55 struct hdmi_data_info { 56 unsigned int enc_in_bus_format; 57 unsigned int enc_out_bus_format; 58 unsigned int enc_in_encoding; 59 unsigned int enc_out_encoding; 60 unsigned int quant_range; 61 unsigned int pix_repet_factor; 62 struct hdmi_vmode video_mode; 63 }; 64 65 struct dw_hdmi_phy_data { 66 enum dw_hdmi_phy_type type; 67 const char *name; 68 unsigned int gen; 69 bool has_svsret; 70 int (*configure)(struct dw_hdmi *hdmi, 71 const struct dw_hdmi_plat_data *pdata, 72 unsigned long mpixelclock); 73 }; 74 75 struct dw_hdmi_i2c { 76 u8 slave_reg; 77 bool is_regaddr; 78 bool is_segment; 79 80 unsigned int scl_high_ns; 81 unsigned int scl_low_ns; 82 }; 83 84 struct dw_hdmi_qp { 85 enum dw_hdmi_devtype dev_type; 86 unsigned int version; 87 struct hdmi_data_info hdmi_data; 88 struct hdmi_edid_data edid_data; 89 const struct dw_hdmi_plat_data *plat_data; 90 struct ddc_adapter adap; 91 92 int vic; 93 int id; 94 95 unsigned long bus_format; 96 bool cable_plugin; 97 bool sink_is_hdmi; 98 bool sink_has_audio; 99 void *regs; 100 void *rk_hdmi; 101 struct dw_hdmi_i2c *i2c; 102 103 struct { 104 const struct dw_hdmi_qp_phy_ops *ops; 105 const char *name; 106 void *data; 107 bool enabled; 108 } phy; 109 110 struct drm_display_mode previous_mode; 111 112 unsigned int sample_rate; 113 unsigned int audio_cts; 114 unsigned int audio_n; 115 bool audio_enable; 116 bool scramble_low_rates; 117 118 void (*write)(struct dw_hdmi_qp *hdmi, u32 val, int offset); 119 u8 (*read)(struct dw_hdmi_qp *hdmi, int offset); 120 121 bool hdcp1x_enable; 122 bool output_bus_format_rgb; 123 }; 124 125 static inline void hdmi_writel(struct dw_hdmi_qp *hdmi, u32 val, int offset) 126 { 127 writel(val, hdmi->regs + offset); 128 } 129 130 static inline u32 hdmi_readl(struct dw_hdmi_qp *hdmi, int offset) 131 { 132 return readl(hdmi->regs + offset); 133 } 134 135 static void 136 hdmi_modb(struct dw_hdmi_qp *hdmi, u32 data, u32 mask, unsigned int reg) 137 { 138 u32 val = hdmi_readl(hdmi, reg) & ~mask; 139 140 val |= data & mask; 141 hdmi_writel(hdmi, val, reg); 142 } 143 144 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 145 { 146 switch (bus_format) { 147 case MEDIA_BUS_FMT_RGB888_1X24: 148 case MEDIA_BUS_FMT_RGB101010_1X30: 149 case MEDIA_BUS_FMT_RGB121212_1X36: 150 case MEDIA_BUS_FMT_RGB161616_1X48: 151 return true; 152 153 default: 154 return false; 155 } 156 } 157 158 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 159 { 160 switch (bus_format) { 161 case MEDIA_BUS_FMT_YUV8_1X24: 162 case MEDIA_BUS_FMT_YUV10_1X30: 163 case MEDIA_BUS_FMT_YUV12_1X36: 164 case MEDIA_BUS_FMT_YUV16_1X48: 165 return true; 166 167 default: 168 return false; 169 } 170 } 171 172 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 173 { 174 switch (bus_format) { 175 case MEDIA_BUS_FMT_UYVY8_1X16: 176 case MEDIA_BUS_FMT_UYVY10_1X20: 177 case MEDIA_BUS_FMT_UYVY12_1X24: 178 return true; 179 180 default: 181 return false; 182 } 183 } 184 185 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 186 { 187 switch (bus_format) { 188 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 189 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 190 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 191 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 192 return true; 193 194 default: 195 return false; 196 } 197 } 198 199 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 200 { 201 switch (bus_format) { 202 case MEDIA_BUS_FMT_RGB888_1X24: 203 case MEDIA_BUS_FMT_YUV8_1X24: 204 case MEDIA_BUS_FMT_UYVY8_1X16: 205 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 206 return 8; 207 208 case MEDIA_BUS_FMT_RGB101010_1X30: 209 case MEDIA_BUS_FMT_YUV10_1X30: 210 case MEDIA_BUS_FMT_UYVY10_1X20: 211 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 212 return 10; 213 214 case MEDIA_BUS_FMT_RGB121212_1X36: 215 case MEDIA_BUS_FMT_YUV12_1X36: 216 case MEDIA_BUS_FMT_UYVY12_1X24: 217 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 218 return 12; 219 220 case MEDIA_BUS_FMT_RGB161616_1X48: 221 case MEDIA_BUS_FMT_YUV16_1X48: 222 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 223 return 16; 224 225 default: 226 return 0; 227 } 228 } 229 230 static bool drm_scdc_set_scrambling(struct ddc_adapter *adapter, bool enable) 231 { 232 u8 config; 233 int ret; 234 235 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 236 if (ret < 0) { 237 debug("Failed to read TMDS config: %d\n", ret); 238 return false; 239 } 240 241 if (enable) 242 config |= SCDC_SCRAMBLING_ENABLE; 243 else 244 config &= ~SCDC_SCRAMBLING_ENABLE; 245 246 ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config); 247 if (ret < 0) { 248 debug("Failed to enable scrambling: %d\n", ret); 249 return false; 250 } 251 252 return true; 253 } 254 255 static bool 256 drm_scdc_set_high_tmds_clock_ratio(struct ddc_adapter *adapter, bool set) 257 { 258 u8 config; 259 int ret; 260 261 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 262 if (ret < 0) { 263 debug("Failed to read TMDS config: %d\n", ret); 264 return false; 265 } 266 267 if (set) 268 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 269 else 270 config &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 271 272 ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config); 273 if (ret < 0) { 274 debug("Failed to set TMDS clock ratio: %d\n", ret); 275 return false; 276 } 277 278 /* 279 * The spec says that a source should wait minimum 1ms and maximum 280 * 100ms after writing the TMDS config for clock ratio. Lets allow a 281 * wait of up to 2ms here. 282 */ 283 udelay(2000); 284 return true; 285 } 286 287 static void dw_hdmi_i2c_init(struct dw_hdmi_qp *hdmi) 288 { 289 /* Software reset */ 290 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 291 292 hdmi_writel(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0); 293 294 hdmi_modb(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0); 295 296 /* Clear DONE and ERROR interrupts */ 297 hdmi_writel(hdmi, I2CM_OP_DONE_CLEAR | I2CM_NACK_RCVD_CLEAR, 298 MAINUNIT_1_INT_CLEAR); 299 } 300 301 static int dw_hdmi_i2c_read(struct dw_hdmi_qp *hdmi, 302 unsigned char *buf, unsigned int length) 303 { 304 struct dw_hdmi_i2c *i2c = hdmi->i2c; 305 int i = 20; 306 u32 intr = 0; 307 308 if (!i2c->is_regaddr) { 309 printf("set read register address to 0\n"); 310 i2c->slave_reg = 0x00; 311 i2c->is_regaddr = true; 312 } 313 314 while (length--) { 315 hdmi_modb(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, 316 I2CM_INTERFACE_CONTROL0); 317 318 hdmi_modb(hdmi, I2CM_FM_READ, I2CM_WR_MASK, 319 I2CM_INTERFACE_CONTROL0); 320 321 while (i--) { 322 udelay(1000); 323 intr = hdmi_readl(hdmi, MAINUNIT_1_INT_STATUS) & 324 (I2CM_OP_DONE_IRQ | I2CM_READ_REQUEST_IRQ | 325 I2CM_NACK_RCVD_IRQ); 326 if (intr) { 327 hdmi_writel(hdmi, intr, MAINUNIT_1_INT_CLEAR); 328 break; 329 } 330 } 331 332 if (!i) { 333 printf("i2c read time out!\n"); 334 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 335 return -EAGAIN; 336 } 337 338 /* Check for error condition on the bus */ 339 if (intr & I2CM_NACK_RCVD_IRQ) { 340 printf("i2c read err!\n"); 341 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 342 return -EIO; 343 } 344 345 *buf++ = hdmi_readl(hdmi, I2CM_INTERFACE_RDDATA_0_3) & 0xff; 346 hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); 347 i = 20; 348 } 349 i2c->is_segment = false; 350 351 return 0; 352 } 353 354 static int dw_hdmi_i2c_write(struct dw_hdmi_qp *hdmi, 355 unsigned char *buf, unsigned int length) 356 { 357 struct dw_hdmi_i2c *i2c = hdmi->i2c; 358 int i = 20; 359 u32 intr = 0; 360 361 if (!i2c->is_regaddr) { 362 /* Use the first write byte as register address */ 363 i2c->slave_reg = buf[0]; 364 length--; 365 buf++; 366 i2c->is_regaddr = true; 367 } 368 369 while (length--) { 370 hdmi_writel(hdmi, *buf++, I2CM_INTERFACE_WRDATA_0_3); 371 hdmi_modb(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, 372 I2CM_INTERFACE_CONTROL0); 373 hdmi_modb(hdmi, I2CM_FM_WRITE, I2CM_WR_MASK, 374 I2CM_INTERFACE_CONTROL0); 375 376 while (i--) { 377 udelay(1000); 378 intr = hdmi_readl(hdmi, MAINUNIT_1_INT_STATUS) & 379 (I2CM_OP_DONE_IRQ | I2CM_READ_REQUEST_IRQ | 380 I2CM_NACK_RCVD_IRQ); 381 if (intr) { 382 hdmi_writel(hdmi, intr, MAINUNIT_1_INT_CLEAR); 383 break; 384 } 385 } 386 387 if (!i) { 388 printf("i2c write time out!\n"); 389 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 390 return -EAGAIN; 391 } 392 393 /* Check for error condition on the bus */ 394 if (intr & I2CM_NACK_RCVD_IRQ) { 395 printf("i2c write nack!\n"); 396 hdmi_writel(hdmi, 0x01, I2CM_CONTROL0); 397 return -EIO; 398 } 399 hdmi_modb(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); 400 i = 20; 401 } 402 403 return 0; 404 } 405 406 static int dw_hdmi_i2c_xfer(struct ddc_adapter *adap, 407 struct i2c_msg *msgs, int num) 408 { 409 struct dw_hdmi_qp *hdmi = container_of(adap, struct dw_hdmi_qp, adap); 410 struct dw_hdmi_i2c *i2c = hdmi->i2c; 411 u8 addr = msgs[0].addr; 412 int i, ret = 0; 413 414 debug("i2c xfer: num: %d, addr: %#x\n", num, addr); 415 416 for (i = 0; i < num; i++) { 417 if (msgs[i].len == 0) { 418 printf("unsupported transfer %d/%d, no data\n", 419 i + 1, num); 420 return -EOPNOTSUPP; 421 } 422 } 423 424 /* Unmute DONE and ERROR interrupts */ 425 hdmi_modb(hdmi, I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, 426 I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, 427 MAINUNIT_1_INT_MASK_N); 428 429 /* Set slave device address taken from the first I2C message */ 430 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1) 431 addr = DDC_ADDR; 432 433 hdmi_modb(hdmi, addr << 5, I2CM_SLVADDR, I2CM_INTERFACE_CONTROL0); 434 435 /* Set slave device register address on transfer */ 436 i2c->is_regaddr = false; 437 438 /* Set segment pointer for I2C extended read mode operation */ 439 i2c->is_segment = false; 440 441 for (i = 0; i < num; i++) { 442 debug("xfer: num: %d/%d, len: %d, flags: %#x\n", 443 i + 1, num, msgs[i].len, msgs[i].flags); 444 445 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 446 i2c->is_segment = true; 447 hdmi_modb(hdmi, DDC_SEGMENT_ADDR, I2CM_SEG_ADDR, 448 I2CM_INTERFACE_CONTROL1); 449 hdmi_modb(hdmi, *msgs[i].buf, I2CM_SEG_PTR, 450 I2CM_INTERFACE_CONTROL1); 451 } else { 452 if (msgs[i].flags & I2C_M_RD) 453 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 454 msgs[i].len); 455 else 456 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 457 msgs[i].len); 458 } 459 if (ret < 0) 460 break; 461 } 462 463 if (!ret) 464 ret = num; 465 466 /* Mute DONE and ERROR interrupts */ 467 hdmi_modb(hdmi, 0, I2CM_OP_DONE_MASK_N | I2CM_NACK_RCVD_MASK_N, 468 MAINUNIT_1_INT_MASK_N); 469 470 return ret; 471 } 472 473 static int dw_hdmi_detect_phy(struct dw_hdmi_qp *hdmi) 474 { 475 /* Vendor PHYs require support from the glue layer. */ 476 if (!hdmi->plat_data->qp_phy_ops || !hdmi->plat_data->phy_name) { 477 dev_err(hdmi->dev, 478 "Vendor HDMI PHY not supported by glue layer\n"); 479 return -ENODEV; 480 } 481 482 hdmi->phy.ops = hdmi->plat_data->qp_phy_ops; 483 hdmi->phy.data = hdmi->plat_data->phy_data; 484 hdmi->phy.name = hdmi->plat_data->phy_name; 485 486 return 0; 487 } 488 489 static unsigned int 490 hdmi_get_tmdsclock(struct dw_hdmi_qp *hdmi, unsigned long mpixelclock) 491 { 492 unsigned int tmdsclock = mpixelclock; 493 unsigned int depth = 494 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format); 495 496 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 497 switch (depth) { 498 case 16: 499 tmdsclock = mpixelclock * 2; 500 break; 501 case 12: 502 tmdsclock = mpixelclock * 3 / 2; 503 break; 504 case 10: 505 tmdsclock = mpixelclock * 5 / 4; 506 break; 507 default: 508 break; 509 } 510 } 511 512 return tmdsclock; 513 } 514 515 static void hdmi_infoframe_set_checksum(u8 *ptr, int size) 516 { 517 u8 csum = 0; 518 int i; 519 520 ptr[3] = 0; 521 /* compute checksum */ 522 for (i = 0; i < size; i++) 523 csum += ptr[i]; 524 525 ptr[3] = 256 - csum; 526 } 527 528 static bool is_hdmi2_sink(struct dw_hdmi_qp *hdmi) 529 { 530 return hdmi->edid_data.display_info.hdmi.scdc.supported || 531 hdmi->edid_data.display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; 532 } 533 534 static void hdmi_config_AVI(struct dw_hdmi_qp *hdmi, struct drm_display_mode *mode) 535 { 536 struct hdmi_avi_infoframe frame; 537 u32 val, i, j; 538 u8 buff[17]; 539 bool is_hdmi2 = false; 540 enum hdmi_quantization_range rgb_quant_range = 541 hdmi->hdmi_data.quant_range; 542 543 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) || 544 hdmi->edid_data.display_info.hdmi.scdc.supported) 545 is_hdmi2 = true; 546 /* Initialise info frame from DRM mode */ 547 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2); 548 549 /* 550 * Ignore monitor selectable quantization, use quantization set 551 * by the user 552 */ 553 drm_hdmi_avi_infoframe_quant_range(&frame, mode, rgb_quant_range, 554 true); 555 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 556 frame.colorspace = HDMI_COLORSPACE_YUV444; 557 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 558 frame.colorspace = HDMI_COLORSPACE_YUV422; 559 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 560 frame.colorspace = HDMI_COLORSPACE_YUV420; 561 else 562 frame.colorspace = HDMI_COLORSPACE_RGB; 563 564 /* Set up colorimetry and quant range */ 565 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 566 switch (hdmi->hdmi_data.enc_out_encoding) { 567 case V4L2_YCBCR_ENC_601: 568 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 569 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 570 else 571 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 572 frame.extended_colorimetry = 573 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 574 break; 575 case V4L2_YCBCR_ENC_709: 576 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 577 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 578 else 579 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 580 frame.extended_colorimetry = 581 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 582 break; 583 case V4L2_YCBCR_ENC_BT2020: 584 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_BT2020) 585 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 586 else 587 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 588 frame.extended_colorimetry = 589 HDMI_EXTENDED_COLORIMETRY_BT2020; 590 break; 591 default: /* Carries no data */ 592 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 593 frame.extended_colorimetry = 594 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 595 break; 596 } 597 598 frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 599 } else { 600 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_BT2020) { 601 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 602 frame.extended_colorimetry = 603 HDMI_EXTENDED_COLORIMETRY_BT2020; 604 } else { 605 frame.colorimetry = HDMI_COLORIMETRY_NONE; 606 frame.extended_colorimetry = 607 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 608 } 609 610 if (is_hdmi2_sink(hdmi) && 611 frame.quantization_range == HDMI_QUANTIZATION_RANGE_FULL) 612 frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_FULL; 613 else 614 frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 615 } 616 617 frame.scan_mode = HDMI_SCAN_MODE_NONE; 618 619 hdmi_avi_infoframe_pack_only(&frame, buff, 17); 620 621 /* mode which vic >= 128 must use avi version 3 */ 622 if (hdmi->vic >= 128) { 623 frame.version = 3; 624 buff[1] = frame.version; 625 buff[4] &= 0x1f; 626 buff[4] |= ((frame.colorspace & 0x7) << 5); 627 buff[7] = hdmi->vic; 628 hdmi_infoframe_set_checksum(buff, 17); 629 } 630 631 /* 632 * The Designware IP uses a different byte format from standard 633 * AVI info frames, though generally the bits are in the correct 634 * bytes. 635 */ 636 637 val = (frame.version << 8) | (frame.length << 16); 638 hdmi_writel(hdmi, val, PKT_AVI_CONTENTS0); 639 640 for (i = 0; i < 4; i++) { 641 for (j = 0; j < 4; j++) { 642 if (i * 4 + j >= 14) 643 break; 644 if (!j) 645 val = buff[i * 4 + j + 3]; 646 val |= buff[i * 4 + j + 3] << (8 * j); 647 } 648 649 hdmi_writel(hdmi, val, PKT_AVI_CONTENTS1 + i * 4); 650 } 651 652 hdmi_modb(hdmi, 0, PKTSCHED_AVI_FIELDRATE, PKTSCHED_PKT_CONFIG1); 653 654 hdmi_modb(hdmi, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, 655 PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, 656 PKTSCHED_PKT_EN); 657 } 658 659 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi_qp *hdmi, 660 struct drm_display_mode *mode) 661 { 662 struct hdmi_vendor_infoframe frame; 663 u8 buffer[10]; 664 u32 val; 665 ssize_t err; 666 int i, reg; 667 668 hdmi_modb(hdmi, 0, PKTSCHED_VSI_TX_EN, PKTSCHED_PKT_EN); 669 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode); 670 if (err < 0) 671 /* 672 * Going into that statement does not means vendor infoframe 673 * fails. It just informed us that vendor infoframe is not 674 * needed for the selected mode. Only 4k or stereoscopic 3D 675 * mode requires vendor infoframe. So just simply return. 676 */ 677 return; 678 679 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 680 if (err < 0) { 681 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 682 err); 683 return; 684 } 685 686 /* vsi header */ 687 val = (buffer[2] << 16) | (buffer[1] << 8) | buffer[0]; 688 hdmi_writel(hdmi, val, PKT_VSI_CONTENTS0); 689 690 reg = PKT_VSI_CONTENTS1; 691 for (i = 3; i < err; i++) { 692 if (i % 4 == 3) 693 val = buffer[i]; 694 if (i % 4 == 0) 695 val |= buffer[i] << 8; 696 if (i % 4 == 1) 697 val |= buffer[i] << 16; 698 if (i % 4 == 2) 699 val |= buffer[i] << 24; 700 701 if ((i % 4 == 2) || (i == (err - 1))) { 702 hdmi_writel(hdmi, val, reg); 703 reg += 4; 704 } 705 } 706 707 hdmi_writel(hdmi, 0, PKT_VSI_CONTENTS7); 708 709 hdmi_modb(hdmi, 0, PKTSCHED_VSI_FIELDRATE, PKTSCHED_PKT_CONFIG1); 710 hdmi_modb(hdmi, PKTSCHED_VSI_TX_EN, PKTSCHED_VSI_TX_EN, 711 PKTSCHED_PKT_EN); 712 } 713 714 static void hdmi_config_CVTEM(struct dw_hdmi_qp *hdmi, 715 struct dw_hdmi_link_config *link_cfg) 716 { 717 u8 ds_type = 0; 718 u8 sync = 1; 719 u8 vfr = 1; 720 u8 afr = 0; 721 u8 new = 1; 722 u8 end = 0; 723 u8 data_set_length = 136; 724 u8 hb1[6] = { 0x80, 0, 0, 0, 0, 0x40 }; 725 u8 *pps_body; 726 u32 val, i, reg; 727 struct drm_display_mode *mode = &hdmi->previous_mode; 728 int hsync, hfront, hback; 729 730 hdmi_modb(hdmi, 0, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_PKT_EN); 731 732 if (!link_cfg->dsc_mode) { 733 printf("don't use dsc mode\n"); 734 return; 735 } 736 737 pps_body = link_cfg->pps_payload; 738 739 hsync = mode->hsync_end - mode->hsync_start; 740 hback = mode->htotal - mode->hsync_end; 741 hfront = mode->hsync_start - mode->hdisplay; 742 743 for (i = 0; i < 6; i++) { 744 val = i << 16 | hb1[i] << 8; 745 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS0 + i * 0x20); 746 } 747 748 val = new << 7 | end << 6 | ds_type << 4 | afr << 3 | 749 vfr << 2 | sync << 1; 750 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS1); 751 752 val = data_set_length << 16 | pps_body[0] << 24; 753 hdmi_writel(hdmi, val, PKT0_EMP_CVTEM_CONTENTS2); 754 755 reg = PKT0_EMP_CVTEM_CONTENTS3; 756 for (i = 1; i < 125; i++) { 757 if (reg == PKT1_EMP_CVTEM_CONTENTS0 || 758 reg == PKT2_EMP_CVTEM_CONTENTS0 || 759 reg == PKT3_EMP_CVTEM_CONTENTS0 || 760 reg == PKT4_EMP_CVTEM_CONTENTS0 || 761 reg == PKT5_EMP_CVTEM_CONTENTS0) { 762 reg += 4; 763 i--; 764 continue; 765 } 766 if (i % 4 == 1) 767 val = pps_body[i]; 768 if (i % 4 == 2) 769 val |= pps_body[i] << 8; 770 if (i % 4 == 3) 771 val |= pps_body[i] << 16; 772 if (!(i % 4)) { 773 val |= pps_body[i] << 24; 774 hdmi_writel(hdmi, val, reg); 775 reg += 4; 776 } 777 } 778 779 val = (hfront & 0xff) << 24 | pps_body[127] << 16 | 780 pps_body[126] << 8 | pps_body[125]; 781 hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS6); 782 783 val = (hback & 0xff) << 24 | ((hsync >> 8) & 0xff) << 16 | 784 (hsync & 0xff) << 8 | ((hfront >> 8) & 0xff); 785 hdmi_writel(hdmi, val, PKT4_EMP_CVTEM_CONTENTS7); 786 787 val = link_cfg->hcactive << 8 | ((hback >> 8) & 0xff); 788 hdmi_writel(hdmi, val, PKT5_EMP_CVTEM_CONTENTS1); 789 790 for (i = PKT5_EMP_CVTEM_CONTENTS2; i <= PKT5_EMP_CVTEM_CONTENTS7; i += 4) 791 hdmi_writel(hdmi, 0, i); 792 793 hdmi_modb(hdmi, PKTSCHED_EMP_CVTEM_TX_EN, PKTSCHED_EMP_CVTEM_TX_EN, 794 PKTSCHED_PKT_EN); 795 } 796 797 static int hdmi_set_frl_mask(int frl_rate) 798 { 799 switch (frl_rate) { 800 case 48: 801 return FRL_12GBPS_4LANE; 802 case 40: 803 return FRL_10GBPS_4LANE; 804 case 32: 805 return FRL_8GBPS_4LANE; 806 case 24: 807 return FRL_6GBPS_4LANE; 808 case 18: 809 return FRL_6GBPS_3LANE; 810 case 9: 811 return FRL_3GBPS_3LANE; 812 } 813 814 return 0; 815 } 816 817 static int hdmi_start_flt(struct dw_hdmi_qp *hdmi, u8 rate) 818 { 819 u8 val; 820 u32 value; 821 u8 ffe_lv = 0; 822 int i = 0; 823 bool ltsp = false; 824 825 hdmi_modb(hdmi, AVP_DATAPATH_VIDEO_SWDISABLE, 826 AVP_DATAPATH_VIDEO_SWDISABLE, GLOBAL_SWDISABLE); 827 828 /* clear flt flags */ 829 drm_scdc_writeb(&hdmi->adap, 0x10, 0xff); 830 831 /* FLT_READY & FFE_LEVELS read */ 832 for (i = 0; i < 20; i++) { 833 drm_scdc_readb(&hdmi->adap, SCDC_STATUS_FLAGS_0, &val); 834 if (val & BIT(6)) 835 break; 836 mdelay(20); 837 } 838 839 if (i == 20) { 840 printf("sink flt isn't ready\n"); 841 return -EINVAL; 842 } 843 844 /* max ffe level 3 */ 845 val = 0 << 4 | hdmi_set_frl_mask(rate); 846 drm_scdc_writeb(&hdmi->adap, 0x31, val); 847 /* select FRL_RATE & FFE_LEVELS */ 848 hdmi_writel(hdmi, ffe_lv, FLT_CONFIG0); 849 850 i = 500; 851 while (i--) { 852 mdelay(4); 853 drm_scdc_readb(&hdmi->adap, 0x10, &val); 854 855 if (!(val & 0x30)) 856 continue; 857 858 if (val & BIT(5)) { 859 u8 reg_val, ln0, ln1, ln2, ln3; 860 861 drm_scdc_readb(&hdmi->adap, 0x41, ®_val); 862 ln0 = reg_val & 0xf; 863 ln1 = (reg_val >> 4) & 0xf; 864 865 drm_scdc_readb(&hdmi->adap, 0x42, ®_val); 866 ln2 = reg_val & 0xf; 867 ln3 = (reg_val >> 4) & 0xf; 868 869 if (!ln0 && !ln1 && !ln2 && !ln3) { 870 printf("goto ltsp\n"); 871 ltsp = true; 872 hdmi_writel(hdmi, 0, FLT_CONFIG1); 873 } else if ((ln0 == 0xf) | (ln1 == 0xf) | (ln2 == 0xf) | (ln3 == 0xf)) { 874 printf("goto lts4\n"); 875 break; 876 } else if ((ln0 == 0xe) | (ln1 == 0xe) | (ln2 == 0xe) | (ln3 == 0xe)) { 877 printf("goto ffe\n"); 878 break; 879 } else { 880 value = (ln3 << 16) | (ln2 << 12) | (ln1 << 8) | (ln0 << 4) | 0xf; 881 hdmi_writel(hdmi, value, FLT_CONFIG1); 882 } 883 } 884 885 drm_scdc_writeb(&hdmi->adap, 0x10, val); 886 887 if ((val & BIT(4)) && ltsp) { 888 hdmi_modb(hdmi, 0, AVP_DATAPATH_VIDEO_SWDISABLE, GLOBAL_SWDISABLE); 889 printf("flt success\n"); 890 break; 891 } 892 } 893 894 if (i < 0) { 895 printf("flt time out\n"); 896 return -ETIMEDOUT; 897 } 898 899 return 0; 900 } 901 902 #define HDMI_MODE_FRL_MASK BIT(30) 903 904 static void hdmi_set_op_mode(struct dw_hdmi_qp *hdmi, 905 struct dw_hdmi_link_config *link_cfg, 906 bool scdc_support) 907 { 908 int frl_rate; 909 int i; 910 911 hdmi_writel(hdmi, 0, FLT_CONFIG0); 912 if (scdc_support) 913 drm_scdc_writeb(&hdmi->adap, 0x31, 0); 914 mdelay(200); 915 if (!link_cfg->frl_mode) { 916 printf("dw hdmi qp use tmds mode\n"); 917 hdmi_modb(hdmi, 0, OPMODE_FRL, LINK_CONFIG0); 918 hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0); 919 return; 920 } 921 922 if (link_cfg->frl_lanes == 4) 923 hdmi_modb(hdmi, OPMODE_FRL_4LANES, OPMODE_FRL_4LANES, 924 LINK_CONFIG0); 925 else 926 hdmi_modb(hdmi, 0, OPMODE_FRL_4LANES, LINK_CONFIG0); 927 928 hdmi_modb(hdmi, 1, OPMODE_FRL, LINK_CONFIG0); 929 930 frl_rate = link_cfg->frl_lanes * link_cfg->rate_per_lane; 931 hdmi_start_flt(hdmi, frl_rate); 932 933 for (i = 0; i < 200; i++) { 934 hdmi_modb(hdmi, PKTSCHED_NULL_TX_EN, PKTSCHED_NULL_TX_EN, PKTSCHED_PKT_EN); 935 udelay(50); 936 hdmi_modb(hdmi, 0, PKTSCHED_NULL_TX_EN, PKTSCHED_PKT_EN); 937 udelay(50); 938 } 939 } 940 941 static int dw_hdmi_setup(struct dw_hdmi_qp *hdmi, 942 struct rockchip_connector *conn, 943 struct drm_display_mode *mode, 944 struct display_state *state) 945 { 946 int ret; 947 void *data = hdmi->plat_data->phy_data; 948 struct dw_hdmi_link_config *link_cfg; 949 struct drm_hdmi_info *hdmi_info = &hdmi->edid_data.display_info.hdmi; 950 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 951 u8 bytes = 0; 952 953 if (!hdmi->vic) 954 printf("Non-CEA mode used in HDMI\n"); 955 else 956 printf("CEA mode used vic=%d\n", hdmi->vic); 957 958 vmode->mpixelclock = mode->clock * 1000; 959 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock); 960 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 961 vmode->mtmdsclock /= 2; 962 printf("mtmdsclock:%d\n", vmode->mtmdsclock); 963 964 if (hdmi->plat_data->get_enc_out_encoding) 965 hdmi->hdmi_data.enc_out_encoding = 966 hdmi->plat_data->get_enc_out_encoding(data); 967 else if (hdmi->vic == 6 || hdmi->vic == 7 || 968 hdmi->vic == 21 || hdmi->vic == 22 || 969 hdmi->vic == 2 || hdmi->vic == 3 || 970 hdmi->vic == 17 || hdmi->vic == 18) 971 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 972 else 973 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 974 975 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 976 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1; 977 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1; 978 } else { 979 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 980 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 981 } 982 983 /* TOFIX: Get input encoding from plat data or fallback to none */ 984 if (hdmi->plat_data->get_enc_in_encoding) 985 hdmi->hdmi_data.enc_in_encoding = 986 hdmi->plat_data->get_enc_in_encoding(data); 987 else if (hdmi->plat_data->input_bus_encoding) 988 hdmi->hdmi_data.enc_in_encoding = 989 hdmi->plat_data->input_bus_encoding; 990 else 991 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 992 993 if (hdmi->plat_data->get_quant_range) 994 hdmi->hdmi_data.quant_range = 995 hdmi->plat_data->get_quant_range(data); 996 else 997 hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 998 999 /* 1000 * According to the dw-hdmi specification 6.4.2 1001 * vp_pr_cd[3:0]: 1002 * 0000b: No pixel repetition (pixel sent only once) 1003 * 0001b: Pixel sent two times (pixel repeated once) 1004 */ 1005 hdmi->hdmi_data.pix_repet_factor = 1006 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0; 1007 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 1008 1009 /* HDMI Initialization Step B.2 */ 1010 ret = hdmi->phy.ops->init(conn, hdmi->rk_hdmi, state); 1011 if (ret) 1012 return ret; 1013 hdmi->phy.enabled = true; 1014 1015 rk3588_set_grf_cfg(hdmi->rk_hdmi); 1016 link_cfg = dw_hdmi_rockchip_get_link_cfg(hdmi->rk_hdmi); 1017 1018 /* not for DVI mode */ 1019 if (hdmi->sink_is_hdmi) { 1020 printf("%s HDMI mode\n", __func__); 1021 hdmi_modb(hdmi, 0, OPMODE_DVI, LINK_CONFIG0); 1022 hdmi_modb(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0); 1023 if (!link_cfg->frl_mode) { 1024 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK) { 1025 drm_scdc_readb(&hdmi->adap, SCDC_SINK_VERSION, &bytes); 1026 drm_scdc_writeb(&hdmi->adap, SCDC_SOURCE_VERSION, 1027 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); 1028 drm_scdc_set_high_tmds_clock_ratio(&hdmi->adap, 1); 1029 drm_scdc_set_scrambling(&hdmi->adap, 1); 1030 hdmi_writel(hdmi, 1, SCRAMB_CONFIG0); 1031 } else { 1032 if (hdmi_info->scdc.supported) { 1033 drm_scdc_set_high_tmds_clock_ratio(&hdmi->adap, 0); 1034 drm_scdc_set_scrambling(&hdmi->adap, 0); 1035 } 1036 hdmi_writel(hdmi, 0, SCRAMB_CONFIG0); 1037 } 1038 } 1039 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 1040 hdmi_config_AVI(hdmi, mode); 1041 hdmi_config_vendor_specific_infoframe(hdmi, mode); 1042 hdmi_config_CVTEM(hdmi, link_cfg); 1043 hdmi_set_op_mode(hdmi, link_cfg, hdmi_info->scdc.supported); 1044 /* clear avmute */ 1045 hdmi_writel(hdmi, 2, PKTSCHED_PKT_CONTROL0); 1046 } else { 1047 hdmi_modb(hdmi, OPMODE_DVI, OPMODE_DVI, LINK_CONFIG0); 1048 printf("%s DVI mode\n", __func__); 1049 } 1050 1051 return 0; 1052 } 1053 1054 int dw_hdmi_detect_hotplug(struct dw_hdmi_qp *hdmi, 1055 struct display_state *state) 1056 { 1057 struct connector_state *conn_state = &state->conn_state; 1058 int ret; 1059 1060 ret = hdmi->phy.ops->read_hpd(hdmi->rk_hdmi); 1061 if (ret || state->force_output) { 1062 if (!hdmi->id) 1063 conn_state->output_if |= VOP_OUTPUT_IF_HDMI0; 1064 else 1065 conn_state->output_if |= VOP_OUTPUT_IF_HDMI1; 1066 } 1067 1068 return ret; 1069 } 1070 1071 int rockchip_dw_hdmi_qp_init(struct rockchip_connector *conn, struct display_state *state) 1072 { 1073 struct connector_state *conn_state = &state->conn_state; 1074 const struct dw_hdmi_plat_data *pdata = 1075 (const struct dw_hdmi_plat_data *)dev_get_driver_data(conn->dev); 1076 void *rk_hdmi = dev_get_priv(conn->dev); 1077 struct dw_hdmi_qp *hdmi; 1078 struct drm_display_mode *mode_buf; 1079 ofnode hdmi_node = conn->dev->node; 1080 struct device_node *ddc_node; 1081 1082 hdmi = malloc(sizeof(struct dw_hdmi_qp)); 1083 if (!hdmi) 1084 return -ENOMEM; 1085 1086 memset(hdmi, 0, sizeof(struct dw_hdmi_qp)); 1087 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 1088 if (!mode_buf) 1089 return -ENOMEM; 1090 1091 hdmi->rk_hdmi = rk_hdmi; 1092 hdmi->id = of_alias_get_id(ofnode_to_np(hdmi_node), "hdmi"); 1093 if (hdmi->id < 0) 1094 hdmi->id = 0; 1095 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, hdmi->id); 1096 1097 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 1098 1099 hdmi->regs = dev_read_addr_ptr(conn->dev); 1100 1101 ddc_node = of_parse_phandle(ofnode_to_np(hdmi_node), "ddc-i2c-bus", 0); 1102 if (ddc_node) { 1103 uclass_get_device_by_ofnode(UCLASS_I2C, np_to_ofnode(ddc_node), 1104 &hdmi->adap.i2c_bus); 1105 if (hdmi->adap.i2c_bus) 1106 hdmi->adap.ops = i2c_get_ops(hdmi->adap.i2c_bus); 1107 } 1108 1109 hdmi->i2c = malloc(sizeof(struct dw_hdmi_i2c)); 1110 if (!hdmi->i2c) 1111 return -ENOMEM; 1112 hdmi->adap.ddc_xfer = dw_hdmi_i2c_xfer; 1113 1114 /* 1115 * Read high and low time from device tree. If not available use 1116 * the default timing scl clock rate is about 99.6KHz. 1117 */ 1118 hdmi->i2c->scl_high_ns = 1119 ofnode_read_s32_default(hdmi_node, 1120 "ddc-i2c-scl-high-time-ns", 4708); 1121 hdmi->i2c->scl_low_ns = 1122 ofnode_read_s32_default(hdmi_node, 1123 "ddc-i2c-scl-low-time-ns", 4916); 1124 1125 dw_hdmi_i2c_init(hdmi); 1126 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1127 1128 hdmi->dev_type = pdata->dev_type; 1129 hdmi->plat_data = pdata; 1130 hdmi->edid_data.mode_buf = mode_buf; 1131 1132 conn->data = hdmi; 1133 1134 dw_hdmi_detect_phy(hdmi); 1135 hdmi_writel(hdmi, 0, MAINUNIT_0_INT_MASK_N); 1136 hdmi_writel(hdmi, 0, MAINUNIT_1_INT_MASK_N); 1137 hdmi_writel(hdmi, 428571429, TIMER_BASE_CONFIG0); 1138 1139 dw_hdmi_qp_set_iomux(hdmi->rk_hdmi); 1140 1141 return 0; 1142 } 1143 1144 void rockchip_dw_hdmi_qp_deinit(struct rockchip_connector *conn, struct display_state *state) 1145 { 1146 struct dw_hdmi_qp *hdmi = conn->data; 1147 1148 if (hdmi->i2c) 1149 free(hdmi->i2c); 1150 if (hdmi->edid_data.mode_buf) 1151 free(hdmi->edid_data.mode_buf); 1152 if (hdmi) 1153 free(hdmi); 1154 } 1155 1156 int rockchip_dw_hdmi_qp_prepare(struct rockchip_connector *conn, struct display_state *state) 1157 { 1158 return 0; 1159 } 1160 1161 static void dw_hdmi_disable(struct rockchip_connector *conn, struct dw_hdmi_qp *hdmi, 1162 struct display_state *state) 1163 { 1164 if (hdmi->phy.enabled) { 1165 hdmi->phy.ops->disable(conn, hdmi->rk_hdmi, state); 1166 hdmi->phy.enabled = false; 1167 } 1168 } 1169 1170 int rockchip_dw_hdmi_qp_enable(struct rockchip_connector *conn, struct display_state *state) 1171 { 1172 struct connector_state *conn_state = &state->conn_state; 1173 struct drm_display_mode *mode = &conn_state->mode; 1174 struct dw_hdmi_qp *hdmi = conn->data; 1175 1176 if (!hdmi) 1177 return -EFAULT; 1178 1179 /* Store the display mode for plugin/DKMS poweron events */ 1180 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 1181 1182 dw_hdmi_setup(hdmi, conn, mode, state); 1183 1184 return 0; 1185 } 1186 1187 int rockchip_dw_hdmi_qp_disable(struct rockchip_connector *conn, struct display_state *state) 1188 { 1189 struct dw_hdmi_qp *hdmi = conn->data; 1190 1191 dw_hdmi_disable(conn, hdmi, state); 1192 return 0; 1193 } 1194 1195 int rockchip_dw_hdmi_qp_get_timing(struct rockchip_connector *conn, struct display_state *state) 1196 { 1197 int ret, i; 1198 struct connector_state *conn_state = &state->conn_state; 1199 struct drm_display_mode *mode = &conn_state->mode; 1200 struct dw_hdmi_qp *hdmi = conn->data; 1201 struct edid *edid = (struct edid *)conn_state->edid; 1202 unsigned int bus_format; 1203 unsigned long enc_out_encoding; 1204 struct overscan *overscan = &conn_state->overscan; 1205 const u8 def_modes_vic[6] = {4, 16, 2, 17, 31, 19}; 1206 1207 if (!hdmi) 1208 return -EFAULT; 1209 1210 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 1211 if (!ret) { 1212 hdmi->sink_is_hdmi = 1213 drm_detect_hdmi_monitor(edid); 1214 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 1215 ret = drm_add_edid_modes(&hdmi->edid_data, conn_state->edid); 1216 } 1217 if (ret < 0) { 1218 hdmi->sink_is_hdmi = true; 1219 hdmi->sink_has_audio = true; 1220 do_cea_modes(&hdmi->edid_data, def_modes_vic, 1221 sizeof(def_modes_vic)); 1222 hdmi->edid_data.preferred_mode = &hdmi->edid_data.mode_buf[0]; 1223 printf("failed to get edid\n"); 1224 } 1225 drm_rk_filter_whitelist(&hdmi->edid_data); 1226 if (hdmi->phy.ops->mode_valid) 1227 hdmi->phy.ops->mode_valid(hdmi->rk_hdmi, state); 1228 drm_mode_max_resolution_filter(&hdmi->edid_data, 1229 &state->crtc_state.max_output); 1230 if (!drm_mode_prune_invalid(&hdmi->edid_data)) { 1231 printf("can't find valid hdmi mode\n"); 1232 return -EINVAL; 1233 } 1234 1235 for (i = 0; i < hdmi->edid_data.modes; i++) 1236 hdmi->edid_data.mode_buf[i].vrefresh = 1237 drm_mode_vrefresh(&hdmi->edid_data.mode_buf[i]); 1238 1239 drm_mode_sort(&hdmi->edid_data); 1240 dw_hdmi_qp_selete_output(&hdmi->edid_data, conn, &bus_format, 1241 overscan, hdmi->dev_type, 1242 hdmi->output_bus_format_rgb, hdmi->rk_hdmi, 1243 state); 1244 1245 *mode = *hdmi->edid_data.preferred_mode; 1246 hdmi->vic = drm_match_cea_mode(mode); 1247 1248 printf("mode:%dx%d bus_format:0x%x\n", mode->hdisplay, mode->vdisplay, bus_format); 1249 conn_state->bus_format = bus_format; 1250 hdmi->hdmi_data.enc_in_bus_format = bus_format; 1251 hdmi->hdmi_data.enc_out_bus_format = bus_format; 1252 1253 switch (bus_format) { 1254 case MEDIA_BUS_FMT_UYVY10_1X20: 1255 conn_state->bus_format = MEDIA_BUS_FMT_YUV10_1X30; 1256 hdmi->hdmi_data.enc_in_bus_format = 1257 MEDIA_BUS_FMT_YUV10_1X30; 1258 break; 1259 case MEDIA_BUS_FMT_UYVY8_1X16: 1260 conn_state->bus_format = MEDIA_BUS_FMT_YUV8_1X24; 1261 hdmi->hdmi_data.enc_in_bus_format = 1262 MEDIA_BUS_FMT_YUV8_1X24; 1263 break; 1264 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1265 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1266 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420; 1267 break; 1268 } 1269 1270 if (hdmi->vic == 6 || hdmi->vic == 7 || hdmi->vic == 21 || 1271 hdmi->vic == 22 || hdmi->vic == 2 || hdmi->vic == 3 || 1272 hdmi->vic == 17 || hdmi->vic == 18) 1273 enc_out_encoding = V4L2_YCBCR_ENC_601; 1274 else 1275 enc_out_encoding = V4L2_YCBCR_ENC_709; 1276 1277 if (enc_out_encoding == V4L2_YCBCR_ENC_BT2020) 1278 conn_state->color_space = V4L2_COLORSPACE_BT2020; 1279 else if (bus_format == MEDIA_BUS_FMT_RGB888_1X24 || 1280 bus_format == MEDIA_BUS_FMT_RGB101010_1X30) 1281 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 1282 else if (enc_out_encoding == V4L2_YCBCR_ENC_709) 1283 conn_state->color_space = V4L2_COLORSPACE_REC709; 1284 else 1285 conn_state->color_space = V4L2_COLORSPACE_SMPTE170M; 1286 1287 return 0; 1288 } 1289 1290 int rockchip_dw_hdmi_qp_detect(struct rockchip_connector *conn, struct display_state *state) 1291 { 1292 int ret; 1293 struct dw_hdmi_qp *hdmi = conn->data; 1294 1295 if (!hdmi) 1296 return -EFAULT; 1297 1298 ret = dw_hdmi_detect_hotplug(hdmi, state); 1299 1300 return ret; 1301 } 1302 1303 int rockchip_dw_hdmi_qp_get_edid(struct rockchip_connector *conn, struct display_state *state) 1304 { 1305 int ret; 1306 struct connector_state *conn_state = &state->conn_state; 1307 struct dw_hdmi_qp *hdmi = conn->data; 1308 1309 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid); 1310 1311 return ret; 1312 } 1313