1 /* 2 * Analogix DP (Display port) core register interface driver. 3 * 4 * Copyright (C) 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 5 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 6 * Author: Jingoo Han <jg1.han@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 */ 13 14 #include <config.h> 15 #include <common.h> 16 #include <errno.h> 17 #include <malloc.h> 18 #include <asm/unaligned.h> 19 #include <linux/list.h> 20 #include <dm/device.h> 21 #include <syscon.h> 22 #include <asm/io.h> 23 #include <asm/gpio.h> 24 #include <linux/iopoll.h> 25 26 #include "rockchip_display.h" 27 #include "rockchip_crtc.h" 28 #include "rockchip_connector.h" 29 #include "analogix_dp.h" 30 31 #define COMMON_INT_MASK_1 0 32 #define COMMON_INT_MASK_2 0 33 #define COMMON_INT_MASK_3 0 34 #define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG) 35 #define INT_STA_MASK INT_HPD 36 37 static void analogix_dp_write(struct analogix_dp_device *dp, u32 reg, u32 val) 38 { 39 readl(dp->reg_base); 40 writel(val, dp->reg_base + reg); 41 writel(val, dp->reg_base + reg); 42 } 43 44 static u32 analogix_dp_read(struct analogix_dp_device *dp, u32 reg) 45 { 46 readl(dp->reg_base + reg); 47 48 return readl(dp->reg_base + reg); 49 } 50 51 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable) 52 { 53 u32 reg; 54 55 if (enable) { 56 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 57 reg |= HDCP_VIDEO_MUTE; 58 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 59 } else { 60 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 61 reg &= ~HDCP_VIDEO_MUTE; 62 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 63 } 64 } 65 66 void analogix_dp_stop_video(struct analogix_dp_device *dp) 67 { 68 u32 reg; 69 70 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 71 reg &= ~VIDEO_EN; 72 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 73 } 74 75 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable) 76 { 77 u32 reg; 78 79 if (enable) 80 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 | 81 LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3; 82 else 83 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | 84 LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0; 85 86 analogix_dp_write(dp, ANALOGIX_DP_LANE_MAP, reg); 87 } 88 89 void analogix_dp_init_analog_param(struct analogix_dp_device *dp) 90 { 91 u32 reg; 92 93 reg = TX_TERMINAL_CTRL_50_OHM; 94 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_1, reg); 95 96 reg = SEL_24M | TX_DVDD_BIT_1_0625V; 97 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_2, reg); 98 99 if (dp->plat_data.dev_type == ROCKCHIP_DP) { 100 reg = REF_CLK_24M; 101 if (dp->plat_data.subdev_type == RK3288_DP || 102 dp->plat_data.subdev_type == RK3368_EDP) 103 reg ^= REF_CLK_MASK; 104 105 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_1, reg); 106 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_2, 0x95); 107 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_3, 0x40); 108 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_4, 0x58); 109 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_5, 0x22); 110 } 111 112 reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO; 113 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_3, reg); 114 115 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | 116 TX_CUR1_2X | TX_CUR_16_MA; 117 analogix_dp_write(dp, ANALOGIX_DP_PLL_FILTER_CTL_1, reg); 118 119 reg = CH3_AMP_400_MV | CH2_AMP_400_MV | 120 CH1_AMP_400_MV | CH0_AMP_400_MV; 121 analogix_dp_write(dp, ANALOGIX_DP_TX_AMP_TUNING_CTL, reg); 122 } 123 124 void analogix_dp_init_interrupt(struct analogix_dp_device *dp) 125 { 126 /* Set interrupt pin assertion polarity as high */ 127 analogix_dp_write(dp, ANALOGIX_DP_INT_CTL, INT_POL1 | INT_POL0); 128 129 /* Clear pending regisers */ 130 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, 0xff); 131 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_2, 0x4f); 132 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_3, 0xe0); 133 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_4, 0xe7); 134 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, 0x63); 135 136 /* 0:mask,1: unmask */ 137 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_1, 0x00); 138 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_2, 0x00); 139 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_3, 0x00); 140 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, 0x00); 141 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, 0x00); 142 } 143 144 void analogix_dp_reset(struct analogix_dp_device *dp) 145 { 146 u32 reg; 147 148 analogix_dp_stop_video(dp); 149 analogix_dp_enable_video_mute(dp, 0); 150 151 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | 152 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | 153 HDCP_FUNC_EN_N | SW_FUNC_EN_N; 154 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg); 155 156 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | 157 SERDES_FIFO_FUNC_EN_N | 158 LS_CLK_DOMAIN_FUNC_EN_N; 159 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 160 161 udelay(30); 162 163 analogix_dp_lane_swap(dp, 0); 164 165 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, 0x0); 166 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, 0x40); 167 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, 0x0); 168 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, 0x0); 169 170 analogix_dp_write(dp, ANALOGIX_DP_PKT_SEND_CTL, 0x0); 171 analogix_dp_write(dp, ANALOGIX_DP_HDCP_CTL, 0x0); 172 173 analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_L, 0x5e); 174 analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_H, 0x1a); 175 176 analogix_dp_write(dp, ANALOGIX_DP_LINK_DEBUG_CTL, 0x10); 177 178 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, 0x0); 179 180 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_FIFO_THRD, 0x0); 181 analogix_dp_write(dp, ANALOGIX_DP_AUDIO_MARGIN, 0x20); 182 183 analogix_dp_write(dp, ANALOGIX_DP_M_VID_GEN_FILTER_TH, 0x4); 184 analogix_dp_write(dp, ANALOGIX_DP_M_AUD_GEN_FILTER_TH, 0x2); 185 186 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, 0x00000101); 187 } 188 189 void analogix_dp_swreset(struct analogix_dp_device *dp) 190 { 191 analogix_dp_write(dp, ANALOGIX_DP_TX_SW_RESET, RESET_DP_TX); 192 } 193 194 void analogix_dp_config_interrupt(struct analogix_dp_device *dp) 195 { 196 u32 reg; 197 198 /* 0: mask, 1: unmask */ 199 reg = COMMON_INT_MASK_1; 200 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_1, reg); 201 202 reg = COMMON_INT_MASK_2; 203 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_2, reg); 204 205 reg = COMMON_INT_MASK_3; 206 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_3, reg); 207 208 reg = COMMON_INT_MASK_4; 209 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg); 210 211 reg = INT_STA_MASK; 212 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg); 213 } 214 215 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp) 216 { 217 u32 reg; 218 219 /* 0: mask, 1: unmask */ 220 reg = analogix_dp_read(dp, ANALOGIX_DP_COMMON_INT_MASK_4); 221 reg &= ~COMMON_INT_MASK_4; 222 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg); 223 224 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA_MASK); 225 reg &= ~INT_STA_MASK; 226 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg); 227 } 228 229 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp) 230 { 231 u32 reg; 232 233 /* 0: mask, 1: unmask */ 234 reg = COMMON_INT_MASK_4; 235 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg); 236 237 reg = INT_STA_MASK; 238 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg); 239 } 240 241 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp) 242 { 243 u32 reg; 244 245 reg = analogix_dp_read(dp, ANALOGIX_DP_DEBUG_CTL); 246 if (reg & PLL_LOCK) 247 return PLL_LOCKED; 248 else 249 return PLL_UNLOCKED; 250 } 251 252 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable) 253 { 254 u32 reg; 255 256 if (enable) { 257 reg = analogix_dp_read(dp, ANALOGIX_DP_PLL_CTL); 258 reg |= DP_PLL_PD; 259 analogix_dp_write(dp, ANALOGIX_DP_PLL_CTL, reg); 260 } else { 261 reg = analogix_dp_read(dp, ANALOGIX_DP_PLL_CTL); 262 reg &= ~DP_PLL_PD; 263 analogix_dp_write(dp, ANALOGIX_DP_PLL_CTL, reg); 264 } 265 } 266 267 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 268 enum analog_power_block block, 269 bool enable) 270 { 271 u32 reg; 272 u32 phy_pd_addr = ANALOGIX_DP_PHY_PD; 273 274 if (dp->plat_data.dev_type == ROCKCHIP_DP) 275 phy_pd_addr = ANALOGIX_DP_PD; 276 277 switch (block) { 278 case AUX_BLOCK: 279 if (enable) { 280 reg = analogix_dp_read(dp, phy_pd_addr); 281 reg |= AUX_PD; 282 analogix_dp_write(dp, phy_pd_addr, reg); 283 } else { 284 reg = analogix_dp_read(dp, phy_pd_addr); 285 reg &= ~AUX_PD; 286 analogix_dp_write(dp, phy_pd_addr, reg); 287 } 288 break; 289 case CH0_BLOCK: 290 if (enable) { 291 reg = analogix_dp_read(dp, phy_pd_addr); 292 reg |= CH0_PD; 293 analogix_dp_write(dp, phy_pd_addr, reg); 294 } else { 295 reg = analogix_dp_read(dp, phy_pd_addr); 296 reg &= ~CH0_PD; 297 analogix_dp_write(dp, phy_pd_addr, reg); 298 } 299 break; 300 case CH1_BLOCK: 301 if (enable) { 302 reg = analogix_dp_read(dp, phy_pd_addr); 303 reg |= CH1_PD; 304 analogix_dp_write(dp, phy_pd_addr, reg); 305 } else { 306 reg = analogix_dp_read(dp, phy_pd_addr); 307 reg &= ~CH1_PD; 308 analogix_dp_write(dp, phy_pd_addr, reg); 309 } 310 break; 311 case CH2_BLOCK: 312 if (enable) { 313 reg = analogix_dp_read(dp, phy_pd_addr); 314 reg |= CH2_PD; 315 analogix_dp_write(dp, phy_pd_addr, reg); 316 } else { 317 reg = analogix_dp_read(dp, phy_pd_addr); 318 reg &= ~CH2_PD; 319 analogix_dp_write(dp, phy_pd_addr, reg); 320 } 321 break; 322 case CH3_BLOCK: 323 if (enable) { 324 reg = analogix_dp_read(dp, phy_pd_addr); 325 reg |= CH3_PD; 326 analogix_dp_write(dp, phy_pd_addr, reg); 327 } else { 328 reg = analogix_dp_read(dp, phy_pd_addr); 329 reg &= ~CH3_PD; 330 analogix_dp_write(dp, phy_pd_addr, reg); 331 } 332 break; 333 case ANALOG_TOTAL: 334 if (enable) { 335 reg = analogix_dp_read(dp, phy_pd_addr); 336 reg |= DP_PHY_PD; 337 analogix_dp_write(dp, phy_pd_addr, reg); 338 } else { 339 reg = analogix_dp_read(dp, phy_pd_addr); 340 reg &= ~DP_PHY_PD; 341 analogix_dp_write(dp, phy_pd_addr, reg); 342 } 343 break; 344 case POWER_ALL: 345 if (enable) { 346 reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD | 347 CH1_PD | CH0_PD; 348 analogix_dp_write(dp, phy_pd_addr, reg); 349 } else { 350 analogix_dp_write(dp, phy_pd_addr, 0x00); 351 } 352 break; 353 default: 354 break; 355 } 356 } 357 358 void analogix_dp_init_analog_func(struct analogix_dp_device *dp) 359 { 360 u32 reg; 361 362 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 363 364 reg = PLL_LOCK_CHG; 365 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, reg); 366 367 reg = analogix_dp_read(dp, ANALOGIX_DP_DEBUG_CTL); 368 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); 369 analogix_dp_write(dp, ANALOGIX_DP_DEBUG_CTL, reg); 370 371 /* Power up PLL */ 372 analogix_dp_set_pll_power_down(dp, 0); 373 374 /* Enable Serdes FIFO function and Link symbol clock domain module */ 375 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2); 376 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N 377 | AUX_FUNC_EN_N); 378 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 379 } 380 381 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp) 382 { 383 u32 reg; 384 385 if (dm_gpio_is_valid(&dp->hpd_gpio)) 386 return; 387 388 reg = HOTPLUG_CHG | HPD_LOST | PLUG; 389 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_4, reg); 390 391 reg = INT_HPD; 392 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg); 393 } 394 395 void analogix_dp_init_hpd(struct analogix_dp_device *dp) 396 { 397 u32 reg; 398 399 if (dm_gpio_is_valid(&dp->hpd_gpio)) 400 return; 401 402 analogix_dp_clear_hotplug_interrupts(dp); 403 404 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 405 reg &= ~(F_HPD | HPD_CTRL); 406 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 407 } 408 409 void analogix_dp_force_hpd(struct analogix_dp_device *dp) 410 { 411 u32 reg; 412 413 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 414 reg |= (F_HPD | HPD_CTRL); 415 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 416 } 417 418 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp) 419 { 420 u32 reg; 421 422 if (dm_gpio_is_valid(&dp->hpd_gpio)) { 423 reg = dm_gpio_get_value(&dp->hpd_gpio); 424 if (reg) 425 return DP_IRQ_TYPE_HP_CABLE_IN; 426 else 427 return DP_IRQ_TYPE_HP_CABLE_OUT; 428 } else { 429 /* Parse hotplug interrupt status register */ 430 reg = analogix_dp_read(dp, ANALOGIX_DP_COMMON_INT_STA_4); 431 432 if (reg & PLUG) 433 return DP_IRQ_TYPE_HP_CABLE_IN; 434 435 if (reg & HPD_LOST) 436 return DP_IRQ_TYPE_HP_CABLE_OUT; 437 438 if (reg & HOTPLUG_CHG) 439 return DP_IRQ_TYPE_HP_CHANGE; 440 441 return DP_IRQ_TYPE_UNKNOWN; 442 } 443 } 444 445 void analogix_dp_reset_aux(struct analogix_dp_device *dp) 446 { 447 u32 reg; 448 449 /* Disable AUX channel module */ 450 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2); 451 reg |= AUX_FUNC_EN_N; 452 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 453 } 454 455 void analogix_dp_init_aux(struct analogix_dp_device *dp) 456 { 457 u32 reg; 458 459 /* Clear inerrupts related to AUX channel */ 460 reg = RPLY_RECEIV | AUX_ERR; 461 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg); 462 463 analogix_dp_reset_aux(dp); 464 465 /* Disable AUX transaction H/W retry */ 466 if (dp->plat_data.dev_type == ROCKCHIP_DP) 467 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) | 468 AUX_HW_RETRY_COUNT_SEL(3) | 469 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; 470 else 471 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | 472 AUX_HW_RETRY_COUNT_SEL(0) | 473 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; 474 analogix_dp_write(dp, ANALOGIX_DP_AUX_HW_RETRY_CTL, reg); 475 476 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ 477 reg = DEFER_CTRL_EN | DEFER_COUNT(1); 478 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_DEFER_CTL, reg); 479 480 /* Enable AUX channel module */ 481 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2); 482 reg &= ~AUX_FUNC_EN_N; 483 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 484 } 485 486 int analogix_dp_detect(struct analogix_dp_device *dp) 487 { 488 u32 reg; 489 490 if (dm_gpio_is_valid(&dp->hpd_gpio)) 491 return dm_gpio_get_value(&dp->hpd_gpio); 492 493 if (dp->force_hpd) 494 analogix_dp_force_hpd(dp); 495 496 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 497 if (reg & HPD_STATUS) 498 return 1; 499 500 return 0; 501 } 502 503 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp) 504 { 505 u32 reg; 506 507 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_1); 508 reg &= ~SW_FUNC_EN_N; 509 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg); 510 } 511 512 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp) 513 { 514 int reg; 515 int retval = 0; 516 int timeout_loop = 0; 517 518 /* Enable AUX CH operation */ 519 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_CTL_2); 520 reg |= AUX_EN; 521 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_2, reg); 522 523 /* Is AUX CH command reply received? */ 524 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA); 525 while (!(reg & RPLY_RECEIV)) { 526 timeout_loop++; 527 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { 528 dev_err(dp->dev, "AUX CH command reply failed!\n"); 529 return -ETIMEDOUT; 530 } 531 532 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA); 533 udelay(11); 534 } 535 536 /* Clear interrupt source for AUX CH command reply */ 537 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg); 538 539 /* Clear interrupt source for AUX CH access error */ 540 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA); 541 if (reg & AUX_ERR) { 542 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, AUX_ERR); 543 return -EREMOTEIO; 544 } 545 546 /* Check AUX CH error access status */ 547 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_STA); 548 if ((reg & AUX_STATUS_MASK) != 0) { 549 dev_err(dp->dev, 550 "AUX CH error happens: %d\n", reg & AUX_STATUS_MASK); 551 return -EREMOTEIO; 552 } 553 554 return retval; 555 } 556 557 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp, 558 unsigned int reg_addr, 559 unsigned char data) 560 { 561 u32 reg; 562 int i; 563 int retval; 564 565 for (i = 0; i < 3; i++) { 566 /* Clear AUX CH data buffer */ 567 reg = BUF_CLR; 568 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 569 570 /* Select DPCD device address */ 571 reg = AUX_ADDR_7_0(reg_addr); 572 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 573 reg = AUX_ADDR_15_8(reg_addr); 574 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); 575 reg = AUX_ADDR_19_16(reg_addr); 576 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); 577 578 /* Write data buffer */ 579 reg = (unsigned int)data; 580 analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0, reg); 581 582 /* 583 * Set DisplayPort transaction and write 1 byte 584 * If bit 3 is 1, DisplayPort transaction. 585 * If Bit 3 is 0, I2C transaction. 586 */ 587 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; 588 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 589 590 /* Start AUX transaction */ 591 retval = analogix_dp_start_aux_transaction(dp); 592 if (retval == 0) 593 break; 594 } 595 596 return retval; 597 } 598 599 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp, 600 unsigned int reg_addr, 601 unsigned char *data) 602 { 603 u32 reg; 604 int i; 605 int retval; 606 607 for (i = 0; i < 3; i++) { 608 /* Clear AUX CH data buffer */ 609 reg = BUF_CLR; 610 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 611 612 /* Select DPCD device address */ 613 reg = AUX_ADDR_7_0(reg_addr); 614 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 615 reg = AUX_ADDR_15_8(reg_addr); 616 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); 617 reg = AUX_ADDR_19_16(reg_addr); 618 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); 619 620 /* 621 * Set DisplayPort transaction and read 1 byte 622 * If bit 3 is 1, DisplayPort transaction. 623 * If Bit 3 is 0, I2C transaction. 624 */ 625 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; 626 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 627 628 /* Start AUX transaction */ 629 retval = analogix_dp_start_aux_transaction(dp); 630 if (retval == 0) 631 break; 632 } 633 634 /* Read data buffer */ 635 reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0); 636 *data = (unsigned char)(reg & 0xff); 637 638 return retval; 639 } 640 641 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp, 642 unsigned int reg_addr, 643 unsigned int count, 644 unsigned char data[]) 645 { 646 u32 reg; 647 unsigned int start_offset; 648 unsigned int cur_data_count; 649 unsigned int cur_data_idx; 650 int i; 651 int retval = 0; 652 653 /* Clear AUX CH data buffer */ 654 reg = BUF_CLR; 655 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 656 657 start_offset = 0; 658 while (start_offset < count) { 659 /* Buffer size of AUX CH is 16 * 4bytes */ 660 if ((count - start_offset) > 16) 661 cur_data_count = 16; 662 else 663 cur_data_count = count - start_offset; 664 665 for (i = 0; i < 3; i++) { 666 /* Select DPCD device address */ 667 reg = AUX_ADDR_7_0(reg_addr + start_offset); 668 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 669 reg = AUX_ADDR_15_8(reg_addr + start_offset); 670 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); 671 reg = AUX_ADDR_19_16(reg_addr + start_offset); 672 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); 673 674 for (cur_data_idx = 0; cur_data_idx < cur_data_count; 675 cur_data_idx++) { 676 reg = data[start_offset + cur_data_idx]; 677 analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0 + 678 4 * cur_data_idx, reg); 679 } 680 681 /* 682 * Set DisplayPort transaction and write 683 * If bit 3 is 1, DisplayPort transaction. 684 * If Bit 3 is 0, I2C transaction. 685 */ 686 reg = AUX_LENGTH(cur_data_count) | 687 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; 688 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 689 690 /* Start AUX transaction */ 691 retval = analogix_dp_start_aux_transaction(dp); 692 if (retval == 0) 693 break; 694 } 695 696 start_offset += cur_data_count; 697 } 698 699 return retval; 700 } 701 702 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp, 703 unsigned int reg_addr, 704 unsigned int count, 705 unsigned char data[]) 706 { 707 u32 reg; 708 unsigned int start_offset; 709 unsigned int cur_data_count; 710 unsigned int cur_data_idx; 711 int i; 712 int retval = 0; 713 714 /* Clear AUX CH data buffer */ 715 reg = BUF_CLR; 716 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 717 718 start_offset = 0; 719 while (start_offset < count) { 720 /* Buffer size of AUX CH is 16 * 4bytes */ 721 if ((count - start_offset) > 16) 722 cur_data_count = 16; 723 else 724 cur_data_count = count - start_offset; 725 726 /* AUX CH Request Transaction process */ 727 for (i = 0; i < 3; i++) { 728 /* Select DPCD device address */ 729 reg = AUX_ADDR_7_0(reg_addr + start_offset); 730 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 731 reg = AUX_ADDR_15_8(reg_addr + start_offset); 732 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); 733 reg = AUX_ADDR_19_16(reg_addr + start_offset); 734 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); 735 736 /* 737 * Set DisplayPort transaction and read 738 * If bit 3 is 1, DisplayPort transaction. 739 * If Bit 3 is 0, I2C transaction. 740 */ 741 reg = AUX_LENGTH(cur_data_count) | 742 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; 743 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 744 745 /* Start AUX transaction */ 746 retval = analogix_dp_start_aux_transaction(dp); 747 if (retval == 0) 748 break; 749 } 750 751 for (cur_data_idx = 0; cur_data_idx < cur_data_count; 752 cur_data_idx++) { 753 reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0 754 + 4 * cur_data_idx); 755 data[start_offset + cur_data_idx] = 756 (unsigned char)reg; 757 } 758 759 start_offset += cur_data_count; 760 } 761 762 return retval; 763 } 764 765 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp, 766 unsigned int device_addr, 767 unsigned int reg_addr) 768 { 769 u32 reg; 770 int retval; 771 772 /* Set EDID device address */ 773 reg = device_addr; 774 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 775 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, 0x0); 776 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, 0x0); 777 778 /* Set offset from base address of EDID device */ 779 analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0, reg_addr); 780 781 /* 782 * Set I2C transaction and write address 783 * If bit 3 is 1, DisplayPort transaction. 784 * If Bit 3 is 0, I2C transaction. 785 */ 786 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT | 787 AUX_TX_COMM_WRITE; 788 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 789 790 /* Start AUX transaction */ 791 retval = analogix_dp_start_aux_transaction(dp); 792 if (retval < 0) 793 return retval; 794 795 return 0; 796 } 797 798 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp, 799 unsigned int device_addr, 800 unsigned int reg_addr, 801 unsigned int *data) 802 { 803 u32 reg; 804 int i; 805 int retval; 806 807 for (i = 0; i < 3; i++) { 808 /* Clear AUX CH data buffer */ 809 reg = BUF_CLR; 810 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 811 812 /* Select EDID device */ 813 retval = analogix_dp_select_i2c_device(dp, device_addr, 814 reg_addr); 815 if (retval != 0) 816 continue; 817 818 /* 819 * Set I2C transaction and read data 820 * If bit 3 is 1, DisplayPort transaction. 821 * If Bit 3 is 0, I2C transaction. 822 */ 823 reg = AUX_TX_COMM_I2C_TRANSACTION | 824 AUX_TX_COMM_READ; 825 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 826 827 /* Start AUX transaction */ 828 retval = analogix_dp_start_aux_transaction(dp); 829 if (retval == 0) 830 break; 831 } 832 833 /* Read data */ 834 if (retval == 0) 835 *data = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0); 836 837 return retval; 838 } 839 840 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp, 841 unsigned int device_addr, 842 unsigned int reg_addr, 843 unsigned int count, 844 unsigned char edid[]) 845 { 846 u32 reg; 847 unsigned int i, j; 848 unsigned int cur_data_idx; 849 unsigned int defer = 0; 850 int retval = 0; 851 852 for (i = 0; i < count; i += 16) { 853 for (j = 0; j < 3; j++) { 854 /* Clear AUX CH data buffer */ 855 reg = BUF_CLR; 856 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 857 858 /* Set normal AUX CH command */ 859 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_CTL_2); 860 reg &= ~ADDR_ONLY; 861 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_2, reg); 862 863 /* 864 * If Rx sends defer, Tx sends only reads 865 * request without sending address 866 */ 867 if (!defer) 868 retval = analogix_dp_select_i2c_device(dp, 869 device_addr, reg_addr + i); 870 else 871 defer = 0; 872 873 if (retval == 0) { 874 /* 875 * Set I2C transaction and write data 876 * If bit 3 is 1, DisplayPort transaction. 877 * If Bit 3 is 0, I2C transaction. 878 */ 879 reg = AUX_LENGTH(16) | 880 AUX_TX_COMM_I2C_TRANSACTION | 881 AUX_TX_COMM_READ; 882 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, 883 reg); 884 885 /* Start AUX transaction */ 886 retval = analogix_dp_start_aux_transaction(dp); 887 if (retval == 0) 888 break; 889 } 890 /* Check if Rx sends defer */ 891 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_RX_COMM); 892 if (reg == AUX_RX_COMM_AUX_DEFER || 893 reg == AUX_RX_COMM_I2C_DEFER) { 894 dev_dbg(dp->dev, "Defer: %d\n\n", reg); 895 defer = 1; 896 } 897 } 898 899 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) { 900 reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0 901 + 4 * cur_data_idx); 902 edid[i + cur_data_idx] = (unsigned char)reg; 903 } 904 } 905 906 return retval; 907 } 908 909 bool analogix_dp_ssc_supported(struct analogix_dp_device *dp) 910 { 911 /* Check if SSC is supported by both sides */ 912 return dp->plat_data.ssc && dp->link_train.ssc; 913 } 914 915 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype) 916 { 917 union phy_configure_opts phy_cfg; 918 u32 reg, status; 919 int ret; 920 921 reg = bwtype; 922 if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62)) 923 analogix_dp_write(dp, ANALOGIX_DP_LINK_BW_SET, reg); 924 925 phy_cfg.dp.lanes = dp->link_train.lane_count; 926 phy_cfg.dp.link_rate = 927 drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100; 928 phy_cfg.dp.ssc = analogix_dp_ssc_supported(dp); 929 phy_cfg.dp.set_lanes = false; 930 phy_cfg.dp.set_rate = true; 931 phy_cfg.dp.set_voltages = false; 932 ret = generic_phy_configure(&dp->phy, &phy_cfg); 933 if (ret) { 934 dev_err(dp->dev, "%s: phy_configure() failed: %d\n", 935 __func__, ret); 936 return; 937 } 938 939 ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status, 940 status != PLL_UNLOCKED, 941 120 * DP_TIMEOUT_LOOP_COUNT); 942 if (ret) { 943 dev_err(dp->dev, "Wait for pll lock failed %d\n", ret); 944 return; 945 } 946 } 947 948 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype) 949 { 950 u32 reg; 951 952 reg = analogix_dp_read(dp, ANALOGIX_DP_LINK_BW_SET); 953 *bwtype = reg; 954 } 955 956 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count) 957 { 958 union phy_configure_opts phy_cfg; 959 u32 reg; 960 int ret; 961 962 reg = count; 963 analogix_dp_write(dp, ANALOGIX_DP_LANE_COUNT_SET, reg); 964 965 phy_cfg.dp.lanes = dp->link_train.lane_count; 966 phy_cfg.dp.set_lanes = true; 967 phy_cfg.dp.set_rate = false; 968 phy_cfg.dp.set_voltages = false; 969 ret = generic_phy_configure(&dp->phy, &phy_cfg); 970 if (ret) { 971 dev_err(dp->dev, "%s: phy_configure() failed: %d\n", 972 __func__, ret); 973 return; 974 } 975 } 976 977 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count) 978 { 979 u32 reg; 980 981 reg = analogix_dp_read(dp, ANALOGIX_DP_LANE_COUNT_SET); 982 *count = reg; 983 } 984 985 void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp) 986 { 987 union phy_configure_opts phy_cfg; 988 u8 lane; 989 int ret; 990 991 for (lane = 0; lane < dp->link_train.lane_count; lane++) { 992 u8 training_lane = dp->link_train.training_lane[lane]; 993 u8 vs, pe; 994 995 analogix_dp_write(dp, 996 ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane, 997 dp->link_train.training_lane[lane]); 998 999 vs = (training_lane >> DP_TRAIN_VOLTAGE_SWING_SHIFT) & 1000 DP_TRAIN_VOLTAGE_SWING_MASK; 1001 pe = (training_lane >> DP_TRAIN_PRE_EMPHASIS_SHIFT) & 1002 DP_TRAIN_PRE_EMPHASIS_MASK; 1003 phy_cfg.dp.voltage[lane] = vs; 1004 phy_cfg.dp.pre[lane] = pe; 1005 } 1006 1007 phy_cfg.dp.lanes = dp->link_train.lane_count; 1008 phy_cfg.dp.set_lanes = false; 1009 phy_cfg.dp.set_rate = false; 1010 phy_cfg.dp.set_voltages = true; 1011 ret = generic_phy_configure(&dp->phy, &phy_cfg); 1012 if (ret) { 1013 dev_err(dp->dev, "%s: phy_configure() failed: %d\n", 1014 __func__, ret); 1015 return; 1016 } 1017 } 1018 1019 u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane) 1020 { 1021 return analogix_dp_read(dp, 1022 ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane); 1023 } 1024 1025 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, 1026 bool enable) 1027 { 1028 u32 reg; 1029 1030 if (enable) { 1031 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 1032 reg |= ENHANCED; 1033 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 1034 } else { 1035 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 1036 reg &= ~ENHANCED; 1037 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 1038 } 1039 } 1040 1041 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, 1042 enum pattern_set pattern) 1043 { 1044 u32 reg; 1045 1046 switch (pattern) { 1047 case PRBS7: 1048 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7; 1049 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1050 break; 1051 case D10_2: 1052 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2; 1053 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1054 break; 1055 case TRAINING_PTN1: 1056 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1; 1057 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1058 break; 1059 case TRAINING_PTN2: 1060 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2; 1061 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1062 break; 1063 case DP_NONE: 1064 reg = SCRAMBLING_ENABLE | 1065 LINK_QUAL_PATTERN_SET_DISABLE | 1066 SW_TRAINING_PATTERN_SET_NORMAL; 1067 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1068 break; 1069 default: 1070 break; 1071 } 1072 } 1073 1074 void analogix_dp_reset_macro(struct analogix_dp_device *dp) 1075 { 1076 u32 reg; 1077 1078 reg = analogix_dp_read(dp, ANALOGIX_DP_PHY_TEST); 1079 reg |= MACRO_RST; 1080 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, reg); 1081 1082 /* 10 us is the minimum reset time. */ 1083 udelay(20); 1084 1085 reg &= ~MACRO_RST; 1086 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, reg); 1087 } 1088 1089 void analogix_dp_init_video(struct analogix_dp_device *dp) 1090 { 1091 u32 reg; 1092 1093 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; 1094 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, reg); 1095 1096 reg = 0x0; 1097 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, reg); 1098 1099 reg = CHA_CRI(4) | CHA_CTRL; 1100 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, reg); 1101 1102 reg = 0x0; 1103 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 1104 1105 reg = VID_HRES_TH(2) | VID_VRES_TH(0); 1106 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_8, reg); 1107 } 1108 1109 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp) 1110 { 1111 u32 reg; 1112 1113 /* Configure the input color depth, color space, dynamic range */ 1114 reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) | 1115 (dp->video_info.color_depth << IN_BPC_SHIFT) | 1116 (dp->video_info.color_space << IN_COLOR_F_SHIFT); 1117 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_2, reg); 1118 1119 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */ 1120 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_3); 1121 reg &= ~IN_YC_COEFFI_MASK; 1122 if (dp->video_info.ycbcr_coeff) 1123 reg |= IN_YC_COEFFI_ITU709; 1124 else 1125 reg |= IN_YC_COEFFI_ITU601; 1126 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_3, reg); 1127 } 1128 1129 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp) 1130 { 1131 u32 reg; 1132 1133 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_1); 1134 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, reg); 1135 1136 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_1); 1137 1138 if (!(reg & DET_STA)) 1139 return -EINVAL; 1140 1141 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_2); 1142 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, reg); 1143 1144 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_2); 1145 1146 if (reg & CHA_STA) 1147 return -EINVAL; 1148 1149 return 0; 1150 } 1151 1152 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, 1153 enum clock_recovery_m_value_type type, 1154 u32 m_value, u32 n_value) 1155 { 1156 u32 reg; 1157 1158 if (type == REGISTER_M) { 1159 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 1160 reg |= FIX_M_VID; 1161 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 1162 reg = m_value & 0xff; 1163 analogix_dp_write(dp, ANALOGIX_DP_M_VID_0, reg); 1164 reg = (m_value >> 8) & 0xff; 1165 analogix_dp_write(dp, ANALOGIX_DP_M_VID_1, reg); 1166 reg = (m_value >> 16) & 0xff; 1167 analogix_dp_write(dp, ANALOGIX_DP_M_VID_2, reg); 1168 1169 reg = n_value & 0xff; 1170 analogix_dp_write(dp, ANALOGIX_DP_N_VID_0, reg); 1171 reg = (n_value >> 8) & 0xff; 1172 analogix_dp_write(dp, ANALOGIX_DP_N_VID_1, reg); 1173 reg = (n_value >> 16) & 0xff; 1174 analogix_dp_write(dp, ANALOGIX_DP_N_VID_2, reg); 1175 } else { 1176 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 1177 reg &= ~FIX_M_VID; 1178 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 1179 1180 analogix_dp_write(dp, ANALOGIX_DP_N_VID_0, 0x00); 1181 analogix_dp_write(dp, ANALOGIX_DP_N_VID_1, 0x80); 1182 analogix_dp_write(dp, ANALOGIX_DP_N_VID_2, 0x00); 1183 } 1184 } 1185 1186 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type) 1187 { 1188 u32 reg; 1189 1190 if (type == VIDEO_TIMING_FROM_CAPTURE) { 1191 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1192 reg &= ~FORMAT_SEL; 1193 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1194 } else { 1195 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1196 reg |= FORMAT_SEL; 1197 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1198 } 1199 } 1200 1201 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable) 1202 { 1203 u32 reg; 1204 1205 if (enable) { 1206 reg = analogix_dp_read(dp, ANALOGIX_DP_SOC_GENERAL_CTL); 1207 reg &= ~VIDEO_MODE_MASK; 1208 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE; 1209 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg); 1210 } else { 1211 reg = analogix_dp_read(dp, ANALOGIX_DP_SOC_GENERAL_CTL); 1212 reg &= ~VIDEO_MODE_MASK; 1213 reg |= VIDEO_MODE_SLAVE_MODE; 1214 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg); 1215 } 1216 } 1217 1218 void analogix_dp_start_video(struct analogix_dp_device *dp) 1219 { 1220 u32 reg; 1221 1222 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 1223 reg |= VIDEO_EN; 1224 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 1225 } 1226 1227 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp) 1228 { 1229 u32 reg; 1230 1231 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 1232 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 1233 1234 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 1235 if (!(reg & STRM_VALID)) 1236 return -EINVAL; 1237 1238 return 0; 1239 } 1240 1241 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp) 1242 { 1243 u32 reg; 1244 1245 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_1); 1246 reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N); 1247 reg |= MASTER_VID_FUNC_EN_N; 1248 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg); 1249 1250 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1251 reg &= ~INTERACE_SCAN_CFG; 1252 reg |= (dp->video_info.interlaced << 2); 1253 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1254 1255 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1256 reg &= ~VSYNC_POLARITY_CFG; 1257 reg |= (dp->video_info.v_sync_polarity << 1); 1258 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1259 1260 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1261 reg &= ~HSYNC_POLARITY_CFG; 1262 reg |= (dp->video_info.h_sync_polarity << 0); 1263 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1264 1265 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; 1266 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg); 1267 } 1268 1269 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp) 1270 { 1271 u32 reg; 1272 1273 reg = analogix_dp_read(dp, ANALOGIX_DP_TRAINING_PTN_SET); 1274 reg &= ~SCRAMBLING_DISABLE; 1275 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1276 } 1277 1278 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp) 1279 { 1280 u32 reg; 1281 1282 reg = analogix_dp_read(dp, ANALOGIX_DP_TRAINING_PTN_SET); 1283 reg |= SCRAMBLING_DISABLE; 1284 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1285 } 1286