1 /* 2 * Analogix DP (Display port) core register interface driver. 3 * 4 * Copyright (C) 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 5 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 6 * Author: Jingoo Han <jg1.han@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 */ 13 14 #include <config.h> 15 #include <common.h> 16 #include <errno.h> 17 #include <malloc.h> 18 #include <asm/unaligned.h> 19 #include <linux/list.h> 20 #include <dm/device.h> 21 #include <syscon.h> 22 #include <asm/io.h> 23 #include <asm/gpio.h> 24 25 #include "rockchip_display.h" 26 #include "rockchip_crtc.h" 27 #include "rockchip_connector.h" 28 #include "analogix_dp.h" 29 30 #define COMMON_INT_MASK_1 0 31 #define COMMON_INT_MASK_2 0 32 #define COMMON_INT_MASK_3 0 33 #define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG) 34 #define INT_STA_MASK INT_HPD 35 36 static void analogix_dp_write(struct analogix_dp_device *dp, u32 reg, u32 val) 37 { 38 readl(dp->reg_base); 39 writel(val, dp->reg_base + reg); 40 writel(val, dp->reg_base + reg); 41 } 42 43 static u32 analogix_dp_read(struct analogix_dp_device *dp, u32 reg) 44 { 45 readl(dp->reg_base + reg); 46 47 return readl(dp->reg_base + reg); 48 } 49 50 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable) 51 { 52 u32 reg; 53 54 if (enable) { 55 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 56 reg |= HDCP_VIDEO_MUTE; 57 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 58 } else { 59 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 60 reg &= ~HDCP_VIDEO_MUTE; 61 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 62 } 63 } 64 65 void analogix_dp_stop_video(struct analogix_dp_device *dp) 66 { 67 u32 reg; 68 69 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 70 reg &= ~VIDEO_EN; 71 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 72 } 73 74 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable) 75 { 76 u32 reg; 77 78 if (enable) 79 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 | 80 LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3; 81 else 82 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | 83 LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0; 84 85 analogix_dp_write(dp, ANALOGIX_DP_LANE_MAP, reg); 86 } 87 88 void analogix_dp_init_analog_param(struct analogix_dp_device *dp) 89 { 90 u32 reg; 91 92 reg = TX_TERMINAL_CTRL_50_OHM; 93 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_1, reg); 94 95 reg = SEL_24M | TX_DVDD_BIT_1_0625V; 96 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_2, reg); 97 98 if (dp->plat_data.dev_type == ROCKCHIP_DP) { 99 reg = REF_CLK_24M; 100 if (dp->plat_data.subdev_type == RK3288_DP || 101 dp->plat_data.subdev_type == RK3368_EDP) 102 reg ^= REF_CLK_MASK; 103 104 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_1, reg); 105 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_2, 0x95); 106 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_3, 0x40); 107 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_4, 0x58); 108 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_5, 0x22); 109 } 110 111 reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO; 112 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_3, reg); 113 114 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | 115 TX_CUR1_2X | TX_CUR_16_MA; 116 analogix_dp_write(dp, ANALOGIX_DP_PLL_FILTER_CTL_1, reg); 117 118 reg = CH3_AMP_400_MV | CH2_AMP_400_MV | 119 CH1_AMP_400_MV | CH0_AMP_400_MV; 120 analogix_dp_write(dp, ANALOGIX_DP_TX_AMP_TUNING_CTL, reg); 121 } 122 123 void analogix_dp_init_interrupt(struct analogix_dp_device *dp) 124 { 125 /* Set interrupt pin assertion polarity as high */ 126 analogix_dp_write(dp, ANALOGIX_DP_INT_CTL, INT_POL1 | INT_POL0); 127 128 /* Clear pending regisers */ 129 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, 0xff); 130 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_2, 0x4f); 131 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_3, 0xe0); 132 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_4, 0xe7); 133 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, 0x63); 134 135 /* 0:mask,1: unmask */ 136 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_1, 0x00); 137 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_2, 0x00); 138 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_3, 0x00); 139 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, 0x00); 140 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, 0x00); 141 } 142 143 void analogix_dp_reset(struct analogix_dp_device *dp) 144 { 145 u32 reg; 146 147 analogix_dp_stop_video(dp); 148 analogix_dp_enable_video_mute(dp, 0); 149 150 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | 151 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | 152 HDCP_FUNC_EN_N | SW_FUNC_EN_N; 153 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg); 154 155 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | 156 SERDES_FIFO_FUNC_EN_N | 157 LS_CLK_DOMAIN_FUNC_EN_N; 158 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 159 160 udelay(30); 161 162 analogix_dp_lane_swap(dp, 0); 163 164 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, 0x0); 165 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, 0x40); 166 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, 0x0); 167 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, 0x0); 168 169 analogix_dp_write(dp, ANALOGIX_DP_PKT_SEND_CTL, 0x0); 170 analogix_dp_write(dp, ANALOGIX_DP_HDCP_CTL, 0x0); 171 172 analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_L, 0x5e); 173 analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_H, 0x1a); 174 175 analogix_dp_write(dp, ANALOGIX_DP_LINK_DEBUG_CTL, 0x10); 176 177 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, 0x0); 178 179 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_FIFO_THRD, 0x0); 180 analogix_dp_write(dp, ANALOGIX_DP_AUDIO_MARGIN, 0x20); 181 182 analogix_dp_write(dp, ANALOGIX_DP_M_VID_GEN_FILTER_TH, 0x4); 183 analogix_dp_write(dp, ANALOGIX_DP_M_AUD_GEN_FILTER_TH, 0x2); 184 185 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, 0x00000101); 186 } 187 188 void analogix_dp_swreset(struct analogix_dp_device *dp) 189 { 190 analogix_dp_write(dp, ANALOGIX_DP_TX_SW_RESET, RESET_DP_TX); 191 } 192 193 void analogix_dp_config_interrupt(struct analogix_dp_device *dp) 194 { 195 u32 reg; 196 197 /* 0: mask, 1: unmask */ 198 reg = COMMON_INT_MASK_1; 199 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_1, reg); 200 201 reg = COMMON_INT_MASK_2; 202 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_2, reg); 203 204 reg = COMMON_INT_MASK_3; 205 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_3, reg); 206 207 reg = COMMON_INT_MASK_4; 208 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg); 209 210 reg = INT_STA_MASK; 211 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg); 212 } 213 214 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp) 215 { 216 u32 reg; 217 218 /* 0: mask, 1: unmask */ 219 reg = analogix_dp_read(dp, ANALOGIX_DP_COMMON_INT_MASK_4); 220 reg &= ~COMMON_INT_MASK_4; 221 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg); 222 223 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA_MASK); 224 reg &= ~INT_STA_MASK; 225 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg); 226 } 227 228 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp) 229 { 230 u32 reg; 231 232 /* 0: mask, 1: unmask */ 233 reg = COMMON_INT_MASK_4; 234 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg); 235 236 reg = INT_STA_MASK; 237 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg); 238 } 239 240 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp) 241 { 242 u32 reg; 243 244 reg = analogix_dp_read(dp, ANALOGIX_DP_DEBUG_CTL); 245 if (reg & PLL_LOCK) 246 return PLL_LOCKED; 247 else 248 return PLL_UNLOCKED; 249 } 250 251 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable) 252 { 253 u32 reg; 254 255 if (enable) { 256 reg = analogix_dp_read(dp, ANALOGIX_DP_PLL_CTL); 257 reg |= DP_PLL_PD; 258 analogix_dp_write(dp, ANALOGIX_DP_PLL_CTL, reg); 259 } else { 260 reg = analogix_dp_read(dp, ANALOGIX_DP_PLL_CTL); 261 reg &= ~DP_PLL_PD; 262 analogix_dp_write(dp, ANALOGIX_DP_PLL_CTL, reg); 263 } 264 } 265 266 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 267 enum analog_power_block block, 268 bool enable) 269 { 270 u32 reg; 271 u32 phy_pd_addr = ANALOGIX_DP_PHY_PD; 272 273 if (dp->plat_data.dev_type == ROCKCHIP_DP) 274 phy_pd_addr = ANALOGIX_DP_PD; 275 276 switch (block) { 277 case AUX_BLOCK: 278 if (enable) { 279 reg = analogix_dp_read(dp, phy_pd_addr); 280 reg |= AUX_PD; 281 analogix_dp_write(dp, phy_pd_addr, reg); 282 } else { 283 reg = analogix_dp_read(dp, phy_pd_addr); 284 reg &= ~AUX_PD; 285 analogix_dp_write(dp, phy_pd_addr, reg); 286 } 287 break; 288 case CH0_BLOCK: 289 if (enable) { 290 reg = analogix_dp_read(dp, phy_pd_addr); 291 reg |= CH0_PD; 292 analogix_dp_write(dp, phy_pd_addr, reg); 293 } else { 294 reg = analogix_dp_read(dp, phy_pd_addr); 295 reg &= ~CH0_PD; 296 analogix_dp_write(dp, phy_pd_addr, reg); 297 } 298 break; 299 case CH1_BLOCK: 300 if (enable) { 301 reg = analogix_dp_read(dp, phy_pd_addr); 302 reg |= CH1_PD; 303 analogix_dp_write(dp, phy_pd_addr, reg); 304 } else { 305 reg = analogix_dp_read(dp, phy_pd_addr); 306 reg &= ~CH1_PD; 307 analogix_dp_write(dp, phy_pd_addr, reg); 308 } 309 break; 310 case CH2_BLOCK: 311 if (enable) { 312 reg = analogix_dp_read(dp, phy_pd_addr); 313 reg |= CH2_PD; 314 analogix_dp_write(dp, phy_pd_addr, reg); 315 } else { 316 reg = analogix_dp_read(dp, phy_pd_addr); 317 reg &= ~CH2_PD; 318 analogix_dp_write(dp, phy_pd_addr, reg); 319 } 320 break; 321 case CH3_BLOCK: 322 if (enable) { 323 reg = analogix_dp_read(dp, phy_pd_addr); 324 reg |= CH3_PD; 325 analogix_dp_write(dp, phy_pd_addr, reg); 326 } else { 327 reg = analogix_dp_read(dp, phy_pd_addr); 328 reg &= ~CH3_PD; 329 analogix_dp_write(dp, phy_pd_addr, reg); 330 } 331 break; 332 case ANALOG_TOTAL: 333 if (enable) { 334 reg = analogix_dp_read(dp, phy_pd_addr); 335 reg |= DP_PHY_PD; 336 analogix_dp_write(dp, phy_pd_addr, reg); 337 } else { 338 reg = analogix_dp_read(dp, phy_pd_addr); 339 reg &= ~DP_PHY_PD; 340 analogix_dp_write(dp, phy_pd_addr, reg); 341 } 342 break; 343 case POWER_ALL: 344 if (enable) { 345 reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD | 346 CH1_PD | CH0_PD; 347 analogix_dp_write(dp, phy_pd_addr, reg); 348 } else { 349 analogix_dp_write(dp, phy_pd_addr, 0x00); 350 } 351 break; 352 default: 353 break; 354 } 355 } 356 357 void analogix_dp_init_analog_func(struct analogix_dp_device *dp) 358 { 359 u32 reg; 360 int timeout_loop = 0; 361 362 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 363 364 reg = PLL_LOCK_CHG; 365 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, reg); 366 367 reg = analogix_dp_read(dp, ANALOGIX_DP_DEBUG_CTL); 368 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); 369 analogix_dp_write(dp, ANALOGIX_DP_DEBUG_CTL, reg); 370 371 /* Power up PLL */ 372 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 373 analogix_dp_set_pll_power_down(dp, 0); 374 375 while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 376 timeout_loop++; 377 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 378 dev_err(dp->dev, 379 "failed to get pll lock status\n"); 380 return; 381 } 382 udelay(20); 383 } 384 } 385 386 /* Enable Serdes FIFO function and Link symbol clock domain module */ 387 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2); 388 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N 389 | AUX_FUNC_EN_N); 390 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 391 } 392 393 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp) 394 { 395 u32 reg; 396 397 if (dm_gpio_is_valid(&dp->hpd_gpio)) 398 return; 399 400 reg = HOTPLUG_CHG | HPD_LOST | PLUG; 401 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_4, reg); 402 403 reg = INT_HPD; 404 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg); 405 } 406 407 void analogix_dp_init_hpd(struct analogix_dp_device *dp) 408 { 409 u32 reg; 410 411 if (dm_gpio_is_valid(&dp->hpd_gpio)) 412 return; 413 414 analogix_dp_clear_hotplug_interrupts(dp); 415 416 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 417 reg &= ~(F_HPD | HPD_CTRL); 418 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 419 } 420 421 void analogix_dp_force_hpd(struct analogix_dp_device *dp) 422 { 423 u32 reg; 424 425 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 426 reg |= (F_HPD | HPD_CTRL); 427 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 428 } 429 430 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp) 431 { 432 u32 reg; 433 434 if (dm_gpio_is_valid(&dp->hpd_gpio)) { 435 reg = dm_gpio_get_value(&dp->hpd_gpio); 436 if (reg) 437 return DP_IRQ_TYPE_HP_CABLE_IN; 438 else 439 return DP_IRQ_TYPE_HP_CABLE_OUT; 440 } else { 441 /* Parse hotplug interrupt status register */ 442 reg = analogix_dp_read(dp, ANALOGIX_DP_COMMON_INT_STA_4); 443 444 if (reg & PLUG) 445 return DP_IRQ_TYPE_HP_CABLE_IN; 446 447 if (reg & HPD_LOST) 448 return DP_IRQ_TYPE_HP_CABLE_OUT; 449 450 if (reg & HOTPLUG_CHG) 451 return DP_IRQ_TYPE_HP_CHANGE; 452 453 return DP_IRQ_TYPE_UNKNOWN; 454 } 455 } 456 457 void analogix_dp_reset_aux(struct analogix_dp_device *dp) 458 { 459 u32 reg; 460 461 /* Disable AUX channel module */ 462 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2); 463 reg |= AUX_FUNC_EN_N; 464 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 465 } 466 467 void analogix_dp_init_aux(struct analogix_dp_device *dp) 468 { 469 u32 reg; 470 471 /* Clear inerrupts related to AUX channel */ 472 reg = RPLY_RECEIV | AUX_ERR; 473 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg); 474 475 analogix_dp_reset_aux(dp); 476 477 /* Disable AUX transaction H/W retry */ 478 if (dp->plat_data.dev_type == ROCKCHIP_DP) 479 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) | 480 AUX_HW_RETRY_COUNT_SEL(3) | 481 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; 482 else 483 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | 484 AUX_HW_RETRY_COUNT_SEL(0) | 485 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; 486 analogix_dp_write(dp, ANALOGIX_DP_AUX_HW_RETRY_CTL, reg); 487 488 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ 489 reg = DEFER_CTRL_EN | DEFER_COUNT(1); 490 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_DEFER_CTL, reg); 491 492 /* Enable AUX channel module */ 493 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2); 494 reg &= ~AUX_FUNC_EN_N; 495 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 496 } 497 498 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp) 499 { 500 u32 reg; 501 502 if (dm_gpio_is_valid(&dp->hpd_gpio)) { 503 if (dm_gpio_get_value(&dp->hpd_gpio)) 504 return 0; 505 } else { 506 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 507 if (reg & HPD_STATUS) 508 return 0; 509 } 510 511 return -EINVAL; 512 } 513 514 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp) 515 { 516 u32 reg; 517 518 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_1); 519 reg &= ~SW_FUNC_EN_N; 520 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg); 521 } 522 523 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp) 524 { 525 int reg; 526 int retval = 0; 527 int timeout_loop = 0; 528 529 /* Enable AUX CH operation */ 530 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_CTL_2); 531 reg |= AUX_EN; 532 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_2, reg); 533 534 /* Is AUX CH command reply received? */ 535 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA); 536 while (!(reg & RPLY_RECEIV)) { 537 timeout_loop++; 538 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { 539 dev_err(dp->dev, "AUX CH command reply failed!\n"); 540 return -ETIMEDOUT; 541 } 542 543 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA); 544 udelay(11); 545 } 546 547 /* Clear interrupt source for AUX CH command reply */ 548 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg); 549 550 /* Clear interrupt source for AUX CH access error */ 551 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA); 552 if (reg & AUX_ERR) { 553 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, AUX_ERR); 554 return -EREMOTEIO; 555 } 556 557 /* Check AUX CH error access status */ 558 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_STA); 559 if ((reg & AUX_STATUS_MASK) != 0) { 560 dev_err(dp->dev, 561 "AUX CH error happens: %d\n", reg & AUX_STATUS_MASK); 562 return -EREMOTEIO; 563 } 564 565 return retval; 566 } 567 568 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp, 569 unsigned int reg_addr, 570 unsigned char data) 571 { 572 u32 reg; 573 int i; 574 int retval; 575 576 for (i = 0; i < 3; i++) { 577 /* Clear AUX CH data buffer */ 578 reg = BUF_CLR; 579 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 580 581 /* Select DPCD device address */ 582 reg = AUX_ADDR_7_0(reg_addr); 583 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 584 reg = AUX_ADDR_15_8(reg_addr); 585 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); 586 reg = AUX_ADDR_19_16(reg_addr); 587 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); 588 589 /* Write data buffer */ 590 reg = (unsigned int)data; 591 analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0, reg); 592 593 /* 594 * Set DisplayPort transaction and write 1 byte 595 * If bit 3 is 1, DisplayPort transaction. 596 * If Bit 3 is 0, I2C transaction. 597 */ 598 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; 599 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 600 601 /* Start AUX transaction */ 602 retval = analogix_dp_start_aux_transaction(dp); 603 if (retval == 0) 604 break; 605 } 606 607 return retval; 608 } 609 610 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp, 611 unsigned int reg_addr, 612 unsigned char *data) 613 { 614 u32 reg; 615 int i; 616 int retval; 617 618 for (i = 0; i < 3; i++) { 619 /* Clear AUX CH data buffer */ 620 reg = BUF_CLR; 621 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 622 623 /* Select DPCD device address */ 624 reg = AUX_ADDR_7_0(reg_addr); 625 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 626 reg = AUX_ADDR_15_8(reg_addr); 627 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); 628 reg = AUX_ADDR_19_16(reg_addr); 629 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); 630 631 /* 632 * Set DisplayPort transaction and read 1 byte 633 * If bit 3 is 1, DisplayPort transaction. 634 * If Bit 3 is 0, I2C transaction. 635 */ 636 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; 637 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 638 639 /* Start AUX transaction */ 640 retval = analogix_dp_start_aux_transaction(dp); 641 if (retval == 0) 642 break; 643 } 644 645 /* Read data buffer */ 646 reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0); 647 *data = (unsigned char)(reg & 0xff); 648 649 return retval; 650 } 651 652 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp, 653 unsigned int reg_addr, 654 unsigned int count, 655 unsigned char data[]) 656 { 657 u32 reg; 658 unsigned int start_offset; 659 unsigned int cur_data_count; 660 unsigned int cur_data_idx; 661 int i; 662 int retval = 0; 663 664 /* Clear AUX CH data buffer */ 665 reg = BUF_CLR; 666 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 667 668 start_offset = 0; 669 while (start_offset < count) { 670 /* Buffer size of AUX CH is 16 * 4bytes */ 671 if ((count - start_offset) > 16) 672 cur_data_count = 16; 673 else 674 cur_data_count = count - start_offset; 675 676 for (i = 0; i < 3; i++) { 677 /* Select DPCD device address */ 678 reg = AUX_ADDR_7_0(reg_addr + start_offset); 679 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 680 reg = AUX_ADDR_15_8(reg_addr + start_offset); 681 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); 682 reg = AUX_ADDR_19_16(reg_addr + start_offset); 683 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); 684 685 for (cur_data_idx = 0; cur_data_idx < cur_data_count; 686 cur_data_idx++) { 687 reg = data[start_offset + cur_data_idx]; 688 analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0 + 689 4 * cur_data_idx, reg); 690 } 691 692 /* 693 * Set DisplayPort transaction and write 694 * If bit 3 is 1, DisplayPort transaction. 695 * If Bit 3 is 0, I2C transaction. 696 */ 697 reg = AUX_LENGTH(cur_data_count) | 698 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; 699 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 700 701 /* Start AUX transaction */ 702 retval = analogix_dp_start_aux_transaction(dp); 703 if (retval == 0) 704 break; 705 } 706 707 start_offset += cur_data_count; 708 } 709 710 return retval; 711 } 712 713 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp, 714 unsigned int reg_addr, 715 unsigned int count, 716 unsigned char data[]) 717 { 718 u32 reg; 719 unsigned int start_offset; 720 unsigned int cur_data_count; 721 unsigned int cur_data_idx; 722 int i; 723 int retval = 0; 724 725 /* Clear AUX CH data buffer */ 726 reg = BUF_CLR; 727 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 728 729 start_offset = 0; 730 while (start_offset < count) { 731 /* Buffer size of AUX CH is 16 * 4bytes */ 732 if ((count - start_offset) > 16) 733 cur_data_count = 16; 734 else 735 cur_data_count = count - start_offset; 736 737 /* AUX CH Request Transaction process */ 738 for (i = 0; i < 3; i++) { 739 /* Select DPCD device address */ 740 reg = AUX_ADDR_7_0(reg_addr + start_offset); 741 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 742 reg = AUX_ADDR_15_8(reg_addr + start_offset); 743 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); 744 reg = AUX_ADDR_19_16(reg_addr + start_offset); 745 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); 746 747 /* 748 * Set DisplayPort transaction and read 749 * If bit 3 is 1, DisplayPort transaction. 750 * If Bit 3 is 0, I2C transaction. 751 */ 752 reg = AUX_LENGTH(cur_data_count) | 753 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; 754 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 755 756 /* Start AUX transaction */ 757 retval = analogix_dp_start_aux_transaction(dp); 758 if (retval == 0) 759 break; 760 } 761 762 for (cur_data_idx = 0; cur_data_idx < cur_data_count; 763 cur_data_idx++) { 764 reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0 765 + 4 * cur_data_idx); 766 data[start_offset + cur_data_idx] = 767 (unsigned char)reg; 768 } 769 770 start_offset += cur_data_count; 771 } 772 773 return retval; 774 } 775 776 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp, 777 unsigned int device_addr, 778 unsigned int reg_addr) 779 { 780 u32 reg; 781 int retval; 782 783 /* Set EDID device address */ 784 reg = device_addr; 785 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 786 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, 0x0); 787 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, 0x0); 788 789 /* Set offset from base address of EDID device */ 790 analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0, reg_addr); 791 792 /* 793 * Set I2C transaction and write address 794 * If bit 3 is 1, DisplayPort transaction. 795 * If Bit 3 is 0, I2C transaction. 796 */ 797 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT | 798 AUX_TX_COMM_WRITE; 799 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 800 801 /* Start AUX transaction */ 802 retval = analogix_dp_start_aux_transaction(dp); 803 if (retval < 0) 804 return retval; 805 806 return 0; 807 } 808 809 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp, 810 unsigned int device_addr, 811 unsigned int reg_addr, 812 unsigned int *data) 813 { 814 u32 reg; 815 int i; 816 int retval; 817 818 for (i = 0; i < 3; i++) { 819 /* Clear AUX CH data buffer */ 820 reg = BUF_CLR; 821 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 822 823 /* Select EDID device */ 824 retval = analogix_dp_select_i2c_device(dp, device_addr, 825 reg_addr); 826 if (retval != 0) 827 continue; 828 829 /* 830 * Set I2C transaction and read data 831 * If bit 3 is 1, DisplayPort transaction. 832 * If Bit 3 is 0, I2C transaction. 833 */ 834 reg = AUX_TX_COMM_I2C_TRANSACTION | 835 AUX_TX_COMM_READ; 836 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 837 838 /* Start AUX transaction */ 839 retval = analogix_dp_start_aux_transaction(dp); 840 if (retval == 0) 841 break; 842 } 843 844 /* Read data */ 845 if (retval == 0) 846 *data = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0); 847 848 return retval; 849 } 850 851 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp, 852 unsigned int device_addr, 853 unsigned int reg_addr, 854 unsigned int count, 855 unsigned char edid[]) 856 { 857 u32 reg; 858 unsigned int i, j; 859 unsigned int cur_data_idx; 860 unsigned int defer = 0; 861 int retval = 0; 862 863 for (i = 0; i < count; i += 16) { 864 for (j = 0; j < 3; j++) { 865 /* Clear AUX CH data buffer */ 866 reg = BUF_CLR; 867 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 868 869 /* Set normal AUX CH command */ 870 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_CTL_2); 871 reg &= ~ADDR_ONLY; 872 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_2, reg); 873 874 /* 875 * If Rx sends defer, Tx sends only reads 876 * request without sending address 877 */ 878 if (!defer) 879 retval = analogix_dp_select_i2c_device(dp, 880 device_addr, reg_addr + i); 881 else 882 defer = 0; 883 884 if (retval == 0) { 885 /* 886 * Set I2C transaction and write data 887 * If bit 3 is 1, DisplayPort transaction. 888 * If Bit 3 is 0, I2C transaction. 889 */ 890 reg = AUX_LENGTH(16) | 891 AUX_TX_COMM_I2C_TRANSACTION | 892 AUX_TX_COMM_READ; 893 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, 894 reg); 895 896 /* Start AUX transaction */ 897 retval = analogix_dp_start_aux_transaction(dp); 898 if (retval == 0) 899 break; 900 } 901 /* Check if Rx sends defer */ 902 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_RX_COMM); 903 if (reg == AUX_RX_COMM_AUX_DEFER || 904 reg == AUX_RX_COMM_I2C_DEFER) { 905 dev_dbg(dp->dev, "Defer: %d\n\n", reg); 906 defer = 1; 907 } 908 } 909 910 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) { 911 reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0 912 + 4 * cur_data_idx); 913 edid[i + cur_data_idx] = (unsigned char)reg; 914 } 915 } 916 917 return retval; 918 } 919 920 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype) 921 { 922 u32 reg; 923 924 reg = bwtype; 925 if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62)) 926 analogix_dp_write(dp, ANALOGIX_DP_LINK_BW_SET, reg); 927 } 928 929 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype) 930 { 931 u32 reg; 932 933 reg = analogix_dp_read(dp, ANALOGIX_DP_LINK_BW_SET); 934 *bwtype = reg; 935 } 936 937 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count) 938 { 939 u32 reg; 940 941 reg = count; 942 analogix_dp_write(dp, ANALOGIX_DP_LANE_COUNT_SET, reg); 943 } 944 945 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count) 946 { 947 u32 reg; 948 949 reg = analogix_dp_read(dp, ANALOGIX_DP_LANE_COUNT_SET); 950 *count = reg; 951 } 952 953 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, 954 bool enable) 955 { 956 u32 reg; 957 958 if (enable) { 959 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 960 reg |= ENHANCED; 961 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 962 } else { 963 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 964 reg &= ~ENHANCED; 965 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 966 } 967 } 968 969 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, 970 enum pattern_set pattern) 971 { 972 u32 reg; 973 974 switch (pattern) { 975 case PRBS7: 976 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7; 977 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 978 break; 979 case D10_2: 980 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2; 981 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 982 break; 983 case TRAINING_PTN1: 984 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1; 985 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 986 break; 987 case TRAINING_PTN2: 988 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2; 989 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 990 break; 991 case DP_NONE: 992 reg = SCRAMBLING_ENABLE | 993 LINK_QUAL_PATTERN_SET_DISABLE | 994 SW_TRAINING_PATTERN_SET_NORMAL; 995 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 996 break; 997 default: 998 break; 999 } 1000 } 1001 1002 void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, 1003 u32 level) 1004 { 1005 u32 reg; 1006 1007 reg = analogix_dp_read(dp, ANALOGIX_DP_LN0_LINK_TRAINING_CTL); 1008 reg &= ~PRE_EMPHASIS_SET_MASK; 1009 reg |= level << PRE_EMPHASIS_SET_SHIFT; 1010 analogix_dp_write(dp, ANALOGIX_DP_LN0_LINK_TRAINING_CTL, reg); 1011 } 1012 1013 void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, 1014 u32 level) 1015 { 1016 u32 reg; 1017 1018 reg = analogix_dp_read(dp, ANALOGIX_DP_LN1_LINK_TRAINING_CTL); 1019 reg &= ~PRE_EMPHASIS_SET_MASK; 1020 reg |= level << PRE_EMPHASIS_SET_SHIFT; 1021 analogix_dp_write(dp, ANALOGIX_DP_LN1_LINK_TRAINING_CTL, reg); 1022 } 1023 1024 void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, 1025 u32 level) 1026 { 1027 u32 reg; 1028 1029 reg = analogix_dp_read(dp, ANALOGIX_DP_LN2_LINK_TRAINING_CTL); 1030 reg &= ~PRE_EMPHASIS_SET_MASK; 1031 reg |= level << PRE_EMPHASIS_SET_SHIFT; 1032 analogix_dp_write(dp, ANALOGIX_DP_LN2_LINK_TRAINING_CTL, reg); 1033 } 1034 1035 void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, 1036 u32 level) 1037 { 1038 u32 reg; 1039 1040 reg = analogix_dp_read(dp, ANALOGIX_DP_LN3_LINK_TRAINING_CTL); 1041 reg &= ~PRE_EMPHASIS_SET_MASK; 1042 reg |= level << PRE_EMPHASIS_SET_SHIFT; 1043 analogix_dp_write(dp, ANALOGIX_DP_LN3_LINK_TRAINING_CTL, reg); 1044 } 1045 1046 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp, 1047 u32 training_lane) 1048 { 1049 u32 reg; 1050 1051 reg = training_lane; 1052 analogix_dp_write(dp, ANALOGIX_DP_LN0_LINK_TRAINING_CTL, reg); 1053 } 1054 1055 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp, 1056 u32 training_lane) 1057 { 1058 u32 reg; 1059 1060 reg = training_lane; 1061 analogix_dp_write(dp, ANALOGIX_DP_LN1_LINK_TRAINING_CTL, reg); 1062 } 1063 1064 void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp, 1065 u32 training_lane) 1066 { 1067 u32 reg; 1068 1069 reg = training_lane; 1070 analogix_dp_write(dp, ANALOGIX_DP_LN2_LINK_TRAINING_CTL, reg); 1071 } 1072 1073 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp, 1074 u32 training_lane) 1075 { 1076 u32 reg; 1077 1078 reg = training_lane; 1079 analogix_dp_write(dp, ANALOGIX_DP_LN3_LINK_TRAINING_CTL, reg); 1080 } 1081 1082 u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp) 1083 { 1084 u32 reg; 1085 1086 reg = analogix_dp_read(dp, ANALOGIX_DP_LN0_LINK_TRAINING_CTL); 1087 return reg; 1088 } 1089 1090 u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp) 1091 { 1092 u32 reg; 1093 1094 reg = analogix_dp_read(dp, ANALOGIX_DP_LN1_LINK_TRAINING_CTL); 1095 return reg; 1096 } 1097 1098 u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp) 1099 { 1100 u32 reg; 1101 1102 reg = analogix_dp_read(dp, ANALOGIX_DP_LN2_LINK_TRAINING_CTL); 1103 return reg; 1104 } 1105 1106 u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp) 1107 { 1108 u32 reg; 1109 1110 reg = analogix_dp_read(dp, ANALOGIX_DP_LN3_LINK_TRAINING_CTL); 1111 return reg; 1112 } 1113 1114 void analogix_dp_reset_macro(struct analogix_dp_device *dp) 1115 { 1116 u32 reg; 1117 1118 reg = analogix_dp_read(dp, ANALOGIX_DP_PHY_TEST); 1119 reg |= MACRO_RST; 1120 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, reg); 1121 1122 /* 10 us is the minimum reset time. */ 1123 udelay(20); 1124 1125 reg &= ~MACRO_RST; 1126 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, reg); 1127 } 1128 1129 void analogix_dp_init_video(struct analogix_dp_device *dp) 1130 { 1131 u32 reg; 1132 1133 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; 1134 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, reg); 1135 1136 reg = 0x0; 1137 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, reg); 1138 1139 reg = CHA_CRI(4) | CHA_CTRL; 1140 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, reg); 1141 1142 reg = 0x0; 1143 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 1144 1145 reg = VID_HRES_TH(2) | VID_VRES_TH(0); 1146 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_8, reg); 1147 } 1148 1149 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp) 1150 { 1151 u32 reg; 1152 1153 /* Configure the input color depth, color space, dynamic range */ 1154 reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) | 1155 (dp->video_info.color_depth << IN_BPC_SHIFT) | 1156 (dp->video_info.color_space << IN_COLOR_F_SHIFT); 1157 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_2, reg); 1158 1159 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */ 1160 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_3); 1161 reg &= ~IN_YC_COEFFI_MASK; 1162 if (dp->video_info.ycbcr_coeff) 1163 reg |= IN_YC_COEFFI_ITU709; 1164 else 1165 reg |= IN_YC_COEFFI_ITU601; 1166 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_3, reg); 1167 } 1168 1169 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp) 1170 { 1171 u32 reg; 1172 1173 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_1); 1174 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, reg); 1175 1176 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_1); 1177 1178 if (!(reg & DET_STA)) 1179 return -EINVAL; 1180 1181 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_2); 1182 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, reg); 1183 1184 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_2); 1185 1186 if (reg & CHA_STA) 1187 return -EINVAL; 1188 1189 return 0; 1190 } 1191 1192 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, 1193 enum clock_recovery_m_value_type type, 1194 u32 m_value, u32 n_value) 1195 { 1196 u32 reg; 1197 1198 if (type == REGISTER_M) { 1199 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 1200 reg |= FIX_M_VID; 1201 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 1202 reg = m_value & 0xff; 1203 analogix_dp_write(dp, ANALOGIX_DP_M_VID_0, reg); 1204 reg = (m_value >> 8) & 0xff; 1205 analogix_dp_write(dp, ANALOGIX_DP_M_VID_1, reg); 1206 reg = (m_value >> 16) & 0xff; 1207 analogix_dp_write(dp, ANALOGIX_DP_M_VID_2, reg); 1208 1209 reg = n_value & 0xff; 1210 analogix_dp_write(dp, ANALOGIX_DP_N_VID_0, reg); 1211 reg = (n_value >> 8) & 0xff; 1212 analogix_dp_write(dp, ANALOGIX_DP_N_VID_1, reg); 1213 reg = (n_value >> 16) & 0xff; 1214 analogix_dp_write(dp, ANALOGIX_DP_N_VID_2, reg); 1215 } else { 1216 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 1217 reg &= ~FIX_M_VID; 1218 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 1219 1220 analogix_dp_write(dp, ANALOGIX_DP_N_VID_0, 0x00); 1221 analogix_dp_write(dp, ANALOGIX_DP_N_VID_1, 0x80); 1222 analogix_dp_write(dp, ANALOGIX_DP_N_VID_2, 0x00); 1223 } 1224 } 1225 1226 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type) 1227 { 1228 u32 reg; 1229 1230 if (type == VIDEO_TIMING_FROM_CAPTURE) { 1231 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1232 reg &= ~FORMAT_SEL; 1233 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1234 } else { 1235 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1236 reg |= FORMAT_SEL; 1237 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1238 } 1239 } 1240 1241 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable) 1242 { 1243 u32 reg; 1244 1245 if (enable) { 1246 reg = analogix_dp_read(dp, ANALOGIX_DP_SOC_GENERAL_CTL); 1247 reg &= ~VIDEO_MODE_MASK; 1248 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE; 1249 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg); 1250 } else { 1251 reg = analogix_dp_read(dp, ANALOGIX_DP_SOC_GENERAL_CTL); 1252 reg &= ~VIDEO_MODE_MASK; 1253 reg |= VIDEO_MODE_SLAVE_MODE; 1254 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg); 1255 } 1256 } 1257 1258 void analogix_dp_start_video(struct analogix_dp_device *dp) 1259 { 1260 u32 reg; 1261 1262 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 1263 reg |= VIDEO_EN; 1264 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 1265 } 1266 1267 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp) 1268 { 1269 u32 reg; 1270 1271 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 1272 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 1273 1274 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 1275 if (!(reg & STRM_VALID)) 1276 return -EINVAL; 1277 1278 return 0; 1279 } 1280 1281 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp) 1282 { 1283 u32 reg; 1284 1285 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_1); 1286 reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N); 1287 reg |= MASTER_VID_FUNC_EN_N; 1288 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg); 1289 1290 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1291 reg &= ~INTERACE_SCAN_CFG; 1292 reg |= (dp->video_info.interlaced << 2); 1293 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1294 1295 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1296 reg &= ~VSYNC_POLARITY_CFG; 1297 reg |= (dp->video_info.v_sync_polarity << 1); 1298 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1299 1300 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1301 reg &= ~HSYNC_POLARITY_CFG; 1302 reg |= (dp->video_info.h_sync_polarity << 0); 1303 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1304 1305 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; 1306 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg); 1307 } 1308 1309 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp) 1310 { 1311 u32 reg; 1312 1313 reg = analogix_dp_read(dp, ANALOGIX_DP_TRAINING_PTN_SET); 1314 reg &= ~SCRAMBLING_DISABLE; 1315 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1316 } 1317 1318 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp) 1319 { 1320 u32 reg; 1321 1322 reg = analogix_dp_read(dp, ANALOGIX_DP_TRAINING_PTN_SET); 1323 reg |= SCRAMBLING_DISABLE; 1324 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1325 } 1326