1 /* 2 * Analogix DP (Display port) core register interface driver. 3 * 4 * Copyright (C) 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 5 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 6 * Author: Jingoo Han <jg1.han@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 */ 13 14 #include <config.h> 15 #include <common.h> 16 #include <errno.h> 17 #include <malloc.h> 18 #include <asm/unaligned.h> 19 #include <linux/list.h> 20 #include <dm/device.h> 21 #include <syscon.h> 22 #include <asm/io.h> 23 #include <asm/gpio.h> 24 25 #include "rockchip_display.h" 26 #include "rockchip_crtc.h" 27 #include "rockchip_connector.h" 28 #include "analogix_dp.h" 29 30 #define COMMON_INT_MASK_1 0 31 #define COMMON_INT_MASK_2 0 32 #define COMMON_INT_MASK_3 0 33 #define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG) 34 #define INT_STA_MASK INT_HPD 35 36 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable) 37 { 38 u32 reg; 39 40 if (enable) { 41 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 42 reg |= HDCP_VIDEO_MUTE; 43 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 44 } else { 45 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 46 reg &= ~HDCP_VIDEO_MUTE; 47 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 48 } 49 } 50 51 void analogix_dp_stop_video(struct analogix_dp_device *dp) 52 { 53 u32 reg; 54 55 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 56 reg &= ~VIDEO_EN; 57 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 58 } 59 60 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable) 61 { 62 u32 reg; 63 64 if (enable) 65 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 | 66 LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3; 67 else 68 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | 69 LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0; 70 71 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP); 72 } 73 74 void analogix_dp_init_analog_param(struct analogix_dp_device *dp) 75 { 76 u32 reg; 77 78 reg = TX_TERMINAL_CTRL_50_OHM; 79 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1); 80 81 reg = SEL_24M | TX_DVDD_BIT_1_0625V; 82 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2); 83 84 if (dp->plat_data.dev_type == ROCKCHIP_DP) { 85 reg = REF_CLK_24M; 86 if (dp->plat_data.subdev_type == RK3288_DP || 87 dp->plat_data.subdev_type == RK3368_EDP) 88 reg ^= REF_CLK_MASK; 89 90 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1); 91 writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2); 92 writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3); 93 writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4); 94 writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5); 95 } 96 97 reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO; 98 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3); 99 100 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | 101 TX_CUR1_2X | TX_CUR_16_MA; 102 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1); 103 104 reg = CH3_AMP_400_MV | CH2_AMP_400_MV | 105 CH1_AMP_400_MV | CH0_AMP_400_MV; 106 writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL); 107 } 108 109 void analogix_dp_init_interrupt(struct analogix_dp_device *dp) 110 { 111 /* Set interrupt pin assertion polarity as high */ 112 writel(INT_POL1 | INT_POL0, dp->reg_base + ANALOGIX_DP_INT_CTL); 113 114 /* Clear pending regisers */ 115 writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); 116 writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2); 117 writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3); 118 writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); 119 writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA); 120 121 /* 0:mask,1: unmask */ 122 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1); 123 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2); 124 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3); 125 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); 126 writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); 127 } 128 129 void analogix_dp_reset(struct analogix_dp_device *dp) 130 { 131 u32 reg; 132 133 analogix_dp_stop_video(dp); 134 analogix_dp_enable_video_mute(dp, 0); 135 136 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | 137 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | 138 HDCP_FUNC_EN_N | SW_FUNC_EN_N; 139 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); 140 141 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | 142 SERDES_FIFO_FUNC_EN_N | 143 LS_CLK_DOMAIN_FUNC_EN_N; 144 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 145 146 udelay(30); 147 148 analogix_dp_lane_swap(dp, 0); 149 150 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); 151 writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); 152 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 153 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 154 155 writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); 156 writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL); 157 158 writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L); 159 writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H); 160 161 writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL); 162 163 writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST); 164 165 writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD); 166 writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN); 167 168 writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH); 169 writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH); 170 171 writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 172 } 173 174 void analogix_dp_swreset(struct analogix_dp_device *dp) 175 { 176 writel(RESET_DP_TX, dp->reg_base + ANALOGIX_DP_TX_SW_RESET); 177 } 178 179 void analogix_dp_config_interrupt(struct analogix_dp_device *dp) 180 { 181 u32 reg; 182 183 /* 0: mask, 1: unmask */ 184 reg = COMMON_INT_MASK_1; 185 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1); 186 187 reg = COMMON_INT_MASK_2; 188 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2); 189 190 reg = COMMON_INT_MASK_3; 191 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3); 192 193 reg = COMMON_INT_MASK_4; 194 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); 195 196 reg = INT_STA_MASK; 197 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); 198 } 199 200 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp) 201 { 202 u32 reg; 203 204 /* 0: mask, 1: unmask */ 205 reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); 206 reg &= ~COMMON_INT_MASK_4; 207 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); 208 209 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA_MASK); 210 reg &= ~INT_STA_MASK; 211 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); 212 } 213 214 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp) 215 { 216 u32 reg; 217 218 /* 0: mask, 1: unmask */ 219 reg = COMMON_INT_MASK_4; 220 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); 221 222 reg = INT_STA_MASK; 223 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); 224 } 225 226 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp) 227 { 228 u32 reg; 229 230 reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL); 231 if (reg & PLL_LOCK) 232 return PLL_LOCKED; 233 else 234 return PLL_UNLOCKED; 235 } 236 237 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable) 238 { 239 u32 reg; 240 241 if (enable) { 242 reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL); 243 reg |= DP_PLL_PD; 244 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL); 245 } else { 246 reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL); 247 reg &= ~DP_PLL_PD; 248 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL); 249 } 250 } 251 252 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 253 enum analog_power_block block, 254 bool enable) 255 { 256 u32 reg; 257 u32 phy_pd_addr = ANALOGIX_DP_PHY_PD; 258 259 if (dp->plat_data.dev_type == ROCKCHIP_DP) 260 phy_pd_addr = ANALOGIX_DP_PD; 261 262 switch (block) { 263 case AUX_BLOCK: 264 if (enable) { 265 reg = readl(dp->reg_base + phy_pd_addr); 266 reg |= AUX_PD; 267 writel(reg, dp->reg_base + phy_pd_addr); 268 } else { 269 reg = readl(dp->reg_base + phy_pd_addr); 270 reg &= ~AUX_PD; 271 writel(reg, dp->reg_base + phy_pd_addr); 272 } 273 break; 274 case CH0_BLOCK: 275 if (enable) { 276 reg = readl(dp->reg_base + phy_pd_addr); 277 reg |= CH0_PD; 278 writel(reg, dp->reg_base + phy_pd_addr); 279 } else { 280 reg = readl(dp->reg_base + phy_pd_addr); 281 reg &= ~CH0_PD; 282 writel(reg, dp->reg_base + phy_pd_addr); 283 } 284 break; 285 case CH1_BLOCK: 286 if (enable) { 287 reg = readl(dp->reg_base + phy_pd_addr); 288 reg |= CH1_PD; 289 writel(reg, dp->reg_base + phy_pd_addr); 290 } else { 291 reg = readl(dp->reg_base + phy_pd_addr); 292 reg &= ~CH1_PD; 293 writel(reg, dp->reg_base + phy_pd_addr); 294 } 295 break; 296 case CH2_BLOCK: 297 if (enable) { 298 reg = readl(dp->reg_base + phy_pd_addr); 299 reg |= CH2_PD; 300 writel(reg, dp->reg_base + phy_pd_addr); 301 } else { 302 reg = readl(dp->reg_base + phy_pd_addr); 303 reg &= ~CH2_PD; 304 writel(reg, dp->reg_base + phy_pd_addr); 305 } 306 break; 307 case CH3_BLOCK: 308 if (enable) { 309 reg = readl(dp->reg_base + phy_pd_addr); 310 reg |= CH3_PD; 311 writel(reg, dp->reg_base + phy_pd_addr); 312 } else { 313 reg = readl(dp->reg_base + phy_pd_addr); 314 reg &= ~CH3_PD; 315 writel(reg, dp->reg_base + phy_pd_addr); 316 } 317 break; 318 case ANALOG_TOTAL: 319 if (enable) { 320 reg = readl(dp->reg_base + phy_pd_addr); 321 reg |= DP_PHY_PD; 322 writel(reg, dp->reg_base + phy_pd_addr); 323 } else { 324 reg = readl(dp->reg_base + phy_pd_addr); 325 reg &= ~DP_PHY_PD; 326 writel(reg, dp->reg_base + phy_pd_addr); 327 } 328 break; 329 case POWER_ALL: 330 if (enable) { 331 reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD | 332 CH1_PD | CH0_PD; 333 writel(reg, dp->reg_base + phy_pd_addr); 334 } else { 335 writel(0x00, dp->reg_base + phy_pd_addr); 336 } 337 break; 338 default: 339 break; 340 } 341 } 342 343 void analogix_dp_init_analog_func(struct analogix_dp_device *dp) 344 { 345 u32 reg; 346 int timeout_loop = 0; 347 348 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 349 350 reg = PLL_LOCK_CHG; 351 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); 352 353 reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL); 354 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); 355 writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL); 356 357 /* Power up PLL */ 358 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 359 analogix_dp_set_pll_power_down(dp, 0); 360 361 while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 362 timeout_loop++; 363 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 364 dev_err(dp->dev, 365 "failed to get pll lock status\n"); 366 return; 367 } 368 udelay(20); 369 } 370 } 371 372 /* Enable Serdes FIFO function and Link symbol clock domain module */ 373 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 374 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N 375 | AUX_FUNC_EN_N); 376 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 377 } 378 379 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp) 380 { 381 u32 reg; 382 383 if (dm_gpio_is_valid(&dp->hpd_gpio)) 384 return; 385 386 reg = HOTPLUG_CHG | HPD_LOST | PLUG; 387 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); 388 389 reg = INT_HPD; 390 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA); 391 } 392 393 void analogix_dp_init_hpd(struct analogix_dp_device *dp) 394 { 395 u32 reg; 396 397 if (dm_gpio_is_valid(&dp->hpd_gpio)) 398 return; 399 400 analogix_dp_clear_hotplug_interrupts(dp); 401 402 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 403 reg &= ~(F_HPD | HPD_CTRL); 404 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 405 } 406 407 void analogix_dp_force_hpd(struct analogix_dp_device *dp) 408 { 409 u32 reg; 410 411 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 412 reg = (F_HPD | HPD_CTRL); 413 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 414 } 415 416 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp) 417 { 418 u32 reg; 419 420 if (dm_gpio_is_valid(&dp->hpd_gpio)) { 421 reg = dm_gpio_get_value(&dp->hpd_gpio); 422 if (reg) 423 return DP_IRQ_TYPE_HP_CABLE_IN; 424 else 425 return DP_IRQ_TYPE_HP_CABLE_OUT; 426 } else { 427 /* Parse hotplug interrupt status register */ 428 reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); 429 430 if (reg & PLUG) 431 return DP_IRQ_TYPE_HP_CABLE_IN; 432 433 if (reg & HPD_LOST) 434 return DP_IRQ_TYPE_HP_CABLE_OUT; 435 436 if (reg & HOTPLUG_CHG) 437 return DP_IRQ_TYPE_HP_CHANGE; 438 439 return DP_IRQ_TYPE_UNKNOWN; 440 } 441 } 442 443 void analogix_dp_reset_aux(struct analogix_dp_device *dp) 444 { 445 u32 reg; 446 447 /* Disable AUX channel module */ 448 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 449 reg |= AUX_FUNC_EN_N; 450 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 451 } 452 453 void analogix_dp_init_aux(struct analogix_dp_device *dp) 454 { 455 u32 reg; 456 457 /* Clear inerrupts related to AUX channel */ 458 reg = RPLY_RECEIV | AUX_ERR; 459 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA); 460 461 analogix_dp_reset_aux(dp); 462 463 /* Disable AUX transaction H/W retry */ 464 if (dp->plat_data.dev_type == ROCKCHIP_DP) 465 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) | 466 AUX_HW_RETRY_COUNT_SEL(3) | 467 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; 468 else 469 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | 470 AUX_HW_RETRY_COUNT_SEL(0) | 471 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; 472 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL); 473 474 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ 475 reg = DEFER_CTRL_EN | DEFER_COUNT(1); 476 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL); 477 478 /* Enable AUX channel module */ 479 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 480 reg &= ~AUX_FUNC_EN_N; 481 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 482 } 483 484 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp) 485 { 486 u32 reg; 487 488 if (dm_gpio_is_valid(&dp->hpd_gpio)) { 489 if (dm_gpio_get_value(&dp->hpd_gpio)) 490 return 0; 491 } else { 492 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 493 if (reg & HPD_STATUS) 494 return 0; 495 } 496 497 return -EINVAL; 498 } 499 500 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp) 501 { 502 u32 reg; 503 504 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1); 505 reg &= ~SW_FUNC_EN_N; 506 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); 507 } 508 509 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp) 510 { 511 int reg; 512 int retval = 0; 513 int timeout_loop = 0; 514 515 /* Enable AUX CH operation */ 516 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); 517 reg |= AUX_EN; 518 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); 519 520 /* Is AUX CH command reply received? */ 521 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); 522 while (!(reg & RPLY_RECEIV)) { 523 timeout_loop++; 524 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { 525 dev_err(dp->dev, "AUX CH command reply failed!\n"); 526 return -ETIMEDOUT; 527 } 528 529 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); 530 udelay(11); 531 } 532 533 /* Clear interrupt source for AUX CH command reply */ 534 writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA); 535 536 /* Clear interrupt source for AUX CH access error */ 537 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); 538 if (reg & AUX_ERR) { 539 writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA); 540 return -EREMOTEIO; 541 } 542 543 /* Check AUX CH error access status */ 544 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA); 545 if ((reg & AUX_STATUS_MASK) != 0) { 546 dev_err(dp->dev, 547 "AUX CH error happens: %d\n", reg & AUX_STATUS_MASK); 548 return -EREMOTEIO; 549 } 550 551 return retval; 552 } 553 554 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp, 555 unsigned int reg_addr, 556 unsigned char data) 557 { 558 u32 reg; 559 int i; 560 int retval; 561 562 for (i = 0; i < 3; i++) { 563 /* Clear AUX CH data buffer */ 564 reg = BUF_CLR; 565 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); 566 567 /* Select DPCD device address */ 568 reg = AUX_ADDR_7_0(reg_addr); 569 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); 570 reg = AUX_ADDR_15_8(reg_addr); 571 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); 572 reg = AUX_ADDR_19_16(reg_addr); 573 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); 574 575 /* Write data buffer */ 576 reg = (unsigned int)data; 577 writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0); 578 579 /* 580 * Set DisplayPort transaction and write 1 byte 581 * If bit 3 is 1, DisplayPort transaction. 582 * If Bit 3 is 0, I2C transaction. 583 */ 584 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; 585 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); 586 587 /* Start AUX transaction */ 588 retval = analogix_dp_start_aux_transaction(dp); 589 if (retval == 0) 590 break; 591 } 592 593 return retval; 594 } 595 596 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp, 597 unsigned int reg_addr, 598 unsigned char *data) 599 { 600 u32 reg; 601 int i; 602 int retval; 603 604 for (i = 0; i < 3; i++) { 605 /* Clear AUX CH data buffer */ 606 reg = BUF_CLR; 607 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); 608 609 /* Select DPCD device address */ 610 reg = AUX_ADDR_7_0(reg_addr); 611 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); 612 reg = AUX_ADDR_15_8(reg_addr); 613 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); 614 reg = AUX_ADDR_19_16(reg_addr); 615 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); 616 617 /* 618 * Set DisplayPort transaction and read 1 byte 619 * If bit 3 is 1, DisplayPort transaction. 620 * If Bit 3 is 0, I2C transaction. 621 */ 622 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; 623 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); 624 625 /* Start AUX transaction */ 626 retval = analogix_dp_start_aux_transaction(dp); 627 if (retval == 0) 628 break; 629 } 630 631 /* Read data buffer */ 632 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0); 633 *data = (unsigned char)(reg & 0xff); 634 635 return retval; 636 } 637 638 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp, 639 unsigned int reg_addr, 640 unsigned int count, 641 unsigned char data[]) 642 { 643 u32 reg; 644 unsigned int start_offset; 645 unsigned int cur_data_count; 646 unsigned int cur_data_idx; 647 int i; 648 int retval = 0; 649 650 /* Clear AUX CH data buffer */ 651 reg = BUF_CLR; 652 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); 653 654 start_offset = 0; 655 while (start_offset < count) { 656 /* Buffer size of AUX CH is 16 * 4bytes */ 657 if ((count - start_offset) > 16) 658 cur_data_count = 16; 659 else 660 cur_data_count = count - start_offset; 661 662 for (i = 0; i < 3; i++) { 663 /* Select DPCD device address */ 664 reg = AUX_ADDR_7_0(reg_addr + start_offset); 665 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); 666 reg = AUX_ADDR_15_8(reg_addr + start_offset); 667 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); 668 reg = AUX_ADDR_19_16(reg_addr + start_offset); 669 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); 670 671 for (cur_data_idx = 0; cur_data_idx < cur_data_count; 672 cur_data_idx++) { 673 reg = data[start_offset + cur_data_idx]; 674 writel(reg, dp->reg_base + 675 ANALOGIX_DP_BUF_DATA_0 + 676 4 * cur_data_idx); 677 } 678 679 /* 680 * Set DisplayPort transaction and write 681 * If bit 3 is 1, DisplayPort transaction. 682 * If Bit 3 is 0, I2C transaction. 683 */ 684 reg = AUX_LENGTH(cur_data_count) | 685 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; 686 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); 687 688 /* Start AUX transaction */ 689 retval = analogix_dp_start_aux_transaction(dp); 690 if (retval == 0) 691 break; 692 } 693 694 start_offset += cur_data_count; 695 } 696 697 return retval; 698 } 699 700 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp, 701 unsigned int reg_addr, 702 unsigned int count, 703 unsigned char data[]) 704 { 705 u32 reg; 706 unsigned int start_offset; 707 unsigned int cur_data_count; 708 unsigned int cur_data_idx; 709 int i; 710 int retval = 0; 711 712 /* Clear AUX CH data buffer */ 713 reg = BUF_CLR; 714 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); 715 716 start_offset = 0; 717 while (start_offset < count) { 718 /* Buffer size of AUX CH is 16 * 4bytes */ 719 if ((count - start_offset) > 16) 720 cur_data_count = 16; 721 else 722 cur_data_count = count - start_offset; 723 724 /* AUX CH Request Transaction process */ 725 for (i = 0; i < 3; i++) { 726 /* Select DPCD device address */ 727 reg = AUX_ADDR_7_0(reg_addr + start_offset); 728 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); 729 reg = AUX_ADDR_15_8(reg_addr + start_offset); 730 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); 731 reg = AUX_ADDR_19_16(reg_addr + start_offset); 732 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); 733 734 /* 735 * Set DisplayPort transaction and read 736 * If bit 3 is 1, DisplayPort transaction. 737 * If Bit 3 is 0, I2C transaction. 738 */ 739 reg = AUX_LENGTH(cur_data_count) | 740 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; 741 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); 742 743 /* Start AUX transaction */ 744 retval = analogix_dp_start_aux_transaction(dp); 745 if (retval == 0) 746 break; 747 } 748 749 for (cur_data_idx = 0; cur_data_idx < cur_data_count; 750 cur_data_idx++) { 751 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0 752 + 4 * cur_data_idx); 753 data[start_offset + cur_data_idx] = 754 (unsigned char)reg; 755 } 756 757 start_offset += cur_data_count; 758 } 759 760 return retval; 761 } 762 763 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp, 764 unsigned int device_addr, 765 unsigned int reg_addr) 766 { 767 u32 reg; 768 int retval; 769 770 /* Set EDID device address */ 771 reg = device_addr; 772 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); 773 writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); 774 writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); 775 776 /* Set offset from base address of EDID device */ 777 writel(reg_addr, dp->reg_base + ANALOGIX_DP_BUF_DATA_0); 778 779 /* 780 * Set I2C transaction and write address 781 * If bit 3 is 1, DisplayPort transaction. 782 * If Bit 3 is 0, I2C transaction. 783 */ 784 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT | 785 AUX_TX_COMM_WRITE; 786 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); 787 788 /* Start AUX transaction */ 789 retval = analogix_dp_start_aux_transaction(dp); 790 if (retval < 0) 791 return retval; 792 793 return 0; 794 } 795 796 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp, 797 unsigned int device_addr, 798 unsigned int reg_addr, 799 unsigned int *data) 800 { 801 u32 reg; 802 int i; 803 int retval; 804 805 for (i = 0; i < 3; i++) { 806 /* Clear AUX CH data buffer */ 807 reg = BUF_CLR; 808 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); 809 810 /* Select EDID device */ 811 retval = analogix_dp_select_i2c_device(dp, device_addr, 812 reg_addr); 813 if (retval != 0) 814 continue; 815 816 /* 817 * Set I2C transaction and read data 818 * If bit 3 is 1, DisplayPort transaction. 819 * If Bit 3 is 0, I2C transaction. 820 */ 821 reg = AUX_TX_COMM_I2C_TRANSACTION | 822 AUX_TX_COMM_READ; 823 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); 824 825 /* Start AUX transaction */ 826 retval = analogix_dp_start_aux_transaction(dp); 827 if (retval == 0) 828 break; 829 } 830 831 /* Read data */ 832 if (retval == 0) 833 *data = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0); 834 835 return retval; 836 } 837 838 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp, 839 unsigned int device_addr, 840 unsigned int reg_addr, 841 unsigned int count, 842 unsigned char edid[]) 843 { 844 u32 reg; 845 unsigned int i, j; 846 unsigned int cur_data_idx; 847 unsigned int defer = 0; 848 int retval = 0; 849 850 for (i = 0; i < count; i += 16) { 851 for (j = 0; j < 3; j++) { 852 /* Clear AUX CH data buffer */ 853 reg = BUF_CLR; 854 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); 855 856 /* Set normal AUX CH command */ 857 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); 858 reg &= ~ADDR_ONLY; 859 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); 860 861 /* 862 * If Rx sends defer, Tx sends only reads 863 * request without sending address 864 */ 865 if (!defer) 866 retval = analogix_dp_select_i2c_device(dp, 867 device_addr, reg_addr + i); 868 else 869 defer = 0; 870 871 if (retval == 0) { 872 /* 873 * Set I2C transaction and write data 874 * If bit 3 is 1, DisplayPort transaction. 875 * If Bit 3 is 0, I2C transaction. 876 */ 877 reg = AUX_LENGTH(16) | 878 AUX_TX_COMM_I2C_TRANSACTION | 879 AUX_TX_COMM_READ; 880 writel(reg, dp->reg_base + 881 ANALOGIX_DP_AUX_CH_CTL_1); 882 883 /* Start AUX transaction */ 884 retval = analogix_dp_start_aux_transaction(dp); 885 if (retval == 0) 886 break; 887 } 888 /* Check if Rx sends defer */ 889 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM); 890 if (reg == AUX_RX_COMM_AUX_DEFER || 891 reg == AUX_RX_COMM_I2C_DEFER) { 892 dev_dbg(dp->dev, "Defer: %d\n\n", reg); 893 defer = 1; 894 } 895 } 896 897 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) { 898 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0 899 + 4 * cur_data_idx); 900 edid[i + cur_data_idx] = (unsigned char)reg; 901 } 902 } 903 904 return retval; 905 } 906 907 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype) 908 { 909 u32 reg; 910 911 reg = bwtype; 912 if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62)) 913 writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET); 914 } 915 916 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype) 917 { 918 u32 reg; 919 920 reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET); 921 *bwtype = reg; 922 } 923 924 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count) 925 { 926 u32 reg; 927 928 reg = count; 929 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET); 930 } 931 932 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count) 933 { 934 u32 reg; 935 936 reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET); 937 *count = reg; 938 } 939 940 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, 941 bool enable) 942 { 943 u32 reg; 944 945 if (enable) { 946 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 947 reg |= ENHANCED; 948 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 949 } else { 950 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 951 reg &= ~ENHANCED; 952 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 953 } 954 } 955 956 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, 957 enum pattern_set pattern) 958 { 959 u32 reg; 960 961 switch (pattern) { 962 case PRBS7: 963 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7; 964 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 965 break; 966 case D10_2: 967 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2; 968 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 969 break; 970 case TRAINING_PTN1: 971 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1; 972 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 973 break; 974 case TRAINING_PTN2: 975 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2; 976 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 977 break; 978 case DP_NONE: 979 reg = SCRAMBLING_ENABLE | 980 LINK_QUAL_PATTERN_SET_DISABLE | 981 SW_TRAINING_PATTERN_SET_NORMAL; 982 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 983 break; 984 default: 985 break; 986 } 987 } 988 989 void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, 990 u32 level) 991 { 992 u32 reg; 993 994 reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); 995 reg &= ~PRE_EMPHASIS_SET_MASK; 996 reg |= level << PRE_EMPHASIS_SET_SHIFT; 997 writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); 998 } 999 1000 void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, 1001 u32 level) 1002 { 1003 u32 reg; 1004 1005 reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); 1006 reg &= ~PRE_EMPHASIS_SET_MASK; 1007 reg |= level << PRE_EMPHASIS_SET_SHIFT; 1008 writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); 1009 } 1010 1011 void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, 1012 u32 level) 1013 { 1014 u32 reg; 1015 1016 reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); 1017 reg &= ~PRE_EMPHASIS_SET_MASK; 1018 reg |= level << PRE_EMPHASIS_SET_SHIFT; 1019 writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); 1020 } 1021 1022 void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, 1023 u32 level) 1024 { 1025 u32 reg; 1026 1027 reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); 1028 reg &= ~PRE_EMPHASIS_SET_MASK; 1029 reg |= level << PRE_EMPHASIS_SET_SHIFT; 1030 writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); 1031 } 1032 1033 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp, 1034 u32 training_lane) 1035 { 1036 u32 reg; 1037 1038 reg = training_lane; 1039 writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); 1040 } 1041 1042 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp, 1043 u32 training_lane) 1044 { 1045 u32 reg; 1046 1047 reg = training_lane; 1048 writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); 1049 } 1050 1051 void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp, 1052 u32 training_lane) 1053 { 1054 u32 reg; 1055 1056 reg = training_lane; 1057 writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); 1058 } 1059 1060 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp, 1061 u32 training_lane) 1062 { 1063 u32 reg; 1064 1065 reg = training_lane; 1066 writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); 1067 } 1068 1069 u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp) 1070 { 1071 u32 reg; 1072 1073 reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); 1074 return reg; 1075 } 1076 1077 u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp) 1078 { 1079 u32 reg; 1080 1081 reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); 1082 return reg; 1083 } 1084 1085 u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp) 1086 { 1087 u32 reg; 1088 1089 reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); 1090 return reg; 1091 } 1092 1093 u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp) 1094 { 1095 u32 reg; 1096 1097 reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); 1098 return reg; 1099 } 1100 1101 void analogix_dp_reset_macro(struct analogix_dp_device *dp) 1102 { 1103 u32 reg; 1104 1105 reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST); 1106 reg |= MACRO_RST; 1107 writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST); 1108 1109 /* 10 us is the minimum reset time. */ 1110 udelay(20); 1111 1112 reg &= ~MACRO_RST; 1113 writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST); 1114 } 1115 1116 void analogix_dp_init_video(struct analogix_dp_device *dp) 1117 { 1118 u32 reg; 1119 1120 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; 1121 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); 1122 1123 reg = 0x0; 1124 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); 1125 1126 reg = CHA_CRI(4) | CHA_CTRL; 1127 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); 1128 1129 reg = 0x0; 1130 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 1131 1132 reg = VID_HRES_TH(2) | VID_VRES_TH(0); 1133 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8); 1134 } 1135 1136 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp) 1137 { 1138 u32 reg; 1139 1140 /* Configure the input color depth, color space, dynamic range */ 1141 reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) | 1142 (dp->video_info.color_depth << IN_BPC_SHIFT) | 1143 (dp->video_info.color_space << IN_COLOR_F_SHIFT); 1144 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2); 1145 1146 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */ 1147 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); 1148 reg &= ~IN_YC_COEFFI_MASK; 1149 if (dp->video_info.ycbcr_coeff) 1150 reg |= IN_YC_COEFFI_ITU709; 1151 else 1152 reg |= IN_YC_COEFFI_ITU601; 1153 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); 1154 } 1155 1156 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp) 1157 { 1158 u32 reg; 1159 1160 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1); 1161 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); 1162 1163 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1); 1164 1165 if (!(reg & DET_STA)) 1166 return -EINVAL; 1167 1168 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2); 1169 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); 1170 1171 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2); 1172 1173 if (reg & CHA_STA) 1174 return -EINVAL; 1175 1176 return 0; 1177 } 1178 1179 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, 1180 enum clock_recovery_m_value_type type, 1181 u32 m_value, u32 n_value) 1182 { 1183 u32 reg; 1184 1185 if (type == REGISTER_M) { 1186 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 1187 reg |= FIX_M_VID; 1188 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 1189 reg = m_value & 0xff; 1190 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0); 1191 reg = (m_value >> 8) & 0xff; 1192 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1); 1193 reg = (m_value >> 16) & 0xff; 1194 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2); 1195 1196 reg = n_value & 0xff; 1197 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0); 1198 reg = (n_value >> 8) & 0xff; 1199 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1); 1200 reg = (n_value >> 16) & 0xff; 1201 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2); 1202 } else { 1203 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 1204 reg &= ~FIX_M_VID; 1205 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 1206 1207 writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0); 1208 writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1); 1209 writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2); 1210 } 1211 } 1212 1213 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type) 1214 { 1215 u32 reg; 1216 1217 if (type == VIDEO_TIMING_FROM_CAPTURE) { 1218 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 1219 reg &= ~FORMAT_SEL; 1220 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 1221 } else { 1222 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 1223 reg |= FORMAT_SEL; 1224 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 1225 } 1226 } 1227 1228 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable) 1229 { 1230 u32 reg; 1231 1232 if (enable) { 1233 reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 1234 reg &= ~VIDEO_MODE_MASK; 1235 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE; 1236 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 1237 } else { 1238 reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 1239 reg &= ~VIDEO_MODE_MASK; 1240 reg |= VIDEO_MODE_SLAVE_MODE; 1241 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 1242 } 1243 } 1244 1245 void analogix_dp_start_video(struct analogix_dp_device *dp) 1246 { 1247 u32 reg; 1248 1249 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 1250 reg |= VIDEO_EN; 1251 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 1252 } 1253 1254 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp) 1255 { 1256 u32 reg; 1257 1258 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 1259 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 1260 1261 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 1262 if (!(reg & STRM_VALID)) 1263 return -EINVAL; 1264 1265 return 0; 1266 } 1267 1268 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp) 1269 { 1270 u32 reg; 1271 1272 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1); 1273 reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N); 1274 reg |= MASTER_VID_FUNC_EN_N; 1275 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); 1276 1277 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 1278 reg &= ~INTERACE_SCAN_CFG; 1279 reg |= (dp->video_info.interlaced << 2); 1280 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 1281 1282 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 1283 reg &= ~VSYNC_POLARITY_CFG; 1284 reg |= (dp->video_info.v_sync_polarity << 1); 1285 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 1286 1287 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 1288 reg &= ~HSYNC_POLARITY_CFG; 1289 reg |= (dp->video_info.h_sync_polarity << 0); 1290 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 1291 1292 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; 1293 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 1294 } 1295 1296 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp) 1297 { 1298 u32 reg; 1299 1300 reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 1301 reg &= ~SCRAMBLING_DISABLE; 1302 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 1303 } 1304 1305 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp) 1306 { 1307 u32 reg; 1308 1309 reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 1310 reg |= SCRAMBLING_DISABLE; 1311 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 1312 } 1313