1 /* 2 * Analogix DP (Display port) core register interface driver. 3 * 4 * Copyright (C) 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 5 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 6 * Author: Jingoo Han <jg1.han@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 */ 13 14 #include <config.h> 15 #include <common.h> 16 #include <errno.h> 17 #include <malloc.h> 18 #include <asm/unaligned.h> 19 #include <linux/list.h> 20 #include <dm/device.h> 21 #include <syscon.h> 22 #include <asm/io.h> 23 #include <asm/gpio.h> 24 #include <linux/iopoll.h> 25 26 #include "rockchip_display.h" 27 #include "rockchip_crtc.h" 28 #include "rockchip_connector.h" 29 #include "analogix_dp.h" 30 31 #define COMMON_INT_MASK_1 0 32 #define COMMON_INT_MASK_2 0 33 #define COMMON_INT_MASK_3 0 34 #define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG) 35 #define INT_STA_MASK INT_HPD 36 37 static void analogix_dp_write(struct analogix_dp_device *dp, u32 reg, u32 val) 38 { 39 readl(dp->reg_base); 40 writel(val, dp->reg_base + reg); 41 writel(val, dp->reg_base + reg); 42 } 43 44 static u32 analogix_dp_read(struct analogix_dp_device *dp, u32 reg) 45 { 46 readl(dp->reg_base + reg); 47 48 return readl(dp->reg_base + reg); 49 } 50 51 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable) 52 { 53 u32 reg; 54 55 if (enable) { 56 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 57 reg |= HDCP_VIDEO_MUTE; 58 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 59 } else { 60 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 61 reg &= ~HDCP_VIDEO_MUTE; 62 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 63 } 64 } 65 66 void analogix_dp_stop_video(struct analogix_dp_device *dp) 67 { 68 u32 reg; 69 70 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 71 reg &= ~VIDEO_EN; 72 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 73 } 74 75 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable) 76 { 77 u32 reg; 78 79 if (enable) 80 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 | 81 LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3; 82 else 83 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | 84 LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0; 85 86 analogix_dp_write(dp, ANALOGIX_DP_LANE_MAP, reg); 87 } 88 89 void analogix_dp_init_analog_param(struct analogix_dp_device *dp) 90 { 91 u32 reg; 92 93 reg = TX_TERMINAL_CTRL_50_OHM; 94 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_1, reg); 95 96 reg = SEL_24M | TX_DVDD_BIT_1_0625V; 97 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_2, reg); 98 99 if (dp->plat_data.dev_type == ROCKCHIP_DP) { 100 reg = REF_CLK_24M; 101 if (dp->plat_data.subdev_type == RK3288_DP || 102 dp->plat_data.subdev_type == RK3368_EDP) 103 reg ^= REF_CLK_MASK; 104 105 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_1, reg); 106 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_2, 0x99); 107 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_3, 0x40); 108 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_4, 0x58); 109 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_5, 0x22); 110 analogix_dp_write(dp, ANALOGIX_DP_BIAS, 0x44); 111 } 112 113 reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO; 114 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_3, reg); 115 116 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | 117 TX_CUR1_2X | TX_CUR_16_MA; 118 analogix_dp_write(dp, ANALOGIX_DP_PLL_FILTER_CTL_1, reg); 119 120 reg = CH3_AMP_400_MV | CH2_AMP_400_MV | 121 CH1_AMP_400_MV | CH0_AMP_400_MV; 122 analogix_dp_write(dp, ANALOGIX_DP_TX_AMP_TUNING_CTL, reg); 123 } 124 125 void analogix_dp_init_interrupt(struct analogix_dp_device *dp) 126 { 127 /* Set interrupt pin assertion polarity as high */ 128 analogix_dp_write(dp, ANALOGIX_DP_INT_CTL, INT_POL1 | INT_POL0); 129 130 /* Clear pending regisers */ 131 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, 0xff); 132 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_2, 0x4f); 133 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_3, 0xe0); 134 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_4, 0xe7); 135 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, 0x63); 136 137 /* 0:mask,1: unmask */ 138 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_1, 0x00); 139 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_2, 0x00); 140 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_3, 0x00); 141 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, 0x00); 142 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, 0x00); 143 } 144 145 void analogix_dp_reset(struct analogix_dp_device *dp) 146 { 147 u32 reg; 148 149 analogix_dp_stop_video(dp); 150 analogix_dp_enable_video_mute(dp, 0); 151 152 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | 153 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | 154 HDCP_FUNC_EN_N | SW_FUNC_EN_N; 155 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg); 156 157 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | 158 SERDES_FIFO_FUNC_EN_N | 159 LS_CLK_DOMAIN_FUNC_EN_N; 160 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 161 162 udelay(30); 163 164 analogix_dp_lane_swap(dp, 0); 165 166 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, 0x0); 167 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, 0x40); 168 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, 0x0); 169 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, 0x0); 170 171 analogix_dp_write(dp, ANALOGIX_DP_PKT_SEND_CTL, 0x0); 172 analogix_dp_write(dp, ANALOGIX_DP_HDCP_CTL, 0x0); 173 174 analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_L, 0x5e); 175 analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_H, 0x1a); 176 177 analogix_dp_write(dp, ANALOGIX_DP_LINK_DEBUG_CTL, 0x10); 178 179 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, 0x0); 180 181 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_FIFO_THRD, 0x0); 182 analogix_dp_write(dp, ANALOGIX_DP_AUDIO_MARGIN, 0x20); 183 184 analogix_dp_write(dp, ANALOGIX_DP_M_VID_GEN_FILTER_TH, 0x4); 185 analogix_dp_write(dp, ANALOGIX_DP_M_AUD_GEN_FILTER_TH, 0x2); 186 187 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, 0x00000101); 188 } 189 190 void analogix_dp_swreset(struct analogix_dp_device *dp) 191 { 192 analogix_dp_write(dp, ANALOGIX_DP_TX_SW_RESET, RESET_DP_TX); 193 } 194 195 void analogix_dp_config_interrupt(struct analogix_dp_device *dp) 196 { 197 u32 reg; 198 199 /* 0: mask, 1: unmask */ 200 reg = COMMON_INT_MASK_1; 201 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_1, reg); 202 203 reg = COMMON_INT_MASK_2; 204 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_2, reg); 205 206 reg = COMMON_INT_MASK_3; 207 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_3, reg); 208 209 reg = COMMON_INT_MASK_4; 210 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg); 211 212 reg = INT_STA_MASK; 213 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg); 214 } 215 216 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp) 217 { 218 u32 reg; 219 220 /* 0: mask, 1: unmask */ 221 reg = analogix_dp_read(dp, ANALOGIX_DP_COMMON_INT_MASK_4); 222 reg &= ~COMMON_INT_MASK_4; 223 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg); 224 225 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA_MASK); 226 reg &= ~INT_STA_MASK; 227 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg); 228 } 229 230 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp) 231 { 232 u32 reg; 233 234 /* 0: mask, 1: unmask */ 235 reg = COMMON_INT_MASK_4; 236 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg); 237 238 reg = INT_STA_MASK; 239 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg); 240 } 241 242 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp) 243 { 244 u32 reg; 245 246 reg = analogix_dp_read(dp, ANALOGIX_DP_DEBUG_CTL); 247 if (reg & PLL_LOCK) 248 return PLL_LOCKED; 249 else 250 return PLL_UNLOCKED; 251 } 252 253 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable) 254 { 255 u32 reg; 256 257 if (enable) { 258 reg = analogix_dp_read(dp, ANALOGIX_DP_PLL_CTL); 259 reg |= DP_PLL_PD; 260 analogix_dp_write(dp, ANALOGIX_DP_PLL_CTL, reg); 261 } else { 262 reg = analogix_dp_read(dp, ANALOGIX_DP_PLL_CTL); 263 reg &= ~DP_PLL_PD; 264 analogix_dp_write(dp, ANALOGIX_DP_PLL_CTL, reg); 265 } 266 } 267 268 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 269 enum analog_power_block block, 270 bool enable) 271 { 272 u32 reg; 273 u32 phy_pd_addr = ANALOGIX_DP_PHY_PD; 274 275 if (dp->plat_data.dev_type == ROCKCHIP_DP) 276 phy_pd_addr = ANALOGIX_DP_PD; 277 278 switch (block) { 279 case AUX_BLOCK: 280 if (enable) { 281 reg = analogix_dp_read(dp, phy_pd_addr); 282 reg |= AUX_PD; 283 analogix_dp_write(dp, phy_pd_addr, reg); 284 } else { 285 reg = analogix_dp_read(dp, phy_pd_addr); 286 reg &= ~AUX_PD; 287 analogix_dp_write(dp, phy_pd_addr, reg); 288 } 289 break; 290 case CH0_BLOCK: 291 if (enable) { 292 reg = analogix_dp_read(dp, phy_pd_addr); 293 reg |= CH0_PD; 294 analogix_dp_write(dp, phy_pd_addr, reg); 295 } else { 296 reg = analogix_dp_read(dp, phy_pd_addr); 297 reg &= ~CH0_PD; 298 analogix_dp_write(dp, phy_pd_addr, reg); 299 } 300 break; 301 case CH1_BLOCK: 302 if (enable) { 303 reg = analogix_dp_read(dp, phy_pd_addr); 304 reg |= CH1_PD; 305 analogix_dp_write(dp, phy_pd_addr, reg); 306 } else { 307 reg = analogix_dp_read(dp, phy_pd_addr); 308 reg &= ~CH1_PD; 309 analogix_dp_write(dp, phy_pd_addr, reg); 310 } 311 break; 312 case CH2_BLOCK: 313 if (enable) { 314 reg = analogix_dp_read(dp, phy_pd_addr); 315 reg |= CH2_PD; 316 analogix_dp_write(dp, phy_pd_addr, reg); 317 } else { 318 reg = analogix_dp_read(dp, phy_pd_addr); 319 reg &= ~CH2_PD; 320 analogix_dp_write(dp, phy_pd_addr, reg); 321 } 322 break; 323 case CH3_BLOCK: 324 if (enable) { 325 reg = analogix_dp_read(dp, phy_pd_addr); 326 reg |= CH3_PD; 327 analogix_dp_write(dp, phy_pd_addr, reg); 328 } else { 329 reg = analogix_dp_read(dp, phy_pd_addr); 330 reg &= ~CH3_PD; 331 analogix_dp_write(dp, phy_pd_addr, reg); 332 } 333 break; 334 case ANALOG_TOTAL: 335 if (enable) { 336 reg = analogix_dp_read(dp, phy_pd_addr); 337 reg |= DP_PHY_PD; 338 analogix_dp_write(dp, phy_pd_addr, reg); 339 } else { 340 reg = analogix_dp_read(dp, phy_pd_addr); 341 reg &= ~DP_PHY_PD; 342 analogix_dp_write(dp, phy_pd_addr, reg); 343 } 344 break; 345 case POWER_ALL: 346 if (enable) { 347 reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD | 348 CH1_PD | CH0_PD; 349 analogix_dp_write(dp, phy_pd_addr, reg); 350 } else { 351 analogix_dp_write(dp, phy_pd_addr, 0x00); 352 } 353 break; 354 default: 355 break; 356 } 357 } 358 359 void analogix_dp_init_analog_func(struct analogix_dp_device *dp) 360 { 361 u32 reg; 362 363 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 364 365 reg = PLL_LOCK_CHG; 366 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, reg); 367 368 reg = analogix_dp_read(dp, ANALOGIX_DP_DEBUG_CTL); 369 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); 370 analogix_dp_write(dp, ANALOGIX_DP_DEBUG_CTL, reg); 371 372 /* Power up PLL */ 373 analogix_dp_set_pll_power_down(dp, 0); 374 375 /* Enable Serdes FIFO function and Link symbol clock domain module */ 376 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2); 377 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N 378 | AUX_FUNC_EN_N); 379 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 380 } 381 382 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp) 383 { 384 u32 reg; 385 386 if (dm_gpio_is_valid(&dp->hpd_gpio)) 387 return; 388 389 reg = HOTPLUG_CHG | HPD_LOST | PLUG; 390 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_4, reg); 391 392 reg = INT_HPD; 393 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg); 394 } 395 396 void analogix_dp_init_hpd(struct analogix_dp_device *dp) 397 { 398 u32 reg; 399 400 if (dm_gpio_is_valid(&dp->hpd_gpio)) 401 return; 402 403 analogix_dp_clear_hotplug_interrupts(dp); 404 405 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 406 reg &= ~(F_HPD | HPD_CTRL); 407 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 408 } 409 410 void analogix_dp_force_hpd(struct analogix_dp_device *dp) 411 { 412 u32 reg; 413 414 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 415 reg |= (F_HPD | HPD_CTRL); 416 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 417 } 418 419 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp) 420 { 421 u32 reg; 422 423 if (dm_gpio_is_valid(&dp->hpd_gpio)) { 424 reg = dm_gpio_get_value(&dp->hpd_gpio); 425 if (reg) 426 return DP_IRQ_TYPE_HP_CABLE_IN; 427 else 428 return DP_IRQ_TYPE_HP_CABLE_OUT; 429 } else { 430 /* Parse hotplug interrupt status register */ 431 reg = analogix_dp_read(dp, ANALOGIX_DP_COMMON_INT_STA_4); 432 433 if (reg & PLUG) 434 return DP_IRQ_TYPE_HP_CABLE_IN; 435 436 if (reg & HPD_LOST) 437 return DP_IRQ_TYPE_HP_CABLE_OUT; 438 439 if (reg & HOTPLUG_CHG) 440 return DP_IRQ_TYPE_HP_CHANGE; 441 442 return DP_IRQ_TYPE_UNKNOWN; 443 } 444 } 445 446 void analogix_dp_reset_aux(struct analogix_dp_device *dp) 447 { 448 u32 reg; 449 450 /* Disable AUX channel module */ 451 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2); 452 reg |= AUX_FUNC_EN_N; 453 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 454 } 455 456 void analogix_dp_init_aux(struct analogix_dp_device *dp) 457 { 458 u32 reg; 459 460 /* Clear inerrupts related to AUX channel */ 461 reg = RPLY_RECEIV | AUX_ERR; 462 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg); 463 464 analogix_dp_reset_aux(dp); 465 466 /* Disable AUX transaction H/W retry */ 467 if (dp->plat_data.dev_type == ROCKCHIP_DP) 468 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) | 469 AUX_HW_RETRY_COUNT_SEL(3) | 470 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; 471 else 472 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | 473 AUX_HW_RETRY_COUNT_SEL(0) | 474 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; 475 analogix_dp_write(dp, ANALOGIX_DP_AUX_HW_RETRY_CTL, reg); 476 477 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ 478 reg = DEFER_CTRL_EN | DEFER_COUNT(1); 479 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_DEFER_CTL, reg); 480 481 /* Enable AUX channel module */ 482 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2); 483 reg &= ~AUX_FUNC_EN_N; 484 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 485 } 486 487 int analogix_dp_detect(struct analogix_dp_device *dp) 488 { 489 u32 reg; 490 491 if (dm_gpio_is_valid(&dp->hpd_gpio)) 492 return dm_gpio_get_value(&dp->hpd_gpio); 493 494 if (dp->force_hpd) 495 analogix_dp_force_hpd(dp); 496 497 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 498 if (reg & HPD_STATUS) 499 return 1; 500 501 return 0; 502 } 503 504 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp) 505 { 506 u32 reg; 507 508 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_1); 509 reg &= ~SW_FUNC_EN_N; 510 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg); 511 } 512 513 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp) 514 { 515 int reg; 516 int retval = 0; 517 int timeout_loop = 0; 518 519 /* Enable AUX CH operation */ 520 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_CTL_2); 521 reg |= AUX_EN; 522 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_2, reg); 523 524 /* Is AUX CH command reply received? */ 525 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA); 526 while (!(reg & RPLY_RECEIV)) { 527 timeout_loop++; 528 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { 529 dev_err(dp->dev, "AUX CH command reply failed!\n"); 530 return -ETIMEDOUT; 531 } 532 533 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA); 534 udelay(11); 535 } 536 537 /* Clear interrupt source for AUX CH command reply */ 538 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg); 539 540 /* Clear interrupt source for AUX CH access error */ 541 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA); 542 if (reg & AUX_ERR) { 543 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, AUX_ERR); 544 return -EREMOTEIO; 545 } 546 547 /* Check AUX CH error access status */ 548 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_STA); 549 if ((reg & AUX_STATUS_MASK) != 0) { 550 dev_err(dp->dev, 551 "AUX CH error happens: %d\n", reg & AUX_STATUS_MASK); 552 return -EREMOTEIO; 553 } 554 555 return retval; 556 } 557 558 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp, 559 unsigned int reg_addr, 560 unsigned char data) 561 { 562 u32 reg; 563 int i; 564 int retval; 565 566 for (i = 0; i < 3; i++) { 567 /* Clear AUX CH data buffer */ 568 reg = BUF_CLR; 569 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 570 571 /* Select DPCD device address */ 572 reg = AUX_ADDR_7_0(reg_addr); 573 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 574 reg = AUX_ADDR_15_8(reg_addr); 575 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); 576 reg = AUX_ADDR_19_16(reg_addr); 577 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); 578 579 /* Write data buffer */ 580 reg = (unsigned int)data; 581 analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0, reg); 582 583 /* 584 * Set DisplayPort transaction and write 1 byte 585 * If bit 3 is 1, DisplayPort transaction. 586 * If Bit 3 is 0, I2C transaction. 587 */ 588 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; 589 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 590 591 /* Start AUX transaction */ 592 retval = analogix_dp_start_aux_transaction(dp); 593 if (retval == 0) 594 break; 595 } 596 597 return retval; 598 } 599 600 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp, 601 unsigned int reg_addr, 602 unsigned char *data) 603 { 604 u32 reg; 605 int i; 606 int retval; 607 608 for (i = 0; i < 3; i++) { 609 /* Clear AUX CH data buffer */ 610 reg = BUF_CLR; 611 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 612 613 /* Select DPCD device address */ 614 reg = AUX_ADDR_7_0(reg_addr); 615 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 616 reg = AUX_ADDR_15_8(reg_addr); 617 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); 618 reg = AUX_ADDR_19_16(reg_addr); 619 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); 620 621 /* 622 * Set DisplayPort transaction and read 1 byte 623 * If bit 3 is 1, DisplayPort transaction. 624 * If Bit 3 is 0, I2C transaction. 625 */ 626 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; 627 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 628 629 /* Start AUX transaction */ 630 retval = analogix_dp_start_aux_transaction(dp); 631 if (retval == 0) 632 break; 633 } 634 635 /* Read data buffer */ 636 reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0); 637 *data = (unsigned char)(reg & 0xff); 638 639 return retval; 640 } 641 642 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp, 643 unsigned int reg_addr, 644 unsigned int count, 645 unsigned char data[]) 646 { 647 u32 reg; 648 unsigned int start_offset; 649 unsigned int cur_data_count; 650 unsigned int cur_data_idx; 651 int i; 652 int retval = 0; 653 654 /* Clear AUX CH data buffer */ 655 reg = BUF_CLR; 656 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 657 658 start_offset = 0; 659 while (start_offset < count) { 660 /* Buffer size of AUX CH is 16 * 4bytes */ 661 if ((count - start_offset) > 16) 662 cur_data_count = 16; 663 else 664 cur_data_count = count - start_offset; 665 666 for (i = 0; i < 3; i++) { 667 /* Select DPCD device address */ 668 reg = AUX_ADDR_7_0(reg_addr + start_offset); 669 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 670 reg = AUX_ADDR_15_8(reg_addr + start_offset); 671 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); 672 reg = AUX_ADDR_19_16(reg_addr + start_offset); 673 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); 674 675 for (cur_data_idx = 0; cur_data_idx < cur_data_count; 676 cur_data_idx++) { 677 reg = data[start_offset + cur_data_idx]; 678 analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0 + 679 4 * cur_data_idx, reg); 680 } 681 682 /* 683 * Set DisplayPort transaction and write 684 * If bit 3 is 1, DisplayPort transaction. 685 * If Bit 3 is 0, I2C transaction. 686 */ 687 reg = AUX_LENGTH(cur_data_count) | 688 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; 689 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 690 691 /* Start AUX transaction */ 692 retval = analogix_dp_start_aux_transaction(dp); 693 if (retval == 0) 694 break; 695 } 696 697 start_offset += cur_data_count; 698 } 699 700 return retval; 701 } 702 703 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp, 704 unsigned int reg_addr, 705 unsigned int count, 706 unsigned char data[]) 707 { 708 u32 reg; 709 unsigned int start_offset; 710 unsigned int cur_data_count; 711 unsigned int cur_data_idx; 712 int i; 713 int retval = 0; 714 715 /* Clear AUX CH data buffer */ 716 reg = BUF_CLR; 717 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 718 719 start_offset = 0; 720 while (start_offset < count) { 721 /* Buffer size of AUX CH is 16 * 4bytes */ 722 if ((count - start_offset) > 16) 723 cur_data_count = 16; 724 else 725 cur_data_count = count - start_offset; 726 727 /* AUX CH Request Transaction process */ 728 for (i = 0; i < 3; i++) { 729 /* Select DPCD device address */ 730 reg = AUX_ADDR_7_0(reg_addr + start_offset); 731 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 732 reg = AUX_ADDR_15_8(reg_addr + start_offset); 733 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); 734 reg = AUX_ADDR_19_16(reg_addr + start_offset); 735 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); 736 737 /* 738 * Set DisplayPort transaction and read 739 * If bit 3 is 1, DisplayPort transaction. 740 * If Bit 3 is 0, I2C transaction. 741 */ 742 reg = AUX_LENGTH(cur_data_count) | 743 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; 744 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 745 746 /* Start AUX transaction */ 747 retval = analogix_dp_start_aux_transaction(dp); 748 if (retval == 0) 749 break; 750 } 751 752 for (cur_data_idx = 0; cur_data_idx < cur_data_count; 753 cur_data_idx++) { 754 reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0 755 + 4 * cur_data_idx); 756 data[start_offset + cur_data_idx] = 757 (unsigned char)reg; 758 } 759 760 start_offset += cur_data_count; 761 } 762 763 return retval; 764 } 765 766 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp, 767 unsigned int device_addr, 768 unsigned int reg_addr) 769 { 770 u32 reg; 771 int retval; 772 773 /* Set EDID device address */ 774 reg = device_addr; 775 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 776 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, 0x0); 777 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, 0x0); 778 779 /* Set offset from base address of EDID device */ 780 analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0, reg_addr); 781 782 /* 783 * Set I2C transaction and write address 784 * If bit 3 is 1, DisplayPort transaction. 785 * If Bit 3 is 0, I2C transaction. 786 */ 787 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT | 788 AUX_TX_COMM_WRITE; 789 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 790 791 /* Start AUX transaction */ 792 retval = analogix_dp_start_aux_transaction(dp); 793 if (retval < 0) 794 return retval; 795 796 return 0; 797 } 798 799 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp, 800 unsigned int device_addr, 801 unsigned int reg_addr, 802 unsigned int *data) 803 { 804 u32 reg; 805 int i; 806 int retval; 807 808 for (i = 0; i < 3; i++) { 809 /* Clear AUX CH data buffer */ 810 reg = BUF_CLR; 811 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 812 813 /* Select EDID device */ 814 retval = analogix_dp_select_i2c_device(dp, device_addr, 815 reg_addr); 816 if (retval != 0) 817 continue; 818 819 /* 820 * Set I2C transaction and read data 821 * If bit 3 is 1, DisplayPort transaction. 822 * If Bit 3 is 0, I2C transaction. 823 */ 824 reg = AUX_TX_COMM_I2C_TRANSACTION | 825 AUX_TX_COMM_READ; 826 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 827 828 /* Start AUX transaction */ 829 retval = analogix_dp_start_aux_transaction(dp); 830 if (retval == 0) 831 break; 832 } 833 834 /* Read data */ 835 if (retval == 0) 836 *data = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0); 837 838 return retval; 839 } 840 841 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp, 842 unsigned int device_addr, 843 unsigned int reg_addr, 844 unsigned int count, 845 unsigned char edid[]) 846 { 847 u32 reg; 848 unsigned int i, j; 849 unsigned int cur_data_idx; 850 unsigned int defer = 0; 851 int retval = 0; 852 853 for (i = 0; i < count; i += 16) { 854 for (j = 0; j < 3; j++) { 855 /* Clear AUX CH data buffer */ 856 reg = BUF_CLR; 857 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 858 859 /* Set normal AUX CH command */ 860 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_CTL_2); 861 reg &= ~ADDR_ONLY; 862 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_2, reg); 863 864 /* 865 * If Rx sends defer, Tx sends only reads 866 * request without sending address 867 */ 868 if (!defer) 869 retval = analogix_dp_select_i2c_device(dp, 870 device_addr, reg_addr + i); 871 else 872 defer = 0; 873 874 if (retval == 0) { 875 /* 876 * Set I2C transaction and write data 877 * If bit 3 is 1, DisplayPort transaction. 878 * If Bit 3 is 0, I2C transaction. 879 */ 880 reg = AUX_LENGTH(16) | 881 AUX_TX_COMM_I2C_TRANSACTION | 882 AUX_TX_COMM_READ; 883 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, 884 reg); 885 886 /* Start AUX transaction */ 887 retval = analogix_dp_start_aux_transaction(dp); 888 if (retval == 0) 889 break; 890 } 891 /* Check if Rx sends defer */ 892 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_RX_COMM); 893 if (reg == AUX_RX_COMM_AUX_DEFER || 894 reg == AUX_RX_COMM_I2C_DEFER) { 895 dev_dbg(dp->dev, "Defer: %d\n\n", reg); 896 defer = 1; 897 } 898 } 899 900 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) { 901 reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0 902 + 4 * cur_data_idx); 903 edid[i + cur_data_idx] = (unsigned char)reg; 904 } 905 } 906 907 return retval; 908 } 909 910 bool analogix_dp_ssc_supported(struct analogix_dp_device *dp) 911 { 912 /* Check if SSC is supported by both sides */ 913 return dp->plat_data.ssc && dp->link_train.ssc; 914 } 915 916 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype) 917 { 918 union phy_configure_opts phy_cfg; 919 u32 reg, status; 920 int ret; 921 922 reg = bwtype; 923 if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62)) 924 analogix_dp_write(dp, ANALOGIX_DP_LINK_BW_SET, reg); 925 926 phy_cfg.dp.lanes = dp->link_train.lane_count; 927 phy_cfg.dp.link_rate = 928 drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100; 929 phy_cfg.dp.ssc = analogix_dp_ssc_supported(dp); 930 phy_cfg.dp.set_lanes = false; 931 phy_cfg.dp.set_rate = true; 932 phy_cfg.dp.set_voltages = false; 933 ret = generic_phy_configure(&dp->phy, &phy_cfg); 934 if (ret) { 935 dev_err(dp->dev, "%s: phy_configure() failed: %d\n", 936 __func__, ret); 937 return; 938 } 939 940 ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status, 941 status != PLL_UNLOCKED, 942 120 * DP_TIMEOUT_LOOP_COUNT); 943 if (ret) { 944 dev_err(dp->dev, "Wait for pll lock failed %d\n", ret); 945 return; 946 } 947 } 948 949 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype) 950 { 951 u32 reg; 952 953 reg = analogix_dp_read(dp, ANALOGIX_DP_LINK_BW_SET); 954 *bwtype = reg; 955 } 956 957 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count) 958 { 959 union phy_configure_opts phy_cfg; 960 u32 reg; 961 int ret; 962 963 reg = count; 964 analogix_dp_write(dp, ANALOGIX_DP_LANE_COUNT_SET, reg); 965 966 phy_cfg.dp.lanes = dp->link_train.lane_count; 967 phy_cfg.dp.set_lanes = true; 968 phy_cfg.dp.set_rate = false; 969 phy_cfg.dp.set_voltages = false; 970 ret = generic_phy_configure(&dp->phy, &phy_cfg); 971 if (ret) { 972 dev_err(dp->dev, "%s: phy_configure() failed: %d\n", 973 __func__, ret); 974 return; 975 } 976 } 977 978 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count) 979 { 980 u32 reg; 981 982 reg = analogix_dp_read(dp, ANALOGIX_DP_LANE_COUNT_SET); 983 *count = reg; 984 } 985 986 void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp) 987 { 988 union phy_configure_opts phy_cfg; 989 u8 lane; 990 int ret; 991 992 for (lane = 0; lane < dp->link_train.lane_count; lane++) { 993 u8 training_lane = dp->link_train.training_lane[lane]; 994 u8 vs, pe; 995 996 analogix_dp_write(dp, 997 ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane, 998 dp->link_train.training_lane[lane]); 999 1000 vs = (training_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >> 1001 DP_TRAIN_VOLTAGE_SWING_SHIFT; 1002 pe = (training_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >> 1003 DP_TRAIN_PRE_EMPHASIS_SHIFT; 1004 phy_cfg.dp.voltage[lane] = vs; 1005 phy_cfg.dp.pre[lane] = pe; 1006 } 1007 1008 phy_cfg.dp.lanes = dp->link_train.lane_count; 1009 phy_cfg.dp.set_lanes = false; 1010 phy_cfg.dp.set_rate = false; 1011 phy_cfg.dp.set_voltages = true; 1012 ret = generic_phy_configure(&dp->phy, &phy_cfg); 1013 if (ret) { 1014 dev_err(dp->dev, "%s: phy_configure() failed: %d\n", 1015 __func__, ret); 1016 return; 1017 } 1018 } 1019 1020 u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane) 1021 { 1022 return analogix_dp_read(dp, 1023 ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane); 1024 } 1025 1026 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, 1027 bool enable) 1028 { 1029 u32 reg; 1030 1031 if (enable) { 1032 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 1033 reg |= ENHANCED; 1034 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 1035 } else { 1036 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 1037 reg &= ~ENHANCED; 1038 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 1039 } 1040 } 1041 1042 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, 1043 enum pattern_set pattern) 1044 { 1045 u32 reg; 1046 1047 switch (pattern) { 1048 case PRBS7: 1049 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7; 1050 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1051 break; 1052 case D10_2: 1053 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2; 1054 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1055 break; 1056 case TRAINING_PTN1: 1057 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1; 1058 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1059 break; 1060 case TRAINING_PTN2: 1061 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2; 1062 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1063 break; 1064 case DP_NONE: 1065 reg = SCRAMBLING_ENABLE | 1066 LINK_QUAL_PATTERN_SET_DISABLE | 1067 SW_TRAINING_PATTERN_SET_NORMAL; 1068 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1069 break; 1070 default: 1071 break; 1072 } 1073 } 1074 1075 void analogix_dp_reset_macro(struct analogix_dp_device *dp) 1076 { 1077 u32 reg; 1078 1079 reg = analogix_dp_read(dp, ANALOGIX_DP_PHY_TEST); 1080 reg |= MACRO_RST; 1081 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, reg); 1082 1083 /* 10 us is the minimum reset time. */ 1084 udelay(20); 1085 1086 reg &= ~MACRO_RST; 1087 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, reg); 1088 } 1089 1090 void analogix_dp_init_video(struct analogix_dp_device *dp) 1091 { 1092 u32 reg; 1093 1094 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; 1095 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, reg); 1096 1097 reg = 0x0; 1098 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, reg); 1099 1100 reg = CHA_CRI(4) | CHA_CTRL; 1101 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, reg); 1102 1103 reg = 0x0; 1104 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 1105 1106 reg = VID_HRES_TH(2) | VID_VRES_TH(0); 1107 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_8, reg); 1108 } 1109 1110 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp) 1111 { 1112 u32 reg; 1113 1114 /* Configure the input color depth, color space, dynamic range */ 1115 reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) | 1116 (dp->video_info.color_depth << IN_BPC_SHIFT) | 1117 (dp->video_info.color_space << IN_COLOR_F_SHIFT); 1118 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_2, reg); 1119 1120 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */ 1121 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_3); 1122 reg &= ~IN_YC_COEFFI_MASK; 1123 if (dp->video_info.ycbcr_coeff) 1124 reg |= IN_YC_COEFFI_ITU709; 1125 else 1126 reg |= IN_YC_COEFFI_ITU601; 1127 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_3, reg); 1128 } 1129 1130 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp) 1131 { 1132 u32 reg; 1133 1134 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_1); 1135 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, reg); 1136 1137 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_1); 1138 1139 if (!(reg & DET_STA)) 1140 return -EINVAL; 1141 1142 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_2); 1143 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, reg); 1144 1145 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_2); 1146 1147 if (reg & CHA_STA) 1148 return -EINVAL; 1149 1150 return 0; 1151 } 1152 1153 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, 1154 enum clock_recovery_m_value_type type, 1155 u32 m_value, u32 n_value) 1156 { 1157 u32 reg; 1158 1159 if (type == REGISTER_M) { 1160 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 1161 reg |= FIX_M_VID; 1162 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 1163 reg = m_value & 0xff; 1164 analogix_dp_write(dp, ANALOGIX_DP_M_VID_0, reg); 1165 reg = (m_value >> 8) & 0xff; 1166 analogix_dp_write(dp, ANALOGIX_DP_M_VID_1, reg); 1167 reg = (m_value >> 16) & 0xff; 1168 analogix_dp_write(dp, ANALOGIX_DP_M_VID_2, reg); 1169 1170 reg = n_value & 0xff; 1171 analogix_dp_write(dp, ANALOGIX_DP_N_VID_0, reg); 1172 reg = (n_value >> 8) & 0xff; 1173 analogix_dp_write(dp, ANALOGIX_DP_N_VID_1, reg); 1174 reg = (n_value >> 16) & 0xff; 1175 analogix_dp_write(dp, ANALOGIX_DP_N_VID_2, reg); 1176 } else { 1177 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 1178 reg &= ~FIX_M_VID; 1179 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 1180 1181 analogix_dp_write(dp, ANALOGIX_DP_N_VID_0, 0x00); 1182 analogix_dp_write(dp, ANALOGIX_DP_N_VID_1, 0x80); 1183 analogix_dp_write(dp, ANALOGIX_DP_N_VID_2, 0x00); 1184 } 1185 } 1186 1187 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type) 1188 { 1189 u32 reg; 1190 1191 if (type == VIDEO_TIMING_FROM_CAPTURE) { 1192 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1193 reg &= ~FORMAT_SEL; 1194 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1195 } else { 1196 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1197 reg |= FORMAT_SEL; 1198 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1199 } 1200 } 1201 1202 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable) 1203 { 1204 u32 reg; 1205 1206 if (enable) { 1207 reg = analogix_dp_read(dp, ANALOGIX_DP_SOC_GENERAL_CTL); 1208 reg &= ~VIDEO_MODE_MASK; 1209 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE; 1210 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg); 1211 } else { 1212 reg = analogix_dp_read(dp, ANALOGIX_DP_SOC_GENERAL_CTL); 1213 reg &= ~VIDEO_MODE_MASK; 1214 reg |= VIDEO_MODE_SLAVE_MODE; 1215 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg); 1216 } 1217 } 1218 1219 void analogix_dp_start_video(struct analogix_dp_device *dp) 1220 { 1221 u32 reg; 1222 1223 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 1224 reg |= VIDEO_EN; 1225 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 1226 } 1227 1228 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp) 1229 { 1230 u32 reg; 1231 1232 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 1233 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 1234 1235 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 1236 if (!(reg & STRM_VALID)) 1237 return -EINVAL; 1238 1239 return 0; 1240 } 1241 1242 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp) 1243 { 1244 u32 reg; 1245 1246 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_1); 1247 reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N); 1248 reg |= MASTER_VID_FUNC_EN_N; 1249 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg); 1250 1251 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1252 reg &= ~INTERACE_SCAN_CFG; 1253 reg |= (dp->video_info.interlaced << 2); 1254 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1255 1256 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1257 reg &= ~VSYNC_POLARITY_CFG; 1258 reg |= (dp->video_info.v_sync_polarity << 1); 1259 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1260 1261 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1262 reg &= ~HSYNC_POLARITY_CFG; 1263 reg |= (dp->video_info.h_sync_polarity << 0); 1264 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1265 1266 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; 1267 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg); 1268 } 1269 1270 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp) 1271 { 1272 u32 reg; 1273 1274 reg = analogix_dp_read(dp, ANALOGIX_DP_TRAINING_PTN_SET); 1275 reg &= ~SCRAMBLING_DISABLE; 1276 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1277 } 1278 1279 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp) 1280 { 1281 u32 reg; 1282 1283 reg = analogix_dp_read(dp, ANALOGIX_DP_TRAINING_PTN_SET); 1284 reg |= SCRAMBLING_DISABLE; 1285 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1286 } 1287