1 /* 2 * Analogix DP (Display port) core register interface driver. 3 * 4 * Copyright (C) 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 5 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 6 * Author: Jingoo Han <jg1.han@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 */ 13 14 #include <config.h> 15 #include <common.h> 16 #include <errno.h> 17 #include <malloc.h> 18 #include <asm/unaligned.h> 19 #include <linux/list.h> 20 #include <dm/device.h> 21 #include <syscon.h> 22 #include <asm/io.h> 23 #include <asm/gpio.h> 24 #include <linux/iopoll.h> 25 26 #include "rockchip_display.h" 27 #include "rockchip_crtc.h" 28 #include "rockchip_connector.h" 29 #include "analogix_dp.h" 30 31 #define COMMON_INT_MASK_1 0 32 #define COMMON_INT_MASK_2 0 33 #define COMMON_INT_MASK_3 0 34 #define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG) 35 #define INT_STA_MASK INT_HPD 36 37 static void analogix_dp_write(struct analogix_dp_device *dp, u32 reg, u32 val) 38 { 39 readl(dp->reg_base); 40 writel(val, dp->reg_base + reg); 41 writel(val, dp->reg_base + reg); 42 } 43 44 static u32 analogix_dp_read(struct analogix_dp_device *dp, u32 reg) 45 { 46 readl(dp->reg_base + reg); 47 48 return readl(dp->reg_base + reg); 49 } 50 51 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable) 52 { 53 u32 reg; 54 55 if (enable) { 56 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 57 reg |= HDCP_VIDEO_MUTE; 58 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 59 } else { 60 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 61 reg &= ~HDCP_VIDEO_MUTE; 62 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 63 } 64 } 65 66 void analogix_dp_stop_video(struct analogix_dp_device *dp) 67 { 68 u32 reg; 69 70 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 71 reg &= ~VIDEO_EN; 72 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 73 } 74 75 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable) 76 { 77 u32 reg; 78 79 if (enable) 80 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 | 81 LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3; 82 else 83 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | 84 LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0; 85 86 analogix_dp_write(dp, ANALOGIX_DP_LANE_MAP, reg); 87 } 88 89 void analogix_dp_init_analog_param(struct analogix_dp_device *dp) 90 { 91 u32 reg; 92 93 reg = TX_TERMINAL_CTRL_50_OHM; 94 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_1, reg); 95 96 reg = SEL_24M | TX_DVDD_BIT_1_0625V; 97 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_2, reg); 98 99 if (dp->plat_data.dev_type == ROCKCHIP_DP) { 100 reg = REF_CLK_24M; 101 if (dp->plat_data.subdev_type == RK3288_DP || 102 dp->plat_data.subdev_type == RK3368_EDP) 103 reg ^= REF_CLK_MASK; 104 105 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_1, reg); 106 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_2, 0x99); 107 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_3, 0x40); 108 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_4, 0x58); 109 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_5, 0x22); 110 analogix_dp_write(dp, ANALOGIX_DP_BIAS, 0x44); 111 } 112 113 reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO; 114 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_3, reg); 115 116 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | 117 TX_CUR1_2X | TX_CUR_16_MA; 118 analogix_dp_write(dp, ANALOGIX_DP_PLL_FILTER_CTL_1, reg); 119 120 reg = CH3_AMP_400_MV | CH2_AMP_400_MV | 121 CH1_AMP_400_MV | CH0_AMP_400_MV; 122 analogix_dp_write(dp, ANALOGIX_DP_TX_AMP_TUNING_CTL, reg); 123 } 124 125 void analogix_dp_init_interrupt(struct analogix_dp_device *dp) 126 { 127 /* Set interrupt pin assertion polarity as high */ 128 analogix_dp_write(dp, ANALOGIX_DP_INT_CTL, INT_POL1 | INT_POL0); 129 130 /* Clear pending regisers */ 131 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, 0xff); 132 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_2, 0x4f); 133 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_3, 0xe0); 134 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_4, 0xe7); 135 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, 0x63); 136 137 /* 0:mask,1: unmask */ 138 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_1, 0x00); 139 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_2, 0x00); 140 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_3, 0x00); 141 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, 0x00); 142 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, 0x00); 143 } 144 145 void analogix_dp_reset(struct analogix_dp_device *dp) 146 { 147 u32 reg; 148 149 analogix_dp_stop_video(dp); 150 analogix_dp_enable_video_mute(dp, 0); 151 152 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | 153 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | 154 HDCP_FUNC_EN_N | SW_FUNC_EN_N; 155 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg); 156 157 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | 158 SERDES_FIFO_FUNC_EN_N | 159 LS_CLK_DOMAIN_FUNC_EN_N; 160 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 161 162 udelay(30); 163 164 analogix_dp_lane_swap(dp, 0); 165 166 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, 0x0); 167 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, 0x40); 168 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, 0x0); 169 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, 0x0); 170 171 analogix_dp_write(dp, ANALOGIX_DP_PKT_SEND_CTL, 0x0); 172 analogix_dp_write(dp, ANALOGIX_DP_HDCP_CTL, 0x0); 173 174 analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_L, 0x5e); 175 analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_H, 0x1a); 176 177 analogix_dp_write(dp, ANALOGIX_DP_LINK_DEBUG_CTL, 0x10); 178 179 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, 0x0); 180 181 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_FIFO_THRD, 0x0); 182 analogix_dp_write(dp, ANALOGIX_DP_AUDIO_MARGIN, 0x20); 183 184 analogix_dp_write(dp, ANALOGIX_DP_M_VID_GEN_FILTER_TH, 0x4); 185 analogix_dp_write(dp, ANALOGIX_DP_M_AUD_GEN_FILTER_TH, 0x2); 186 187 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, 0x00000101); 188 } 189 190 void analogix_dp_swreset(struct analogix_dp_device *dp) 191 { 192 analogix_dp_write(dp, ANALOGIX_DP_TX_SW_RESET, RESET_DP_TX); 193 } 194 195 void analogix_dp_config_interrupt(struct analogix_dp_device *dp) 196 { 197 u32 reg; 198 199 /* 0: mask, 1: unmask */ 200 reg = COMMON_INT_MASK_1; 201 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_1, reg); 202 203 reg = COMMON_INT_MASK_2; 204 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_2, reg); 205 206 reg = COMMON_INT_MASK_3; 207 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_3, reg); 208 209 reg = COMMON_INT_MASK_4; 210 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg); 211 212 reg = INT_STA_MASK; 213 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg); 214 } 215 216 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp) 217 { 218 u32 reg; 219 220 /* 0: mask, 1: unmask */ 221 reg = analogix_dp_read(dp, ANALOGIX_DP_COMMON_INT_MASK_4); 222 reg &= ~COMMON_INT_MASK_4; 223 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg); 224 225 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA_MASK); 226 reg &= ~INT_STA_MASK; 227 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg); 228 } 229 230 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp) 231 { 232 u32 reg; 233 234 /* 0: mask, 1: unmask */ 235 reg = COMMON_INT_MASK_4; 236 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg); 237 238 reg = INT_STA_MASK; 239 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg); 240 } 241 242 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp) 243 { 244 u32 reg; 245 246 reg = analogix_dp_read(dp, ANALOGIX_DP_DEBUG_CTL); 247 if (reg & PLL_LOCK) 248 return PLL_LOCKED; 249 else 250 return PLL_UNLOCKED; 251 } 252 253 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable) 254 { 255 u32 reg; 256 257 if (enable) { 258 reg = analogix_dp_read(dp, ANALOGIX_DP_PLL_CTL); 259 reg |= DP_PLL_PD; 260 analogix_dp_write(dp, ANALOGIX_DP_PLL_CTL, reg); 261 } else { 262 reg = analogix_dp_read(dp, ANALOGIX_DP_PLL_CTL); 263 reg &= ~DP_PLL_PD; 264 analogix_dp_write(dp, ANALOGIX_DP_PLL_CTL, reg); 265 } 266 } 267 268 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 269 enum analog_power_block block, 270 bool enable) 271 { 272 u32 reg; 273 u32 phy_pd_addr = ANALOGIX_DP_PHY_PD; 274 275 if (dp->plat_data.dev_type == ROCKCHIP_DP) 276 phy_pd_addr = ANALOGIX_DP_PD; 277 278 switch (block) { 279 case AUX_BLOCK: 280 if (enable) { 281 reg = analogix_dp_read(dp, phy_pd_addr); 282 reg |= AUX_PD; 283 analogix_dp_write(dp, phy_pd_addr, reg); 284 } else { 285 reg = analogix_dp_read(dp, phy_pd_addr); 286 reg &= ~AUX_PD; 287 analogix_dp_write(dp, phy_pd_addr, reg); 288 } 289 break; 290 case CH0_BLOCK: 291 if (enable) { 292 reg = analogix_dp_read(dp, phy_pd_addr); 293 reg |= CH0_PD; 294 analogix_dp_write(dp, phy_pd_addr, reg); 295 } else { 296 reg = analogix_dp_read(dp, phy_pd_addr); 297 reg &= ~CH0_PD; 298 analogix_dp_write(dp, phy_pd_addr, reg); 299 } 300 break; 301 case CH1_BLOCK: 302 if (enable) { 303 reg = analogix_dp_read(dp, phy_pd_addr); 304 reg |= CH1_PD; 305 analogix_dp_write(dp, phy_pd_addr, reg); 306 } else { 307 reg = analogix_dp_read(dp, phy_pd_addr); 308 reg &= ~CH1_PD; 309 analogix_dp_write(dp, phy_pd_addr, reg); 310 } 311 break; 312 case CH2_BLOCK: 313 if (enable) { 314 reg = analogix_dp_read(dp, phy_pd_addr); 315 reg |= CH2_PD; 316 analogix_dp_write(dp, phy_pd_addr, reg); 317 } else { 318 reg = analogix_dp_read(dp, phy_pd_addr); 319 reg &= ~CH2_PD; 320 analogix_dp_write(dp, phy_pd_addr, reg); 321 } 322 break; 323 case CH3_BLOCK: 324 if (enable) { 325 reg = analogix_dp_read(dp, phy_pd_addr); 326 reg |= CH3_PD; 327 analogix_dp_write(dp, phy_pd_addr, reg); 328 } else { 329 reg = analogix_dp_read(dp, phy_pd_addr); 330 reg &= ~CH3_PD; 331 analogix_dp_write(dp, phy_pd_addr, reg); 332 } 333 break; 334 case ANALOG_TOTAL: 335 if (enable) { 336 reg = analogix_dp_read(dp, phy_pd_addr); 337 reg |= DP_PHY_PD; 338 analogix_dp_write(dp, phy_pd_addr, reg); 339 } else { 340 reg = analogix_dp_read(dp, phy_pd_addr); 341 reg &= ~DP_PHY_PD; 342 analogix_dp_write(dp, phy_pd_addr, reg); 343 } 344 break; 345 case POWER_ALL: 346 if (enable) { 347 reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD | 348 CH1_PD | CH0_PD; 349 analogix_dp_write(dp, phy_pd_addr, reg); 350 } else { 351 analogix_dp_write(dp, phy_pd_addr, 0x00); 352 } 353 break; 354 default: 355 break; 356 } 357 } 358 359 void analogix_dp_init_analog_func(struct analogix_dp_device *dp) 360 { 361 u32 reg; 362 363 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 364 365 reg = PLL_LOCK_CHG; 366 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, reg); 367 368 reg = analogix_dp_read(dp, ANALOGIX_DP_DEBUG_CTL); 369 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); 370 analogix_dp_write(dp, ANALOGIX_DP_DEBUG_CTL, reg); 371 372 /* Power up PLL */ 373 analogix_dp_set_pll_power_down(dp, 0); 374 375 /* Enable Serdes FIFO function and Link symbol clock domain module */ 376 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2); 377 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N 378 | AUX_FUNC_EN_N); 379 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 380 } 381 382 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp) 383 { 384 u32 reg; 385 386 if (dm_gpio_is_valid(&dp->hpd_gpio)) 387 return; 388 389 reg = HOTPLUG_CHG | HPD_LOST | PLUG; 390 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_4, reg); 391 392 reg = INT_HPD; 393 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg); 394 } 395 396 void analogix_dp_init_hpd(struct analogix_dp_device *dp) 397 { 398 u32 reg; 399 400 if (dm_gpio_is_valid(&dp->hpd_gpio)) 401 return; 402 403 analogix_dp_clear_hotplug_interrupts(dp); 404 405 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 406 reg &= ~(F_HPD | HPD_CTRL); 407 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 408 } 409 410 void analogix_dp_force_hpd(struct analogix_dp_device *dp) 411 { 412 u32 reg; 413 414 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 415 reg |= (F_HPD | HPD_CTRL); 416 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 417 } 418 419 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp) 420 { 421 u32 reg; 422 423 if (dm_gpio_is_valid(&dp->hpd_gpio)) { 424 reg = dm_gpio_get_value(&dp->hpd_gpio); 425 if (reg) 426 return DP_IRQ_TYPE_HP_CABLE_IN; 427 else 428 return DP_IRQ_TYPE_HP_CABLE_OUT; 429 } else { 430 /* Parse hotplug interrupt status register */ 431 reg = analogix_dp_read(dp, ANALOGIX_DP_COMMON_INT_STA_4); 432 433 if (reg & PLUG) 434 return DP_IRQ_TYPE_HP_CABLE_IN; 435 436 if (reg & HPD_LOST) 437 return DP_IRQ_TYPE_HP_CABLE_OUT; 438 439 if (reg & HOTPLUG_CHG) 440 return DP_IRQ_TYPE_HP_CHANGE; 441 442 return DP_IRQ_TYPE_UNKNOWN; 443 } 444 } 445 446 void analogix_dp_reset_aux(struct analogix_dp_device *dp) 447 { 448 u32 reg; 449 450 /* Disable AUX channel module */ 451 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2); 452 reg |= AUX_FUNC_EN_N; 453 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 454 } 455 456 void analogix_dp_init_aux(struct analogix_dp_device *dp) 457 { 458 u32 reg; 459 460 /* Clear inerrupts related to AUX channel */ 461 reg = RPLY_RECEIV | AUX_ERR; 462 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg); 463 464 analogix_dp_reset_aux(dp); 465 466 /* Disable AUX transaction H/W retry */ 467 if (dp->plat_data.dev_type == ROCKCHIP_DP) 468 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) | 469 AUX_HW_RETRY_COUNT_SEL(3) | 470 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; 471 else 472 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | 473 AUX_HW_RETRY_COUNT_SEL(0) | 474 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; 475 analogix_dp_write(dp, ANALOGIX_DP_AUX_HW_RETRY_CTL, reg); 476 477 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ 478 reg = DEFER_CTRL_EN | DEFER_COUNT(1); 479 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_DEFER_CTL, reg); 480 481 /* Enable AUX channel module */ 482 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2); 483 reg &= ~AUX_FUNC_EN_N; 484 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 485 } 486 487 int analogix_dp_detect(struct analogix_dp_device *dp) 488 { 489 u32 reg; 490 491 if (dm_gpio_is_valid(&dp->hpd_gpio)) 492 return dm_gpio_get_value(&dp->hpd_gpio); 493 494 if (dp->force_hpd) 495 analogix_dp_force_hpd(dp); 496 497 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 498 if (reg & HPD_STATUS) 499 return 1; 500 501 return 0; 502 } 503 504 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp) 505 { 506 u32 reg; 507 508 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_1); 509 reg &= ~SW_FUNC_EN_N; 510 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg); 511 } 512 513 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp) 514 { 515 u32 reg; 516 517 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 518 if (reg & HPD_STATUS) 519 return 0; 520 521 return -EINVAL; 522 } 523 524 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp) 525 { 526 int reg; 527 int retval = 0; 528 int timeout_loop = 0; 529 530 /* Enable AUX CH operation */ 531 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_CTL_2); 532 reg |= AUX_EN; 533 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_2, reg); 534 535 /* Is AUX CH command reply received? */ 536 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA); 537 while (!(reg & RPLY_RECEIV)) { 538 timeout_loop++; 539 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { 540 dev_err(dp->dev, "AUX CH command reply failed!\n"); 541 return -ETIMEDOUT; 542 } 543 544 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA); 545 udelay(11); 546 } 547 548 /* Clear interrupt source for AUX CH command reply */ 549 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg); 550 551 /* Clear interrupt source for AUX CH access error */ 552 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA); 553 if (reg & AUX_ERR) { 554 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, AUX_ERR); 555 return -EREMOTEIO; 556 } 557 558 /* Check AUX CH error access status */ 559 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_STA); 560 if ((reg & AUX_STATUS_MASK) != 0) { 561 dev_err(dp->dev, 562 "AUX CH error happens: %d\n", reg & AUX_STATUS_MASK); 563 return -EREMOTEIO; 564 } 565 566 return retval; 567 } 568 569 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp, 570 unsigned int reg_addr, 571 unsigned char data) 572 { 573 u32 reg; 574 int i; 575 int retval; 576 577 for (i = 0; i < 3; i++) { 578 /* Clear AUX CH data buffer */ 579 reg = BUF_CLR; 580 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 581 582 /* Select DPCD device address */ 583 reg = AUX_ADDR_7_0(reg_addr); 584 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 585 reg = AUX_ADDR_15_8(reg_addr); 586 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); 587 reg = AUX_ADDR_19_16(reg_addr); 588 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); 589 590 /* Write data buffer */ 591 reg = (unsigned int)data; 592 analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0, reg); 593 594 /* 595 * Set DisplayPort transaction and write 1 byte 596 * If bit 3 is 1, DisplayPort transaction. 597 * If Bit 3 is 0, I2C transaction. 598 */ 599 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; 600 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 601 602 /* Start AUX transaction */ 603 retval = analogix_dp_start_aux_transaction(dp); 604 if (retval == 0) 605 break; 606 } 607 608 return retval; 609 } 610 611 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp, 612 unsigned int reg_addr, 613 unsigned char *data) 614 { 615 u32 reg; 616 int i; 617 int retval; 618 619 for (i = 0; i < 3; i++) { 620 /* Clear AUX CH data buffer */ 621 reg = BUF_CLR; 622 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 623 624 /* Select DPCD device address */ 625 reg = AUX_ADDR_7_0(reg_addr); 626 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 627 reg = AUX_ADDR_15_8(reg_addr); 628 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); 629 reg = AUX_ADDR_19_16(reg_addr); 630 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); 631 632 /* 633 * Set DisplayPort transaction and read 1 byte 634 * If bit 3 is 1, DisplayPort transaction. 635 * If Bit 3 is 0, I2C transaction. 636 */ 637 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; 638 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 639 640 /* Start AUX transaction */ 641 retval = analogix_dp_start_aux_transaction(dp); 642 if (retval == 0) 643 break; 644 } 645 646 /* Read data buffer */ 647 reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0); 648 *data = (unsigned char)(reg & 0xff); 649 650 return retval; 651 } 652 653 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp, 654 unsigned int reg_addr, 655 unsigned int count, 656 unsigned char data[]) 657 { 658 u32 reg; 659 unsigned int start_offset; 660 unsigned int cur_data_count; 661 unsigned int cur_data_idx; 662 int i; 663 int retval = 0; 664 665 /* Clear AUX CH data buffer */ 666 reg = BUF_CLR; 667 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 668 669 start_offset = 0; 670 while (start_offset < count) { 671 /* Buffer size of AUX CH is 16 * 4bytes */ 672 if ((count - start_offset) > 16) 673 cur_data_count = 16; 674 else 675 cur_data_count = count - start_offset; 676 677 for (i = 0; i < 3; i++) { 678 /* Select DPCD device address */ 679 reg = AUX_ADDR_7_0(reg_addr + start_offset); 680 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 681 reg = AUX_ADDR_15_8(reg_addr + start_offset); 682 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); 683 reg = AUX_ADDR_19_16(reg_addr + start_offset); 684 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); 685 686 for (cur_data_idx = 0; cur_data_idx < cur_data_count; 687 cur_data_idx++) { 688 reg = data[start_offset + cur_data_idx]; 689 analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0 + 690 4 * cur_data_idx, reg); 691 } 692 693 /* 694 * Set DisplayPort transaction and write 695 * If bit 3 is 1, DisplayPort transaction. 696 * If Bit 3 is 0, I2C transaction. 697 */ 698 reg = AUX_LENGTH(cur_data_count) | 699 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; 700 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 701 702 /* Start AUX transaction */ 703 retval = analogix_dp_start_aux_transaction(dp); 704 if (retval == 0) 705 break; 706 } 707 708 start_offset += cur_data_count; 709 } 710 711 return retval; 712 } 713 714 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp, 715 unsigned int reg_addr, 716 unsigned int count, 717 unsigned char data[]) 718 { 719 u32 reg; 720 unsigned int start_offset; 721 unsigned int cur_data_count; 722 unsigned int cur_data_idx; 723 int i; 724 int retval = 0; 725 726 /* Clear AUX CH data buffer */ 727 reg = BUF_CLR; 728 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 729 730 start_offset = 0; 731 while (start_offset < count) { 732 /* Buffer size of AUX CH is 16 * 4bytes */ 733 if ((count - start_offset) > 16) 734 cur_data_count = 16; 735 else 736 cur_data_count = count - start_offset; 737 738 /* AUX CH Request Transaction process */ 739 for (i = 0; i < 3; i++) { 740 /* Select DPCD device address */ 741 reg = AUX_ADDR_7_0(reg_addr + start_offset); 742 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 743 reg = AUX_ADDR_15_8(reg_addr + start_offset); 744 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); 745 reg = AUX_ADDR_19_16(reg_addr + start_offset); 746 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); 747 748 /* 749 * Set DisplayPort transaction and read 750 * If bit 3 is 1, DisplayPort transaction. 751 * If Bit 3 is 0, I2C transaction. 752 */ 753 reg = AUX_LENGTH(cur_data_count) | 754 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; 755 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 756 757 /* Start AUX transaction */ 758 retval = analogix_dp_start_aux_transaction(dp); 759 if (retval == 0) 760 break; 761 } 762 763 for (cur_data_idx = 0; cur_data_idx < cur_data_count; 764 cur_data_idx++) { 765 reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0 766 + 4 * cur_data_idx); 767 data[start_offset + cur_data_idx] = 768 (unsigned char)reg; 769 } 770 771 start_offset += cur_data_count; 772 } 773 774 return retval; 775 } 776 777 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp, 778 unsigned int device_addr, 779 unsigned int reg_addr) 780 { 781 u32 reg; 782 int retval; 783 784 /* Set EDID device address */ 785 reg = device_addr; 786 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 787 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, 0x0); 788 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, 0x0); 789 790 /* Set offset from base address of EDID device */ 791 analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0, reg_addr); 792 793 /* 794 * Set I2C transaction and write address 795 * If bit 3 is 1, DisplayPort transaction. 796 * If Bit 3 is 0, I2C transaction. 797 */ 798 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT | 799 AUX_TX_COMM_WRITE; 800 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 801 802 /* Start AUX transaction */ 803 retval = analogix_dp_start_aux_transaction(dp); 804 if (retval < 0) 805 return retval; 806 807 return 0; 808 } 809 810 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp, 811 unsigned int device_addr, 812 unsigned int reg_addr, 813 unsigned int *data) 814 { 815 u32 reg; 816 int i; 817 int retval; 818 819 for (i = 0; i < 3; i++) { 820 /* Clear AUX CH data buffer */ 821 reg = BUF_CLR; 822 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 823 824 /* Select EDID device */ 825 retval = analogix_dp_select_i2c_device(dp, device_addr, 826 reg_addr); 827 if (retval != 0) 828 continue; 829 830 /* 831 * Set I2C transaction and read data 832 * If bit 3 is 1, DisplayPort transaction. 833 * If Bit 3 is 0, I2C transaction. 834 */ 835 reg = AUX_TX_COMM_I2C_TRANSACTION | 836 AUX_TX_COMM_READ; 837 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 838 839 /* Start AUX transaction */ 840 retval = analogix_dp_start_aux_transaction(dp); 841 if (retval == 0) 842 break; 843 } 844 845 /* Read data */ 846 if (retval == 0) 847 *data = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0); 848 849 return retval; 850 } 851 852 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp, 853 unsigned int device_addr, 854 unsigned int reg_addr, 855 unsigned int count, 856 unsigned char edid[]) 857 { 858 u32 reg; 859 unsigned int i, j; 860 unsigned int cur_data_idx; 861 unsigned int defer = 0; 862 int retval = 0; 863 864 for (i = 0; i < count; i += 16) { 865 for (j = 0; j < 3; j++) { 866 /* Clear AUX CH data buffer */ 867 reg = BUF_CLR; 868 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 869 870 /* Set normal AUX CH command */ 871 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_CTL_2); 872 reg &= ~ADDR_ONLY; 873 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_2, reg); 874 875 /* 876 * If Rx sends defer, Tx sends only reads 877 * request without sending address 878 */ 879 if (!defer) 880 retval = analogix_dp_select_i2c_device(dp, 881 device_addr, reg_addr + i); 882 else 883 defer = 0; 884 885 if (retval == 0) { 886 /* 887 * Set I2C transaction and write data 888 * If bit 3 is 1, DisplayPort transaction. 889 * If Bit 3 is 0, I2C transaction. 890 */ 891 reg = AUX_LENGTH(16) | 892 AUX_TX_COMM_I2C_TRANSACTION | 893 AUX_TX_COMM_READ; 894 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, 895 reg); 896 897 /* Start AUX transaction */ 898 retval = analogix_dp_start_aux_transaction(dp); 899 if (retval == 0) 900 break; 901 } 902 /* Check if Rx sends defer */ 903 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_RX_COMM); 904 if (reg == AUX_RX_COMM_AUX_DEFER || 905 reg == AUX_RX_COMM_I2C_DEFER) { 906 dev_dbg(dp->dev, "Defer: %d\n\n", reg); 907 defer = 1; 908 } 909 } 910 911 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) { 912 reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0 913 + 4 * cur_data_idx); 914 edid[i + cur_data_idx] = (unsigned char)reg; 915 } 916 } 917 918 return retval; 919 } 920 921 bool analogix_dp_ssc_supported(struct analogix_dp_device *dp) 922 { 923 /* Check if SSC is supported by both sides */ 924 return dp->plat_data.ssc && dp->link_train.ssc; 925 } 926 927 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype) 928 { 929 union phy_configure_opts phy_cfg; 930 u32 status; 931 int ret; 932 933 analogix_dp_write(dp, ANALOGIX_DP_LINK_BW_SET, bwtype); 934 935 phy_cfg.dp.lanes = dp->link_train.lane_count; 936 phy_cfg.dp.link_rate = 937 drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100; 938 phy_cfg.dp.ssc = analogix_dp_ssc_supported(dp); 939 phy_cfg.dp.set_lanes = false; 940 phy_cfg.dp.set_rate = true; 941 phy_cfg.dp.set_voltages = false; 942 ret = generic_phy_configure(&dp->phy, &phy_cfg); 943 if (ret) { 944 dev_err(dp->dev, "%s: phy_configure() failed: %d\n", 945 __func__, ret); 946 return; 947 } 948 949 ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status, 950 status != PLL_UNLOCKED, 951 120 * DP_TIMEOUT_LOOP_COUNT); 952 if (ret) { 953 dev_err(dp->dev, "Wait for pll lock failed %d\n", ret); 954 return; 955 } 956 } 957 958 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype) 959 { 960 u32 reg; 961 962 reg = analogix_dp_read(dp, ANALOGIX_DP_LINK_BW_SET); 963 *bwtype = reg; 964 } 965 966 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count) 967 { 968 union phy_configure_opts phy_cfg; 969 u32 reg; 970 int ret; 971 972 reg = count; 973 analogix_dp_write(dp, ANALOGIX_DP_LANE_COUNT_SET, reg); 974 975 phy_cfg.dp.lanes = dp->link_train.lane_count; 976 phy_cfg.dp.set_lanes = true; 977 phy_cfg.dp.set_rate = false; 978 phy_cfg.dp.set_voltages = false; 979 ret = generic_phy_configure(&dp->phy, &phy_cfg); 980 if (ret) { 981 dev_err(dp->dev, "%s: phy_configure() failed: %d\n", 982 __func__, ret); 983 return; 984 } 985 } 986 987 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count) 988 { 989 u32 reg; 990 991 reg = analogix_dp_read(dp, ANALOGIX_DP_LANE_COUNT_SET); 992 *count = reg; 993 } 994 995 void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp) 996 { 997 union phy_configure_opts phy_cfg; 998 u8 lane; 999 int ret; 1000 1001 for (lane = 0; lane < dp->link_train.lane_count; lane++) { 1002 u8 training_lane = dp->link_train.training_lane[lane]; 1003 u8 vs, pe; 1004 1005 analogix_dp_write(dp, 1006 ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane, 1007 dp->link_train.training_lane[lane]); 1008 1009 vs = (training_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >> 1010 DP_TRAIN_VOLTAGE_SWING_SHIFT; 1011 pe = (training_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >> 1012 DP_TRAIN_PRE_EMPHASIS_SHIFT; 1013 phy_cfg.dp.voltage[lane] = vs; 1014 phy_cfg.dp.pre[lane] = pe; 1015 } 1016 1017 phy_cfg.dp.lanes = dp->link_train.lane_count; 1018 phy_cfg.dp.link_rate = 1019 drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100; 1020 phy_cfg.dp.set_lanes = false; 1021 phy_cfg.dp.set_rate = false; 1022 phy_cfg.dp.set_voltages = true; 1023 ret = generic_phy_configure(&dp->phy, &phy_cfg); 1024 if (ret) { 1025 dev_err(dp->dev, "%s: phy_configure() failed: %d\n", 1026 __func__, ret); 1027 return; 1028 } 1029 } 1030 1031 u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane) 1032 { 1033 return analogix_dp_read(dp, 1034 ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane); 1035 } 1036 1037 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, 1038 bool enable) 1039 { 1040 u32 reg; 1041 1042 if (enable) { 1043 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 1044 reg |= ENHANCED; 1045 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 1046 } else { 1047 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 1048 reg &= ~ENHANCED; 1049 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 1050 } 1051 } 1052 1053 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, 1054 enum pattern_set pattern) 1055 { 1056 u32 reg; 1057 1058 switch (pattern) { 1059 case PRBS7: 1060 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7; 1061 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1062 break; 1063 case D10_2: 1064 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2; 1065 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1066 break; 1067 case TRAINING_PTN1: 1068 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1; 1069 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1070 break; 1071 case TRAINING_PTN2: 1072 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2; 1073 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1074 break; 1075 case TRAINING_PTN3: 1076 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN3; 1077 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1078 break; 1079 case DP_NONE: 1080 reg = SCRAMBLING_ENABLE | 1081 LINK_QUAL_PATTERN_SET_DISABLE | 1082 SW_TRAINING_PATTERN_SET_NORMAL; 1083 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1084 break; 1085 default: 1086 break; 1087 } 1088 } 1089 1090 void analogix_dp_reset_macro(struct analogix_dp_device *dp) 1091 { 1092 u32 reg; 1093 1094 reg = analogix_dp_read(dp, ANALOGIX_DP_PHY_TEST); 1095 reg |= MACRO_RST; 1096 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, reg); 1097 1098 /* 10 us is the minimum reset time. */ 1099 udelay(20); 1100 1101 reg &= ~MACRO_RST; 1102 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, reg); 1103 } 1104 1105 void analogix_dp_init_video(struct analogix_dp_device *dp) 1106 { 1107 u32 reg; 1108 1109 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; 1110 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, reg); 1111 1112 reg = 0x0; 1113 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, reg); 1114 1115 reg = CHA_CRI(4) | CHA_CTRL; 1116 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, reg); 1117 1118 reg = 0x0; 1119 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 1120 1121 reg = VID_HRES_TH(2) | VID_VRES_TH(0); 1122 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_8, reg); 1123 } 1124 1125 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp) 1126 { 1127 u32 reg; 1128 1129 /* Configure the input color depth, color space, dynamic range */ 1130 reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) | 1131 (dp->video_info.color_depth << IN_BPC_SHIFT) | 1132 (dp->video_info.color_space << IN_COLOR_F_SHIFT); 1133 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_2, reg); 1134 1135 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */ 1136 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_3); 1137 reg &= ~IN_YC_COEFFI_MASK; 1138 if (dp->video_info.ycbcr_coeff) 1139 reg |= IN_YC_COEFFI_ITU709; 1140 else 1141 reg |= IN_YC_COEFFI_ITU601; 1142 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_3, reg); 1143 } 1144 1145 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp) 1146 { 1147 u32 reg; 1148 1149 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_1); 1150 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, reg); 1151 1152 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_1); 1153 1154 if (!(reg & DET_STA)) 1155 return -EINVAL; 1156 1157 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_2); 1158 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, reg); 1159 1160 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_2); 1161 1162 if (reg & CHA_STA) 1163 return -EINVAL; 1164 1165 return 0; 1166 } 1167 1168 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, 1169 enum clock_recovery_m_value_type type, 1170 u32 m_value, u32 n_value) 1171 { 1172 u32 reg; 1173 1174 if (type == REGISTER_M) { 1175 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 1176 reg |= FIX_M_VID; 1177 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 1178 reg = m_value & 0xff; 1179 analogix_dp_write(dp, ANALOGIX_DP_M_VID_0, reg); 1180 reg = (m_value >> 8) & 0xff; 1181 analogix_dp_write(dp, ANALOGIX_DP_M_VID_1, reg); 1182 reg = (m_value >> 16) & 0xff; 1183 analogix_dp_write(dp, ANALOGIX_DP_M_VID_2, reg); 1184 1185 reg = n_value & 0xff; 1186 analogix_dp_write(dp, ANALOGIX_DP_N_VID_0, reg); 1187 reg = (n_value >> 8) & 0xff; 1188 analogix_dp_write(dp, ANALOGIX_DP_N_VID_1, reg); 1189 reg = (n_value >> 16) & 0xff; 1190 analogix_dp_write(dp, ANALOGIX_DP_N_VID_2, reg); 1191 } else { 1192 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 1193 reg &= ~FIX_M_VID; 1194 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 1195 1196 analogix_dp_write(dp, ANALOGIX_DP_N_VID_0, 0x00); 1197 analogix_dp_write(dp, ANALOGIX_DP_N_VID_1, 0x80); 1198 analogix_dp_write(dp, ANALOGIX_DP_N_VID_2, 0x00); 1199 } 1200 } 1201 1202 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type) 1203 { 1204 u32 reg; 1205 1206 if (type == VIDEO_TIMING_FROM_CAPTURE) { 1207 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1208 reg &= ~FORMAT_SEL; 1209 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1210 } else { 1211 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1212 reg |= FORMAT_SEL; 1213 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1214 } 1215 } 1216 1217 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable) 1218 { 1219 u32 reg; 1220 1221 if (enable) { 1222 reg = analogix_dp_read(dp, ANALOGIX_DP_SOC_GENERAL_CTL); 1223 reg &= ~VIDEO_MODE_MASK; 1224 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE; 1225 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg); 1226 } else { 1227 reg = analogix_dp_read(dp, ANALOGIX_DP_SOC_GENERAL_CTL); 1228 reg &= ~VIDEO_MODE_MASK; 1229 reg |= VIDEO_MODE_SLAVE_MODE; 1230 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg); 1231 } 1232 } 1233 1234 void analogix_dp_start_video(struct analogix_dp_device *dp) 1235 { 1236 u32 reg; 1237 1238 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 1239 reg |= VIDEO_EN; 1240 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 1241 } 1242 1243 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp) 1244 { 1245 u32 reg; 1246 1247 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 1248 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 1249 1250 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 1251 if (!(reg & STRM_VALID)) 1252 return -EINVAL; 1253 1254 return 0; 1255 } 1256 1257 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp) 1258 { 1259 u32 reg; 1260 1261 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_1); 1262 reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N); 1263 reg |= MASTER_VID_FUNC_EN_N; 1264 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg); 1265 1266 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1267 reg &= ~INTERACE_SCAN_CFG; 1268 reg |= (dp->video_info.interlaced << 2); 1269 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1270 1271 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1272 reg &= ~VSYNC_POLARITY_CFG; 1273 reg |= (dp->video_info.v_sync_polarity << 1); 1274 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1275 1276 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1277 reg &= ~HSYNC_POLARITY_CFG; 1278 reg |= (dp->video_info.h_sync_polarity << 0); 1279 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1280 1281 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; 1282 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg); 1283 } 1284 1285 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp) 1286 { 1287 u32 reg; 1288 1289 reg = analogix_dp_read(dp, ANALOGIX_DP_TRAINING_PTN_SET); 1290 reg &= ~SCRAMBLING_DISABLE; 1291 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1292 } 1293 1294 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp) 1295 { 1296 u32 reg; 1297 1298 reg = analogix_dp_read(dp, ANALOGIX_DP_TRAINING_PTN_SET); 1299 reg |= SCRAMBLING_DISABLE; 1300 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1301 } 1302