1 /* 2 * Analogix DP (Display port) core register interface driver. 3 * 4 * Copyright (C) 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 5 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 6 * Author: Jingoo Han <jg1.han@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 */ 13 14 #include <config.h> 15 #include <common.h> 16 #include <errno.h> 17 #include <malloc.h> 18 #include <asm/unaligned.h> 19 #include <linux/list.h> 20 #include <dm/device.h> 21 #include <syscon.h> 22 #include <asm/io.h> 23 #include <asm/gpio.h> 24 #include <linux/iopoll.h> 25 26 #include "rockchip_display.h" 27 #include "rockchip_crtc.h" 28 #include "rockchip_connector.h" 29 #include "analogix_dp.h" 30 31 #define COMMON_INT_MASK_1 0 32 #define COMMON_INT_MASK_2 0 33 #define COMMON_INT_MASK_3 0 34 #define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG) 35 #define INT_STA_MASK INT_HPD 36 37 static void analogix_dp_write(struct analogix_dp_device *dp, u32 reg, u32 val) 38 { 39 readl(dp->reg_base); 40 writel(val, dp->reg_base + reg); 41 writel(val, dp->reg_base + reg); 42 } 43 44 static u32 analogix_dp_read(struct analogix_dp_device *dp, u32 reg) 45 { 46 readl(dp->reg_base + reg); 47 48 return readl(dp->reg_base + reg); 49 } 50 51 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable) 52 { 53 u32 reg; 54 55 if (enable) { 56 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 57 reg |= HDCP_VIDEO_MUTE; 58 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 59 } else { 60 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 61 reg &= ~HDCP_VIDEO_MUTE; 62 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 63 } 64 } 65 66 void analogix_dp_stop_video(struct analogix_dp_device *dp) 67 { 68 u32 reg; 69 70 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 71 reg &= ~VIDEO_EN; 72 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 73 } 74 75 static void analogix_dp_set_lane_map(struct analogix_dp_device *dp) 76 { 77 u32 i, reg = 0; 78 79 for (i = 0; i < dp->video_info.max_lane_count; i++) 80 reg |= dp->lane_map[i] << (2 * i); 81 82 analogix_dp_write(dp, ANALOGIX_DP_LANE_MAP, reg); 83 } 84 85 void analogix_dp_init_analog_param(struct analogix_dp_device *dp) 86 { 87 u32 reg; 88 89 reg = TX_TERMINAL_CTRL_50_OHM; 90 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_1, reg); 91 92 reg = SEL_24M | TX_DVDD_BIT_1_0625V; 93 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_2, reg); 94 95 if (dp->plat_data.dev_type == ROCKCHIP_DP) { 96 reg = REF_CLK_24M; 97 if (dp->plat_data.subdev_type == RK3288_DP || 98 dp->plat_data.subdev_type == RK3368_EDP) 99 reg ^= REF_CLK_MASK; 100 101 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_1, reg); 102 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_2, 0x99); 103 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_3, 0x40); 104 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_4, 0x58); 105 analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_5, 0x22); 106 analogix_dp_write(dp, ANALOGIX_DP_BIAS, 0x44); 107 } 108 109 reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO; 110 analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_3, reg); 111 112 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | 113 TX_CUR1_2X | TX_CUR_16_MA; 114 analogix_dp_write(dp, ANALOGIX_DP_PLL_FILTER_CTL_1, reg); 115 116 reg = CH3_AMP_400_MV | CH2_AMP_400_MV | 117 CH1_AMP_400_MV | CH0_AMP_400_MV; 118 analogix_dp_write(dp, ANALOGIX_DP_TX_AMP_TUNING_CTL, reg); 119 } 120 121 void analogix_dp_init_interrupt(struct analogix_dp_device *dp) 122 { 123 /* Set interrupt pin assertion polarity as high */ 124 analogix_dp_write(dp, ANALOGIX_DP_INT_CTL, INT_POL1 | INT_POL0); 125 126 /* Clear pending regisers */ 127 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, 0xff); 128 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_2, 0x4f); 129 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_3, 0xe0); 130 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_4, 0xe7); 131 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, 0x63); 132 133 /* 0:mask,1: unmask */ 134 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_1, 0x00); 135 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_2, 0x00); 136 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_3, 0x00); 137 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, 0x00); 138 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, 0x00); 139 } 140 141 void analogix_dp_reset(struct analogix_dp_device *dp) 142 { 143 u32 reg; 144 145 analogix_dp_stop_video(dp); 146 analogix_dp_enable_video_mute(dp, 0); 147 148 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | 149 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | 150 HDCP_FUNC_EN_N | SW_FUNC_EN_N; 151 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg); 152 153 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | 154 SERDES_FIFO_FUNC_EN_N | 155 LS_CLK_DOMAIN_FUNC_EN_N; 156 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 157 158 udelay(30); 159 160 analogix_dp_set_lane_map(dp); 161 162 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, 0x0); 163 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, 0x40); 164 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, 0x0); 165 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, 0x0); 166 167 analogix_dp_write(dp, ANALOGIX_DP_PKT_SEND_CTL, 0x0); 168 analogix_dp_write(dp, ANALOGIX_DP_HDCP_CTL, 0x0); 169 170 analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_L, 0x5e); 171 analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_H, 0x1a); 172 173 analogix_dp_write(dp, ANALOGIX_DP_LINK_DEBUG_CTL, 0x10); 174 175 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, 0x0); 176 177 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_FIFO_THRD, 0x0); 178 analogix_dp_write(dp, ANALOGIX_DP_AUDIO_MARGIN, 0x20); 179 180 analogix_dp_write(dp, ANALOGIX_DP_M_VID_GEN_FILTER_TH, 0x4); 181 analogix_dp_write(dp, ANALOGIX_DP_M_AUD_GEN_FILTER_TH, 0x2); 182 183 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, 0x00000101); 184 } 185 186 void analogix_dp_swreset(struct analogix_dp_device *dp) 187 { 188 analogix_dp_write(dp, ANALOGIX_DP_TX_SW_RESET, RESET_DP_TX); 189 } 190 191 void analogix_dp_config_interrupt(struct analogix_dp_device *dp) 192 { 193 u32 reg; 194 195 /* 0: mask, 1: unmask */ 196 reg = COMMON_INT_MASK_1; 197 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_1, reg); 198 199 reg = COMMON_INT_MASK_2; 200 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_2, reg); 201 202 reg = COMMON_INT_MASK_3; 203 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_3, reg); 204 205 reg = COMMON_INT_MASK_4; 206 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg); 207 208 reg = INT_STA_MASK; 209 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg); 210 } 211 212 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp) 213 { 214 u32 reg; 215 216 /* 0: mask, 1: unmask */ 217 reg = analogix_dp_read(dp, ANALOGIX_DP_COMMON_INT_MASK_4); 218 reg &= ~COMMON_INT_MASK_4; 219 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg); 220 221 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA_MASK); 222 reg &= ~INT_STA_MASK; 223 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg); 224 } 225 226 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp) 227 { 228 u32 reg; 229 230 /* 0: mask, 1: unmask */ 231 reg = COMMON_INT_MASK_4; 232 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg); 233 234 reg = INT_STA_MASK; 235 analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, reg); 236 } 237 238 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp) 239 { 240 u32 reg; 241 242 reg = analogix_dp_read(dp, ANALOGIX_DP_DEBUG_CTL); 243 if (reg & PLL_LOCK) 244 return PLL_LOCKED; 245 else 246 return PLL_UNLOCKED; 247 } 248 249 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable) 250 { 251 u32 reg; 252 253 if (enable) { 254 reg = analogix_dp_read(dp, ANALOGIX_DP_PLL_CTL); 255 reg |= DP_PLL_PD; 256 analogix_dp_write(dp, ANALOGIX_DP_PLL_CTL, reg); 257 } else { 258 reg = analogix_dp_read(dp, ANALOGIX_DP_PLL_CTL); 259 reg &= ~DP_PLL_PD; 260 analogix_dp_write(dp, ANALOGIX_DP_PLL_CTL, reg); 261 } 262 } 263 264 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 265 enum analog_power_block block, 266 bool enable) 267 { 268 u32 reg; 269 u32 phy_pd_addr = ANALOGIX_DP_PHY_PD; 270 271 if (dp->plat_data.dev_type == ROCKCHIP_DP) 272 phy_pd_addr = ANALOGIX_DP_PD; 273 274 switch (block) { 275 case AUX_BLOCK: 276 if (enable) { 277 reg = analogix_dp_read(dp, phy_pd_addr); 278 reg |= AUX_PD; 279 analogix_dp_write(dp, phy_pd_addr, reg); 280 } else { 281 reg = analogix_dp_read(dp, phy_pd_addr); 282 reg &= ~AUX_PD; 283 analogix_dp_write(dp, phy_pd_addr, reg); 284 } 285 break; 286 case CH0_BLOCK: 287 if (enable) { 288 reg = analogix_dp_read(dp, phy_pd_addr); 289 reg |= CH0_PD; 290 analogix_dp_write(dp, phy_pd_addr, reg); 291 } else { 292 reg = analogix_dp_read(dp, phy_pd_addr); 293 reg &= ~CH0_PD; 294 analogix_dp_write(dp, phy_pd_addr, reg); 295 } 296 break; 297 case CH1_BLOCK: 298 if (enable) { 299 reg = analogix_dp_read(dp, phy_pd_addr); 300 reg |= CH1_PD; 301 analogix_dp_write(dp, phy_pd_addr, reg); 302 } else { 303 reg = analogix_dp_read(dp, phy_pd_addr); 304 reg &= ~CH1_PD; 305 analogix_dp_write(dp, phy_pd_addr, reg); 306 } 307 break; 308 case CH2_BLOCK: 309 if (enable) { 310 reg = analogix_dp_read(dp, phy_pd_addr); 311 reg |= CH2_PD; 312 analogix_dp_write(dp, phy_pd_addr, reg); 313 } else { 314 reg = analogix_dp_read(dp, phy_pd_addr); 315 reg &= ~CH2_PD; 316 analogix_dp_write(dp, phy_pd_addr, reg); 317 } 318 break; 319 case CH3_BLOCK: 320 if (enable) { 321 reg = analogix_dp_read(dp, phy_pd_addr); 322 reg |= CH3_PD; 323 analogix_dp_write(dp, phy_pd_addr, reg); 324 } else { 325 reg = analogix_dp_read(dp, phy_pd_addr); 326 reg &= ~CH3_PD; 327 analogix_dp_write(dp, phy_pd_addr, reg); 328 } 329 break; 330 case ANALOG_TOTAL: 331 if (enable) { 332 reg = analogix_dp_read(dp, phy_pd_addr); 333 reg |= DP_PHY_PD; 334 analogix_dp_write(dp, phy_pd_addr, reg); 335 } else { 336 reg = analogix_dp_read(dp, phy_pd_addr); 337 reg &= ~DP_PHY_PD; 338 analogix_dp_write(dp, phy_pd_addr, reg); 339 } 340 break; 341 case POWER_ALL: 342 if (enable) { 343 reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD | 344 CH1_PD | CH0_PD; 345 analogix_dp_write(dp, phy_pd_addr, reg); 346 } else { 347 analogix_dp_write(dp, phy_pd_addr, 0x00); 348 } 349 break; 350 default: 351 break; 352 } 353 } 354 355 void analogix_dp_init_analog_func(struct analogix_dp_device *dp) 356 { 357 u32 reg; 358 359 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 360 361 reg = PLL_LOCK_CHG; 362 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, reg); 363 364 reg = analogix_dp_read(dp, ANALOGIX_DP_DEBUG_CTL); 365 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); 366 analogix_dp_write(dp, ANALOGIX_DP_DEBUG_CTL, reg); 367 368 /* Power up PLL */ 369 analogix_dp_set_pll_power_down(dp, 0); 370 371 /* Enable Serdes FIFO function and Link symbol clock domain module */ 372 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2); 373 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N 374 | AUX_FUNC_EN_N); 375 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 376 } 377 378 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp) 379 { 380 u32 reg; 381 382 if (dm_gpio_is_valid(&dp->hpd_gpio)) 383 return; 384 385 reg = HOTPLUG_CHG | HPD_LOST | PLUG; 386 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_4, reg); 387 388 reg = INT_HPD; 389 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg); 390 } 391 392 void analogix_dp_init_hpd(struct analogix_dp_device *dp) 393 { 394 u32 reg; 395 396 if (dm_gpio_is_valid(&dp->hpd_gpio)) 397 return; 398 399 analogix_dp_clear_hotplug_interrupts(dp); 400 401 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 402 reg &= ~(F_HPD | HPD_CTRL); 403 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 404 } 405 406 void analogix_dp_force_hpd(struct analogix_dp_device *dp) 407 { 408 u32 reg; 409 410 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 411 reg |= (F_HPD | HPD_CTRL); 412 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 413 } 414 415 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp) 416 { 417 u32 reg; 418 419 if (dm_gpio_is_valid(&dp->hpd_gpio)) { 420 reg = dm_gpio_get_value(&dp->hpd_gpio); 421 if (reg) 422 return DP_IRQ_TYPE_HP_CABLE_IN; 423 else 424 return DP_IRQ_TYPE_HP_CABLE_OUT; 425 } else { 426 /* Parse hotplug interrupt status register */ 427 reg = analogix_dp_read(dp, ANALOGIX_DP_COMMON_INT_STA_4); 428 429 if (reg & PLUG) 430 return DP_IRQ_TYPE_HP_CABLE_IN; 431 432 if (reg & HPD_LOST) 433 return DP_IRQ_TYPE_HP_CABLE_OUT; 434 435 if (reg & HOTPLUG_CHG) 436 return DP_IRQ_TYPE_HP_CHANGE; 437 438 return DP_IRQ_TYPE_UNKNOWN; 439 } 440 } 441 442 void analogix_dp_reset_aux(struct analogix_dp_device *dp) 443 { 444 u32 reg; 445 446 /* Disable AUX channel module */ 447 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2); 448 reg |= AUX_FUNC_EN_N; 449 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 450 } 451 452 void analogix_dp_init_aux(struct analogix_dp_device *dp) 453 { 454 u32 reg; 455 456 /* Clear inerrupts related to AUX channel */ 457 reg = RPLY_RECEIV | AUX_ERR; 458 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg); 459 460 analogix_dp_reset_aux(dp); 461 462 /* Disable AUX transaction H/W retry */ 463 if (dp->plat_data.dev_type == ROCKCHIP_DP) 464 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) | 465 AUX_HW_RETRY_COUNT_SEL(3) | 466 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; 467 else 468 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | 469 AUX_HW_RETRY_COUNT_SEL(0) | 470 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; 471 analogix_dp_write(dp, ANALOGIX_DP_AUX_HW_RETRY_CTL, reg); 472 473 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ 474 reg = DEFER_CTRL_EN | DEFER_COUNT(1); 475 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_DEFER_CTL, reg); 476 477 /* Enable AUX channel module */ 478 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2); 479 reg &= ~AUX_FUNC_EN_N; 480 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_2, reg); 481 } 482 483 int analogix_dp_detect(struct analogix_dp_device *dp) 484 { 485 u32 reg; 486 487 if (dm_gpio_is_valid(&dp->hpd_gpio)) 488 return dm_gpio_get_value(&dp->hpd_gpio); 489 490 if (dp->force_hpd) 491 analogix_dp_force_hpd(dp); 492 493 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 494 if (reg & HPD_STATUS) 495 return 1; 496 497 return 0; 498 } 499 500 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp) 501 { 502 u32 reg; 503 504 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_1); 505 reg &= ~SW_FUNC_EN_N; 506 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg); 507 } 508 509 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp) 510 { 511 u32 reg; 512 513 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 514 if (reg & HPD_STATUS) 515 return 0; 516 517 return -EINVAL; 518 } 519 520 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp) 521 { 522 int reg; 523 int retval = 0; 524 int timeout_loop = 0; 525 526 /* Enable AUX CH operation */ 527 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_CTL_2); 528 reg |= AUX_EN; 529 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_2, reg); 530 531 /* Is AUX CH command reply received? */ 532 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA); 533 while (!(reg & RPLY_RECEIV)) { 534 timeout_loop++; 535 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { 536 dev_err(dp->dev, "AUX CH command reply failed!\n"); 537 return -ETIMEDOUT; 538 } 539 540 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA); 541 udelay(11); 542 } 543 544 /* Clear interrupt source for AUX CH command reply */ 545 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, reg); 546 547 /* Clear interrupt source for AUX CH access error */ 548 reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA); 549 if (reg & AUX_ERR) { 550 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, AUX_ERR); 551 return -EREMOTEIO; 552 } 553 554 /* Check AUX CH error access status */ 555 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_STA); 556 if ((reg & AUX_STATUS_MASK) != 0) { 557 dev_err(dp->dev, 558 "AUX CH error happens: %d\n", reg & AUX_STATUS_MASK); 559 return -EREMOTEIO; 560 } 561 562 return retval; 563 } 564 565 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp, 566 unsigned int device_addr, 567 unsigned int reg_addr) 568 { 569 u32 reg; 570 int retval; 571 572 /* Set EDID device address */ 573 reg = device_addr; 574 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 575 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, 0x0); 576 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, 0x0); 577 578 /* Set offset from base address of EDID device */ 579 analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0, reg_addr); 580 581 /* 582 * Set I2C transaction and write address 583 * If bit 3 is 1, DisplayPort transaction. 584 * If Bit 3 is 0, I2C transaction. 585 */ 586 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT | 587 AUX_TX_COMM_WRITE; 588 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 589 590 /* Start AUX transaction */ 591 retval = analogix_dp_start_aux_transaction(dp); 592 if (retval < 0) 593 return retval; 594 595 return 0; 596 } 597 598 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp, 599 unsigned int device_addr, 600 unsigned int reg_addr, 601 unsigned int *data) 602 { 603 u32 reg; 604 int i; 605 int retval; 606 607 for (i = 0; i < 3; i++) { 608 /* Clear AUX CH data buffer */ 609 reg = BUF_CLR; 610 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 611 612 /* Select EDID device */ 613 retval = analogix_dp_select_i2c_device(dp, device_addr, 614 reg_addr); 615 if (retval != 0) 616 continue; 617 618 /* 619 * Set I2C transaction and read data 620 * If bit 3 is 1, DisplayPort transaction. 621 * If Bit 3 is 0, I2C transaction. 622 */ 623 reg = AUX_TX_COMM_I2C_TRANSACTION | 624 AUX_TX_COMM_READ; 625 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 626 627 /* Start AUX transaction */ 628 retval = analogix_dp_start_aux_transaction(dp); 629 if (retval == 0) 630 break; 631 } 632 633 /* Read data */ 634 if (retval == 0) 635 *data = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0); 636 637 return retval; 638 } 639 640 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp, 641 unsigned int device_addr, 642 unsigned int reg_addr, 643 unsigned int count, 644 unsigned char edid[]) 645 { 646 u32 reg; 647 unsigned int i, j; 648 unsigned int cur_data_idx; 649 unsigned int defer = 0; 650 int retval = 0; 651 652 for (i = 0; i < count; i += 16) { 653 for (j = 0; j < 3; j++) { 654 /* Clear AUX CH data buffer */ 655 reg = BUF_CLR; 656 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 657 658 /* Set normal AUX CH command */ 659 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_CTL_2); 660 reg &= ~ADDR_ONLY; 661 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_2, reg); 662 663 /* 664 * If Rx sends defer, Tx sends only reads 665 * request without sending address 666 */ 667 if (!defer) 668 retval = analogix_dp_select_i2c_device(dp, 669 device_addr, reg_addr + i); 670 else 671 defer = 0; 672 673 if (retval == 0) { 674 /* 675 * Set I2C transaction and write data 676 * If bit 3 is 1, DisplayPort transaction. 677 * If Bit 3 is 0, I2C transaction. 678 */ 679 reg = AUX_LENGTH(16) | 680 AUX_TX_COMM_I2C_TRANSACTION | 681 AUX_TX_COMM_READ; 682 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, 683 reg); 684 685 /* Start AUX transaction */ 686 retval = analogix_dp_start_aux_transaction(dp); 687 if (retval == 0) 688 break; 689 } 690 /* Check if Rx sends defer */ 691 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_RX_COMM); 692 if (reg == AUX_RX_COMM_AUX_DEFER || 693 reg == AUX_RX_COMM_I2C_DEFER) { 694 dev_dbg(dp->dev, "Defer: %d\n\n", reg); 695 defer = 1; 696 } 697 } 698 699 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) { 700 reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0 701 + 4 * cur_data_idx); 702 edid[i + cur_data_idx] = (unsigned char)reg; 703 } 704 } 705 706 return retval; 707 } 708 709 bool analogix_dp_ssc_supported(struct analogix_dp_device *dp) 710 { 711 /* Check if SSC is supported by both sides */ 712 return dp->plat_data.ssc && dp->link_train.ssc; 713 } 714 715 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype) 716 { 717 union phy_configure_opts phy_cfg; 718 u32 status; 719 int ret; 720 721 analogix_dp_write(dp, ANALOGIX_DP_LINK_BW_SET, bwtype); 722 723 phy_cfg.dp.lanes = dp->link_train.lane_count; 724 phy_cfg.dp.link_rate = 725 drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100; 726 phy_cfg.dp.ssc = analogix_dp_ssc_supported(dp); 727 phy_cfg.dp.set_lanes = false; 728 phy_cfg.dp.set_rate = true; 729 phy_cfg.dp.set_voltages = false; 730 ret = generic_phy_configure(&dp->phy, &phy_cfg); 731 if (ret) { 732 dev_err(dp->dev, "%s: phy_configure() failed: %d\n", 733 __func__, ret); 734 return; 735 } 736 737 ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status, 738 status != PLL_UNLOCKED, 739 120 * DP_TIMEOUT_LOOP_COUNT); 740 if (ret) { 741 dev_err(dp->dev, "Wait for pll lock failed %d\n", ret); 742 return; 743 } 744 } 745 746 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype) 747 { 748 u32 reg; 749 750 reg = analogix_dp_read(dp, ANALOGIX_DP_LINK_BW_SET); 751 *bwtype = reg; 752 } 753 754 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count) 755 { 756 union phy_configure_opts phy_cfg; 757 u32 reg; 758 int ret; 759 760 reg = count; 761 analogix_dp_write(dp, ANALOGIX_DP_LANE_COUNT_SET, reg); 762 763 phy_cfg.dp.lanes = dp->link_train.lane_count; 764 phy_cfg.dp.set_lanes = true; 765 phy_cfg.dp.set_rate = false; 766 phy_cfg.dp.set_voltages = false; 767 ret = generic_phy_configure(&dp->phy, &phy_cfg); 768 if (ret) { 769 dev_err(dp->dev, "%s: phy_configure() failed: %d\n", 770 __func__, ret); 771 return; 772 } 773 } 774 775 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count) 776 { 777 u32 reg; 778 779 reg = analogix_dp_read(dp, ANALOGIX_DP_LANE_COUNT_SET); 780 *count = reg; 781 } 782 783 void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp) 784 { 785 union phy_configure_opts phy_cfg; 786 u8 lane; 787 int ret; 788 789 for (lane = 0; lane < dp->link_train.lane_count; lane++) { 790 u8 training_lane = dp->link_train.training_lane[lane]; 791 u8 vs, pe; 792 793 analogix_dp_write(dp, 794 ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane, 795 dp->link_train.training_lane[lane]); 796 797 vs = (training_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >> 798 DP_TRAIN_VOLTAGE_SWING_SHIFT; 799 pe = (training_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >> 800 DP_TRAIN_PRE_EMPHASIS_SHIFT; 801 phy_cfg.dp.voltage[lane] = vs; 802 phy_cfg.dp.pre[lane] = pe; 803 } 804 805 phy_cfg.dp.lanes = dp->link_train.lane_count; 806 phy_cfg.dp.link_rate = 807 drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100; 808 phy_cfg.dp.set_lanes = false; 809 phy_cfg.dp.set_rate = false; 810 phy_cfg.dp.set_voltages = true; 811 ret = generic_phy_configure(&dp->phy, &phy_cfg); 812 if (ret) { 813 dev_err(dp->dev, "%s: phy_configure() failed: %d\n", 814 __func__, ret); 815 return; 816 } 817 } 818 819 u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane) 820 { 821 return analogix_dp_read(dp, 822 ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane); 823 } 824 825 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, 826 bool enable) 827 { 828 u32 reg; 829 830 if (enable) { 831 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 832 reg |= ENHANCED; 833 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 834 } else { 835 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 836 reg &= ~ENHANCED; 837 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 838 } 839 } 840 841 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, 842 enum pattern_set pattern) 843 { 844 u32 reg; 845 846 switch (pattern) { 847 case PRBS7: 848 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7; 849 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 850 break; 851 case D10_2: 852 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2; 853 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 854 break; 855 case TRAINING_PTN1: 856 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1; 857 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 858 break; 859 case TRAINING_PTN2: 860 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2; 861 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 862 break; 863 case TRAINING_PTN3: 864 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN3; 865 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 866 break; 867 case DP_NONE: 868 reg = SCRAMBLING_ENABLE | 869 LINK_QUAL_PATTERN_SET_DISABLE | 870 SW_TRAINING_PATTERN_SET_NORMAL; 871 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 872 break; 873 default: 874 break; 875 } 876 } 877 878 void analogix_dp_reset_macro(struct analogix_dp_device *dp) 879 { 880 u32 reg; 881 882 reg = analogix_dp_read(dp, ANALOGIX_DP_PHY_TEST); 883 reg |= MACRO_RST; 884 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, reg); 885 886 /* 10 us is the minimum reset time. */ 887 udelay(20); 888 889 reg &= ~MACRO_RST; 890 analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, reg); 891 } 892 893 void analogix_dp_init_video(struct analogix_dp_device *dp) 894 { 895 u32 reg; 896 897 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; 898 analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, reg); 899 900 reg = 0x0; 901 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, reg); 902 903 reg = CHA_CRI(4) | CHA_CTRL; 904 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, reg); 905 906 if (dp->video_info.force_stream_valid) { 907 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 908 reg |= VALID_CTRL | F_VALID; 909 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 910 } 911 912 reg = VID_HRES_TH(2) | VID_VRES_TH(0); 913 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_8, reg); 914 } 915 916 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp) 917 { 918 u32 reg; 919 920 /* Configure the input color depth, color space, dynamic range */ 921 reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) | 922 (dp->video_info.color_depth << IN_BPC_SHIFT) | 923 (dp->video_info.color_space << IN_COLOR_F_SHIFT); 924 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_2, reg); 925 926 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */ 927 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_3); 928 reg &= ~IN_YC_COEFFI_MASK; 929 if (dp->video_info.ycbcr_coeff) 930 reg |= IN_YC_COEFFI_ITU709; 931 else 932 reg |= IN_YC_COEFFI_ITU601; 933 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_3, reg); 934 } 935 936 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp) 937 { 938 u32 reg; 939 940 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_1); 941 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, reg); 942 943 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_1); 944 945 if (!(reg & DET_STA)) 946 return -EINVAL; 947 948 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_2); 949 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, reg); 950 951 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_2); 952 953 if (reg & CHA_STA) 954 return -EINVAL; 955 956 return 0; 957 } 958 959 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, 960 enum clock_recovery_m_value_type type, 961 u32 m_value, u32 n_value) 962 { 963 u32 reg; 964 965 if (type == REGISTER_M) { 966 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 967 reg |= FIX_M_VID; 968 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 969 reg = m_value & 0xff; 970 analogix_dp_write(dp, ANALOGIX_DP_M_VID_0, reg); 971 reg = (m_value >> 8) & 0xff; 972 analogix_dp_write(dp, ANALOGIX_DP_M_VID_1, reg); 973 reg = (m_value >> 16) & 0xff; 974 analogix_dp_write(dp, ANALOGIX_DP_M_VID_2, reg); 975 976 reg = n_value & 0xff; 977 analogix_dp_write(dp, ANALOGIX_DP_N_VID_0, reg); 978 reg = (n_value >> 8) & 0xff; 979 analogix_dp_write(dp, ANALOGIX_DP_N_VID_1, reg); 980 reg = (n_value >> 16) & 0xff; 981 analogix_dp_write(dp, ANALOGIX_DP_N_VID_2, reg); 982 } else { 983 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4); 984 reg &= ~FIX_M_VID; 985 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, reg); 986 987 analogix_dp_write(dp, ANALOGIX_DP_N_VID_0, 0x00); 988 analogix_dp_write(dp, ANALOGIX_DP_N_VID_1, 0x80); 989 analogix_dp_write(dp, ANALOGIX_DP_N_VID_2, 0x00); 990 } 991 } 992 993 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type) 994 { 995 u32 reg; 996 997 if (type == VIDEO_TIMING_FROM_CAPTURE) { 998 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 999 reg &= ~FORMAT_SEL; 1000 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1001 } else { 1002 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1003 reg |= FORMAT_SEL; 1004 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1005 } 1006 } 1007 1008 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable) 1009 { 1010 u32 reg; 1011 1012 if (enable) { 1013 reg = analogix_dp_read(dp, ANALOGIX_DP_SOC_GENERAL_CTL); 1014 reg &= ~VIDEO_MODE_MASK; 1015 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE; 1016 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg); 1017 } else { 1018 reg = analogix_dp_read(dp, ANALOGIX_DP_SOC_GENERAL_CTL); 1019 reg &= ~VIDEO_MODE_MASK; 1020 reg |= VIDEO_MODE_SLAVE_MODE; 1021 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg); 1022 } 1023 } 1024 1025 void analogix_dp_start_video(struct analogix_dp_device *dp) 1026 { 1027 u32 reg; 1028 1029 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); 1030 reg |= VIDEO_EN; 1031 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); 1032 } 1033 1034 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp) 1035 { 1036 u32 reg; 1037 1038 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 1039 analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg); 1040 1041 reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3); 1042 if (!(reg & STRM_VALID)) 1043 return -EINVAL; 1044 1045 return 0; 1046 } 1047 1048 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp) 1049 { 1050 u32 reg; 1051 1052 reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_1); 1053 reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N); 1054 reg |= MASTER_VID_FUNC_EN_N; 1055 analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg); 1056 1057 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1058 reg &= ~INTERACE_SCAN_CFG; 1059 reg |= (dp->video_info.interlaced << 2); 1060 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1061 1062 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1063 reg &= ~VSYNC_POLARITY_CFG; 1064 reg |= (dp->video_info.v_sync_polarity << 1); 1065 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1066 1067 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1068 reg &= ~HSYNC_POLARITY_CFG; 1069 reg |= (dp->video_info.h_sync_polarity << 0); 1070 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1071 1072 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; 1073 analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, reg); 1074 } 1075 1076 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp) 1077 { 1078 u32 reg; 1079 1080 reg = analogix_dp_read(dp, ANALOGIX_DP_TRAINING_PTN_SET); 1081 reg &= ~SCRAMBLING_DISABLE; 1082 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1083 } 1084 1085 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp) 1086 { 1087 u32 reg; 1088 1089 reg = analogix_dp_read(dp, ANALOGIX_DP_TRAINING_PTN_SET); 1090 reg |= SCRAMBLING_DISABLE; 1091 analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg); 1092 } 1093 1094 void analogix_dp_set_video_format(struct analogix_dp_device *dp, 1095 const struct drm_display_mode *mode) 1096 { 1097 unsigned int hsw, hfp, hbp, vsw, vfp, vbp; 1098 1099 dp->video_info.interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 1100 1101 if (dp->plat_data.subdev_type == RK3588_EDP) { 1102 dp->video_info.v_sync_polarity = true; 1103 dp->video_info.h_sync_polarity = true; 1104 } else { 1105 dp->video_info.v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); 1106 dp->video_info.h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); 1107 } 1108 1109 hsw = mode->hsync_end - mode->hsync_start; 1110 hfp = mode->hsync_start - mode->hdisplay; 1111 hbp = mode->htotal - mode->hsync_end; 1112 vsw = mode->vsync_end - mode->vsync_start; 1113 vfp = mode->vsync_start - mode->vdisplay; 1114 vbp = mode->vtotal - mode->vsync_end; 1115 1116 /* Set Video Format Parameters */ 1117 analogix_dp_write(dp, ANALOGIX_DP_TOTAL_LINE_CFG_L, 1118 TOTAL_LINE_CFG_L(mode->vtotal)); 1119 analogix_dp_write(dp, ANALOGIX_DP_TOTAL_LINE_CFG_H, 1120 TOTAL_LINE_CFG_H(mode->vtotal >> 8)); 1121 analogix_dp_write(dp, ANALOGIX_DP_ACTIVE_LINE_CFG_L, 1122 ACTIVE_LINE_CFG_L(mode->vdisplay)); 1123 analogix_dp_write(dp, ANALOGIX_DP_ACTIVE_LINE_CFG_H, 1124 ACTIVE_LINE_CFG_H(mode->vdisplay >> 8)); 1125 analogix_dp_write(dp, ANALOGIX_DP_V_F_PORCH_CFG, 1126 V_F_PORCH_CFG(vfp)); 1127 analogix_dp_write(dp, ANALOGIX_DP_V_SYNC_WIDTH_CFG, 1128 V_SYNC_WIDTH_CFG(vsw)); 1129 analogix_dp_write(dp, ANALOGIX_DP_V_B_PORCH_CFG, 1130 V_B_PORCH_CFG(vbp)); 1131 analogix_dp_write(dp, ANALOGIX_DP_TOTAL_PIXEL_CFG_L, 1132 TOTAL_PIXEL_CFG_L(mode->htotal)); 1133 analogix_dp_write(dp, ANALOGIX_DP_TOTAL_PIXEL_CFG_H, 1134 TOTAL_PIXEL_CFG_H(mode->htotal >> 8)); 1135 analogix_dp_write(dp, ANALOGIX_DP_ACTIVE_PIXEL_CFG_L, 1136 ACTIVE_PIXEL_CFG_L(mode->hdisplay)); 1137 analogix_dp_write(dp, ANALOGIX_DP_ACTIVE_PIXEL_CFG_H, 1138 ACTIVE_PIXEL_CFG_H(mode->hdisplay >> 8)); 1139 analogix_dp_write(dp, ANALOGIX_DP_H_F_PORCH_CFG_L, 1140 H_F_PORCH_CFG_L(hfp)); 1141 analogix_dp_write(dp, ANALOGIX_DP_H_F_PORCH_CFG_H, 1142 H_F_PORCH_CFG_H(hfp >> 8)); 1143 analogix_dp_write(dp, ANALOGIX_DP_H_SYNC_CFG_L, 1144 H_SYNC_CFG_L(hsw)); 1145 analogix_dp_write(dp, ANALOGIX_DP_H_SYNC_CFG_H, 1146 H_SYNC_CFG_H(hsw >> 8)); 1147 analogix_dp_write(dp, ANALOGIX_DP_H_B_PORCH_CFG_L, 1148 H_B_PORCH_CFG_L(hbp)); 1149 analogix_dp_write(dp, ANALOGIX_DP_H_B_PORCH_CFG_H, 1150 H_B_PORCH_CFG_H(hbp >> 8)); 1151 } 1152 1153 void analogix_dp_video_bist_enable(struct analogix_dp_device *dp) 1154 { 1155 u32 reg; 1156 1157 /* Enable Video BIST */ 1158 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_4, BIST_EN); 1159 1160 /* 1161 * Note that if BIST_EN is set to 1, F_SEL must be cleared to 0 1162 * although video format information comes from registers set by user. 1163 */ 1164 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_10); 1165 reg &= ~FORMAT_SEL; 1166 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_10, reg); 1167 } 1168 1169 enum { 1170 AUX_STATUS_OK, 1171 AUX_STATUS_NACK_ERROR, 1172 AUX_STATUS_TIMEOUT_ERROR, 1173 AUX_STATUS_UNKNOWN_ERROR, 1174 AUX_STATUS_MUCH_DEFER_ERROR, 1175 AUX_STATUS_TX_SHORT_ERROR, 1176 AUX_STATUS_RX_SHORT_ERROR, 1177 AUX_STATUS_NACK_WITHOUT_M_ERROR, 1178 AUX_STATUS_I2C_NACK_ERROR 1179 }; 1180 1181 ssize_t analogix_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 1182 { 1183 struct analogix_dp_device *dp = dev_get_priv(aux->dev); 1184 u32 reg; 1185 u8 *buffer = msg->buffer; 1186 unsigned int i; 1187 int num_transferred = 0; 1188 int ret; 1189 1190 /* Buffer size of AUX CH is 16 bytes */ 1191 if (WARN_ON(msg->size > 16)) 1192 return -E2BIG; 1193 1194 /* Clear AUX CH data buffer */ 1195 reg = BUF_CLR; 1196 analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg); 1197 1198 switch (msg->request & ~DP_AUX_I2C_MOT) { 1199 case DP_AUX_I2C_WRITE: 1200 reg = AUX_TX_COMM_WRITE | AUX_TX_COMM_I2C_TRANSACTION; 1201 if (msg->request & DP_AUX_I2C_MOT) 1202 reg |= AUX_TX_COMM_MOT; 1203 break; 1204 1205 case DP_AUX_I2C_READ: 1206 reg = AUX_TX_COMM_READ | AUX_TX_COMM_I2C_TRANSACTION; 1207 if (msg->request & DP_AUX_I2C_MOT) 1208 reg |= AUX_TX_COMM_MOT; 1209 break; 1210 1211 case DP_AUX_NATIVE_WRITE: 1212 reg = AUX_TX_COMM_WRITE | AUX_TX_COMM_DP_TRANSACTION; 1213 break; 1214 1215 case DP_AUX_NATIVE_READ: 1216 reg = AUX_TX_COMM_READ | AUX_TX_COMM_DP_TRANSACTION; 1217 break; 1218 1219 default: 1220 return -EINVAL; 1221 } 1222 1223 reg |= AUX_LENGTH(msg->size); 1224 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg); 1225 1226 /* Select DPCD device address */ 1227 reg = AUX_ADDR_7_0(msg->address); 1228 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg); 1229 reg = AUX_ADDR_15_8(msg->address); 1230 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg); 1231 reg = AUX_ADDR_19_16(msg->address); 1232 analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg); 1233 1234 if (!(msg->request & DP_AUX_I2C_READ)) { 1235 for (i = 0; i < msg->size; i++) { 1236 reg = buffer[i]; 1237 analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0 + 4 * i, 1238 reg); 1239 num_transferred++; 1240 } 1241 } 1242 1243 /* Enable AUX CH operation */ 1244 reg = AUX_EN; 1245 1246 /* Zero-sized messages specify address-only transactions. */ 1247 if (msg->size < 1) 1248 reg |= ADDR_ONLY; 1249 1250 analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_2, reg); 1251 1252 ret = readx_poll_timeout(readl, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2, 1253 reg, !(reg & AUX_EN), 500 * 1000); 1254 if (ret) { 1255 dev_err(dp->dev, "AUX CH enable timeout!\n"); 1256 goto aux_error; 1257 } 1258 1259 /* TODO: Wait for an interrupt instead of looping? */ 1260 /* Is AUX CH command reply received? */ 1261 ret = readx_poll_timeout(readl, dp->reg_base + ANALOGIX_DP_INT_STA, 1262 reg, reg & RPLY_RECEIV, 20 * 1000); 1263 if (ret) { 1264 dev_err(dp->dev, "AUX CH cmd reply timeout!\n"); 1265 goto aux_error; 1266 } 1267 1268 /* Clear interrupt source for AUX CH command reply */ 1269 analogix_dp_write(dp, ANALOGIX_DP_INT_STA, RPLY_RECEIV); 1270 1271 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_STA); 1272 if ((reg & AUX_STATUS_MASK) == AUX_STATUS_TIMEOUT_ERROR) 1273 return -ETIMEDOUT; 1274 1275 if (msg->request & DP_AUX_I2C_READ) { 1276 size_t buf_data_count; 1277 1278 reg = analogix_dp_read(dp, ANALOGIX_DP_BUFFER_DATA_CTL); 1279 buf_data_count = BUF_DATA_COUNT(reg); 1280 1281 if (buf_data_count != msg->size) 1282 return -EBUSY; 1283 1284 for (i = 0; i < msg->size; i++) { 1285 reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0 + 1286 4 * i); 1287 buffer[i] = (unsigned char)reg; 1288 num_transferred++; 1289 } 1290 } 1291 1292 /* Check if Rx sends defer */ 1293 reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_RX_COMM); 1294 if (reg == AUX_RX_COMM_AUX_DEFER) 1295 msg->reply = DP_AUX_NATIVE_REPLY_DEFER; 1296 else if (reg == AUX_RX_COMM_I2C_DEFER) 1297 msg->reply = DP_AUX_I2C_REPLY_DEFER; 1298 else if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE || 1299 (msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_READ) 1300 msg->reply = DP_AUX_I2C_REPLY_ACK; 1301 else if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE || 1302 (msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_READ) 1303 msg->reply = DP_AUX_NATIVE_REPLY_ACK; 1304 1305 return (num_transferred == msg->size) ? num_transferred : -EBUSY; 1306 1307 aux_error: 1308 /* if aux err happen, reset aux */ 1309 analogix_dp_init_aux(dp); 1310 1311 return -EREMOTEIO; 1312 } 1313 1314 void analogix_dp_enable_assr_mode(struct analogix_dp_device *dp, bool enable) 1315 { 1316 u32 reg; 1317 1318 if (enable) { 1319 reg = analogix_dp_read(dp, ANALOGIX_DP_LINK_POLICY); 1320 reg |= ALTERNATE_SR_ENABLE; 1321 analogix_dp_write(dp, ANALOGIX_DP_LINK_POLICY, reg); 1322 } else { 1323 reg = analogix_dp_read(dp, ANALOGIX_DP_LINK_POLICY); 1324 reg &= ~ALTERNATE_SR_ENABLE; 1325 analogix_dp_write(dp, ANALOGIX_DP_LINK_POLICY, reg); 1326 } 1327 } 1328 1329 bool analogix_dp_get_assr_mode(struct analogix_dp_device *dp) 1330 { 1331 u32 reg; 1332 1333 reg = analogix_dp_read(dp, ANALOGIX_DP_LINK_POLICY); 1334 1335 return !!(reg & ALTERNATE_SR_ENABLE); 1336 } 1337