1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __DRM_ANALOGIX_DP_H__ 8 #define __DRM_ANALOGIX_DP_H__ 9 10 #include <generic-phy.h> 11 #include <power-domain.h> 12 #include <regmap.h> 13 #include <reset.h> 14 15 #include <drm/drm_dp_helper.h> 16 17 #include "rockchip_connector.h" 18 19 #define ANALOGIX_DP_TX_SW_RESET 0x14 20 #define ANALOGIX_DP_FUNC_EN_1 0x18 21 #define ANALOGIX_DP_FUNC_EN_2 0x1C 22 #define ANALOGIX_DP_VIDEO_CTL_1 0x20 23 #define ANALOGIX_DP_VIDEO_CTL_2 0x24 24 #define ANALOGIX_DP_VIDEO_CTL_3 0x28 25 #define ANALOGIX_DP_VIDEO_CTL_4 0x2C 26 #define ANALOGIX_DP_VIDEO_CTL_8 0x3C 27 #define ANALOGIX_DP_VIDEO_CTL_10 0x44 28 29 #define ANALOGIX_DP_TOTAL_LINE_CFG_L 0x48 30 #define ANALOGIX_DP_TOTAL_LINE_CFG_H 0x4C 31 #define ANALOGIX_DP_ACTIVE_LINE_CFG_L 0x50 32 #define ANALOGIX_DP_ACTIVE_LINE_CFG_H 0x54 33 #define ANALOGIX_DP_V_F_PORCH_CFG 0x58 34 #define ANALOGIX_DP_V_SYNC_WIDTH_CFG 0x5C 35 #define ANALOGIX_DP_V_B_PORCH_CFG 0x60 36 #define ANALOGIX_DP_TOTAL_PIXEL_CFG_L 0x64 37 #define ANALOGIX_DP_TOTAL_PIXEL_CFG_H 0x68 38 #define ANALOGIX_DP_ACTIVE_PIXEL_CFG_L 0x6C 39 #define ANALOGIX_DP_ACTIVE_PIXEL_CFG_H 0x70 40 #define ANALOGIX_DP_H_F_PORCH_CFG_L 0x74 41 #define ANALOGIX_DP_H_F_PORCH_CFG_H 0x78 42 #define ANALOGIX_DP_H_SYNC_CFG_L 0x7C 43 #define ANALOGIX_DP_H_SYNC_CFG_H 0x80 44 #define ANALOGIX_DP_H_B_PORCH_CFG_L 0x84 45 #define ANALOGIX_DP_H_B_PORCH_CFG_H 0x88 46 47 #define ANALOGIX_DP_PLL_REG_1 0xfc 48 #define ANALOGIX_DP_PLL_REG_2 0x9e4 49 #define ANALOGIX_DP_PLL_REG_3 0x9e8 50 #define ANALOGIX_DP_PLL_REG_4 0x9ec 51 #define ANALOGIX_DP_PLL_REG_5 0xa00 52 53 #define ANALOGIX_DP_BIAS 0x124 54 #define ANALOGIX_DP_PD 0x12c 55 56 #define ANALOGIX_DP_LANE_MAP 0x35C 57 58 #define ANALOGIX_DP_ANALOG_CTL_1 0x370 59 #define ANALOGIX_DP_ANALOG_CTL_2 0x374 60 #define ANALOGIX_DP_ANALOG_CTL_3 0x378 61 #define ANALOGIX_DP_PLL_FILTER_CTL_1 0x37C 62 #define ANALOGIX_DP_TX_AMP_TUNING_CTL 0x380 63 64 #define ANALOGIX_DP_AUX_HW_RETRY_CTL 0x390 65 66 #define ANALOGIX_DP_COMMON_INT_STA_1 0x3C4 67 #define ANALOGIX_DP_COMMON_INT_STA_2 0x3C8 68 #define ANALOGIX_DP_COMMON_INT_STA_3 0x3CC 69 #define ANALOGIX_DP_COMMON_INT_STA_4 0x3D0 70 #define ANALOGIX_DP_INT_STA 0x3DC 71 #define ANALOGIX_DP_COMMON_INT_MASK_1 0x3E0 72 #define ANALOGIX_DP_COMMON_INT_MASK_2 0x3E4 73 #define ANALOGIX_DP_COMMON_INT_MASK_3 0x3E8 74 #define ANALOGIX_DP_COMMON_INT_MASK_4 0x3EC 75 #define ANALOGIX_DP_INT_STA_MASK 0x3F8 76 #define ANALOGIX_DP_INT_CTL 0x3FC 77 78 #define ANALOGIX_DP_SYS_CTL_1 0x600 79 #define ANALOGIX_DP_SYS_CTL_2 0x604 80 #define ANALOGIX_DP_SYS_CTL_3 0x608 81 #define ANALOGIX_DP_SYS_CTL_4 0x60C 82 83 #define ANALOGIX_DP_PKT_SEND_CTL 0x640 84 #define ANALOGIX_DP_HDCP_CTL 0x648 85 86 #define ANALOGIX_DP_LINK_BW_SET 0x680 87 #define ANALOGIX_DP_LANE_COUNT_SET 0x684 88 #define ANALOGIX_DP_TRAINING_PTN_SET 0x688 89 #define ANALOGIX_DP_LN0_LINK_TRAINING_CTL 0x68C 90 #define ANALOGIX_DP_LN1_LINK_TRAINING_CTL 0x690 91 #define ANALOGIX_DP_LN2_LINK_TRAINING_CTL 0x694 92 #define ANALOGIX_DP_LN3_LINK_TRAINING_CTL 0x698 93 94 #define ANALOGIX_DP_DEBUG_CTL 0x6C0 95 #define ANALOGIX_DP_HPD_DEGLITCH_L 0x6C4 96 #define ANALOGIX_DP_HPD_DEGLITCH_H 0x6C8 97 #define ANALOGIX_DP_LINK_DEBUG_CTL 0x6E0 98 99 #define ANALOGIX_DP_M_VID_0 0x700 100 #define ANALOGIX_DP_M_VID_1 0x704 101 #define ANALOGIX_DP_M_VID_2 0x708 102 #define ANALOGIX_DP_N_VID_0 0x70C 103 #define ANALOGIX_DP_N_VID_1 0x710 104 #define ANALOGIX_DP_N_VID_2 0x714 105 106 #define ANALOGIX_DP_PLL_CTL 0x71C 107 #define ANALOGIX_DP_PHY_PD 0x720 108 #define ANALOGIX_DP_PHY_TEST 0x724 109 110 #define ANALOGIX_DP_VIDEO_FIFO_THRD 0x730 111 #define ANALOGIX_DP_AUDIO_MARGIN 0x73C 112 113 #define ANALOGIX_DP_M_VID_GEN_FILTER_TH 0x764 114 #define ANALOGIX_DP_M_AUD_GEN_FILTER_TH 0x778 115 #define ANALOGIX_DP_AUX_CH_STA 0x780 116 #define ANALOGIX_DP_AUX_CH_DEFER_CTL 0x788 117 #define ANALOGIX_DP_AUX_RX_COMM 0x78C 118 #define ANALOGIX_DP_BUFFER_DATA_CTL 0x790 119 #define ANALOGIX_DP_AUX_CH_CTL_1 0x794 120 #define ANALOGIX_DP_AUX_ADDR_7_0 0x798 121 #define ANALOGIX_DP_AUX_ADDR_15_8 0x79C 122 #define ANALOGIX_DP_AUX_ADDR_19_16 0x7A0 123 #define ANALOGIX_DP_AUX_CH_CTL_2 0x7A4 124 125 #define ANALOGIX_DP_BUF_DATA_0 0x7C0 126 127 #define ANALOGIX_DP_SOC_GENERAL_CTL 0x800 128 129 #define ANALOGIX_DP_LINK_POLICY 0x9D8 130 131 /* ANALOGIX_DP_TX_SW_RESET */ 132 #define RESET_DP_TX (0x1 << 0) 133 134 /* ANALOGIX_DP_FUNC_EN_1 */ 135 #define MASTER_VID_FUNC_EN_N (0x1 << 7) 136 #define SLAVE_VID_FUNC_EN_N (0x1 << 5) 137 #define AUD_FIFO_FUNC_EN_N (0x1 << 4) 138 #define AUD_FUNC_EN_N (0x1 << 3) 139 #define HDCP_FUNC_EN_N (0x1 << 2) 140 #define CRC_FUNC_EN_N (0x1 << 1) 141 #define SW_FUNC_EN_N (0x1 << 0) 142 143 /* ANALOGIX_DP_FUNC_EN_2 */ 144 #define SSC_FUNC_EN_N (0x1 << 7) 145 #define AUX_FUNC_EN_N (0x1 << 2) 146 #define SERDES_FIFO_FUNC_EN_N (0x1 << 1) 147 #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) 148 149 /* ANALOGIX_DP_VIDEO_CTL_1 */ 150 #define VIDEO_EN (0x1 << 7) 151 #define HDCP_VIDEO_MUTE (0x1 << 6) 152 153 /* ANALOGIX_DP_VIDEO_CTL_4 */ 154 #define BIST_EN (0x1 << 3) 155 #define BIST_WIDTH(x) (((x) & 0x1) << 2) 156 #define BIST_TYPE(x) (((x) & 0x3) << 0) 157 158 /* ANALOGIX_DP_VIDEO_CTL_1 */ 159 #define IN_D_RANGE_MASK (0x1 << 7) 160 #define IN_D_RANGE_SHIFT (7) 161 #define IN_D_RANGE_CEA (0x1 << 7) 162 #define IN_D_RANGE_VESA (0x0 << 7) 163 #define IN_BPC_MASK (0x7 << 4) 164 #define IN_BPC_SHIFT (4) 165 #define IN_BPC_12_BITS (0x3 << 4) 166 #define IN_BPC_10_BITS (0x2 << 4) 167 #define IN_BPC_8_BITS (0x1 << 4) 168 #define IN_BPC_6_BITS (0x0 << 4) 169 #define IN_COLOR_F_MASK (0x3 << 0) 170 #define IN_COLOR_F_SHIFT (0) 171 #define IN_COLOR_F_YCBCR444 (0x2 << 0) 172 #define IN_COLOR_F_YCBCR422 (0x1 << 0) 173 #define IN_COLOR_F_RGB (0x0 << 0) 174 175 /* ANALOGIX_DP_VIDEO_CTL_3 */ 176 #define IN_YC_COEFFI_MASK (0x1 << 7) 177 #define IN_YC_COEFFI_SHIFT (7) 178 #define IN_YC_COEFFI_ITU709 (0x1 << 7) 179 #define IN_YC_COEFFI_ITU601 (0x0 << 7) 180 #define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) 181 #define VID_CHK_UPDATE_TYPE_SHIFT (4) 182 #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) 183 #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) 184 185 /* ANALOGIX_DP_VIDEO_CTL_8 */ 186 #define VID_HRES_TH(x) (((x) & 0xf) << 4) 187 #define VID_VRES_TH(x) (((x) & 0xf) << 0) 188 189 /* ANALOGIX_DP_VIDEO_CTL_10 */ 190 #define FORMAT_SEL (0x1 << 4) 191 #define INTERACE_SCAN_CFG (0x1 << 2) 192 #define VSYNC_POLARITY_CFG (0x1 << 1) 193 #define HSYNC_POLARITY_CFG (0x1 << 0) 194 195 /* ANALOGIX_DP_TOTAL_LINE_CFG_L */ 196 #define TOTAL_LINE_CFG_L(x) (((x) & 0xff) << 0) 197 198 /* ANALOGIX_DP_TOTAL_LINE_CFG_H */ 199 #define TOTAL_LINE_CFG_H(x) (((x) & 0xf) << 0) 200 201 /* ANALOGIX_DP_ACTIVE_LINE_CFG_L */ 202 #define ACTIVE_LINE_CFG_L(x) (((x) & 0xff) << 0) 203 204 /* ANALOGIX_DP_ACTIVE_LINE_CFG_H */ 205 #define ACTIVE_LINE_CFG_H(x) (((x) & 0xf) << 0) 206 207 /* ANALOGIX_DP_V_F_PORCH_CFG */ 208 #define V_F_PORCH_CFG(x) (((x) & 0xff) << 0) 209 210 /* ANALOGIX_DP_V_SYNC_WIDTH_CFG */ 211 #define V_SYNC_WIDTH_CFG(x) (((x) & 0xff) << 0) 212 213 /* ANALOGIX_DP_V_B_PORCH_CFG */ 214 #define V_B_PORCH_CFG(x) (((x) & 0xff) << 0) 215 216 /* ANALOGIX_DP_TOTAL_PIXEL_CFG_L */ 217 #define TOTAL_PIXEL_CFG_L(x) (((x) & 0xff) << 0) 218 219 /* ANALOGIX_DP_TOTAL_PIXEL_CFG_H */ 220 #define TOTAL_PIXEL_CFG_H(x) (((x) & 0x3f) << 0) 221 222 /* ANALOGIX_DP_ACTIVE_PIXEL_CFG_L */ 223 #define ACTIVE_PIXEL_CFG_L(x) (((x) & 0xff) << 0) 224 225 /* ANALOGIX_DP_ACTIVE_PIXEL_CFG_H */ 226 #define ACTIVE_PIXEL_CFG_H(x) (((x) & 0x3f) << 0) 227 228 /* ANALOGIX_DP_H_F_PORCH_CFG_L */ 229 #define H_F_PORCH_CFG_L(x) (((x) & 0xff) << 0) 230 231 /* ANALOGIX_DP_H_F_PORCH_CFG_H */ 232 #define H_F_PORCH_CFG_H(x) (((x) & 0xf) << 0) 233 234 /* ANALOGIX_DP_H_SYNC_CFG_L */ 235 #define H_SYNC_CFG_L(x) (((x) & 0xff) << 0) 236 237 /* ANALOGIX_DP_H_SYNC_CFG_H */ 238 #define H_SYNC_CFG_H(x) (((x) & 0xf) << 0) 239 240 /* ANALOGIX_DP_H_B_PORCH_CFG_L */ 241 #define H_B_PORCH_CFG_L(x) (((x) & 0xff) << 0) 242 243 /* ANALOGIX_DP_H_B_PORCH_CFG_H */ 244 #define H_B_PORCH_CFG_H(x) (((x) & 0xf) << 0) 245 246 /* ANALOGIX_DP_PLL_REG_1 */ 247 #define REF_CLK_24M (0x1 << 0) 248 #define REF_CLK_27M (0x0 << 0) 249 #define REF_CLK_MASK (0x1 << 0) 250 251 /* ANALOGIX_DP_LANE_MAP */ 252 #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) 253 #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) 254 #define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6) 255 #define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6) 256 #define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4) 257 #define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4) 258 #define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4) 259 #define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4) 260 #define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2) 261 #define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2) 262 #define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2) 263 #define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2) 264 #define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0) 265 #define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0) 266 #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) 267 #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) 268 269 /* ANALOGIX_DP_ANALOG_CTL_1 */ 270 #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) 271 272 /* ANALOGIX_DP_ANALOG_CTL_2 */ 273 #define SEL_24M (0x1 << 3) 274 #define TX_DVDD_BIT_1_0625V (0x4 << 0) 275 276 /* ANALOGIX_DP_ANALOG_CTL_3 */ 277 #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) 278 #define VCO_BIT_600_MICRO (0x5 << 0) 279 280 /* ANALOGIX_DP_PLL_FILTER_CTL_1 */ 281 #define PD_RING_OSC (0x1 << 6) 282 #define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) 283 #define TX_CUR1_2X (0x1 << 2) 284 #define TX_CUR_16_MA (0x3 << 0) 285 286 /* ANALOGIX_DP_TX_AMP_TUNING_CTL */ 287 #define CH3_AMP_400_MV (0x0 << 24) 288 #define CH2_AMP_400_MV (0x0 << 16) 289 #define CH1_AMP_400_MV (0x0 << 8) 290 #define CH0_AMP_400_MV (0x0 << 0) 291 292 /* ANALOGIX_DP_AUX_HW_RETRY_CTL */ 293 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) 294 #define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) 295 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) 296 #define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3) 297 #define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3) 298 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) 299 #define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0) 300 301 /* ANALOGIX_DP_COMMON_INT_STA_1 */ 302 #define VSYNC_DET (0x1 << 7) 303 #define PLL_LOCK_CHG (0x1 << 6) 304 #define SPDIF_ERR (0x1 << 5) 305 #define SPDIF_UNSTBL (0x1 << 4) 306 #define VID_FORMAT_CHG (0x1 << 3) 307 #define AUD_CLK_CHG (0x1 << 2) 308 #define VID_CLK_CHG (0x1 << 1) 309 #define SW_INT (0x1 << 0) 310 311 /* ANALOGIX_DP_COMMON_INT_STA_2 */ 312 #define ENC_EN_CHG (0x1 << 6) 313 #define HW_BKSV_RDY (0x1 << 3) 314 #define HW_SHA_DONE (0x1 << 2) 315 #define HW_AUTH_STATE_CHG (0x1 << 1) 316 #define HW_AUTH_DONE (0x1 << 0) 317 318 /* ANALOGIX_DP_COMMON_INT_STA_3 */ 319 #define AFIFO_UNDER (0x1 << 7) 320 #define AFIFO_OVER (0x1 << 6) 321 #define R0_CHK_FLAG (0x1 << 5) 322 323 /* ANALOGIX_DP_COMMON_INT_STA_4 */ 324 #define PSR_ACTIVE (0x1 << 7) 325 #define PSR_INACTIVE (0x1 << 6) 326 #define SPDIF_BI_PHASE_ERR (0x1 << 5) 327 #define HOTPLUG_CHG (0x1 << 2) 328 #define HPD_LOST (0x1 << 1) 329 #define PLUG (0x1 << 0) 330 331 /* ANALOGIX_DP_INT_STA */ 332 #define INT_HPD (0x1 << 6) 333 #define HW_TRAINING_FINISH (0x1 << 5) 334 #define RPLY_RECEIV (0x1 << 1) 335 #define AUX_ERR (0x1 << 0) 336 337 /* ANALOGIX_DP_INT_CTL */ 338 #define SOFT_INT_CTRL (0x1 << 2) 339 #define INT_POL1 (0x1 << 1) 340 #define INT_POL0 (0x1 << 0) 341 342 /* ANALOGIX_DP_SYS_CTL_1 */ 343 #define DET_STA (0x1 << 2) 344 #define FORCE_DET (0x1 << 1) 345 #define DET_CTRL (0x1 << 0) 346 347 /* ANALOGIX_DP_SYS_CTL_2 */ 348 #define CHA_CRI(x) (((x) & 0xf) << 4) 349 #define CHA_STA (0x1 << 2) 350 #define FORCE_CHA (0x1 << 1) 351 #define CHA_CTRL (0x1 << 0) 352 353 /* ANALOGIX_DP_SYS_CTL_3 */ 354 #define HPD_STATUS (0x1 << 6) 355 #define F_HPD (0x1 << 5) 356 #define HPD_CTRL (0x1 << 4) 357 #define HDCP_RDY (0x1 << 3) 358 #define STRM_VALID (0x1 << 2) 359 #define F_VALID (0x1 << 1) 360 #define VALID_CTRL (0x1 << 0) 361 362 /* ANALOGIX_DP_SYS_CTL_4 */ 363 #define FIX_M_AUD (0x1 << 4) 364 #define ENHANCED (0x1 << 3) 365 #define FIX_M_VID (0x1 << 2) 366 #define M_VID_UPDATE_CTRL (0x3 << 0) 367 368 /* ANALOGIX_DP_TRAINING_PTN_SET */ 369 #define SCRAMBLER_TYPE (0x1 << 9) 370 #define HW_LINK_TRAINING_PATTERN (0x1 << 8) 371 #define SCRAMBLING_DISABLE (0x1 << 5) 372 #define SCRAMBLING_ENABLE (0x0 << 5) 373 #define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2) 374 #define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) 375 #define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) 376 #define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) 377 #define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) 378 #define SW_TRAINING_PATTERN_SET_PTN3 (0x3 << 0) 379 #define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) 380 #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) 381 #define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) 382 383 /* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */ 384 #define PRE_EMPHASIS_SET_MASK (0x3 << 3) 385 #define PRE_EMPHASIS_SET_SHIFT (3) 386 387 /* ANALOGIX_DP_DEBUG_CTL */ 388 #define PLL_LOCK (0x1 << 4) 389 #define F_PLL_LOCK (0x1 << 3) 390 #define PLL_LOCK_CTRL (0x1 << 2) 391 #define PN_INV (0x1 << 0) 392 393 /* ANALOGIX_DP_PLL_CTL */ 394 #define DP_PLL_PD (0x1 << 7) 395 #define DP_PLL_RESET (0x1 << 6) 396 #define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) 397 #define DP_PLL_REF_BIT_1_1250V (0x5 << 0) 398 #define DP_PLL_REF_BIT_1_2500V (0x7 << 0) 399 400 /* ANALOGIX_DP_PHY_PD */ 401 #define DP_PHY_PD (0x1 << 5) 402 #define AUX_PD (0x1 << 4) 403 #define CH3_PD (0x1 << 3) 404 #define CH2_PD (0x1 << 2) 405 #define CH1_PD (0x1 << 1) 406 #define CH0_PD (0x1 << 0) 407 408 /* ANALOGIX_DP_PHY_TEST */ 409 #define MACRO_RST (0x1 << 5) 410 #define CH1_TEST (0x1 << 1) 411 #define CH0_TEST (0x1 << 0) 412 413 /* ANALOGIX_DP_AUX_CH_STA */ 414 #define AUX_BUSY (0x1 << 4) 415 #define AUX_STATUS_MASK (0xf << 0) 416 417 /* ANALOGIX_DP_AUX_CH_DEFER_CTL */ 418 #define DEFER_CTRL_EN (0x1 << 7) 419 #define DEFER_COUNT(x) (((x) & 0x7f) << 0) 420 421 /* ANALOGIX_DP_AUX_RX_COMM */ 422 #define AUX_RX_COMM_I2C_DEFER (0x2 << 2) 423 #define AUX_RX_COMM_AUX_DEFER (0x2 << 0) 424 425 /* ANALOGIX_DP_BUFFER_DATA_CTL */ 426 #define BUF_CLR (0x1 << 7) 427 #define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0) 428 429 /* ANALOGIX_DP_AUX_CH_CTL_1 */ 430 #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) 431 #define AUX_TX_COMM_MASK (0xf << 0) 432 #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) 433 #define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) 434 #define AUX_TX_COMM_MOT (0x1 << 2) 435 #define AUX_TX_COMM_WRITE (0x0 << 0) 436 #define AUX_TX_COMM_READ (0x1 << 0) 437 438 /* ANALOGIX_DP_AUX_ADDR_7_0 */ 439 #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) 440 441 /* ANALOGIX_DP_AUX_ADDR_15_8 */ 442 #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) 443 444 /* ANALOGIX_DP_AUX_ADDR_19_16 */ 445 #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) 446 447 /* ANALOGIX_DP_AUX_CH_CTL_2 */ 448 #define ADDR_ONLY (0x1 << 1) 449 #define AUX_EN (0x1 << 0) 450 451 /* ANALOGIX_DP_SOC_GENERAL_CTL */ 452 #define AUDIO_MODE_SPDIF_MODE (0x1 << 8) 453 #define AUDIO_MODE_MASTER_MODE (0x0 << 8) 454 #define MASTER_VIDEO_INTERLACE_EN (0x1 << 4) 455 #define VIDEO_MASTER_CLK_SEL (0x1 << 2) 456 #define VIDEO_MASTER_MODE_EN (0x1 << 1) 457 #define VIDEO_MODE_MASK (0x1 << 0) 458 #define VIDEO_MODE_SLAVE_MODE (0x1 << 0) 459 #define VIDEO_MODE_MASTER_MODE (0x0 << 0) 460 461 /* ANALOGIX_DP_LINK_POLICY */ 462 #define ALTERNATE_SR_ENABLE (0x1 << 7) 463 464 #define DP_TIMEOUT_LOOP_COUNT 100 465 #define MAX_CR_LOOP 5 466 #define MAX_EQ_LOOP 5 467 468 /* I2C EDID Chip ID, Slave Address */ 469 #define I2C_EDID_DEVICE_ADDR 0x50 470 #define I2C_E_EDID_DEVICE_ADDR 0x30 471 472 #define EDID_BLOCK_LENGTH 0x80 473 #define EDID_HEADER_PATTERN 0x00 474 #define EDID_EXTENSION_FLAG 0x7e 475 #define EDID_CHECKSUM 0x7f 476 477 /* DP_MAX_LANE_COUNT */ 478 #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1) 479 #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f) 480 481 /* DP_LANE_COUNT_SET */ 482 #define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f) 483 484 /* DP_TRAINING_LANE0_SET */ 485 #define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3) 486 #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3) 487 #define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0) 488 #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3) 489 490 /* Supported link rate in eDP 1.4 */ 491 #define EDP_LINK_BW_2_16 0x08 492 #define EDP_LINK_BW_2_43 0x09 493 #define EDP_LINK_BW_3_24 0x0c 494 #define EDP_LINK_BW_4_32 0x10 495 496 enum link_lane_count_type { 497 LANE_COUNT1 = 1, 498 LANE_COUNT2 = 2, 499 LANE_COUNT4 = 4 500 }; 501 502 enum link_training_state { 503 START, 504 CLOCK_RECOVERY, 505 EQUALIZER_TRAINING, 506 FINISHED, 507 FAILED 508 }; 509 510 enum voltage_swing_level { 511 VOLTAGE_LEVEL_0, 512 VOLTAGE_LEVEL_1, 513 VOLTAGE_LEVEL_2, 514 VOLTAGE_LEVEL_3, 515 }; 516 517 enum pre_emphasis_level { 518 PRE_EMPHASIS_LEVEL_0, 519 PRE_EMPHASIS_LEVEL_1, 520 PRE_EMPHASIS_LEVEL_2, 521 PRE_EMPHASIS_LEVEL_3, 522 }; 523 524 enum pattern_set { 525 PRBS7, 526 D10_2, 527 TRAINING_PTN1, 528 TRAINING_PTN2, 529 TRAINING_PTN3, 530 DP_NONE 531 }; 532 533 enum color_space { 534 COLOR_RGB, 535 COLOR_YCBCR422, 536 COLOR_YCBCR444 537 }; 538 539 enum color_depth { 540 COLOR_6, 541 COLOR_8, 542 COLOR_10, 543 COLOR_12 544 }; 545 546 enum color_coefficient { 547 COLOR_YCBCR601, 548 COLOR_YCBCR709 549 }; 550 551 enum dynamic_range { 552 VESA, 553 CEA 554 }; 555 556 enum pll_status { 557 PLL_UNLOCKED, 558 PLL_LOCKED 559 }; 560 561 enum clock_recovery_m_value_type { 562 CALCULATED_M, 563 REGISTER_M 564 }; 565 566 enum video_timing_recognition_type { 567 VIDEO_TIMING_FROM_CAPTURE, 568 VIDEO_TIMING_FROM_REGISTER 569 }; 570 571 enum analog_power_block { 572 AUX_BLOCK, 573 CH0_BLOCK, 574 CH1_BLOCK, 575 CH2_BLOCK, 576 CH3_BLOCK, 577 ANALOG_TOTAL, 578 POWER_ALL 579 }; 580 581 enum dp_irq_type { 582 DP_IRQ_TYPE_HP_CABLE_IN = BIT(0), 583 DP_IRQ_TYPE_HP_CABLE_OUT = BIT(1), 584 DP_IRQ_TYPE_HP_CHANGE = BIT(2), 585 DP_IRQ_TYPE_UNKNOWN = BIT(3), 586 }; 587 588 struct video_info { 589 char *name; 590 struct drm_display_mode mode; 591 592 bool h_sync_polarity; 593 bool v_sync_polarity; 594 bool interlaced; 595 596 enum color_space color_space; 597 enum dynamic_range dynamic_range; 598 enum color_coefficient ycbcr_coeff; 599 enum color_depth color_depth; 600 601 int max_link_rate; 602 enum link_lane_count_type max_lane_count; 603 604 bool force_stream_valid; 605 606 u32 bpc; 607 }; 608 609 struct link_train { 610 int eq_loop; 611 int cr_loop[4]; 612 613 u8 link_rate; 614 u8 lane_count; 615 u8 training_lane[4]; 616 bool ssc; 617 618 enum link_training_state lt_state; 619 }; 620 621 enum analogix_dp_devtype { 622 EXYNOS_DP, 623 ROCKCHIP_DP, 624 }; 625 626 enum analogix_dp_sub_devtype { 627 RK3288_DP, 628 RK3368_EDP, 629 RK3399_EDP, 630 RK3568_EDP, 631 RK3576_EDP, 632 RK3588_EDP 633 }; 634 635 struct analogix_dp_plat_data { 636 enum analogix_dp_devtype dev_type; 637 enum analogix_dp_sub_devtype subdev_type; 638 bool ssc; 639 bool support_dp_mode; 640 u8 max_bpc; 641 }; 642 643 struct analogix_dp_device { 644 struct rockchip_connector connector; 645 int id; 646 int nr_link_rate_table; 647 int link_rate_table[DP_MAX_SUPPORTED_RATES]; 648 int link_rate_select; 649 struct udevice *dev; 650 void *reg_base; 651 struct regmap *grf; 652 struct phy phy; 653 #if defined(CONFIG_MOS_SUPPORT) && !defined(CONFIG_SPL_BUILD) 654 struct power_domain pwrdom; 655 struct clk_bulk clks; 656 #endif 657 struct reset_ctl_bulk resets; 658 struct gpio_desc hpd_gpio; 659 bool force_hpd; 660 struct video_info video_info; 661 struct link_train link_train; 662 struct drm_display_mode *mode; 663 struct analogix_dp_plat_data plat_data; 664 unsigned char edid[EDID_BLOCK_LENGTH * 2]; 665 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 666 bool video_bist_enable; 667 u32 lane_map[4]; 668 struct drm_dp_aux aux; 669 const struct analogix_dp_output_format *output_fmt; 670 bool dp_mode; 671 }; 672 673 struct analogix_dp_output_format { 674 u32 bus_format; 675 u32 color_format; 676 u8 bpc; 677 }; 678 679 /* analogix_dp_reg.c */ 680 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable); 681 void analogix_dp_stop_video(struct analogix_dp_device *dp); 682 void analogix_dp_init_analog_param(struct analogix_dp_device *dp); 683 void analogix_dp_init_interrupt(struct analogix_dp_device *dp); 684 void analogix_dp_reset(struct analogix_dp_device *dp); 685 void analogix_dp_swreset(struct analogix_dp_device *dp); 686 void analogix_dp_config_interrupt(struct analogix_dp_device *dp); 687 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp); 688 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp); 689 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp); 690 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable); 691 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 692 enum analog_power_block block, 693 bool enable); 694 void analogix_dp_init_analog_func(struct analogix_dp_device *dp); 695 void analogix_dp_init_hpd(struct analogix_dp_device *dp); 696 void analogix_dp_force_hpd(struct analogix_dp_device *dp); 697 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp); 698 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp); 699 void analogix_dp_reset_aux(struct analogix_dp_device *dp); 700 void analogix_dp_init_aux(struct analogix_dp_device *dp); 701 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp); 702 int analogix_dp_detect(struct analogix_dp_device *dp); 703 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp); 704 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp); 705 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp, 706 unsigned int device_addr, 707 unsigned int reg_addr); 708 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp, 709 unsigned int device_addr, 710 unsigned int reg_addr, 711 unsigned int *data); 712 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp, 713 unsigned int device_addr, 714 unsigned int reg_addr, 715 unsigned int count, 716 unsigned char edid[]); 717 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype); 718 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype); 719 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count); 720 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count); 721 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, 722 bool enable); 723 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, 724 enum pattern_set pattern); 725 void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp); 726 u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane); 727 void analogix_dp_reset_macro(struct analogix_dp_device *dp); 728 void analogix_dp_init_video(struct analogix_dp_device *dp); 729 730 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp); 731 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp); 732 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, 733 enum clock_recovery_m_value_type type, 734 u32 m_value, 735 u32 n_value); 736 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type); 737 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, 738 bool enable); 739 void analogix_dp_start_video(struct analogix_dp_device *dp); 740 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp); 741 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp); 742 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp); 743 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp); 744 bool analogix_dp_ssc_supported(struct analogix_dp_device *dp); 745 void analogix_dp_set_video_format(struct analogix_dp_device *dp, 746 const struct drm_display_mode *mode); 747 void analogix_dp_video_bist_enable(struct analogix_dp_device *dp); 748 ssize_t analogix_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg); 749 void analogix_dp_enable_assr_mode(struct analogix_dp_device *dp, bool enable); 750 bool analogix_dp_get_assr_mode(struct analogix_dp_device *dp); 751 752 #endif /* __DRM_ANALOGIX_DP__ */ 753