1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __DRM_ANALOGIX_DP_H__ 8 #define __DRM_ANALOGIX_DP_H__ 9 10 #include <generic-phy.h> 11 #include <reset.h> 12 13 #include <drm/drm_dp_helper.h> 14 15 #define ANALOGIX_DP_TX_SW_RESET 0x14 16 #define ANALOGIX_DP_FUNC_EN_1 0x18 17 #define ANALOGIX_DP_FUNC_EN_2 0x1C 18 #define ANALOGIX_DP_VIDEO_CTL_1 0x20 19 #define ANALOGIX_DP_VIDEO_CTL_2 0x24 20 #define ANALOGIX_DP_VIDEO_CTL_3 0x28 21 22 #define ANALOGIX_DP_VIDEO_CTL_8 0x3C 23 #define ANALOGIX_DP_VIDEO_CTL_10 0x44 24 25 #define ANALOGIX_DP_PLL_REG_1 0xfc 26 #define ANALOGIX_DP_PLL_REG_2 0x9e4 27 #define ANALOGIX_DP_PLL_REG_3 0x9e8 28 #define ANALOGIX_DP_PLL_REG_4 0x9ec 29 #define ANALOGIX_DP_PLL_REG_5 0xa00 30 31 #define ANALOGIX_DP_PD 0x12c 32 33 #define ANALOGIX_DP_LANE_MAP 0x35C 34 35 #define ANALOGIX_DP_ANALOG_CTL_1 0x370 36 #define ANALOGIX_DP_ANALOG_CTL_2 0x374 37 #define ANALOGIX_DP_ANALOG_CTL_3 0x378 38 #define ANALOGIX_DP_PLL_FILTER_CTL_1 0x37C 39 #define ANALOGIX_DP_TX_AMP_TUNING_CTL 0x380 40 41 #define ANALOGIX_DP_AUX_HW_RETRY_CTL 0x390 42 43 #define ANALOGIX_DP_COMMON_INT_STA_1 0x3C4 44 #define ANALOGIX_DP_COMMON_INT_STA_2 0x3C8 45 #define ANALOGIX_DP_COMMON_INT_STA_3 0x3CC 46 #define ANALOGIX_DP_COMMON_INT_STA_4 0x3D0 47 #define ANALOGIX_DP_INT_STA 0x3DC 48 #define ANALOGIX_DP_COMMON_INT_MASK_1 0x3E0 49 #define ANALOGIX_DP_COMMON_INT_MASK_2 0x3E4 50 #define ANALOGIX_DP_COMMON_INT_MASK_3 0x3E8 51 #define ANALOGIX_DP_COMMON_INT_MASK_4 0x3EC 52 #define ANALOGIX_DP_INT_STA_MASK 0x3F8 53 #define ANALOGIX_DP_INT_CTL 0x3FC 54 55 #define ANALOGIX_DP_SYS_CTL_1 0x600 56 #define ANALOGIX_DP_SYS_CTL_2 0x604 57 #define ANALOGIX_DP_SYS_CTL_3 0x608 58 #define ANALOGIX_DP_SYS_CTL_4 0x60C 59 60 #define ANALOGIX_DP_PKT_SEND_CTL 0x640 61 #define ANALOGIX_DP_HDCP_CTL 0x648 62 63 #define ANALOGIX_DP_LINK_BW_SET 0x680 64 #define ANALOGIX_DP_LANE_COUNT_SET 0x684 65 #define ANALOGIX_DP_TRAINING_PTN_SET 0x688 66 #define ANALOGIX_DP_LN0_LINK_TRAINING_CTL 0x68C 67 #define ANALOGIX_DP_LN1_LINK_TRAINING_CTL 0x690 68 #define ANALOGIX_DP_LN2_LINK_TRAINING_CTL 0x694 69 #define ANALOGIX_DP_LN3_LINK_TRAINING_CTL 0x698 70 71 #define ANALOGIX_DP_DEBUG_CTL 0x6C0 72 #define ANALOGIX_DP_HPD_DEGLITCH_L 0x6C4 73 #define ANALOGIX_DP_HPD_DEGLITCH_H 0x6C8 74 #define ANALOGIX_DP_LINK_DEBUG_CTL 0x6E0 75 76 #define ANALOGIX_DP_M_VID_0 0x700 77 #define ANALOGIX_DP_M_VID_1 0x704 78 #define ANALOGIX_DP_M_VID_2 0x708 79 #define ANALOGIX_DP_N_VID_0 0x70C 80 #define ANALOGIX_DP_N_VID_1 0x710 81 #define ANALOGIX_DP_N_VID_2 0x714 82 83 #define ANALOGIX_DP_PLL_CTL 0x71C 84 #define ANALOGIX_DP_PHY_PD 0x720 85 #define ANALOGIX_DP_PHY_TEST 0x724 86 87 #define ANALOGIX_DP_VIDEO_FIFO_THRD 0x730 88 #define ANALOGIX_DP_AUDIO_MARGIN 0x73C 89 90 #define ANALOGIX_DP_M_VID_GEN_FILTER_TH 0x764 91 #define ANALOGIX_DP_M_AUD_GEN_FILTER_TH 0x778 92 #define ANALOGIX_DP_AUX_CH_STA 0x780 93 #define ANALOGIX_DP_AUX_CH_DEFER_CTL 0x788 94 #define ANALOGIX_DP_AUX_RX_COMM 0x78C 95 #define ANALOGIX_DP_BUFFER_DATA_CTL 0x790 96 #define ANALOGIX_DP_AUX_CH_CTL_1 0x794 97 #define ANALOGIX_DP_AUX_ADDR_7_0 0x798 98 #define ANALOGIX_DP_AUX_ADDR_15_8 0x79C 99 #define ANALOGIX_DP_AUX_ADDR_19_16 0x7A0 100 #define ANALOGIX_DP_AUX_CH_CTL_2 0x7A4 101 102 #define ANALOGIX_DP_BUF_DATA_0 0x7C0 103 104 #define ANALOGIX_DP_SOC_GENERAL_CTL 0x800 105 106 /* ANALOGIX_DP_TX_SW_RESET */ 107 #define RESET_DP_TX (0x1 << 0) 108 109 /* ANALOGIX_DP_FUNC_EN_1 */ 110 #define MASTER_VID_FUNC_EN_N (0x1 << 7) 111 #define SLAVE_VID_FUNC_EN_N (0x1 << 5) 112 #define AUD_FIFO_FUNC_EN_N (0x1 << 4) 113 #define AUD_FUNC_EN_N (0x1 << 3) 114 #define HDCP_FUNC_EN_N (0x1 << 2) 115 #define CRC_FUNC_EN_N (0x1 << 1) 116 #define SW_FUNC_EN_N (0x1 << 0) 117 118 /* ANALOGIX_DP_FUNC_EN_2 */ 119 #define SSC_FUNC_EN_N (0x1 << 7) 120 #define AUX_FUNC_EN_N (0x1 << 2) 121 #define SERDES_FIFO_FUNC_EN_N (0x1 << 1) 122 #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) 123 124 /* ANALOGIX_DP_VIDEO_CTL_1 */ 125 #define VIDEO_EN (0x1 << 7) 126 #define HDCP_VIDEO_MUTE (0x1 << 6) 127 128 /* ANALOGIX_DP_VIDEO_CTL_1 */ 129 #define IN_D_RANGE_MASK (0x1 << 7) 130 #define IN_D_RANGE_SHIFT (7) 131 #define IN_D_RANGE_CEA (0x1 << 7) 132 #define IN_D_RANGE_VESA (0x0 << 7) 133 #define IN_BPC_MASK (0x7 << 4) 134 #define IN_BPC_SHIFT (4) 135 #define IN_BPC_12_BITS (0x3 << 4) 136 #define IN_BPC_10_BITS (0x2 << 4) 137 #define IN_BPC_8_BITS (0x1 << 4) 138 #define IN_BPC_6_BITS (0x0 << 4) 139 #define IN_COLOR_F_MASK (0x3 << 0) 140 #define IN_COLOR_F_SHIFT (0) 141 #define IN_COLOR_F_YCBCR444 (0x2 << 0) 142 #define IN_COLOR_F_YCBCR422 (0x1 << 0) 143 #define IN_COLOR_F_RGB (0x0 << 0) 144 145 /* ANALOGIX_DP_VIDEO_CTL_3 */ 146 #define IN_YC_COEFFI_MASK (0x1 << 7) 147 #define IN_YC_COEFFI_SHIFT (7) 148 #define IN_YC_COEFFI_ITU709 (0x1 << 7) 149 #define IN_YC_COEFFI_ITU601 (0x0 << 7) 150 #define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) 151 #define VID_CHK_UPDATE_TYPE_SHIFT (4) 152 #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) 153 #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) 154 155 /* ANALOGIX_DP_VIDEO_CTL_8 */ 156 #define VID_HRES_TH(x) (((x) & 0xf) << 4) 157 #define VID_VRES_TH(x) (((x) & 0xf) << 0) 158 159 /* ANALOGIX_DP_VIDEO_CTL_10 */ 160 #define FORMAT_SEL (0x1 << 4) 161 #define INTERACE_SCAN_CFG (0x1 << 2) 162 #define VSYNC_POLARITY_CFG (0x1 << 1) 163 #define HSYNC_POLARITY_CFG (0x1 << 0) 164 165 /* ANALOGIX_DP_PLL_REG_1 */ 166 #define REF_CLK_24M (0x1 << 0) 167 #define REF_CLK_27M (0x0 << 0) 168 #define REF_CLK_MASK (0x1 << 0) 169 170 /* ANALOGIX_DP_LANE_MAP */ 171 #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) 172 #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) 173 #define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6) 174 #define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6) 175 #define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4) 176 #define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4) 177 #define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4) 178 #define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4) 179 #define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2) 180 #define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2) 181 #define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2) 182 #define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2) 183 #define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0) 184 #define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0) 185 #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) 186 #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) 187 188 /* ANALOGIX_DP_ANALOG_CTL_1 */ 189 #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) 190 191 /* ANALOGIX_DP_ANALOG_CTL_2 */ 192 #define SEL_24M (0x1 << 3) 193 #define TX_DVDD_BIT_1_0625V (0x4 << 0) 194 195 /* ANALOGIX_DP_ANALOG_CTL_3 */ 196 #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) 197 #define VCO_BIT_600_MICRO (0x5 << 0) 198 199 /* ANALOGIX_DP_PLL_FILTER_CTL_1 */ 200 #define PD_RING_OSC (0x1 << 6) 201 #define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) 202 #define TX_CUR1_2X (0x1 << 2) 203 #define TX_CUR_16_MA (0x3 << 0) 204 205 /* ANALOGIX_DP_TX_AMP_TUNING_CTL */ 206 #define CH3_AMP_400_MV (0x0 << 24) 207 #define CH2_AMP_400_MV (0x0 << 16) 208 #define CH1_AMP_400_MV (0x0 << 8) 209 #define CH0_AMP_400_MV (0x0 << 0) 210 211 /* ANALOGIX_DP_AUX_HW_RETRY_CTL */ 212 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) 213 #define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) 214 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) 215 #define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3) 216 #define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3) 217 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) 218 #define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0) 219 220 /* ANALOGIX_DP_COMMON_INT_STA_1 */ 221 #define VSYNC_DET (0x1 << 7) 222 #define PLL_LOCK_CHG (0x1 << 6) 223 #define SPDIF_ERR (0x1 << 5) 224 #define SPDIF_UNSTBL (0x1 << 4) 225 #define VID_FORMAT_CHG (0x1 << 3) 226 #define AUD_CLK_CHG (0x1 << 2) 227 #define VID_CLK_CHG (0x1 << 1) 228 #define SW_INT (0x1 << 0) 229 230 /* ANALOGIX_DP_COMMON_INT_STA_2 */ 231 #define ENC_EN_CHG (0x1 << 6) 232 #define HW_BKSV_RDY (0x1 << 3) 233 #define HW_SHA_DONE (0x1 << 2) 234 #define HW_AUTH_STATE_CHG (0x1 << 1) 235 #define HW_AUTH_DONE (0x1 << 0) 236 237 /* ANALOGIX_DP_COMMON_INT_STA_3 */ 238 #define AFIFO_UNDER (0x1 << 7) 239 #define AFIFO_OVER (0x1 << 6) 240 #define R0_CHK_FLAG (0x1 << 5) 241 242 /* ANALOGIX_DP_COMMON_INT_STA_4 */ 243 #define PSR_ACTIVE (0x1 << 7) 244 #define PSR_INACTIVE (0x1 << 6) 245 #define SPDIF_BI_PHASE_ERR (0x1 << 5) 246 #define HOTPLUG_CHG (0x1 << 2) 247 #define HPD_LOST (0x1 << 1) 248 #define PLUG (0x1 << 0) 249 250 /* ANALOGIX_DP_INT_STA */ 251 #define INT_HPD (0x1 << 6) 252 #define HW_TRAINING_FINISH (0x1 << 5) 253 #define RPLY_RECEIV (0x1 << 1) 254 #define AUX_ERR (0x1 << 0) 255 256 /* ANALOGIX_DP_INT_CTL */ 257 #define SOFT_INT_CTRL (0x1 << 2) 258 #define INT_POL1 (0x1 << 1) 259 #define INT_POL0 (0x1 << 0) 260 261 /* ANALOGIX_DP_SYS_CTL_1 */ 262 #define DET_STA (0x1 << 2) 263 #define FORCE_DET (0x1 << 1) 264 #define DET_CTRL (0x1 << 0) 265 266 /* ANALOGIX_DP_SYS_CTL_2 */ 267 #define CHA_CRI(x) (((x) & 0xf) << 4) 268 #define CHA_STA (0x1 << 2) 269 #define FORCE_CHA (0x1 << 1) 270 #define CHA_CTRL (0x1 << 0) 271 272 /* ANALOGIX_DP_SYS_CTL_3 */ 273 #define HPD_STATUS (0x1 << 6) 274 #define F_HPD (0x1 << 5) 275 #define HPD_CTRL (0x1 << 4) 276 #define HDCP_RDY (0x1 << 3) 277 #define STRM_VALID (0x1 << 2) 278 #define F_VALID (0x1 << 1) 279 #define VALID_CTRL (0x1 << 0) 280 281 /* ANALOGIX_DP_SYS_CTL_4 */ 282 #define FIX_M_AUD (0x1 << 4) 283 #define ENHANCED (0x1 << 3) 284 #define FIX_M_VID (0x1 << 2) 285 #define M_VID_UPDATE_CTRL (0x3 << 0) 286 287 /* ANALOGIX_DP_TRAINING_PTN_SET */ 288 #define SCRAMBLER_TYPE (0x1 << 9) 289 #define HW_LINK_TRAINING_PATTERN (0x1 << 8) 290 #define SCRAMBLING_DISABLE (0x1 << 5) 291 #define SCRAMBLING_ENABLE (0x0 << 5) 292 #define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2) 293 #define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) 294 #define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) 295 #define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) 296 #define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) 297 #define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) 298 #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) 299 #define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) 300 301 /* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */ 302 #define PRE_EMPHASIS_SET_MASK (0x3 << 3) 303 #define PRE_EMPHASIS_SET_SHIFT (3) 304 305 /* ANALOGIX_DP_DEBUG_CTL */ 306 #define PLL_LOCK (0x1 << 4) 307 #define F_PLL_LOCK (0x1 << 3) 308 #define PLL_LOCK_CTRL (0x1 << 2) 309 #define PN_INV (0x1 << 0) 310 311 /* ANALOGIX_DP_PLL_CTL */ 312 #define DP_PLL_PD (0x1 << 7) 313 #define DP_PLL_RESET (0x1 << 6) 314 #define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) 315 #define DP_PLL_REF_BIT_1_1250V (0x5 << 0) 316 #define DP_PLL_REF_BIT_1_2500V (0x7 << 0) 317 318 /* ANALOGIX_DP_PHY_PD */ 319 #define DP_PHY_PD (0x1 << 5) 320 #define AUX_PD (0x1 << 4) 321 #define CH3_PD (0x1 << 3) 322 #define CH2_PD (0x1 << 2) 323 #define CH1_PD (0x1 << 1) 324 #define CH0_PD (0x1 << 0) 325 326 /* ANALOGIX_DP_PHY_TEST */ 327 #define MACRO_RST (0x1 << 5) 328 #define CH1_TEST (0x1 << 1) 329 #define CH0_TEST (0x1 << 0) 330 331 /* ANALOGIX_DP_AUX_CH_STA */ 332 #define AUX_BUSY (0x1 << 4) 333 #define AUX_STATUS_MASK (0xf << 0) 334 335 /* ANALOGIX_DP_AUX_CH_DEFER_CTL */ 336 #define DEFER_CTRL_EN (0x1 << 7) 337 #define DEFER_COUNT(x) (((x) & 0x7f) << 0) 338 339 /* ANALOGIX_DP_AUX_RX_COMM */ 340 #define AUX_RX_COMM_I2C_DEFER (0x2 << 2) 341 #define AUX_RX_COMM_AUX_DEFER (0x2 << 0) 342 343 /* ANALOGIX_DP_BUFFER_DATA_CTL */ 344 #define BUF_CLR (0x1 << 7) 345 #define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0) 346 347 /* ANALOGIX_DP_AUX_CH_CTL_1 */ 348 #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) 349 #define AUX_TX_COMM_MASK (0xf << 0) 350 #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) 351 #define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) 352 #define AUX_TX_COMM_MOT (0x1 << 2) 353 #define AUX_TX_COMM_WRITE (0x0 << 0) 354 #define AUX_TX_COMM_READ (0x1 << 0) 355 356 /* ANALOGIX_DP_AUX_ADDR_7_0 */ 357 #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) 358 359 /* ANALOGIX_DP_AUX_ADDR_15_8 */ 360 #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) 361 362 /* ANALOGIX_DP_AUX_ADDR_19_16 */ 363 #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) 364 365 /* ANALOGIX_DP_AUX_CH_CTL_2 */ 366 #define ADDR_ONLY (0x1 << 1) 367 #define AUX_EN (0x1 << 0) 368 369 /* ANALOGIX_DP_SOC_GENERAL_CTL */ 370 #define AUDIO_MODE_SPDIF_MODE (0x1 << 8) 371 #define AUDIO_MODE_MASTER_MODE (0x0 << 8) 372 #define MASTER_VIDEO_INTERLACE_EN (0x1 << 4) 373 #define VIDEO_MASTER_CLK_SEL (0x1 << 2) 374 #define VIDEO_MASTER_MODE_EN (0x1 << 1) 375 #define VIDEO_MODE_MASK (0x1 << 0) 376 #define VIDEO_MODE_SLAVE_MODE (0x1 << 0) 377 #define VIDEO_MODE_MASTER_MODE (0x0 << 0) 378 379 #define DP_TIMEOUT_LOOP_COUNT 100 380 #define MAX_CR_LOOP 5 381 #define MAX_EQ_LOOP 5 382 383 /* I2C EDID Chip ID, Slave Address */ 384 #define I2C_EDID_DEVICE_ADDR 0x50 385 #define I2C_E_EDID_DEVICE_ADDR 0x30 386 387 #define EDID_BLOCK_LENGTH 0x80 388 #define EDID_HEADER_PATTERN 0x00 389 #define EDID_EXTENSION_FLAG 0x7e 390 #define EDID_CHECKSUM 0x7f 391 392 /* DP_MAX_LANE_COUNT */ 393 #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1) 394 #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f) 395 396 /* DP_LANE_COUNT_SET */ 397 #define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f) 398 399 /* DP_TRAINING_LANE0_SET */ 400 #define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3) 401 #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3) 402 #define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0) 403 #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3) 404 405 enum link_lane_count_type { 406 LANE_COUNT1 = 1, 407 LANE_COUNT2 = 2, 408 LANE_COUNT4 = 4 409 }; 410 411 enum link_training_state { 412 START, 413 CLOCK_RECOVERY, 414 EQUALIZER_TRAINING, 415 FINISHED, 416 FAILED 417 }; 418 419 enum voltage_swing_level { 420 VOLTAGE_LEVEL_0, 421 VOLTAGE_LEVEL_1, 422 VOLTAGE_LEVEL_2, 423 VOLTAGE_LEVEL_3, 424 }; 425 426 enum pre_emphasis_level { 427 PRE_EMPHASIS_LEVEL_0, 428 PRE_EMPHASIS_LEVEL_1, 429 PRE_EMPHASIS_LEVEL_2, 430 PRE_EMPHASIS_LEVEL_3, 431 }; 432 433 enum pattern_set { 434 PRBS7, 435 D10_2, 436 TRAINING_PTN1, 437 TRAINING_PTN2, 438 DP_NONE 439 }; 440 441 enum color_space { 442 COLOR_RGB, 443 COLOR_YCBCR422, 444 COLOR_YCBCR444 445 }; 446 447 enum color_depth { 448 COLOR_6, 449 COLOR_8, 450 COLOR_10, 451 COLOR_12 452 }; 453 454 enum color_coefficient { 455 COLOR_YCBCR601, 456 COLOR_YCBCR709 457 }; 458 459 enum dynamic_range { 460 VESA, 461 CEA 462 }; 463 464 enum pll_status { 465 PLL_UNLOCKED, 466 PLL_LOCKED 467 }; 468 469 enum clock_recovery_m_value_type { 470 CALCULATED_M, 471 REGISTER_M 472 }; 473 474 enum video_timing_recognition_type { 475 VIDEO_TIMING_FROM_CAPTURE, 476 VIDEO_TIMING_FROM_REGISTER 477 }; 478 479 enum analog_power_block { 480 AUX_BLOCK, 481 CH0_BLOCK, 482 CH1_BLOCK, 483 CH2_BLOCK, 484 CH3_BLOCK, 485 ANALOG_TOTAL, 486 POWER_ALL 487 }; 488 489 enum dp_irq_type { 490 DP_IRQ_TYPE_HP_CABLE_IN = BIT(0), 491 DP_IRQ_TYPE_HP_CABLE_OUT = BIT(1), 492 DP_IRQ_TYPE_HP_CHANGE = BIT(2), 493 DP_IRQ_TYPE_UNKNOWN = BIT(3), 494 }; 495 496 struct video_info { 497 char *name; 498 499 bool h_sync_polarity; 500 bool v_sync_polarity; 501 bool interlaced; 502 503 enum color_space color_space; 504 enum dynamic_range dynamic_range; 505 enum color_coefficient ycbcr_coeff; 506 enum color_depth color_depth; 507 508 int max_link_rate; 509 enum link_lane_count_type max_lane_count; 510 }; 511 512 struct link_train { 513 int eq_loop; 514 int cr_loop[4]; 515 516 u8 link_rate; 517 u8 lane_count; 518 u8 training_lane[4]; 519 bool ssc; 520 521 enum link_training_state lt_state; 522 }; 523 524 enum analogix_dp_devtype { 525 EXYNOS_DP, 526 ROCKCHIP_DP, 527 }; 528 529 enum analogix_dp_sub_devtype { 530 RK3288_DP, 531 RK3368_EDP, 532 RK3399_EDP, 533 RK3568_EDP, 534 }; 535 536 struct analogix_dp_plat_data { 537 enum analogix_dp_devtype dev_type; 538 enum analogix_dp_sub_devtype subdev_type; 539 bool ssc; 540 }; 541 542 struct analogix_dp_device { 543 int id; 544 struct udevice *dev; 545 void *reg_base; 546 struct phy phy; 547 struct reset_ctl_bulk resets; 548 struct gpio_desc hpd_gpio; 549 bool force_hpd; 550 struct video_info video_info; 551 struct link_train link_train; 552 struct drm_display_mode *mode; 553 struct analogix_dp_plat_data plat_data; 554 unsigned char edid[EDID_BLOCK_LENGTH * 2]; 555 }; 556 557 /* analogix_dp_reg.c */ 558 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable); 559 void analogix_dp_stop_video(struct analogix_dp_device *dp); 560 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable); 561 void analogix_dp_init_analog_param(struct analogix_dp_device *dp); 562 void analogix_dp_init_interrupt(struct analogix_dp_device *dp); 563 void analogix_dp_reset(struct analogix_dp_device *dp); 564 void analogix_dp_swreset(struct analogix_dp_device *dp); 565 void analogix_dp_config_interrupt(struct analogix_dp_device *dp); 566 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp); 567 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp); 568 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp); 569 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable); 570 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 571 enum analog_power_block block, 572 bool enable); 573 void analogix_dp_init_analog_func(struct analogix_dp_device *dp); 574 void analogix_dp_init_hpd(struct analogix_dp_device *dp); 575 void analogix_dp_force_hpd(struct analogix_dp_device *dp); 576 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp); 577 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp); 578 void analogix_dp_reset_aux(struct analogix_dp_device *dp); 579 void analogix_dp_init_aux(struct analogix_dp_device *dp); 580 int analogix_dp_detect(struct analogix_dp_device *dp); 581 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp); 582 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp); 583 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp, 584 unsigned int reg_addr, 585 unsigned char data); 586 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp, 587 unsigned int reg_addr, 588 unsigned char *data); 589 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp, 590 unsigned int reg_addr, 591 unsigned int count, 592 unsigned char data[]); 593 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp, 594 unsigned int reg_addr, 595 unsigned int count, 596 unsigned char data[]); 597 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp, 598 unsigned int device_addr, 599 unsigned int reg_addr); 600 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp, 601 unsigned int device_addr, 602 unsigned int reg_addr, 603 unsigned int *data); 604 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp, 605 unsigned int device_addr, 606 unsigned int reg_addr, 607 unsigned int count, 608 unsigned char edid[]); 609 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype); 610 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype); 611 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count); 612 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count); 613 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, 614 bool enable); 615 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, 616 enum pattern_set pattern); 617 void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp); 618 u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane); 619 void analogix_dp_reset_macro(struct analogix_dp_device *dp); 620 void analogix_dp_init_video(struct analogix_dp_device *dp); 621 622 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp); 623 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp); 624 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, 625 enum clock_recovery_m_value_type type, 626 u32 m_value, 627 u32 n_value); 628 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type); 629 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, 630 bool enable); 631 void analogix_dp_start_video(struct analogix_dp_device *dp); 632 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp); 633 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp); 634 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp); 635 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp); 636 bool analogix_dp_ssc_supported(struct analogix_dp_device *dp); 637 638 #endif /* __DRM_ANALOGIX_DP__ */ 639