1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __DRM_ANALOGIX_DP_H__ 8 #define __DRM_ANALOGIX_DP_H__ 9 10 #include <reset.h> 11 12 /* 13 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that 14 * DP and DPCD versions are independent. Differences from 1.0 are not noted, 15 * 1.0 devices basically don't exist in the wild. 16 * 17 * Abbreviations, in chronological order: 18 * 19 * eDP: Embedded DisplayPort version 1 20 * DPI: DisplayPort Interoperability Guideline v1.1a 21 * 1.2: DisplayPort 1.2 22 * MST: Multistream Transport - part of DP 1.2a 23 * 24 * 1.2 formally includes both eDP and DPI definitions. 25 */ 26 27 #define DP_AUX_MAX_PAYLOAD_BYTES 16 28 29 #define DP_AUX_I2C_WRITE 0x0 30 #define DP_AUX_I2C_READ 0x1 31 #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2 32 #define DP_AUX_I2C_MOT 0x4 33 #define DP_AUX_NATIVE_WRITE 0x8 34 #define DP_AUX_NATIVE_READ 0x9 35 36 #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) 37 #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) 38 #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) 39 #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) 40 41 #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) 42 #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) 43 #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) 44 #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) 45 46 /* AUX CH addresses */ 47 /* DPCD */ 48 #define DP_DPCD_REV 0x000 49 50 #define DP_MAX_LINK_RATE 0x001 51 52 #define DP_MAX_LANE_COUNT 0x002 53 # define DP_MAX_LANE_COUNT_MASK 0x1f 54 # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ 55 # define DP_ENHANCED_FRAME_CAP (1 << 7) 56 57 #define DP_MAX_DOWNSPREAD 0x003 58 # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) 59 60 #define DP_NORP 0x004 61 62 #define DP_DOWNSTREAMPORT_PRESENT 0x005 63 # define DP_DWN_STRM_PORT_PRESENT (1 << 0) 64 # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 65 # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) 66 # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) 67 # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) 68 # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) 69 # define DP_FORMAT_CONVERSION (1 << 3) 70 # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ 71 72 #define DP_MAIN_LINK_CHANNEL_CODING 0x006 73 74 #define DP_DOWN_STREAM_PORT_COUNT 0x007 75 # define DP_PORT_COUNT_MASK 0x0f 76 # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ 77 # define DP_OUI_SUPPORT (1 << 7) 78 79 #define DP_RECEIVE_PORT_0_CAP_0 0x008 80 # define DP_LOCAL_EDID_PRESENT (1 << 1) 81 # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) 82 83 #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009 84 85 #define DP_RECEIVE_PORT_1_CAP_0 0x00a 86 #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b 87 88 #define DP_I2C_SPEED_CAP 0x00c /* DPI */ 89 # define DP_I2C_SPEED_1K 0x01 90 # define DP_I2C_SPEED_5K 0x02 91 # define DP_I2C_SPEED_10K 0x04 92 # define DP_I2C_SPEED_100K 0x08 93 # define DP_I2C_SPEED_400K 0x10 94 # define DP_I2C_SPEED_1M 0x20 95 96 #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ 97 # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0) 98 # define DP_FRAMING_CHANGE_CAP (1 << 1) 99 # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */ 100 101 #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ 102 103 #define DP_ADAPTER_CAP 0x00f /* 1.2 */ 104 # define DP_FORCE_LOAD_SENSE_CAP (1 << 0) 105 # define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1) 106 107 #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ 108 # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ 109 110 /* Multiple stream transport */ 111 #define DP_FAUX_CAP 0x020 /* 1.2 */ 112 # define DP_FAUX_CAP_1 (1 << 0) 113 114 #define DP_MSTM_CAP 0x021 /* 1.2 */ 115 # define DP_MST_CAP (1 << 0) 116 117 #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */ 118 119 /* AV_SYNC_DATA_BLOCK 1.2 */ 120 #define DP_AV_GRANULARITY 0x023 121 # define DP_AG_FACTOR_MASK (0xf << 0) 122 # define DP_AG_FACTOR_3MS (0 << 0) 123 # define DP_AG_FACTOR_2MS (1 << 0) 124 # define DP_AG_FACTOR_1MS (2 << 0) 125 # define DP_AG_FACTOR_500US (3 << 0) 126 # define DP_AG_FACTOR_200US (4 << 0) 127 # define DP_AG_FACTOR_100US (5 << 0) 128 # define DP_AG_FACTOR_10US (6 << 0) 129 # define DP_AG_FACTOR_1US (7 << 0) 130 # define DP_VG_FACTOR_MASK (0xf << 4) 131 # define DP_VG_FACTOR_3MS (0 << 4) 132 # define DP_VG_FACTOR_2MS (1 << 4) 133 # define DP_VG_FACTOR_1MS (2 << 4) 134 # define DP_VG_FACTOR_500US (3 << 4) 135 # define DP_VG_FACTOR_200US (4 << 4) 136 # define DP_VG_FACTOR_100US (5 << 4) 137 138 #define DP_AUD_DEC_LAT0 0x024 139 #define DP_AUD_DEC_LAT1 0x025 140 141 #define DP_AUD_PP_LAT0 0x026 142 #define DP_AUD_PP_LAT1 0x027 143 144 #define DP_VID_INTER_LAT 0x028 145 146 #define DP_VID_PROG_LAT 0x029 147 148 #define DP_REP_LAT 0x02a 149 150 #define DP_AUD_DEL_INS0 0x02b 151 #define DP_AUD_DEL_INS1 0x02c 152 #define DP_AUD_DEL_INS2 0x02d 153 /* End of AV_SYNC_DATA_BLOCK */ 154 155 #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ 156 # define DP_ALPM_CAP (1 << 0) 157 158 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ 159 # define DP_AUX_FRAME_SYNC_CAP (1 << 0) 160 161 #define DP_GUID 0x030 /* 1.2 */ 162 163 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ 164 # define DP_PSR_IS_SUPPORTED 1 165 # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ 166 167 #define DP_PSR_CAPS 0x071 /* XXX 1.2? */ 168 # define DP_PSR_NO_TRAIN_ON_EXIT 1 169 # define DP_PSR_SETUP_TIME_330 (0 << 1) 170 # define DP_PSR_SETUP_TIME_275 (1 << 1) 171 # define DP_PSR_SETUP_TIME_220 (2 << 1) 172 # define DP_PSR_SETUP_TIME_165 (3 << 1) 173 # define DP_PSR_SETUP_TIME_110 (4 << 1) 174 # define DP_PSR_SETUP_TIME_55 (5 << 1) 175 # define DP_PSR_SETUP_TIME_0 (6 << 1) 176 # define DP_PSR_SETUP_TIME_MASK (7 << 1) 177 # define DP_PSR_SETUP_TIME_SHIFT 1 178 179 /* 180 * 0x80-0x8f describe downstream port capabilities, but there are two layouts 181 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, 182 * each port's descriptor is one byte wide. If it was set, each port's is 183 * four bytes wide, starting with the one byte from the base info. As of 184 * DP interop v1.1a only VGA defines additional detail. 185 */ 186 187 /* offset 0 */ 188 #define DP_DOWNSTREAM_PORT_0 0x80 189 # define DP_DS_PORT_TYPE_MASK (7 << 0) 190 # define DP_DS_PORT_TYPE_DP 0 191 # define DP_DS_PORT_TYPE_VGA 1 192 # define DP_DS_PORT_TYPE_DVI 2 193 # define DP_DS_PORT_TYPE_HDMI 3 194 # define DP_DS_PORT_TYPE_NON_EDID 4 195 # define DP_DS_PORT_HPD (1 << 3) 196 /* offset 1 for VGA is maximum megapixels per second / 8 */ 197 /* offset 2 */ 198 # define DP_DS_VGA_MAX_BPC_MASK (3 << 0) 199 # define DP_DS_VGA_8BPC 0 200 # define DP_DS_VGA_10BPC 1 201 # define DP_DS_VGA_12BPC 2 202 # define DP_DS_VGA_16BPC 3 203 204 /* link configuration */ 205 #define DP_LINK_BW_SET 0x100 206 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ 207 # define DP_LINK_BW_1_62 0x06 208 # define DP_LINK_BW_2_7 0x0a 209 # define DP_LINK_BW_5_4 0x14 /* 1.2 */ 210 211 #define DP_LANE_COUNT_SET 0x101 212 # define DP_LANE_COUNT_MASK 0x0f 213 # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) 214 215 #define DP_TRAINING_PATTERN_SET 0x102 216 # define DP_TRAINING_PATTERN_DISABLE 0 217 # define DP_TRAINING_PATTERN_1 1 218 # define DP_TRAINING_PATTERN_2 2 219 # define DP_TRAINING_PATTERN_3 3 /* 1.2 */ 220 # define DP_TRAINING_PATTERN_MASK 0x3 221 222 /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */ 223 # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2) 224 # define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2) 225 # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2) 226 # define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2) 227 # define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2) 228 229 # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) 230 # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) 231 232 # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) 233 # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) 234 # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) 235 # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) 236 237 #define DP_TRAINING_LANE0_SET 0x103 238 #define DP_TRAINING_LANE1_SET 0x104 239 #define DP_TRAINING_LANE2_SET 0x105 240 #define DP_TRAINING_LANE3_SET 0x106 241 242 # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 243 # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 244 # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) 245 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) 246 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) 247 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) 248 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) 249 250 # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) 251 # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) 252 # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) 253 # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) 254 # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) 255 256 # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 257 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) 258 259 #define DP_DOWNSPREAD_CTRL 0x107 260 # define DP_SPREAD_AMP_0_5 (1 << 4) 261 # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ 262 263 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 264 # define DP_SET_ANSI_8B10B (1 << 0) 265 266 #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ 267 /* bitmask as for DP_I2C_SPEED_CAP */ 268 269 #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ 270 # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0) 271 # define DP_FRAMING_CHANGE_ENABLE (1 << 1) 272 # define DP_PANEL_SELF_TEST_ENABLE (1 << 7) 273 274 #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */ 275 #define DP_LINK_QUAL_LANE1_SET 0x10c 276 #define DP_LINK_QUAL_LANE2_SET 0x10d 277 #define DP_LINK_QUAL_LANE3_SET 0x10e 278 # define DP_LINK_QUAL_PATTERN_DISABLE 0 279 # define DP_LINK_QUAL_PATTERN_D10_2 1 280 # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2 281 # define DP_LINK_QUAL_PATTERN_PRBS7 3 282 # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4 283 # define DP_LINK_QUAL_PATTERN_HBR2_EYE 5 284 # define DP_LINK_QUAL_PATTERN_MASK 7 285 286 #define DP_TRAINING_LANE0_1_SET2 0x10f 287 #define DP_TRAINING_LANE2_3_SET2 0x110 288 # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0) 289 # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2) 290 # define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4) 291 # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6) 292 293 #define DP_MSTM_CTRL 0x111 /* 1.2 */ 294 # define DP_MST_EN (1 << 0) 295 # define DP_UP_REQ_EN (1 << 1) 296 # define DP_UPSTREAM_IS_SRC (1 << 2) 297 298 #define DP_AUDIO_DELAY0 0x112 /* 1.2 */ 299 #define DP_AUDIO_DELAY1 0x113 300 #define DP_AUDIO_DELAY2 0x114 301 302 #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */ 303 # define DP_LINK_RATE_SET_SHIFT 0 304 # define DP_LINK_RATE_SET_MASK (7 << 0) 305 306 #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ 307 # define DP_ALPM_ENABLE (1 << 0) 308 # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) 309 310 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ 311 # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0) 312 # define DP_IRQ_HPD_ENABLE (1 << 1) 313 314 #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */ 315 # define DP_PWR_NOT_NEEDED (1 << 0) 316 317 #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */ 318 # define DP_AUX_FRAME_SYNC_VALID (1 << 0) 319 320 #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ 321 # define DP_PSR_ENABLE (1 << 0) 322 # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) 323 # define DP_PSR_CRC_VERIFICATION (1 << 2) 324 # define DP_PSR_FRAME_CAPTURE (1 << 3) 325 # define DP_PSR_SELECTIVE_UPDATE (1 << 4) 326 # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5) 327 328 #define DP_ADAPTER_CTRL 0x1a0 329 # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) 330 331 #define DP_BRANCH_DEVICE_CTRL 0x1a1 332 # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) 333 334 #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 335 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 336 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 337 338 #define DP_SINK_COUNT 0x200 339 /* prior to 1.2 bit 7 was reserved mbz */ 340 # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) 341 # define DP_SINK_CP_READY (1 << 6) 342 343 #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 344 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) 345 # define DP_AUTOMATED_TEST_REQUEST (1 << 1) 346 # define DP_CP_IRQ (1 << 2) 347 # define DP_MCCS_IRQ (1 << 3) 348 # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ 349 # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ 350 # define DP_SINK_SPECIFIC_IRQ (1 << 6) 351 352 #define DP_LANE0_1_STATUS 0x202 353 #define DP_LANE2_3_STATUS 0x203 354 # define DP_LANE_CR_DONE (1 << 0) 355 # define DP_LANE_CHANNEL_EQ_DONE (1 << 1) 356 # define DP_LANE_SYMBOL_LOCKED (1 << 2) 357 358 #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ 359 DP_LANE_CHANNEL_EQ_DONE | \ 360 DP_LANE_SYMBOL_LOCKED) 361 362 #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 363 364 #define DP_INTERLANE_ALIGN_DONE (1 << 0) 365 #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) 366 #define DP_LINK_STATUS_UPDATED (1 << 7) 367 368 #define DP_SINK_STATUS 0x205 369 370 #define DP_RECEIVE_PORT_0_STATUS (1 << 0) 371 #define DP_RECEIVE_PORT_1_STATUS (1 << 1) 372 373 #define DP_ADJUST_REQUEST_LANE0_1 0x206 374 #define DP_ADJUST_REQUEST_LANE2_3 0x207 375 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 376 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 377 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c 378 # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 379 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 380 # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 381 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 382 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 383 384 #define DP_TEST_REQUEST 0x218 385 # define DP_TEST_LINK_TRAINING (1 << 0) 386 # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) 387 # define DP_TEST_LINK_EDID_READ (1 << 2) 388 # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ 389 # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ 390 391 #define DP_TEST_LINK_RATE 0x219 392 # define DP_LINK_RATE_162 (0x6) 393 # define DP_LINK_RATE_27 (0xa) 394 395 #define DP_TEST_LANE_COUNT 0x220 396 397 #define DP_TEST_PATTERN 0x221 398 399 #define DP_TEST_CRC_R_CR 0x240 400 #define DP_TEST_CRC_G_Y 0x242 401 #define DP_TEST_CRC_B_CB 0x244 402 403 #define DP_TEST_SINK_MISC 0x246 404 # define DP_TEST_CRC_SUPPORTED (1 << 5) 405 # define DP_TEST_COUNT_MASK 0xf 406 407 #define DP_TEST_RESPONSE 0x260 408 # define DP_TEST_ACK (1 << 0) 409 # define DP_TEST_NAK (1 << 1) 410 # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) 411 412 #define DP_TEST_EDID_CHECKSUM 0x261 413 414 #define DP_TEST_SINK 0x270 415 # define DP_TEST_SINK_START (1 << 0) 416 417 #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ 418 # define DP_PAYLOAD_TABLE_UPDATED (1 << 0) 419 # define DP_PAYLOAD_ACT_HANDLED (1 << 1) 420 421 #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ 422 /* up to ID_SLOT_63 at 0x2ff */ 423 424 #define DP_SOURCE_OUI 0x300 425 #define DP_SINK_OUI 0x400 426 #define DP_BRANCH_OUI 0x500 427 428 #define DP_SET_POWER 0x600 429 # define DP_SET_POWER_D0 0x1 430 # define DP_SET_POWER_D3 0x2 431 # define DP_SET_POWER_MASK 0x3 432 433 #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ 434 # define DP_EDP_11 0x00 435 # define DP_EDP_12 0x01 436 # define DP_EDP_13 0x02 437 # define DP_EDP_14 0x03 438 439 #define DP_EDP_GENERAL_CAP_1 0x701 440 441 #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702 442 443 #define DP_EDP_GENERAL_CAP_2 0x703 444 445 #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */ 446 447 #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720 448 449 #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721 450 451 #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722 452 #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723 453 454 #define DP_EDP_PWMGEN_BIT_COUNT 0x724 455 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725 456 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726 457 458 #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727 459 460 #define DP_EDP_BACKLIGHT_FREQ_SET 0x728 461 462 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a 463 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b 464 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c 465 466 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d 467 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e 468 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f 469 470 #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732 471 #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733 472 473 #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */ 474 #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */ 475 476 #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ 477 #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ 478 #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ 479 #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ 480 481 #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */ 482 /* 0-5 sink count */ 483 # define DP_SINK_COUNT_CP_READY (1 << 6) 484 485 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */ 486 487 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ 488 489 #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ 490 491 #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ 492 # define DP_PSR_LINK_CRC_ERROR (1 << 0) 493 # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) 494 # define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */ 495 496 #define DP_PSR_ESI 0x2007 /* XXX 1.2? */ 497 # define DP_PSR_CAPS_CHANGE (1 << 0) 498 499 #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ 500 # define DP_PSR_SINK_INACTIVE 0 501 # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 502 # define DP_PSR_SINK_ACTIVE_RFB 2 503 # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 504 # define DP_PSR_SINK_ACTIVE_RESYNC 4 505 # define DP_PSR_SINK_INTERNAL_ERROR 7 506 # define DP_PSR_SINK_STATE_MASK 0x07 507 508 #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ 509 # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0) 510 511 /* DP 1.2 Sideband message defines */ 512 /* peer device type - DP 1.2a Table 2-92 */ 513 #define DP_PEER_DEVICE_NONE 0x0 514 #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 515 #define DP_PEER_DEVICE_MST_BRANCHING 0x2 516 #define DP_PEER_DEVICE_SST_SINK 0x3 517 #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 518 519 /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ 520 #define DP_LINK_ADDRESS 0x01 521 #define DP_CONNECTION_STATUS_NOTIFY 0x02 522 #define DP_ENUM_PATH_RESOURCES 0x10 523 #define DP_ALLOCATE_PAYLOAD 0x11 524 #define DP_QUERY_PAYLOAD 0x12 525 #define DP_RESOURCE_STATUS_NOTIFY 0x13 526 #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 527 #define DP_REMOTE_DPCD_READ 0x20 528 #define DP_REMOTE_DPCD_WRITE 0x21 529 #define DP_REMOTE_I2C_READ 0x22 530 #define DP_REMOTE_I2C_WRITE 0x23 531 #define DP_POWER_UP_PHY 0x24 532 #define DP_POWER_DOWN_PHY 0x25 533 #define DP_SINK_EVENT_NOTIFY 0x30 534 #define DP_QUERY_STREAM_ENC_STATUS 0x38 535 536 /* DP 1.2 MST sideband nak reasons - table 2.84 */ 537 #define DP_NAK_WRITE_FAILURE 0x01 538 #define DP_NAK_INVALID_READ 0x02 539 #define DP_NAK_CRC_FAILURE 0x03 540 #define DP_NAK_BAD_PARAM 0x04 541 #define DP_NAK_DEFER 0x05 542 #define DP_NAK_LINK_FAILURE 0x06 543 #define DP_NAK_NO_RESOURCES 0x07 544 #define DP_NAK_DPCD_FAIL 0x08 545 #define DP_NAK_I2C_NAK 0x09 546 #define DP_NAK_ALLOCATE_FAIL 0x0a 547 548 #define ANALOGIX_DP_TX_SW_RESET 0x14 549 #define ANALOGIX_DP_FUNC_EN_1 0x18 550 #define ANALOGIX_DP_FUNC_EN_2 0x1C 551 #define ANALOGIX_DP_VIDEO_CTL_1 0x20 552 #define ANALOGIX_DP_VIDEO_CTL_2 0x24 553 #define ANALOGIX_DP_VIDEO_CTL_3 0x28 554 555 #define ANALOGIX_DP_VIDEO_CTL_8 0x3C 556 #define ANALOGIX_DP_VIDEO_CTL_10 0x44 557 558 #define ANALOGIX_DP_PLL_REG_1 0xfc 559 #define ANALOGIX_DP_PLL_REG_2 0x9e4 560 #define ANALOGIX_DP_PLL_REG_3 0x9e8 561 #define ANALOGIX_DP_PLL_REG_4 0x9ec 562 #define ANALOGIX_DP_PLL_REG_5 0xa00 563 564 #define ANALOGIX_DP_PD 0x12c 565 566 #define ANALOGIX_DP_LANE_MAP 0x35C 567 568 #define ANALOGIX_DP_ANALOG_CTL_1 0x370 569 #define ANALOGIX_DP_ANALOG_CTL_2 0x374 570 #define ANALOGIX_DP_ANALOG_CTL_3 0x378 571 #define ANALOGIX_DP_PLL_FILTER_CTL_1 0x37C 572 #define ANALOGIX_DP_TX_AMP_TUNING_CTL 0x380 573 574 #define ANALOGIX_DP_AUX_HW_RETRY_CTL 0x390 575 576 #define ANALOGIX_DP_COMMON_INT_STA_1 0x3C4 577 #define ANALOGIX_DP_COMMON_INT_STA_2 0x3C8 578 #define ANALOGIX_DP_COMMON_INT_STA_3 0x3CC 579 #define ANALOGIX_DP_COMMON_INT_STA_4 0x3D0 580 #define ANALOGIX_DP_INT_STA 0x3DC 581 #define ANALOGIX_DP_COMMON_INT_MASK_1 0x3E0 582 #define ANALOGIX_DP_COMMON_INT_MASK_2 0x3E4 583 #define ANALOGIX_DP_COMMON_INT_MASK_3 0x3E8 584 #define ANALOGIX_DP_COMMON_INT_MASK_4 0x3EC 585 #define ANALOGIX_DP_INT_STA_MASK 0x3F8 586 #define ANALOGIX_DP_INT_CTL 0x3FC 587 588 #define ANALOGIX_DP_SYS_CTL_1 0x600 589 #define ANALOGIX_DP_SYS_CTL_2 0x604 590 #define ANALOGIX_DP_SYS_CTL_3 0x608 591 #define ANALOGIX_DP_SYS_CTL_4 0x60C 592 593 #define ANALOGIX_DP_PKT_SEND_CTL 0x640 594 #define ANALOGIX_DP_HDCP_CTL 0x648 595 596 #define ANALOGIX_DP_LINK_BW_SET 0x680 597 #define ANALOGIX_DP_LANE_COUNT_SET 0x684 598 #define ANALOGIX_DP_TRAINING_PTN_SET 0x688 599 #define ANALOGIX_DP_LN0_LINK_TRAINING_CTL 0x68C 600 #define ANALOGIX_DP_LN1_LINK_TRAINING_CTL 0x690 601 #define ANALOGIX_DP_LN2_LINK_TRAINING_CTL 0x694 602 #define ANALOGIX_DP_LN3_LINK_TRAINING_CTL 0x698 603 604 #define ANALOGIX_DP_DEBUG_CTL 0x6C0 605 #define ANALOGIX_DP_HPD_DEGLITCH_L 0x6C4 606 #define ANALOGIX_DP_HPD_DEGLITCH_H 0x6C8 607 #define ANALOGIX_DP_LINK_DEBUG_CTL 0x6E0 608 609 #define ANALOGIX_DP_M_VID_0 0x700 610 #define ANALOGIX_DP_M_VID_1 0x704 611 #define ANALOGIX_DP_M_VID_2 0x708 612 #define ANALOGIX_DP_N_VID_0 0x70C 613 #define ANALOGIX_DP_N_VID_1 0x710 614 #define ANALOGIX_DP_N_VID_2 0x714 615 616 #define ANALOGIX_DP_PLL_CTL 0x71C 617 #define ANALOGIX_DP_PHY_PD 0x720 618 #define ANALOGIX_DP_PHY_TEST 0x724 619 620 #define ANALOGIX_DP_VIDEO_FIFO_THRD 0x730 621 #define ANALOGIX_DP_AUDIO_MARGIN 0x73C 622 623 #define ANALOGIX_DP_M_VID_GEN_FILTER_TH 0x764 624 #define ANALOGIX_DP_M_AUD_GEN_FILTER_TH 0x778 625 #define ANALOGIX_DP_AUX_CH_STA 0x780 626 #define ANALOGIX_DP_AUX_CH_DEFER_CTL 0x788 627 #define ANALOGIX_DP_AUX_RX_COMM 0x78C 628 #define ANALOGIX_DP_BUFFER_DATA_CTL 0x790 629 #define ANALOGIX_DP_AUX_CH_CTL_1 0x794 630 #define ANALOGIX_DP_AUX_ADDR_7_0 0x798 631 #define ANALOGIX_DP_AUX_ADDR_15_8 0x79C 632 #define ANALOGIX_DP_AUX_ADDR_19_16 0x7A0 633 #define ANALOGIX_DP_AUX_CH_CTL_2 0x7A4 634 635 #define ANALOGIX_DP_BUF_DATA_0 0x7C0 636 637 #define ANALOGIX_DP_SOC_GENERAL_CTL 0x800 638 639 /* ANALOGIX_DP_TX_SW_RESET */ 640 #define RESET_DP_TX (0x1 << 0) 641 642 /* ANALOGIX_DP_FUNC_EN_1 */ 643 #define MASTER_VID_FUNC_EN_N (0x1 << 7) 644 #define SLAVE_VID_FUNC_EN_N (0x1 << 5) 645 #define AUD_FIFO_FUNC_EN_N (0x1 << 4) 646 #define AUD_FUNC_EN_N (0x1 << 3) 647 #define HDCP_FUNC_EN_N (0x1 << 2) 648 #define CRC_FUNC_EN_N (0x1 << 1) 649 #define SW_FUNC_EN_N (0x1 << 0) 650 651 /* ANALOGIX_DP_FUNC_EN_2 */ 652 #define SSC_FUNC_EN_N (0x1 << 7) 653 #define AUX_FUNC_EN_N (0x1 << 2) 654 #define SERDES_FIFO_FUNC_EN_N (0x1 << 1) 655 #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) 656 657 /* ANALOGIX_DP_VIDEO_CTL_1 */ 658 #define VIDEO_EN (0x1 << 7) 659 #define HDCP_VIDEO_MUTE (0x1 << 6) 660 661 /* ANALOGIX_DP_VIDEO_CTL_1 */ 662 #define IN_D_RANGE_MASK (0x1 << 7) 663 #define IN_D_RANGE_SHIFT (7) 664 #define IN_D_RANGE_CEA (0x1 << 7) 665 #define IN_D_RANGE_VESA (0x0 << 7) 666 #define IN_BPC_MASK (0x7 << 4) 667 #define IN_BPC_SHIFT (4) 668 #define IN_BPC_12_BITS (0x3 << 4) 669 #define IN_BPC_10_BITS (0x2 << 4) 670 #define IN_BPC_8_BITS (0x1 << 4) 671 #define IN_BPC_6_BITS (0x0 << 4) 672 #define IN_COLOR_F_MASK (0x3 << 0) 673 #define IN_COLOR_F_SHIFT (0) 674 #define IN_COLOR_F_YCBCR444 (0x2 << 0) 675 #define IN_COLOR_F_YCBCR422 (0x1 << 0) 676 #define IN_COLOR_F_RGB (0x0 << 0) 677 678 /* ANALOGIX_DP_VIDEO_CTL_3 */ 679 #define IN_YC_COEFFI_MASK (0x1 << 7) 680 #define IN_YC_COEFFI_SHIFT (7) 681 #define IN_YC_COEFFI_ITU709 (0x1 << 7) 682 #define IN_YC_COEFFI_ITU601 (0x0 << 7) 683 #define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) 684 #define VID_CHK_UPDATE_TYPE_SHIFT (4) 685 #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) 686 #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) 687 688 /* ANALOGIX_DP_VIDEO_CTL_8 */ 689 #define VID_HRES_TH(x) (((x) & 0xf) << 4) 690 #define VID_VRES_TH(x) (((x) & 0xf) << 0) 691 692 /* ANALOGIX_DP_VIDEO_CTL_10 */ 693 #define FORMAT_SEL (0x1 << 4) 694 #define INTERACE_SCAN_CFG (0x1 << 2) 695 #define VSYNC_POLARITY_CFG (0x1 << 1) 696 #define HSYNC_POLARITY_CFG (0x1 << 0) 697 698 /* ANALOGIX_DP_PLL_REG_1 */ 699 #define REF_CLK_24M (0x1 << 0) 700 #define REF_CLK_27M (0x0 << 0) 701 #define REF_CLK_MASK (0x1 << 0) 702 703 /* ANALOGIX_DP_LANE_MAP */ 704 #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) 705 #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) 706 #define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6) 707 #define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6) 708 #define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4) 709 #define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4) 710 #define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4) 711 #define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4) 712 #define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2) 713 #define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2) 714 #define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2) 715 #define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2) 716 #define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0) 717 #define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0) 718 #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) 719 #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) 720 721 /* ANALOGIX_DP_ANALOG_CTL_1 */ 722 #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) 723 724 /* ANALOGIX_DP_ANALOG_CTL_2 */ 725 #define SEL_24M (0x1 << 3) 726 #define TX_DVDD_BIT_1_0625V (0x4 << 0) 727 728 /* ANALOGIX_DP_ANALOG_CTL_3 */ 729 #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) 730 #define VCO_BIT_600_MICRO (0x5 << 0) 731 732 /* ANALOGIX_DP_PLL_FILTER_CTL_1 */ 733 #define PD_RING_OSC (0x1 << 6) 734 #define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) 735 #define TX_CUR1_2X (0x1 << 2) 736 #define TX_CUR_16_MA (0x3 << 0) 737 738 /* ANALOGIX_DP_TX_AMP_TUNING_CTL */ 739 #define CH3_AMP_400_MV (0x0 << 24) 740 #define CH2_AMP_400_MV (0x0 << 16) 741 #define CH1_AMP_400_MV (0x0 << 8) 742 #define CH0_AMP_400_MV (0x0 << 0) 743 744 /* ANALOGIX_DP_AUX_HW_RETRY_CTL */ 745 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) 746 #define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) 747 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) 748 #define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3) 749 #define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3) 750 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) 751 #define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0) 752 753 /* ANALOGIX_DP_COMMON_INT_STA_1 */ 754 #define VSYNC_DET (0x1 << 7) 755 #define PLL_LOCK_CHG (0x1 << 6) 756 #define SPDIF_ERR (0x1 << 5) 757 #define SPDIF_UNSTBL (0x1 << 4) 758 #define VID_FORMAT_CHG (0x1 << 3) 759 #define AUD_CLK_CHG (0x1 << 2) 760 #define VID_CLK_CHG (0x1 << 1) 761 #define SW_INT (0x1 << 0) 762 763 /* ANALOGIX_DP_COMMON_INT_STA_2 */ 764 #define ENC_EN_CHG (0x1 << 6) 765 #define HW_BKSV_RDY (0x1 << 3) 766 #define HW_SHA_DONE (0x1 << 2) 767 #define HW_AUTH_STATE_CHG (0x1 << 1) 768 #define HW_AUTH_DONE (0x1 << 0) 769 770 /* ANALOGIX_DP_COMMON_INT_STA_3 */ 771 #define AFIFO_UNDER (0x1 << 7) 772 #define AFIFO_OVER (0x1 << 6) 773 #define R0_CHK_FLAG (0x1 << 5) 774 775 /* ANALOGIX_DP_COMMON_INT_STA_4 */ 776 #define PSR_ACTIVE (0x1 << 7) 777 #define PSR_INACTIVE (0x1 << 6) 778 #define SPDIF_BI_PHASE_ERR (0x1 << 5) 779 #define HOTPLUG_CHG (0x1 << 2) 780 #define HPD_LOST (0x1 << 1) 781 #define PLUG (0x1 << 0) 782 783 /* ANALOGIX_DP_INT_STA */ 784 #define INT_HPD (0x1 << 6) 785 #define HW_TRAINING_FINISH (0x1 << 5) 786 #define RPLY_RECEIV (0x1 << 1) 787 #define AUX_ERR (0x1 << 0) 788 789 /* ANALOGIX_DP_INT_CTL */ 790 #define SOFT_INT_CTRL (0x1 << 2) 791 #define INT_POL1 (0x1 << 1) 792 #define INT_POL0 (0x1 << 0) 793 794 /* ANALOGIX_DP_SYS_CTL_1 */ 795 #define DET_STA (0x1 << 2) 796 #define FORCE_DET (0x1 << 1) 797 #define DET_CTRL (0x1 << 0) 798 799 /* ANALOGIX_DP_SYS_CTL_2 */ 800 #define CHA_CRI(x) (((x) & 0xf) << 4) 801 #define CHA_STA (0x1 << 2) 802 #define FORCE_CHA (0x1 << 1) 803 #define CHA_CTRL (0x1 << 0) 804 805 /* ANALOGIX_DP_SYS_CTL_3 */ 806 #define HPD_STATUS (0x1 << 6) 807 #define F_HPD (0x1 << 5) 808 #define HPD_CTRL (0x1 << 4) 809 #define HDCP_RDY (0x1 << 3) 810 #define STRM_VALID (0x1 << 2) 811 #define F_VALID (0x1 << 1) 812 #define VALID_CTRL (0x1 << 0) 813 814 /* ANALOGIX_DP_SYS_CTL_4 */ 815 #define FIX_M_AUD (0x1 << 4) 816 #define ENHANCED (0x1 << 3) 817 #define FIX_M_VID (0x1 << 2) 818 #define M_VID_UPDATE_CTRL (0x3 << 0) 819 820 /* ANALOGIX_DP_TRAINING_PTN_SET */ 821 #define SCRAMBLER_TYPE (0x1 << 9) 822 #define HW_LINK_TRAINING_PATTERN (0x1 << 8) 823 #define SCRAMBLING_DISABLE (0x1 << 5) 824 #define SCRAMBLING_ENABLE (0x0 << 5) 825 #define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2) 826 #define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) 827 #define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) 828 #define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) 829 #define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) 830 #define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) 831 #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) 832 #define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) 833 834 /* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */ 835 #define PRE_EMPHASIS_SET_MASK (0x3 << 3) 836 #define PRE_EMPHASIS_SET_SHIFT (3) 837 838 /* ANALOGIX_DP_DEBUG_CTL */ 839 #define PLL_LOCK (0x1 << 4) 840 #define F_PLL_LOCK (0x1 << 3) 841 #define PLL_LOCK_CTRL (0x1 << 2) 842 #define PN_INV (0x1 << 0) 843 844 /* ANALOGIX_DP_PLL_CTL */ 845 #define DP_PLL_PD (0x1 << 7) 846 #define DP_PLL_RESET (0x1 << 6) 847 #define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) 848 #define DP_PLL_REF_BIT_1_1250V (0x5 << 0) 849 #define DP_PLL_REF_BIT_1_2500V (0x7 << 0) 850 851 /* ANALOGIX_DP_PHY_PD */ 852 #define DP_PHY_PD (0x1 << 5) 853 #define AUX_PD (0x1 << 4) 854 #define CH3_PD (0x1 << 3) 855 #define CH2_PD (0x1 << 2) 856 #define CH1_PD (0x1 << 1) 857 #define CH0_PD (0x1 << 0) 858 859 /* ANALOGIX_DP_PHY_TEST */ 860 #define MACRO_RST (0x1 << 5) 861 #define CH1_TEST (0x1 << 1) 862 #define CH0_TEST (0x1 << 0) 863 864 /* ANALOGIX_DP_AUX_CH_STA */ 865 #define AUX_BUSY (0x1 << 4) 866 #define AUX_STATUS_MASK (0xf << 0) 867 868 /* ANALOGIX_DP_AUX_CH_DEFER_CTL */ 869 #define DEFER_CTRL_EN (0x1 << 7) 870 #define DEFER_COUNT(x) (((x) & 0x7f) << 0) 871 872 /* ANALOGIX_DP_AUX_RX_COMM */ 873 #define AUX_RX_COMM_I2C_DEFER (0x2 << 2) 874 #define AUX_RX_COMM_AUX_DEFER (0x2 << 0) 875 876 /* ANALOGIX_DP_BUFFER_DATA_CTL */ 877 #define BUF_CLR (0x1 << 7) 878 #define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0) 879 880 /* ANALOGIX_DP_AUX_CH_CTL_1 */ 881 #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) 882 #define AUX_TX_COMM_MASK (0xf << 0) 883 #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) 884 #define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) 885 #define AUX_TX_COMM_MOT (0x1 << 2) 886 #define AUX_TX_COMM_WRITE (0x0 << 0) 887 #define AUX_TX_COMM_READ (0x1 << 0) 888 889 /* ANALOGIX_DP_AUX_ADDR_7_0 */ 890 #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) 891 892 /* ANALOGIX_DP_AUX_ADDR_15_8 */ 893 #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) 894 895 /* ANALOGIX_DP_AUX_ADDR_19_16 */ 896 #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) 897 898 /* ANALOGIX_DP_AUX_CH_CTL_2 */ 899 #define ADDR_ONLY (0x1 << 1) 900 #define AUX_EN (0x1 << 0) 901 902 /* ANALOGIX_DP_SOC_GENERAL_CTL */ 903 #define AUDIO_MODE_SPDIF_MODE (0x1 << 8) 904 #define AUDIO_MODE_MASTER_MODE (0x0 << 8) 905 #define MASTER_VIDEO_INTERLACE_EN (0x1 << 4) 906 #define VIDEO_MASTER_CLK_SEL (0x1 << 2) 907 #define VIDEO_MASTER_MODE_EN (0x1 << 1) 908 #define VIDEO_MODE_MASK (0x1 << 0) 909 #define VIDEO_MODE_SLAVE_MODE (0x1 << 0) 910 #define VIDEO_MODE_MASTER_MODE (0x0 << 0) 911 912 #define DP_TIMEOUT_LOOP_COUNT 100 913 #define MAX_CR_LOOP 5 914 #define MAX_EQ_LOOP 5 915 916 /* I2C EDID Chip ID, Slave Address */ 917 #define I2C_EDID_DEVICE_ADDR 0x50 918 #define I2C_E_EDID_DEVICE_ADDR 0x30 919 920 #define EDID_BLOCK_LENGTH 0x80 921 #define EDID_HEADER_PATTERN 0x00 922 #define EDID_EXTENSION_FLAG 0x7e 923 #define EDID_CHECKSUM 0x7f 924 925 /* DP_MAX_LANE_COUNT */ 926 #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1) 927 #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f) 928 929 /* DP_LANE_COUNT_SET */ 930 #define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f) 931 932 /* DP_TRAINING_LANE0_SET */ 933 #define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3) 934 #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3) 935 #define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0) 936 #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3) 937 938 enum link_lane_count_type { 939 LANE_COUNT1 = 1, 940 LANE_COUNT2 = 2, 941 LANE_COUNT4 = 4 942 }; 943 944 enum link_training_state { 945 START, 946 CLOCK_RECOVERY, 947 EQUALIZER_TRAINING, 948 FINISHED, 949 FAILED 950 }; 951 952 enum voltage_swing_level { 953 VOLTAGE_LEVEL_0, 954 VOLTAGE_LEVEL_1, 955 VOLTAGE_LEVEL_2, 956 VOLTAGE_LEVEL_3, 957 }; 958 959 enum pre_emphasis_level { 960 PRE_EMPHASIS_LEVEL_0, 961 PRE_EMPHASIS_LEVEL_1, 962 PRE_EMPHASIS_LEVEL_2, 963 PRE_EMPHASIS_LEVEL_3, 964 }; 965 966 enum pattern_set { 967 PRBS7, 968 D10_2, 969 TRAINING_PTN1, 970 TRAINING_PTN2, 971 DP_NONE 972 }; 973 974 enum color_space { 975 COLOR_RGB, 976 COLOR_YCBCR422, 977 COLOR_YCBCR444 978 }; 979 980 enum color_depth { 981 COLOR_6, 982 COLOR_8, 983 COLOR_10, 984 COLOR_12 985 }; 986 987 enum color_coefficient { 988 COLOR_YCBCR601, 989 COLOR_YCBCR709 990 }; 991 992 enum dynamic_range { 993 VESA, 994 CEA 995 }; 996 997 enum pll_status { 998 PLL_UNLOCKED, 999 PLL_LOCKED 1000 }; 1001 1002 enum clock_recovery_m_value_type { 1003 CALCULATED_M, 1004 REGISTER_M 1005 }; 1006 1007 enum video_timing_recognition_type { 1008 VIDEO_TIMING_FROM_CAPTURE, 1009 VIDEO_TIMING_FROM_REGISTER 1010 }; 1011 1012 enum analog_power_block { 1013 AUX_BLOCK, 1014 CH0_BLOCK, 1015 CH1_BLOCK, 1016 CH2_BLOCK, 1017 CH3_BLOCK, 1018 ANALOG_TOTAL, 1019 POWER_ALL 1020 }; 1021 1022 enum dp_irq_type { 1023 DP_IRQ_TYPE_HP_CABLE_IN = BIT(0), 1024 DP_IRQ_TYPE_HP_CABLE_OUT = BIT(1), 1025 DP_IRQ_TYPE_HP_CHANGE = BIT(2), 1026 DP_IRQ_TYPE_UNKNOWN = BIT(3), 1027 }; 1028 1029 struct video_info { 1030 char *name; 1031 1032 bool h_sync_polarity; 1033 bool v_sync_polarity; 1034 bool interlaced; 1035 1036 enum color_space color_space; 1037 enum dynamic_range dynamic_range; 1038 enum color_coefficient ycbcr_coeff; 1039 enum color_depth color_depth; 1040 1041 int max_link_rate; 1042 enum link_lane_count_type max_lane_count; 1043 }; 1044 1045 struct link_train { 1046 int eq_loop; 1047 int cr_loop[4]; 1048 1049 u8 link_rate; 1050 u8 lane_count; 1051 u8 training_lane[4]; 1052 1053 enum link_training_state lt_state; 1054 }; 1055 1056 enum analogix_dp_devtype { 1057 EXYNOS_DP, 1058 ROCKCHIP_DP, 1059 }; 1060 1061 enum analogix_dp_sub_devtype { 1062 RK3288_DP, 1063 RK3368_EDP, 1064 RK3399_EDP, 1065 }; 1066 1067 struct analogix_dp_plat_data { 1068 enum analogix_dp_devtype dev_type; 1069 enum analogix_dp_sub_devtype subdev_type; 1070 }; 1071 1072 struct analogix_dp_device { 1073 struct udevice *dev; 1074 void *reg_base; 1075 void *grf; 1076 struct reset_ctl reset; 1077 struct gpio_desc hpd_gpio; 1078 struct video_info video_info; 1079 struct link_train link_train; 1080 struct drm_display_mode *mode; 1081 struct analogix_dp_plat_data plat_data; 1082 unsigned char edid[EDID_BLOCK_LENGTH * 2]; 1083 }; 1084 1085 /* analogix_dp_reg.c */ 1086 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable); 1087 void analogix_dp_stop_video(struct analogix_dp_device *dp); 1088 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable); 1089 void analogix_dp_init_analog_param(struct analogix_dp_device *dp); 1090 void analogix_dp_init_interrupt(struct analogix_dp_device *dp); 1091 void analogix_dp_reset(struct analogix_dp_device *dp); 1092 void analogix_dp_swreset(struct analogix_dp_device *dp); 1093 void analogix_dp_config_interrupt(struct analogix_dp_device *dp); 1094 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp); 1095 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp); 1096 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp); 1097 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable); 1098 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 1099 enum analog_power_block block, 1100 bool enable); 1101 void analogix_dp_init_analog_func(struct analogix_dp_device *dp); 1102 void analogix_dp_init_hpd(struct analogix_dp_device *dp); 1103 void analogix_dp_force_hpd(struct analogix_dp_device *dp); 1104 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp); 1105 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp); 1106 void analogix_dp_reset_aux(struct analogix_dp_device *dp); 1107 void analogix_dp_init_aux(struct analogix_dp_device *dp); 1108 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp); 1109 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp); 1110 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp); 1111 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp, 1112 unsigned int reg_addr, 1113 unsigned char data); 1114 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp, 1115 unsigned int reg_addr, 1116 unsigned char *data); 1117 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp, 1118 unsigned int reg_addr, 1119 unsigned int count, 1120 unsigned char data[]); 1121 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp, 1122 unsigned int reg_addr, 1123 unsigned int count, 1124 unsigned char data[]); 1125 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp, 1126 unsigned int device_addr, 1127 unsigned int reg_addr); 1128 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp, 1129 unsigned int device_addr, 1130 unsigned int reg_addr, 1131 unsigned int *data); 1132 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp, 1133 unsigned int device_addr, 1134 unsigned int reg_addr, 1135 unsigned int count, 1136 unsigned char edid[]); 1137 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype); 1138 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype); 1139 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count); 1140 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count); 1141 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, 1142 bool enable); 1143 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, 1144 enum pattern_set pattern); 1145 void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, 1146 u32 level); 1147 void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, 1148 u32 level); 1149 void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, 1150 u32 level); 1151 void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, 1152 u32 level); 1153 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp, 1154 u32 training_lane); 1155 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp, 1156 u32 training_lane); 1157 void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp, 1158 u32 training_lane); 1159 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp, 1160 u32 training_lane); 1161 u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp); 1162 u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp); 1163 u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp); 1164 u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp); 1165 void analogix_dp_reset_macro(struct analogix_dp_device *dp); 1166 void analogix_dp_init_video(struct analogix_dp_device *dp); 1167 1168 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp); 1169 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp); 1170 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, 1171 enum clock_recovery_m_value_type type, 1172 u32 m_value, 1173 u32 n_value); 1174 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type); 1175 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, 1176 bool enable); 1177 void analogix_dp_start_video(struct analogix_dp_device *dp); 1178 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp); 1179 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp); 1180 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp); 1181 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp); 1182 1183 #endif /* __DRM_ANALOGIX_DP__ */ 1184