1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __DRM_ANALOGIX_DP_H__ 8 #define __DRM_ANALOGIX_DP_H__ 9 10 #include <generic-phy.h> 11 #include <regmap.h> 12 #include <reset.h> 13 14 #include <drm/drm_dp_helper.h> 15 16 #define ANALOGIX_DP_TX_SW_RESET 0x14 17 #define ANALOGIX_DP_FUNC_EN_1 0x18 18 #define ANALOGIX_DP_FUNC_EN_2 0x1C 19 #define ANALOGIX_DP_VIDEO_CTL_1 0x20 20 #define ANALOGIX_DP_VIDEO_CTL_2 0x24 21 #define ANALOGIX_DP_VIDEO_CTL_3 0x28 22 23 #define ANALOGIX_DP_VIDEO_CTL_8 0x3C 24 #define ANALOGIX_DP_VIDEO_CTL_10 0x44 25 26 #define ANALOGIX_DP_PLL_REG_1 0xfc 27 #define ANALOGIX_DP_PLL_REG_2 0x9e4 28 #define ANALOGIX_DP_PLL_REG_3 0x9e8 29 #define ANALOGIX_DP_PLL_REG_4 0x9ec 30 #define ANALOGIX_DP_PLL_REG_5 0xa00 31 32 #define ANALOGIX_DP_BIAS 0x124 33 #define ANALOGIX_DP_PD 0x12c 34 35 #define ANALOGIX_DP_LANE_MAP 0x35C 36 37 #define ANALOGIX_DP_ANALOG_CTL_1 0x370 38 #define ANALOGIX_DP_ANALOG_CTL_2 0x374 39 #define ANALOGIX_DP_ANALOG_CTL_3 0x378 40 #define ANALOGIX_DP_PLL_FILTER_CTL_1 0x37C 41 #define ANALOGIX_DP_TX_AMP_TUNING_CTL 0x380 42 43 #define ANALOGIX_DP_AUX_HW_RETRY_CTL 0x390 44 45 #define ANALOGIX_DP_COMMON_INT_STA_1 0x3C4 46 #define ANALOGIX_DP_COMMON_INT_STA_2 0x3C8 47 #define ANALOGIX_DP_COMMON_INT_STA_3 0x3CC 48 #define ANALOGIX_DP_COMMON_INT_STA_4 0x3D0 49 #define ANALOGIX_DP_INT_STA 0x3DC 50 #define ANALOGIX_DP_COMMON_INT_MASK_1 0x3E0 51 #define ANALOGIX_DP_COMMON_INT_MASK_2 0x3E4 52 #define ANALOGIX_DP_COMMON_INT_MASK_3 0x3E8 53 #define ANALOGIX_DP_COMMON_INT_MASK_4 0x3EC 54 #define ANALOGIX_DP_INT_STA_MASK 0x3F8 55 #define ANALOGIX_DP_INT_CTL 0x3FC 56 57 #define ANALOGIX_DP_SYS_CTL_1 0x600 58 #define ANALOGIX_DP_SYS_CTL_2 0x604 59 #define ANALOGIX_DP_SYS_CTL_3 0x608 60 #define ANALOGIX_DP_SYS_CTL_4 0x60C 61 62 #define ANALOGIX_DP_PKT_SEND_CTL 0x640 63 #define ANALOGIX_DP_HDCP_CTL 0x648 64 65 #define ANALOGIX_DP_LINK_BW_SET 0x680 66 #define ANALOGIX_DP_LANE_COUNT_SET 0x684 67 #define ANALOGIX_DP_TRAINING_PTN_SET 0x688 68 #define ANALOGIX_DP_LN0_LINK_TRAINING_CTL 0x68C 69 #define ANALOGIX_DP_LN1_LINK_TRAINING_CTL 0x690 70 #define ANALOGIX_DP_LN2_LINK_TRAINING_CTL 0x694 71 #define ANALOGIX_DP_LN3_LINK_TRAINING_CTL 0x698 72 73 #define ANALOGIX_DP_DEBUG_CTL 0x6C0 74 #define ANALOGIX_DP_HPD_DEGLITCH_L 0x6C4 75 #define ANALOGIX_DP_HPD_DEGLITCH_H 0x6C8 76 #define ANALOGIX_DP_LINK_DEBUG_CTL 0x6E0 77 78 #define ANALOGIX_DP_M_VID_0 0x700 79 #define ANALOGIX_DP_M_VID_1 0x704 80 #define ANALOGIX_DP_M_VID_2 0x708 81 #define ANALOGIX_DP_N_VID_0 0x70C 82 #define ANALOGIX_DP_N_VID_1 0x710 83 #define ANALOGIX_DP_N_VID_2 0x714 84 85 #define ANALOGIX_DP_PLL_CTL 0x71C 86 #define ANALOGIX_DP_PHY_PD 0x720 87 #define ANALOGIX_DP_PHY_TEST 0x724 88 89 #define ANALOGIX_DP_VIDEO_FIFO_THRD 0x730 90 #define ANALOGIX_DP_AUDIO_MARGIN 0x73C 91 92 #define ANALOGIX_DP_M_VID_GEN_FILTER_TH 0x764 93 #define ANALOGIX_DP_M_AUD_GEN_FILTER_TH 0x778 94 #define ANALOGIX_DP_AUX_CH_STA 0x780 95 #define ANALOGIX_DP_AUX_CH_DEFER_CTL 0x788 96 #define ANALOGIX_DP_AUX_RX_COMM 0x78C 97 #define ANALOGIX_DP_BUFFER_DATA_CTL 0x790 98 #define ANALOGIX_DP_AUX_CH_CTL_1 0x794 99 #define ANALOGIX_DP_AUX_ADDR_7_0 0x798 100 #define ANALOGIX_DP_AUX_ADDR_15_8 0x79C 101 #define ANALOGIX_DP_AUX_ADDR_19_16 0x7A0 102 #define ANALOGIX_DP_AUX_CH_CTL_2 0x7A4 103 104 #define ANALOGIX_DP_BUF_DATA_0 0x7C0 105 106 #define ANALOGIX_DP_SOC_GENERAL_CTL 0x800 107 108 /* ANALOGIX_DP_TX_SW_RESET */ 109 #define RESET_DP_TX (0x1 << 0) 110 111 /* ANALOGIX_DP_FUNC_EN_1 */ 112 #define MASTER_VID_FUNC_EN_N (0x1 << 7) 113 #define SLAVE_VID_FUNC_EN_N (0x1 << 5) 114 #define AUD_FIFO_FUNC_EN_N (0x1 << 4) 115 #define AUD_FUNC_EN_N (0x1 << 3) 116 #define HDCP_FUNC_EN_N (0x1 << 2) 117 #define CRC_FUNC_EN_N (0x1 << 1) 118 #define SW_FUNC_EN_N (0x1 << 0) 119 120 /* ANALOGIX_DP_FUNC_EN_2 */ 121 #define SSC_FUNC_EN_N (0x1 << 7) 122 #define AUX_FUNC_EN_N (0x1 << 2) 123 #define SERDES_FIFO_FUNC_EN_N (0x1 << 1) 124 #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) 125 126 /* ANALOGIX_DP_VIDEO_CTL_1 */ 127 #define VIDEO_EN (0x1 << 7) 128 #define HDCP_VIDEO_MUTE (0x1 << 6) 129 130 /* ANALOGIX_DP_VIDEO_CTL_1 */ 131 #define IN_D_RANGE_MASK (0x1 << 7) 132 #define IN_D_RANGE_SHIFT (7) 133 #define IN_D_RANGE_CEA (0x1 << 7) 134 #define IN_D_RANGE_VESA (0x0 << 7) 135 #define IN_BPC_MASK (0x7 << 4) 136 #define IN_BPC_SHIFT (4) 137 #define IN_BPC_12_BITS (0x3 << 4) 138 #define IN_BPC_10_BITS (0x2 << 4) 139 #define IN_BPC_8_BITS (0x1 << 4) 140 #define IN_BPC_6_BITS (0x0 << 4) 141 #define IN_COLOR_F_MASK (0x3 << 0) 142 #define IN_COLOR_F_SHIFT (0) 143 #define IN_COLOR_F_YCBCR444 (0x2 << 0) 144 #define IN_COLOR_F_YCBCR422 (0x1 << 0) 145 #define IN_COLOR_F_RGB (0x0 << 0) 146 147 /* ANALOGIX_DP_VIDEO_CTL_3 */ 148 #define IN_YC_COEFFI_MASK (0x1 << 7) 149 #define IN_YC_COEFFI_SHIFT (7) 150 #define IN_YC_COEFFI_ITU709 (0x1 << 7) 151 #define IN_YC_COEFFI_ITU601 (0x0 << 7) 152 #define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) 153 #define VID_CHK_UPDATE_TYPE_SHIFT (4) 154 #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) 155 #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) 156 157 /* ANALOGIX_DP_VIDEO_CTL_8 */ 158 #define VID_HRES_TH(x) (((x) & 0xf) << 4) 159 #define VID_VRES_TH(x) (((x) & 0xf) << 0) 160 161 /* ANALOGIX_DP_VIDEO_CTL_10 */ 162 #define FORMAT_SEL (0x1 << 4) 163 #define INTERACE_SCAN_CFG (0x1 << 2) 164 #define VSYNC_POLARITY_CFG (0x1 << 1) 165 #define HSYNC_POLARITY_CFG (0x1 << 0) 166 167 /* ANALOGIX_DP_PLL_REG_1 */ 168 #define REF_CLK_24M (0x1 << 0) 169 #define REF_CLK_27M (0x0 << 0) 170 #define REF_CLK_MASK (0x1 << 0) 171 172 /* ANALOGIX_DP_LANE_MAP */ 173 #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) 174 #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) 175 #define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6) 176 #define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6) 177 #define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4) 178 #define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4) 179 #define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4) 180 #define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4) 181 #define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2) 182 #define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2) 183 #define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2) 184 #define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2) 185 #define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0) 186 #define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0) 187 #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) 188 #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) 189 190 /* ANALOGIX_DP_ANALOG_CTL_1 */ 191 #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) 192 193 /* ANALOGIX_DP_ANALOG_CTL_2 */ 194 #define SEL_24M (0x1 << 3) 195 #define TX_DVDD_BIT_1_0625V (0x4 << 0) 196 197 /* ANALOGIX_DP_ANALOG_CTL_3 */ 198 #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) 199 #define VCO_BIT_600_MICRO (0x5 << 0) 200 201 /* ANALOGIX_DP_PLL_FILTER_CTL_1 */ 202 #define PD_RING_OSC (0x1 << 6) 203 #define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) 204 #define TX_CUR1_2X (0x1 << 2) 205 #define TX_CUR_16_MA (0x3 << 0) 206 207 /* ANALOGIX_DP_TX_AMP_TUNING_CTL */ 208 #define CH3_AMP_400_MV (0x0 << 24) 209 #define CH2_AMP_400_MV (0x0 << 16) 210 #define CH1_AMP_400_MV (0x0 << 8) 211 #define CH0_AMP_400_MV (0x0 << 0) 212 213 /* ANALOGIX_DP_AUX_HW_RETRY_CTL */ 214 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) 215 #define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) 216 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) 217 #define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3) 218 #define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3) 219 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) 220 #define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0) 221 222 /* ANALOGIX_DP_COMMON_INT_STA_1 */ 223 #define VSYNC_DET (0x1 << 7) 224 #define PLL_LOCK_CHG (0x1 << 6) 225 #define SPDIF_ERR (0x1 << 5) 226 #define SPDIF_UNSTBL (0x1 << 4) 227 #define VID_FORMAT_CHG (0x1 << 3) 228 #define AUD_CLK_CHG (0x1 << 2) 229 #define VID_CLK_CHG (0x1 << 1) 230 #define SW_INT (0x1 << 0) 231 232 /* ANALOGIX_DP_COMMON_INT_STA_2 */ 233 #define ENC_EN_CHG (0x1 << 6) 234 #define HW_BKSV_RDY (0x1 << 3) 235 #define HW_SHA_DONE (0x1 << 2) 236 #define HW_AUTH_STATE_CHG (0x1 << 1) 237 #define HW_AUTH_DONE (0x1 << 0) 238 239 /* ANALOGIX_DP_COMMON_INT_STA_3 */ 240 #define AFIFO_UNDER (0x1 << 7) 241 #define AFIFO_OVER (0x1 << 6) 242 #define R0_CHK_FLAG (0x1 << 5) 243 244 /* ANALOGIX_DP_COMMON_INT_STA_4 */ 245 #define PSR_ACTIVE (0x1 << 7) 246 #define PSR_INACTIVE (0x1 << 6) 247 #define SPDIF_BI_PHASE_ERR (0x1 << 5) 248 #define HOTPLUG_CHG (0x1 << 2) 249 #define HPD_LOST (0x1 << 1) 250 #define PLUG (0x1 << 0) 251 252 /* ANALOGIX_DP_INT_STA */ 253 #define INT_HPD (0x1 << 6) 254 #define HW_TRAINING_FINISH (0x1 << 5) 255 #define RPLY_RECEIV (0x1 << 1) 256 #define AUX_ERR (0x1 << 0) 257 258 /* ANALOGIX_DP_INT_CTL */ 259 #define SOFT_INT_CTRL (0x1 << 2) 260 #define INT_POL1 (0x1 << 1) 261 #define INT_POL0 (0x1 << 0) 262 263 /* ANALOGIX_DP_SYS_CTL_1 */ 264 #define DET_STA (0x1 << 2) 265 #define FORCE_DET (0x1 << 1) 266 #define DET_CTRL (0x1 << 0) 267 268 /* ANALOGIX_DP_SYS_CTL_2 */ 269 #define CHA_CRI(x) (((x) & 0xf) << 4) 270 #define CHA_STA (0x1 << 2) 271 #define FORCE_CHA (0x1 << 1) 272 #define CHA_CTRL (0x1 << 0) 273 274 /* ANALOGIX_DP_SYS_CTL_3 */ 275 #define HPD_STATUS (0x1 << 6) 276 #define F_HPD (0x1 << 5) 277 #define HPD_CTRL (0x1 << 4) 278 #define HDCP_RDY (0x1 << 3) 279 #define STRM_VALID (0x1 << 2) 280 #define F_VALID (0x1 << 1) 281 #define VALID_CTRL (0x1 << 0) 282 283 /* ANALOGIX_DP_SYS_CTL_4 */ 284 #define FIX_M_AUD (0x1 << 4) 285 #define ENHANCED (0x1 << 3) 286 #define FIX_M_VID (0x1 << 2) 287 #define M_VID_UPDATE_CTRL (0x3 << 0) 288 289 /* ANALOGIX_DP_TRAINING_PTN_SET */ 290 #define SCRAMBLER_TYPE (0x1 << 9) 291 #define HW_LINK_TRAINING_PATTERN (0x1 << 8) 292 #define SCRAMBLING_DISABLE (0x1 << 5) 293 #define SCRAMBLING_ENABLE (0x0 << 5) 294 #define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2) 295 #define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) 296 #define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) 297 #define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) 298 #define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) 299 #define SW_TRAINING_PATTERN_SET_PTN3 (0x3 << 0) 300 #define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) 301 #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) 302 #define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) 303 304 /* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */ 305 #define PRE_EMPHASIS_SET_MASK (0x3 << 3) 306 #define PRE_EMPHASIS_SET_SHIFT (3) 307 308 /* ANALOGIX_DP_DEBUG_CTL */ 309 #define PLL_LOCK (0x1 << 4) 310 #define F_PLL_LOCK (0x1 << 3) 311 #define PLL_LOCK_CTRL (0x1 << 2) 312 #define PN_INV (0x1 << 0) 313 314 /* ANALOGIX_DP_PLL_CTL */ 315 #define DP_PLL_PD (0x1 << 7) 316 #define DP_PLL_RESET (0x1 << 6) 317 #define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) 318 #define DP_PLL_REF_BIT_1_1250V (0x5 << 0) 319 #define DP_PLL_REF_BIT_1_2500V (0x7 << 0) 320 321 /* ANALOGIX_DP_PHY_PD */ 322 #define DP_PHY_PD (0x1 << 5) 323 #define AUX_PD (0x1 << 4) 324 #define CH3_PD (0x1 << 3) 325 #define CH2_PD (0x1 << 2) 326 #define CH1_PD (0x1 << 1) 327 #define CH0_PD (0x1 << 0) 328 329 /* ANALOGIX_DP_PHY_TEST */ 330 #define MACRO_RST (0x1 << 5) 331 #define CH1_TEST (0x1 << 1) 332 #define CH0_TEST (0x1 << 0) 333 334 /* ANALOGIX_DP_AUX_CH_STA */ 335 #define AUX_BUSY (0x1 << 4) 336 #define AUX_STATUS_MASK (0xf << 0) 337 338 /* ANALOGIX_DP_AUX_CH_DEFER_CTL */ 339 #define DEFER_CTRL_EN (0x1 << 7) 340 #define DEFER_COUNT(x) (((x) & 0x7f) << 0) 341 342 /* ANALOGIX_DP_AUX_RX_COMM */ 343 #define AUX_RX_COMM_I2C_DEFER (0x2 << 2) 344 #define AUX_RX_COMM_AUX_DEFER (0x2 << 0) 345 346 /* ANALOGIX_DP_BUFFER_DATA_CTL */ 347 #define BUF_CLR (0x1 << 7) 348 #define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0) 349 350 /* ANALOGIX_DP_AUX_CH_CTL_1 */ 351 #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) 352 #define AUX_TX_COMM_MASK (0xf << 0) 353 #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) 354 #define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) 355 #define AUX_TX_COMM_MOT (0x1 << 2) 356 #define AUX_TX_COMM_WRITE (0x0 << 0) 357 #define AUX_TX_COMM_READ (0x1 << 0) 358 359 /* ANALOGIX_DP_AUX_ADDR_7_0 */ 360 #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) 361 362 /* ANALOGIX_DP_AUX_ADDR_15_8 */ 363 #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) 364 365 /* ANALOGIX_DP_AUX_ADDR_19_16 */ 366 #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) 367 368 /* ANALOGIX_DP_AUX_CH_CTL_2 */ 369 #define ADDR_ONLY (0x1 << 1) 370 #define AUX_EN (0x1 << 0) 371 372 /* ANALOGIX_DP_SOC_GENERAL_CTL */ 373 #define AUDIO_MODE_SPDIF_MODE (0x1 << 8) 374 #define AUDIO_MODE_MASTER_MODE (0x0 << 8) 375 #define MASTER_VIDEO_INTERLACE_EN (0x1 << 4) 376 #define VIDEO_MASTER_CLK_SEL (0x1 << 2) 377 #define VIDEO_MASTER_MODE_EN (0x1 << 1) 378 #define VIDEO_MODE_MASK (0x1 << 0) 379 #define VIDEO_MODE_SLAVE_MODE (0x1 << 0) 380 #define VIDEO_MODE_MASTER_MODE (0x0 << 0) 381 382 #define DP_TIMEOUT_LOOP_COUNT 100 383 #define MAX_CR_LOOP 5 384 #define MAX_EQ_LOOP 5 385 386 /* I2C EDID Chip ID, Slave Address */ 387 #define I2C_EDID_DEVICE_ADDR 0x50 388 #define I2C_E_EDID_DEVICE_ADDR 0x30 389 390 #define EDID_BLOCK_LENGTH 0x80 391 #define EDID_HEADER_PATTERN 0x00 392 #define EDID_EXTENSION_FLAG 0x7e 393 #define EDID_CHECKSUM 0x7f 394 395 /* DP_MAX_LANE_COUNT */ 396 #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1) 397 #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f) 398 399 /* DP_LANE_COUNT_SET */ 400 #define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f) 401 402 /* DP_TRAINING_LANE0_SET */ 403 #define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3) 404 #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3) 405 #define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0) 406 #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3) 407 408 enum link_lane_count_type { 409 LANE_COUNT1 = 1, 410 LANE_COUNT2 = 2, 411 LANE_COUNT4 = 4 412 }; 413 414 enum link_training_state { 415 START, 416 CLOCK_RECOVERY, 417 EQUALIZER_TRAINING, 418 FINISHED, 419 FAILED 420 }; 421 422 enum voltage_swing_level { 423 VOLTAGE_LEVEL_0, 424 VOLTAGE_LEVEL_1, 425 VOLTAGE_LEVEL_2, 426 VOLTAGE_LEVEL_3, 427 }; 428 429 enum pre_emphasis_level { 430 PRE_EMPHASIS_LEVEL_0, 431 PRE_EMPHASIS_LEVEL_1, 432 PRE_EMPHASIS_LEVEL_2, 433 PRE_EMPHASIS_LEVEL_3, 434 }; 435 436 enum pattern_set { 437 PRBS7, 438 D10_2, 439 TRAINING_PTN1, 440 TRAINING_PTN2, 441 TRAINING_PTN3, 442 DP_NONE 443 }; 444 445 enum color_space { 446 COLOR_RGB, 447 COLOR_YCBCR422, 448 COLOR_YCBCR444 449 }; 450 451 enum color_depth { 452 COLOR_6, 453 COLOR_8, 454 COLOR_10, 455 COLOR_12 456 }; 457 458 enum color_coefficient { 459 COLOR_YCBCR601, 460 COLOR_YCBCR709 461 }; 462 463 enum dynamic_range { 464 VESA, 465 CEA 466 }; 467 468 enum pll_status { 469 PLL_UNLOCKED, 470 PLL_LOCKED 471 }; 472 473 enum clock_recovery_m_value_type { 474 CALCULATED_M, 475 REGISTER_M 476 }; 477 478 enum video_timing_recognition_type { 479 VIDEO_TIMING_FROM_CAPTURE, 480 VIDEO_TIMING_FROM_REGISTER 481 }; 482 483 enum analog_power_block { 484 AUX_BLOCK, 485 CH0_BLOCK, 486 CH1_BLOCK, 487 CH2_BLOCK, 488 CH3_BLOCK, 489 ANALOG_TOTAL, 490 POWER_ALL 491 }; 492 493 enum dp_irq_type { 494 DP_IRQ_TYPE_HP_CABLE_IN = BIT(0), 495 DP_IRQ_TYPE_HP_CABLE_OUT = BIT(1), 496 DP_IRQ_TYPE_HP_CHANGE = BIT(2), 497 DP_IRQ_TYPE_UNKNOWN = BIT(3), 498 }; 499 500 struct video_info { 501 char *name; 502 503 bool h_sync_polarity; 504 bool v_sync_polarity; 505 bool interlaced; 506 507 enum color_space color_space; 508 enum dynamic_range dynamic_range; 509 enum color_coefficient ycbcr_coeff; 510 enum color_depth color_depth; 511 512 int max_link_rate; 513 enum link_lane_count_type max_lane_count; 514 }; 515 516 struct link_train { 517 int eq_loop; 518 int cr_loop[4]; 519 520 u8 link_rate; 521 u8 lane_count; 522 u8 training_lane[4]; 523 bool ssc; 524 525 enum link_training_state lt_state; 526 }; 527 528 enum analogix_dp_devtype { 529 EXYNOS_DP, 530 ROCKCHIP_DP, 531 }; 532 533 enum analogix_dp_sub_devtype { 534 RK3288_DP, 535 RK3368_EDP, 536 RK3399_EDP, 537 RK3568_EDP, 538 RK3588_EDP 539 }; 540 541 struct analogix_dp_plat_data { 542 enum analogix_dp_devtype dev_type; 543 enum analogix_dp_sub_devtype subdev_type; 544 bool ssc; 545 }; 546 547 struct analogix_dp_device { 548 int id; 549 struct udevice *dev; 550 void *reg_base; 551 struct regmap *grf; 552 struct phy phy; 553 struct reset_ctl_bulk resets; 554 struct gpio_desc hpd_gpio; 555 bool force_hpd; 556 struct video_info video_info; 557 struct link_train link_train; 558 struct drm_display_mode *mode; 559 struct analogix_dp_plat_data plat_data; 560 unsigned char edid[EDID_BLOCK_LENGTH * 2]; 561 }; 562 563 /* analogix_dp_reg.c */ 564 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable); 565 void analogix_dp_stop_video(struct analogix_dp_device *dp); 566 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable); 567 void analogix_dp_init_analog_param(struct analogix_dp_device *dp); 568 void analogix_dp_init_interrupt(struct analogix_dp_device *dp); 569 void analogix_dp_reset(struct analogix_dp_device *dp); 570 void analogix_dp_swreset(struct analogix_dp_device *dp); 571 void analogix_dp_config_interrupt(struct analogix_dp_device *dp); 572 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp); 573 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp); 574 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp); 575 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable); 576 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 577 enum analog_power_block block, 578 bool enable); 579 void analogix_dp_init_analog_func(struct analogix_dp_device *dp); 580 void analogix_dp_init_hpd(struct analogix_dp_device *dp); 581 void analogix_dp_force_hpd(struct analogix_dp_device *dp); 582 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp); 583 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp); 584 void analogix_dp_reset_aux(struct analogix_dp_device *dp); 585 void analogix_dp_init_aux(struct analogix_dp_device *dp); 586 int analogix_dp_detect(struct analogix_dp_device *dp); 587 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp); 588 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp); 589 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp, 590 unsigned int reg_addr, 591 unsigned char data); 592 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp, 593 unsigned int reg_addr, 594 unsigned char *data); 595 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp, 596 unsigned int reg_addr, 597 unsigned int count, 598 unsigned char data[]); 599 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp, 600 unsigned int reg_addr, 601 unsigned int count, 602 unsigned char data[]); 603 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp, 604 unsigned int device_addr, 605 unsigned int reg_addr); 606 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp, 607 unsigned int device_addr, 608 unsigned int reg_addr, 609 unsigned int *data); 610 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp, 611 unsigned int device_addr, 612 unsigned int reg_addr, 613 unsigned int count, 614 unsigned char edid[]); 615 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype); 616 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype); 617 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count); 618 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count); 619 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, 620 bool enable); 621 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, 622 enum pattern_set pattern); 623 void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp); 624 u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane); 625 void analogix_dp_reset_macro(struct analogix_dp_device *dp); 626 void analogix_dp_init_video(struct analogix_dp_device *dp); 627 628 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp); 629 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp); 630 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, 631 enum clock_recovery_m_value_type type, 632 u32 m_value, 633 u32 n_value); 634 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type); 635 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, 636 bool enable); 637 void analogix_dp_start_video(struct analogix_dp_device *dp); 638 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp); 639 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp); 640 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp); 641 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp); 642 bool analogix_dp_ssc_supported(struct analogix_dp_device *dp); 643 644 #endif /* __DRM_ANALOGIX_DP__ */ 645