1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __DRM_ANALOGIX_DP_H__ 8 #define __DRM_ANALOGIX_DP_H__ 9 10 #include <generic-phy.h> 11 #include <reset.h> 12 13 #include <drm/drm_dp_helper.h> 14 15 #define ANALOGIX_DP_TX_SW_RESET 0x14 16 #define ANALOGIX_DP_FUNC_EN_1 0x18 17 #define ANALOGIX_DP_FUNC_EN_2 0x1C 18 #define ANALOGIX_DP_VIDEO_CTL_1 0x20 19 #define ANALOGIX_DP_VIDEO_CTL_2 0x24 20 #define ANALOGIX_DP_VIDEO_CTL_3 0x28 21 22 #define ANALOGIX_DP_VIDEO_CTL_8 0x3C 23 #define ANALOGIX_DP_VIDEO_CTL_10 0x44 24 25 #define ANALOGIX_DP_PLL_REG_1 0xfc 26 #define ANALOGIX_DP_PLL_REG_2 0x9e4 27 #define ANALOGIX_DP_PLL_REG_3 0x9e8 28 #define ANALOGIX_DP_PLL_REG_4 0x9ec 29 #define ANALOGIX_DP_PLL_REG_5 0xa00 30 31 #define ANALOGIX_DP_BIAS 0x124 32 #define ANALOGIX_DP_PD 0x12c 33 34 #define ANALOGIX_DP_LANE_MAP 0x35C 35 36 #define ANALOGIX_DP_ANALOG_CTL_1 0x370 37 #define ANALOGIX_DP_ANALOG_CTL_2 0x374 38 #define ANALOGIX_DP_ANALOG_CTL_3 0x378 39 #define ANALOGIX_DP_PLL_FILTER_CTL_1 0x37C 40 #define ANALOGIX_DP_TX_AMP_TUNING_CTL 0x380 41 42 #define ANALOGIX_DP_AUX_HW_RETRY_CTL 0x390 43 44 #define ANALOGIX_DP_COMMON_INT_STA_1 0x3C4 45 #define ANALOGIX_DP_COMMON_INT_STA_2 0x3C8 46 #define ANALOGIX_DP_COMMON_INT_STA_3 0x3CC 47 #define ANALOGIX_DP_COMMON_INT_STA_4 0x3D0 48 #define ANALOGIX_DP_INT_STA 0x3DC 49 #define ANALOGIX_DP_COMMON_INT_MASK_1 0x3E0 50 #define ANALOGIX_DP_COMMON_INT_MASK_2 0x3E4 51 #define ANALOGIX_DP_COMMON_INT_MASK_3 0x3E8 52 #define ANALOGIX_DP_COMMON_INT_MASK_4 0x3EC 53 #define ANALOGIX_DP_INT_STA_MASK 0x3F8 54 #define ANALOGIX_DP_INT_CTL 0x3FC 55 56 #define ANALOGIX_DP_SYS_CTL_1 0x600 57 #define ANALOGIX_DP_SYS_CTL_2 0x604 58 #define ANALOGIX_DP_SYS_CTL_3 0x608 59 #define ANALOGIX_DP_SYS_CTL_4 0x60C 60 61 #define ANALOGIX_DP_PKT_SEND_CTL 0x640 62 #define ANALOGIX_DP_HDCP_CTL 0x648 63 64 #define ANALOGIX_DP_LINK_BW_SET 0x680 65 #define ANALOGIX_DP_LANE_COUNT_SET 0x684 66 #define ANALOGIX_DP_TRAINING_PTN_SET 0x688 67 #define ANALOGIX_DP_LN0_LINK_TRAINING_CTL 0x68C 68 #define ANALOGIX_DP_LN1_LINK_TRAINING_CTL 0x690 69 #define ANALOGIX_DP_LN2_LINK_TRAINING_CTL 0x694 70 #define ANALOGIX_DP_LN3_LINK_TRAINING_CTL 0x698 71 72 #define ANALOGIX_DP_DEBUG_CTL 0x6C0 73 #define ANALOGIX_DP_HPD_DEGLITCH_L 0x6C4 74 #define ANALOGIX_DP_HPD_DEGLITCH_H 0x6C8 75 #define ANALOGIX_DP_LINK_DEBUG_CTL 0x6E0 76 77 #define ANALOGIX_DP_M_VID_0 0x700 78 #define ANALOGIX_DP_M_VID_1 0x704 79 #define ANALOGIX_DP_M_VID_2 0x708 80 #define ANALOGIX_DP_N_VID_0 0x70C 81 #define ANALOGIX_DP_N_VID_1 0x710 82 #define ANALOGIX_DP_N_VID_2 0x714 83 84 #define ANALOGIX_DP_PLL_CTL 0x71C 85 #define ANALOGIX_DP_PHY_PD 0x720 86 #define ANALOGIX_DP_PHY_TEST 0x724 87 88 #define ANALOGIX_DP_VIDEO_FIFO_THRD 0x730 89 #define ANALOGIX_DP_AUDIO_MARGIN 0x73C 90 91 #define ANALOGIX_DP_M_VID_GEN_FILTER_TH 0x764 92 #define ANALOGIX_DP_M_AUD_GEN_FILTER_TH 0x778 93 #define ANALOGIX_DP_AUX_CH_STA 0x780 94 #define ANALOGIX_DP_AUX_CH_DEFER_CTL 0x788 95 #define ANALOGIX_DP_AUX_RX_COMM 0x78C 96 #define ANALOGIX_DP_BUFFER_DATA_CTL 0x790 97 #define ANALOGIX_DP_AUX_CH_CTL_1 0x794 98 #define ANALOGIX_DP_AUX_ADDR_7_0 0x798 99 #define ANALOGIX_DP_AUX_ADDR_15_8 0x79C 100 #define ANALOGIX_DP_AUX_ADDR_19_16 0x7A0 101 #define ANALOGIX_DP_AUX_CH_CTL_2 0x7A4 102 103 #define ANALOGIX_DP_BUF_DATA_0 0x7C0 104 105 #define ANALOGIX_DP_SOC_GENERAL_CTL 0x800 106 107 /* ANALOGIX_DP_TX_SW_RESET */ 108 #define RESET_DP_TX (0x1 << 0) 109 110 /* ANALOGIX_DP_FUNC_EN_1 */ 111 #define MASTER_VID_FUNC_EN_N (0x1 << 7) 112 #define SLAVE_VID_FUNC_EN_N (0x1 << 5) 113 #define AUD_FIFO_FUNC_EN_N (0x1 << 4) 114 #define AUD_FUNC_EN_N (0x1 << 3) 115 #define HDCP_FUNC_EN_N (0x1 << 2) 116 #define CRC_FUNC_EN_N (0x1 << 1) 117 #define SW_FUNC_EN_N (0x1 << 0) 118 119 /* ANALOGIX_DP_FUNC_EN_2 */ 120 #define SSC_FUNC_EN_N (0x1 << 7) 121 #define AUX_FUNC_EN_N (0x1 << 2) 122 #define SERDES_FIFO_FUNC_EN_N (0x1 << 1) 123 #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) 124 125 /* ANALOGIX_DP_VIDEO_CTL_1 */ 126 #define VIDEO_EN (0x1 << 7) 127 #define HDCP_VIDEO_MUTE (0x1 << 6) 128 129 /* ANALOGIX_DP_VIDEO_CTL_1 */ 130 #define IN_D_RANGE_MASK (0x1 << 7) 131 #define IN_D_RANGE_SHIFT (7) 132 #define IN_D_RANGE_CEA (0x1 << 7) 133 #define IN_D_RANGE_VESA (0x0 << 7) 134 #define IN_BPC_MASK (0x7 << 4) 135 #define IN_BPC_SHIFT (4) 136 #define IN_BPC_12_BITS (0x3 << 4) 137 #define IN_BPC_10_BITS (0x2 << 4) 138 #define IN_BPC_8_BITS (0x1 << 4) 139 #define IN_BPC_6_BITS (0x0 << 4) 140 #define IN_COLOR_F_MASK (0x3 << 0) 141 #define IN_COLOR_F_SHIFT (0) 142 #define IN_COLOR_F_YCBCR444 (0x2 << 0) 143 #define IN_COLOR_F_YCBCR422 (0x1 << 0) 144 #define IN_COLOR_F_RGB (0x0 << 0) 145 146 /* ANALOGIX_DP_VIDEO_CTL_3 */ 147 #define IN_YC_COEFFI_MASK (0x1 << 7) 148 #define IN_YC_COEFFI_SHIFT (7) 149 #define IN_YC_COEFFI_ITU709 (0x1 << 7) 150 #define IN_YC_COEFFI_ITU601 (0x0 << 7) 151 #define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) 152 #define VID_CHK_UPDATE_TYPE_SHIFT (4) 153 #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) 154 #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) 155 156 /* ANALOGIX_DP_VIDEO_CTL_8 */ 157 #define VID_HRES_TH(x) (((x) & 0xf) << 4) 158 #define VID_VRES_TH(x) (((x) & 0xf) << 0) 159 160 /* ANALOGIX_DP_VIDEO_CTL_10 */ 161 #define FORMAT_SEL (0x1 << 4) 162 #define INTERACE_SCAN_CFG (0x1 << 2) 163 #define VSYNC_POLARITY_CFG (0x1 << 1) 164 #define HSYNC_POLARITY_CFG (0x1 << 0) 165 166 /* ANALOGIX_DP_PLL_REG_1 */ 167 #define REF_CLK_24M (0x1 << 0) 168 #define REF_CLK_27M (0x0 << 0) 169 #define REF_CLK_MASK (0x1 << 0) 170 171 /* ANALOGIX_DP_LANE_MAP */ 172 #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) 173 #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) 174 #define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6) 175 #define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6) 176 #define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4) 177 #define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4) 178 #define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4) 179 #define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4) 180 #define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2) 181 #define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2) 182 #define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2) 183 #define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2) 184 #define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0) 185 #define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0) 186 #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) 187 #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) 188 189 /* ANALOGIX_DP_ANALOG_CTL_1 */ 190 #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) 191 192 /* ANALOGIX_DP_ANALOG_CTL_2 */ 193 #define SEL_24M (0x1 << 3) 194 #define TX_DVDD_BIT_1_0625V (0x4 << 0) 195 196 /* ANALOGIX_DP_ANALOG_CTL_3 */ 197 #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) 198 #define VCO_BIT_600_MICRO (0x5 << 0) 199 200 /* ANALOGIX_DP_PLL_FILTER_CTL_1 */ 201 #define PD_RING_OSC (0x1 << 6) 202 #define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) 203 #define TX_CUR1_2X (0x1 << 2) 204 #define TX_CUR_16_MA (0x3 << 0) 205 206 /* ANALOGIX_DP_TX_AMP_TUNING_CTL */ 207 #define CH3_AMP_400_MV (0x0 << 24) 208 #define CH2_AMP_400_MV (0x0 << 16) 209 #define CH1_AMP_400_MV (0x0 << 8) 210 #define CH0_AMP_400_MV (0x0 << 0) 211 212 /* ANALOGIX_DP_AUX_HW_RETRY_CTL */ 213 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) 214 #define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) 215 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) 216 #define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3) 217 #define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3) 218 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) 219 #define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0) 220 221 /* ANALOGIX_DP_COMMON_INT_STA_1 */ 222 #define VSYNC_DET (0x1 << 7) 223 #define PLL_LOCK_CHG (0x1 << 6) 224 #define SPDIF_ERR (0x1 << 5) 225 #define SPDIF_UNSTBL (0x1 << 4) 226 #define VID_FORMAT_CHG (0x1 << 3) 227 #define AUD_CLK_CHG (0x1 << 2) 228 #define VID_CLK_CHG (0x1 << 1) 229 #define SW_INT (0x1 << 0) 230 231 /* ANALOGIX_DP_COMMON_INT_STA_2 */ 232 #define ENC_EN_CHG (0x1 << 6) 233 #define HW_BKSV_RDY (0x1 << 3) 234 #define HW_SHA_DONE (0x1 << 2) 235 #define HW_AUTH_STATE_CHG (0x1 << 1) 236 #define HW_AUTH_DONE (0x1 << 0) 237 238 /* ANALOGIX_DP_COMMON_INT_STA_3 */ 239 #define AFIFO_UNDER (0x1 << 7) 240 #define AFIFO_OVER (0x1 << 6) 241 #define R0_CHK_FLAG (0x1 << 5) 242 243 /* ANALOGIX_DP_COMMON_INT_STA_4 */ 244 #define PSR_ACTIVE (0x1 << 7) 245 #define PSR_INACTIVE (0x1 << 6) 246 #define SPDIF_BI_PHASE_ERR (0x1 << 5) 247 #define HOTPLUG_CHG (0x1 << 2) 248 #define HPD_LOST (0x1 << 1) 249 #define PLUG (0x1 << 0) 250 251 /* ANALOGIX_DP_INT_STA */ 252 #define INT_HPD (0x1 << 6) 253 #define HW_TRAINING_FINISH (0x1 << 5) 254 #define RPLY_RECEIV (0x1 << 1) 255 #define AUX_ERR (0x1 << 0) 256 257 /* ANALOGIX_DP_INT_CTL */ 258 #define SOFT_INT_CTRL (0x1 << 2) 259 #define INT_POL1 (0x1 << 1) 260 #define INT_POL0 (0x1 << 0) 261 262 /* ANALOGIX_DP_SYS_CTL_1 */ 263 #define DET_STA (0x1 << 2) 264 #define FORCE_DET (0x1 << 1) 265 #define DET_CTRL (0x1 << 0) 266 267 /* ANALOGIX_DP_SYS_CTL_2 */ 268 #define CHA_CRI(x) (((x) & 0xf) << 4) 269 #define CHA_STA (0x1 << 2) 270 #define FORCE_CHA (0x1 << 1) 271 #define CHA_CTRL (0x1 << 0) 272 273 /* ANALOGIX_DP_SYS_CTL_3 */ 274 #define HPD_STATUS (0x1 << 6) 275 #define F_HPD (0x1 << 5) 276 #define HPD_CTRL (0x1 << 4) 277 #define HDCP_RDY (0x1 << 3) 278 #define STRM_VALID (0x1 << 2) 279 #define F_VALID (0x1 << 1) 280 #define VALID_CTRL (0x1 << 0) 281 282 /* ANALOGIX_DP_SYS_CTL_4 */ 283 #define FIX_M_AUD (0x1 << 4) 284 #define ENHANCED (0x1 << 3) 285 #define FIX_M_VID (0x1 << 2) 286 #define M_VID_UPDATE_CTRL (0x3 << 0) 287 288 /* ANALOGIX_DP_TRAINING_PTN_SET */ 289 #define SCRAMBLER_TYPE (0x1 << 9) 290 #define HW_LINK_TRAINING_PATTERN (0x1 << 8) 291 #define SCRAMBLING_DISABLE (0x1 << 5) 292 #define SCRAMBLING_ENABLE (0x0 << 5) 293 #define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2) 294 #define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) 295 #define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) 296 #define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) 297 #define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) 298 #define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) 299 #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) 300 #define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) 301 302 /* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */ 303 #define PRE_EMPHASIS_SET_MASK (0x3 << 3) 304 #define PRE_EMPHASIS_SET_SHIFT (3) 305 306 /* ANALOGIX_DP_DEBUG_CTL */ 307 #define PLL_LOCK (0x1 << 4) 308 #define F_PLL_LOCK (0x1 << 3) 309 #define PLL_LOCK_CTRL (0x1 << 2) 310 #define PN_INV (0x1 << 0) 311 312 /* ANALOGIX_DP_PLL_CTL */ 313 #define DP_PLL_PD (0x1 << 7) 314 #define DP_PLL_RESET (0x1 << 6) 315 #define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) 316 #define DP_PLL_REF_BIT_1_1250V (0x5 << 0) 317 #define DP_PLL_REF_BIT_1_2500V (0x7 << 0) 318 319 /* ANALOGIX_DP_PHY_PD */ 320 #define DP_PHY_PD (0x1 << 5) 321 #define AUX_PD (0x1 << 4) 322 #define CH3_PD (0x1 << 3) 323 #define CH2_PD (0x1 << 2) 324 #define CH1_PD (0x1 << 1) 325 #define CH0_PD (0x1 << 0) 326 327 /* ANALOGIX_DP_PHY_TEST */ 328 #define MACRO_RST (0x1 << 5) 329 #define CH1_TEST (0x1 << 1) 330 #define CH0_TEST (0x1 << 0) 331 332 /* ANALOGIX_DP_AUX_CH_STA */ 333 #define AUX_BUSY (0x1 << 4) 334 #define AUX_STATUS_MASK (0xf << 0) 335 336 /* ANALOGIX_DP_AUX_CH_DEFER_CTL */ 337 #define DEFER_CTRL_EN (0x1 << 7) 338 #define DEFER_COUNT(x) (((x) & 0x7f) << 0) 339 340 /* ANALOGIX_DP_AUX_RX_COMM */ 341 #define AUX_RX_COMM_I2C_DEFER (0x2 << 2) 342 #define AUX_RX_COMM_AUX_DEFER (0x2 << 0) 343 344 /* ANALOGIX_DP_BUFFER_DATA_CTL */ 345 #define BUF_CLR (0x1 << 7) 346 #define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0) 347 348 /* ANALOGIX_DP_AUX_CH_CTL_1 */ 349 #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) 350 #define AUX_TX_COMM_MASK (0xf << 0) 351 #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) 352 #define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) 353 #define AUX_TX_COMM_MOT (0x1 << 2) 354 #define AUX_TX_COMM_WRITE (0x0 << 0) 355 #define AUX_TX_COMM_READ (0x1 << 0) 356 357 /* ANALOGIX_DP_AUX_ADDR_7_0 */ 358 #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) 359 360 /* ANALOGIX_DP_AUX_ADDR_15_8 */ 361 #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) 362 363 /* ANALOGIX_DP_AUX_ADDR_19_16 */ 364 #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) 365 366 /* ANALOGIX_DP_AUX_CH_CTL_2 */ 367 #define ADDR_ONLY (0x1 << 1) 368 #define AUX_EN (0x1 << 0) 369 370 /* ANALOGIX_DP_SOC_GENERAL_CTL */ 371 #define AUDIO_MODE_SPDIF_MODE (0x1 << 8) 372 #define AUDIO_MODE_MASTER_MODE (0x0 << 8) 373 #define MASTER_VIDEO_INTERLACE_EN (0x1 << 4) 374 #define VIDEO_MASTER_CLK_SEL (0x1 << 2) 375 #define VIDEO_MASTER_MODE_EN (0x1 << 1) 376 #define VIDEO_MODE_MASK (0x1 << 0) 377 #define VIDEO_MODE_SLAVE_MODE (0x1 << 0) 378 #define VIDEO_MODE_MASTER_MODE (0x0 << 0) 379 380 #define DP_TIMEOUT_LOOP_COUNT 100 381 #define MAX_CR_LOOP 5 382 #define MAX_EQ_LOOP 5 383 384 /* I2C EDID Chip ID, Slave Address */ 385 #define I2C_EDID_DEVICE_ADDR 0x50 386 #define I2C_E_EDID_DEVICE_ADDR 0x30 387 388 #define EDID_BLOCK_LENGTH 0x80 389 #define EDID_HEADER_PATTERN 0x00 390 #define EDID_EXTENSION_FLAG 0x7e 391 #define EDID_CHECKSUM 0x7f 392 393 /* DP_MAX_LANE_COUNT */ 394 #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1) 395 #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f) 396 397 /* DP_LANE_COUNT_SET */ 398 #define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f) 399 400 /* DP_TRAINING_LANE0_SET */ 401 #define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3) 402 #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3) 403 #define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0) 404 #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3) 405 406 enum link_lane_count_type { 407 LANE_COUNT1 = 1, 408 LANE_COUNT2 = 2, 409 LANE_COUNT4 = 4 410 }; 411 412 enum link_training_state { 413 START, 414 CLOCK_RECOVERY, 415 EQUALIZER_TRAINING, 416 FINISHED, 417 FAILED 418 }; 419 420 enum voltage_swing_level { 421 VOLTAGE_LEVEL_0, 422 VOLTAGE_LEVEL_1, 423 VOLTAGE_LEVEL_2, 424 VOLTAGE_LEVEL_3, 425 }; 426 427 enum pre_emphasis_level { 428 PRE_EMPHASIS_LEVEL_0, 429 PRE_EMPHASIS_LEVEL_1, 430 PRE_EMPHASIS_LEVEL_2, 431 PRE_EMPHASIS_LEVEL_3, 432 }; 433 434 enum pattern_set { 435 PRBS7, 436 D10_2, 437 TRAINING_PTN1, 438 TRAINING_PTN2, 439 DP_NONE 440 }; 441 442 enum color_space { 443 COLOR_RGB, 444 COLOR_YCBCR422, 445 COLOR_YCBCR444 446 }; 447 448 enum color_depth { 449 COLOR_6, 450 COLOR_8, 451 COLOR_10, 452 COLOR_12 453 }; 454 455 enum color_coefficient { 456 COLOR_YCBCR601, 457 COLOR_YCBCR709 458 }; 459 460 enum dynamic_range { 461 VESA, 462 CEA 463 }; 464 465 enum pll_status { 466 PLL_UNLOCKED, 467 PLL_LOCKED 468 }; 469 470 enum clock_recovery_m_value_type { 471 CALCULATED_M, 472 REGISTER_M 473 }; 474 475 enum video_timing_recognition_type { 476 VIDEO_TIMING_FROM_CAPTURE, 477 VIDEO_TIMING_FROM_REGISTER 478 }; 479 480 enum analog_power_block { 481 AUX_BLOCK, 482 CH0_BLOCK, 483 CH1_BLOCK, 484 CH2_BLOCK, 485 CH3_BLOCK, 486 ANALOG_TOTAL, 487 POWER_ALL 488 }; 489 490 enum dp_irq_type { 491 DP_IRQ_TYPE_HP_CABLE_IN = BIT(0), 492 DP_IRQ_TYPE_HP_CABLE_OUT = BIT(1), 493 DP_IRQ_TYPE_HP_CHANGE = BIT(2), 494 DP_IRQ_TYPE_UNKNOWN = BIT(3), 495 }; 496 497 struct video_info { 498 char *name; 499 500 bool h_sync_polarity; 501 bool v_sync_polarity; 502 bool interlaced; 503 504 enum color_space color_space; 505 enum dynamic_range dynamic_range; 506 enum color_coefficient ycbcr_coeff; 507 enum color_depth color_depth; 508 509 int max_link_rate; 510 enum link_lane_count_type max_lane_count; 511 }; 512 513 struct link_train { 514 int eq_loop; 515 int cr_loop[4]; 516 517 u8 link_rate; 518 u8 lane_count; 519 u8 training_lane[4]; 520 bool ssc; 521 522 enum link_training_state lt_state; 523 }; 524 525 enum analogix_dp_devtype { 526 EXYNOS_DP, 527 ROCKCHIP_DP, 528 }; 529 530 enum analogix_dp_sub_devtype { 531 RK3288_DP, 532 RK3368_EDP, 533 RK3399_EDP, 534 RK3568_EDP, 535 }; 536 537 struct analogix_dp_plat_data { 538 enum analogix_dp_devtype dev_type; 539 enum analogix_dp_sub_devtype subdev_type; 540 bool ssc; 541 }; 542 543 struct analogix_dp_device { 544 int id; 545 struct udevice *dev; 546 void *reg_base; 547 struct phy phy; 548 struct reset_ctl_bulk resets; 549 struct gpio_desc hpd_gpio; 550 bool force_hpd; 551 struct video_info video_info; 552 struct link_train link_train; 553 struct drm_display_mode *mode; 554 struct analogix_dp_plat_data plat_data; 555 unsigned char edid[EDID_BLOCK_LENGTH * 2]; 556 }; 557 558 /* analogix_dp_reg.c */ 559 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable); 560 void analogix_dp_stop_video(struct analogix_dp_device *dp); 561 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable); 562 void analogix_dp_init_analog_param(struct analogix_dp_device *dp); 563 void analogix_dp_init_interrupt(struct analogix_dp_device *dp); 564 void analogix_dp_reset(struct analogix_dp_device *dp); 565 void analogix_dp_swreset(struct analogix_dp_device *dp); 566 void analogix_dp_config_interrupt(struct analogix_dp_device *dp); 567 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp); 568 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp); 569 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp); 570 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable); 571 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 572 enum analog_power_block block, 573 bool enable); 574 void analogix_dp_init_analog_func(struct analogix_dp_device *dp); 575 void analogix_dp_init_hpd(struct analogix_dp_device *dp); 576 void analogix_dp_force_hpd(struct analogix_dp_device *dp); 577 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp); 578 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp); 579 void analogix_dp_reset_aux(struct analogix_dp_device *dp); 580 void analogix_dp_init_aux(struct analogix_dp_device *dp); 581 int analogix_dp_detect(struct analogix_dp_device *dp); 582 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp); 583 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp); 584 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp, 585 unsigned int reg_addr, 586 unsigned char data); 587 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp, 588 unsigned int reg_addr, 589 unsigned char *data); 590 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp, 591 unsigned int reg_addr, 592 unsigned int count, 593 unsigned char data[]); 594 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp, 595 unsigned int reg_addr, 596 unsigned int count, 597 unsigned char data[]); 598 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp, 599 unsigned int device_addr, 600 unsigned int reg_addr); 601 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp, 602 unsigned int device_addr, 603 unsigned int reg_addr, 604 unsigned int *data); 605 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp, 606 unsigned int device_addr, 607 unsigned int reg_addr, 608 unsigned int count, 609 unsigned char edid[]); 610 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype); 611 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype); 612 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count); 613 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count); 614 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, 615 bool enable); 616 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, 617 enum pattern_set pattern); 618 void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp); 619 u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane); 620 void analogix_dp_reset_macro(struct analogix_dp_device *dp); 621 void analogix_dp_init_video(struct analogix_dp_device *dp); 622 623 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp); 624 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp); 625 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, 626 enum clock_recovery_m_value_type type, 627 u32 m_value, 628 u32 n_value); 629 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type); 630 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, 631 bool enable); 632 void analogix_dp_start_video(struct analogix_dp_device *dp); 633 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp); 634 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp); 635 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp); 636 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp); 637 bool analogix_dp_ssc_supported(struct analogix_dp_device *dp); 638 639 #endif /* __DRM_ANALOGIX_DP__ */ 640