1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __DRM_ANALOGIX_DP_H__ 8 #define __DRM_ANALOGIX_DP_H__ 9 10 #include <generic-phy.h> 11 #include <regmap.h> 12 #include <reset.h> 13 14 #include <drm/drm_dp_helper.h> 15 16 #include "rockchip_connector.h" 17 18 #define ANALOGIX_DP_TX_SW_RESET 0x14 19 #define ANALOGIX_DP_FUNC_EN_1 0x18 20 #define ANALOGIX_DP_FUNC_EN_2 0x1C 21 #define ANALOGIX_DP_VIDEO_CTL_1 0x20 22 #define ANALOGIX_DP_VIDEO_CTL_2 0x24 23 #define ANALOGIX_DP_VIDEO_CTL_3 0x28 24 #define ANALOGIX_DP_VIDEO_CTL_4 0x2C 25 #define ANALOGIX_DP_VIDEO_CTL_8 0x3C 26 #define ANALOGIX_DP_VIDEO_CTL_10 0x44 27 28 #define ANALOGIX_DP_TOTAL_LINE_CFG_L 0x48 29 #define ANALOGIX_DP_TOTAL_LINE_CFG_H 0x4C 30 #define ANALOGIX_DP_ACTIVE_LINE_CFG_L 0x50 31 #define ANALOGIX_DP_ACTIVE_LINE_CFG_H 0x54 32 #define ANALOGIX_DP_V_F_PORCH_CFG 0x58 33 #define ANALOGIX_DP_V_SYNC_WIDTH_CFG 0x5C 34 #define ANALOGIX_DP_V_B_PORCH_CFG 0x60 35 #define ANALOGIX_DP_TOTAL_PIXEL_CFG_L 0x64 36 #define ANALOGIX_DP_TOTAL_PIXEL_CFG_H 0x68 37 #define ANALOGIX_DP_ACTIVE_PIXEL_CFG_L 0x6C 38 #define ANALOGIX_DP_ACTIVE_PIXEL_CFG_H 0x70 39 #define ANALOGIX_DP_H_F_PORCH_CFG_L 0x74 40 #define ANALOGIX_DP_H_F_PORCH_CFG_H 0x78 41 #define ANALOGIX_DP_H_SYNC_CFG_L 0x7C 42 #define ANALOGIX_DP_H_SYNC_CFG_H 0x80 43 #define ANALOGIX_DP_H_B_PORCH_CFG_L 0x84 44 #define ANALOGIX_DP_H_B_PORCH_CFG_H 0x88 45 46 #define ANALOGIX_DP_PLL_REG_1 0xfc 47 #define ANALOGIX_DP_PLL_REG_2 0x9e4 48 #define ANALOGIX_DP_PLL_REG_3 0x9e8 49 #define ANALOGIX_DP_PLL_REG_4 0x9ec 50 #define ANALOGIX_DP_PLL_REG_5 0xa00 51 52 #define ANALOGIX_DP_BIAS 0x124 53 #define ANALOGIX_DP_PD 0x12c 54 55 #define ANALOGIX_DP_LANE_MAP 0x35C 56 57 #define ANALOGIX_DP_ANALOG_CTL_1 0x370 58 #define ANALOGIX_DP_ANALOG_CTL_2 0x374 59 #define ANALOGIX_DP_ANALOG_CTL_3 0x378 60 #define ANALOGIX_DP_PLL_FILTER_CTL_1 0x37C 61 #define ANALOGIX_DP_TX_AMP_TUNING_CTL 0x380 62 63 #define ANALOGIX_DP_AUX_HW_RETRY_CTL 0x390 64 65 #define ANALOGIX_DP_COMMON_INT_STA_1 0x3C4 66 #define ANALOGIX_DP_COMMON_INT_STA_2 0x3C8 67 #define ANALOGIX_DP_COMMON_INT_STA_3 0x3CC 68 #define ANALOGIX_DP_COMMON_INT_STA_4 0x3D0 69 #define ANALOGIX_DP_INT_STA 0x3DC 70 #define ANALOGIX_DP_COMMON_INT_MASK_1 0x3E0 71 #define ANALOGIX_DP_COMMON_INT_MASK_2 0x3E4 72 #define ANALOGIX_DP_COMMON_INT_MASK_3 0x3E8 73 #define ANALOGIX_DP_COMMON_INT_MASK_4 0x3EC 74 #define ANALOGIX_DP_INT_STA_MASK 0x3F8 75 #define ANALOGIX_DP_INT_CTL 0x3FC 76 77 #define ANALOGIX_DP_SYS_CTL_1 0x600 78 #define ANALOGIX_DP_SYS_CTL_2 0x604 79 #define ANALOGIX_DP_SYS_CTL_3 0x608 80 #define ANALOGIX_DP_SYS_CTL_4 0x60C 81 82 #define ANALOGIX_DP_PKT_SEND_CTL 0x640 83 #define ANALOGIX_DP_HDCP_CTL 0x648 84 85 #define ANALOGIX_DP_LINK_BW_SET 0x680 86 #define ANALOGIX_DP_LANE_COUNT_SET 0x684 87 #define ANALOGIX_DP_TRAINING_PTN_SET 0x688 88 #define ANALOGIX_DP_LN0_LINK_TRAINING_CTL 0x68C 89 #define ANALOGIX_DP_LN1_LINK_TRAINING_CTL 0x690 90 #define ANALOGIX_DP_LN2_LINK_TRAINING_CTL 0x694 91 #define ANALOGIX_DP_LN3_LINK_TRAINING_CTL 0x698 92 93 #define ANALOGIX_DP_DEBUG_CTL 0x6C0 94 #define ANALOGIX_DP_HPD_DEGLITCH_L 0x6C4 95 #define ANALOGIX_DP_HPD_DEGLITCH_H 0x6C8 96 #define ANALOGIX_DP_LINK_DEBUG_CTL 0x6E0 97 98 #define ANALOGIX_DP_M_VID_0 0x700 99 #define ANALOGIX_DP_M_VID_1 0x704 100 #define ANALOGIX_DP_M_VID_2 0x708 101 #define ANALOGIX_DP_N_VID_0 0x70C 102 #define ANALOGIX_DP_N_VID_1 0x710 103 #define ANALOGIX_DP_N_VID_2 0x714 104 105 #define ANALOGIX_DP_PLL_CTL 0x71C 106 #define ANALOGIX_DP_PHY_PD 0x720 107 #define ANALOGIX_DP_PHY_TEST 0x724 108 109 #define ANALOGIX_DP_VIDEO_FIFO_THRD 0x730 110 #define ANALOGIX_DP_AUDIO_MARGIN 0x73C 111 112 #define ANALOGIX_DP_M_VID_GEN_FILTER_TH 0x764 113 #define ANALOGIX_DP_M_AUD_GEN_FILTER_TH 0x778 114 #define ANALOGIX_DP_AUX_CH_STA 0x780 115 #define ANALOGIX_DP_AUX_CH_DEFER_CTL 0x788 116 #define ANALOGIX_DP_AUX_RX_COMM 0x78C 117 #define ANALOGIX_DP_BUFFER_DATA_CTL 0x790 118 #define ANALOGIX_DP_AUX_CH_CTL_1 0x794 119 #define ANALOGIX_DP_AUX_ADDR_7_0 0x798 120 #define ANALOGIX_DP_AUX_ADDR_15_8 0x79C 121 #define ANALOGIX_DP_AUX_ADDR_19_16 0x7A0 122 #define ANALOGIX_DP_AUX_CH_CTL_2 0x7A4 123 124 #define ANALOGIX_DP_BUF_DATA_0 0x7C0 125 126 #define ANALOGIX_DP_SOC_GENERAL_CTL 0x800 127 128 #define ANALOGIX_DP_LINK_POLICY 0x9D8 129 130 /* ANALOGIX_DP_TX_SW_RESET */ 131 #define RESET_DP_TX (0x1 << 0) 132 133 /* ANALOGIX_DP_FUNC_EN_1 */ 134 #define MASTER_VID_FUNC_EN_N (0x1 << 7) 135 #define SLAVE_VID_FUNC_EN_N (0x1 << 5) 136 #define AUD_FIFO_FUNC_EN_N (0x1 << 4) 137 #define AUD_FUNC_EN_N (0x1 << 3) 138 #define HDCP_FUNC_EN_N (0x1 << 2) 139 #define CRC_FUNC_EN_N (0x1 << 1) 140 #define SW_FUNC_EN_N (0x1 << 0) 141 142 /* ANALOGIX_DP_FUNC_EN_2 */ 143 #define SSC_FUNC_EN_N (0x1 << 7) 144 #define AUX_FUNC_EN_N (0x1 << 2) 145 #define SERDES_FIFO_FUNC_EN_N (0x1 << 1) 146 #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) 147 148 /* ANALOGIX_DP_VIDEO_CTL_1 */ 149 #define VIDEO_EN (0x1 << 7) 150 #define HDCP_VIDEO_MUTE (0x1 << 6) 151 152 /* ANALOGIX_DP_VIDEO_CTL_4 */ 153 #define BIST_EN (0x1 << 3) 154 #define BIST_WIDTH(x) (((x) & 0x1) << 2) 155 #define BIST_TYPE(x) (((x) & 0x3) << 0) 156 157 /* ANALOGIX_DP_VIDEO_CTL_1 */ 158 #define IN_D_RANGE_MASK (0x1 << 7) 159 #define IN_D_RANGE_SHIFT (7) 160 #define IN_D_RANGE_CEA (0x1 << 7) 161 #define IN_D_RANGE_VESA (0x0 << 7) 162 #define IN_BPC_MASK (0x7 << 4) 163 #define IN_BPC_SHIFT (4) 164 #define IN_BPC_12_BITS (0x3 << 4) 165 #define IN_BPC_10_BITS (0x2 << 4) 166 #define IN_BPC_8_BITS (0x1 << 4) 167 #define IN_BPC_6_BITS (0x0 << 4) 168 #define IN_COLOR_F_MASK (0x3 << 0) 169 #define IN_COLOR_F_SHIFT (0) 170 #define IN_COLOR_F_YCBCR444 (0x2 << 0) 171 #define IN_COLOR_F_YCBCR422 (0x1 << 0) 172 #define IN_COLOR_F_RGB (0x0 << 0) 173 174 /* ANALOGIX_DP_VIDEO_CTL_3 */ 175 #define IN_YC_COEFFI_MASK (0x1 << 7) 176 #define IN_YC_COEFFI_SHIFT (7) 177 #define IN_YC_COEFFI_ITU709 (0x1 << 7) 178 #define IN_YC_COEFFI_ITU601 (0x0 << 7) 179 #define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) 180 #define VID_CHK_UPDATE_TYPE_SHIFT (4) 181 #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) 182 #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) 183 184 /* ANALOGIX_DP_VIDEO_CTL_8 */ 185 #define VID_HRES_TH(x) (((x) & 0xf) << 4) 186 #define VID_VRES_TH(x) (((x) & 0xf) << 0) 187 188 /* ANALOGIX_DP_VIDEO_CTL_10 */ 189 #define FORMAT_SEL (0x1 << 4) 190 #define INTERACE_SCAN_CFG (0x1 << 2) 191 #define VSYNC_POLARITY_CFG (0x1 << 1) 192 #define HSYNC_POLARITY_CFG (0x1 << 0) 193 194 /* ANALOGIX_DP_TOTAL_LINE_CFG_L */ 195 #define TOTAL_LINE_CFG_L(x) (((x) & 0xff) << 0) 196 197 /* ANALOGIX_DP_TOTAL_LINE_CFG_H */ 198 #define TOTAL_LINE_CFG_H(x) (((x) & 0xf) << 0) 199 200 /* ANALOGIX_DP_ACTIVE_LINE_CFG_L */ 201 #define ACTIVE_LINE_CFG_L(x) (((x) & 0xff) << 0) 202 203 /* ANALOGIX_DP_ACTIVE_LINE_CFG_H */ 204 #define ACTIVE_LINE_CFG_H(x) (((x) & 0xf) << 0) 205 206 /* ANALOGIX_DP_V_F_PORCH_CFG */ 207 #define V_F_PORCH_CFG(x) (((x) & 0xff) << 0) 208 209 /* ANALOGIX_DP_V_SYNC_WIDTH_CFG */ 210 #define V_SYNC_WIDTH_CFG(x) (((x) & 0xff) << 0) 211 212 /* ANALOGIX_DP_V_B_PORCH_CFG */ 213 #define V_B_PORCH_CFG(x) (((x) & 0xff) << 0) 214 215 /* ANALOGIX_DP_TOTAL_PIXEL_CFG_L */ 216 #define TOTAL_PIXEL_CFG_L(x) (((x) & 0xff) << 0) 217 218 /* ANALOGIX_DP_TOTAL_PIXEL_CFG_H */ 219 #define TOTAL_PIXEL_CFG_H(x) (((x) & 0x3f) << 0) 220 221 /* ANALOGIX_DP_ACTIVE_PIXEL_CFG_L */ 222 #define ACTIVE_PIXEL_CFG_L(x) (((x) & 0xff) << 0) 223 224 /* ANALOGIX_DP_ACTIVE_PIXEL_CFG_H */ 225 #define ACTIVE_PIXEL_CFG_H(x) (((x) & 0x3f) << 0) 226 227 /* ANALOGIX_DP_H_F_PORCH_CFG_L */ 228 #define H_F_PORCH_CFG_L(x) (((x) & 0xff) << 0) 229 230 /* ANALOGIX_DP_H_F_PORCH_CFG_H */ 231 #define H_F_PORCH_CFG_H(x) (((x) & 0xf) << 0) 232 233 /* ANALOGIX_DP_H_SYNC_CFG_L */ 234 #define H_SYNC_CFG_L(x) (((x) & 0xff) << 0) 235 236 /* ANALOGIX_DP_H_SYNC_CFG_H */ 237 #define H_SYNC_CFG_H(x) (((x) & 0xf) << 0) 238 239 /* ANALOGIX_DP_H_B_PORCH_CFG_L */ 240 #define H_B_PORCH_CFG_L(x) (((x) & 0xff) << 0) 241 242 /* ANALOGIX_DP_H_B_PORCH_CFG_H */ 243 #define H_B_PORCH_CFG_H(x) (((x) & 0xf) << 0) 244 245 /* ANALOGIX_DP_PLL_REG_1 */ 246 #define REF_CLK_24M (0x1 << 0) 247 #define REF_CLK_27M (0x0 << 0) 248 #define REF_CLK_MASK (0x1 << 0) 249 250 /* ANALOGIX_DP_LANE_MAP */ 251 #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) 252 #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) 253 #define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6) 254 #define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6) 255 #define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4) 256 #define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4) 257 #define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4) 258 #define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4) 259 #define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2) 260 #define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2) 261 #define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2) 262 #define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2) 263 #define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0) 264 #define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0) 265 #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) 266 #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) 267 268 /* ANALOGIX_DP_ANALOG_CTL_1 */ 269 #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) 270 271 /* ANALOGIX_DP_ANALOG_CTL_2 */ 272 #define SEL_24M (0x1 << 3) 273 #define TX_DVDD_BIT_1_0625V (0x4 << 0) 274 275 /* ANALOGIX_DP_ANALOG_CTL_3 */ 276 #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) 277 #define VCO_BIT_600_MICRO (0x5 << 0) 278 279 /* ANALOGIX_DP_PLL_FILTER_CTL_1 */ 280 #define PD_RING_OSC (0x1 << 6) 281 #define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) 282 #define TX_CUR1_2X (0x1 << 2) 283 #define TX_CUR_16_MA (0x3 << 0) 284 285 /* ANALOGIX_DP_TX_AMP_TUNING_CTL */ 286 #define CH3_AMP_400_MV (0x0 << 24) 287 #define CH2_AMP_400_MV (0x0 << 16) 288 #define CH1_AMP_400_MV (0x0 << 8) 289 #define CH0_AMP_400_MV (0x0 << 0) 290 291 /* ANALOGIX_DP_AUX_HW_RETRY_CTL */ 292 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) 293 #define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) 294 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) 295 #define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3) 296 #define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3) 297 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) 298 #define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0) 299 300 /* ANALOGIX_DP_COMMON_INT_STA_1 */ 301 #define VSYNC_DET (0x1 << 7) 302 #define PLL_LOCK_CHG (0x1 << 6) 303 #define SPDIF_ERR (0x1 << 5) 304 #define SPDIF_UNSTBL (0x1 << 4) 305 #define VID_FORMAT_CHG (0x1 << 3) 306 #define AUD_CLK_CHG (0x1 << 2) 307 #define VID_CLK_CHG (0x1 << 1) 308 #define SW_INT (0x1 << 0) 309 310 /* ANALOGIX_DP_COMMON_INT_STA_2 */ 311 #define ENC_EN_CHG (0x1 << 6) 312 #define HW_BKSV_RDY (0x1 << 3) 313 #define HW_SHA_DONE (0x1 << 2) 314 #define HW_AUTH_STATE_CHG (0x1 << 1) 315 #define HW_AUTH_DONE (0x1 << 0) 316 317 /* ANALOGIX_DP_COMMON_INT_STA_3 */ 318 #define AFIFO_UNDER (0x1 << 7) 319 #define AFIFO_OVER (0x1 << 6) 320 #define R0_CHK_FLAG (0x1 << 5) 321 322 /* ANALOGIX_DP_COMMON_INT_STA_4 */ 323 #define PSR_ACTIVE (0x1 << 7) 324 #define PSR_INACTIVE (0x1 << 6) 325 #define SPDIF_BI_PHASE_ERR (0x1 << 5) 326 #define HOTPLUG_CHG (0x1 << 2) 327 #define HPD_LOST (0x1 << 1) 328 #define PLUG (0x1 << 0) 329 330 /* ANALOGIX_DP_INT_STA */ 331 #define INT_HPD (0x1 << 6) 332 #define HW_TRAINING_FINISH (0x1 << 5) 333 #define RPLY_RECEIV (0x1 << 1) 334 #define AUX_ERR (0x1 << 0) 335 336 /* ANALOGIX_DP_INT_CTL */ 337 #define SOFT_INT_CTRL (0x1 << 2) 338 #define INT_POL1 (0x1 << 1) 339 #define INT_POL0 (0x1 << 0) 340 341 /* ANALOGIX_DP_SYS_CTL_1 */ 342 #define DET_STA (0x1 << 2) 343 #define FORCE_DET (0x1 << 1) 344 #define DET_CTRL (0x1 << 0) 345 346 /* ANALOGIX_DP_SYS_CTL_2 */ 347 #define CHA_CRI(x) (((x) & 0xf) << 4) 348 #define CHA_STA (0x1 << 2) 349 #define FORCE_CHA (0x1 << 1) 350 #define CHA_CTRL (0x1 << 0) 351 352 /* ANALOGIX_DP_SYS_CTL_3 */ 353 #define HPD_STATUS (0x1 << 6) 354 #define F_HPD (0x1 << 5) 355 #define HPD_CTRL (0x1 << 4) 356 #define HDCP_RDY (0x1 << 3) 357 #define STRM_VALID (0x1 << 2) 358 #define F_VALID (0x1 << 1) 359 #define VALID_CTRL (0x1 << 0) 360 361 /* ANALOGIX_DP_SYS_CTL_4 */ 362 #define FIX_M_AUD (0x1 << 4) 363 #define ENHANCED (0x1 << 3) 364 #define FIX_M_VID (0x1 << 2) 365 #define M_VID_UPDATE_CTRL (0x3 << 0) 366 367 /* ANALOGIX_DP_TRAINING_PTN_SET */ 368 #define SCRAMBLER_TYPE (0x1 << 9) 369 #define HW_LINK_TRAINING_PATTERN (0x1 << 8) 370 #define SCRAMBLING_DISABLE (0x1 << 5) 371 #define SCRAMBLING_ENABLE (0x0 << 5) 372 #define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2) 373 #define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) 374 #define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) 375 #define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) 376 #define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) 377 #define SW_TRAINING_PATTERN_SET_PTN3 (0x3 << 0) 378 #define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) 379 #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) 380 #define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) 381 382 /* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */ 383 #define PRE_EMPHASIS_SET_MASK (0x3 << 3) 384 #define PRE_EMPHASIS_SET_SHIFT (3) 385 386 /* ANALOGIX_DP_DEBUG_CTL */ 387 #define PLL_LOCK (0x1 << 4) 388 #define F_PLL_LOCK (0x1 << 3) 389 #define PLL_LOCK_CTRL (0x1 << 2) 390 #define PN_INV (0x1 << 0) 391 392 /* ANALOGIX_DP_PLL_CTL */ 393 #define DP_PLL_PD (0x1 << 7) 394 #define DP_PLL_RESET (0x1 << 6) 395 #define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) 396 #define DP_PLL_REF_BIT_1_1250V (0x5 << 0) 397 #define DP_PLL_REF_BIT_1_2500V (0x7 << 0) 398 399 /* ANALOGIX_DP_PHY_PD */ 400 #define DP_PHY_PD (0x1 << 5) 401 #define AUX_PD (0x1 << 4) 402 #define CH3_PD (0x1 << 3) 403 #define CH2_PD (0x1 << 2) 404 #define CH1_PD (0x1 << 1) 405 #define CH0_PD (0x1 << 0) 406 407 /* ANALOGIX_DP_PHY_TEST */ 408 #define MACRO_RST (0x1 << 5) 409 #define CH1_TEST (0x1 << 1) 410 #define CH0_TEST (0x1 << 0) 411 412 /* ANALOGIX_DP_AUX_CH_STA */ 413 #define AUX_BUSY (0x1 << 4) 414 #define AUX_STATUS_MASK (0xf << 0) 415 416 /* ANALOGIX_DP_AUX_CH_DEFER_CTL */ 417 #define DEFER_CTRL_EN (0x1 << 7) 418 #define DEFER_COUNT(x) (((x) & 0x7f) << 0) 419 420 /* ANALOGIX_DP_AUX_RX_COMM */ 421 #define AUX_RX_COMM_I2C_DEFER (0x2 << 2) 422 #define AUX_RX_COMM_AUX_DEFER (0x2 << 0) 423 424 /* ANALOGIX_DP_BUFFER_DATA_CTL */ 425 #define BUF_CLR (0x1 << 7) 426 #define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0) 427 428 /* ANALOGIX_DP_AUX_CH_CTL_1 */ 429 #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) 430 #define AUX_TX_COMM_MASK (0xf << 0) 431 #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) 432 #define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) 433 #define AUX_TX_COMM_MOT (0x1 << 2) 434 #define AUX_TX_COMM_WRITE (0x0 << 0) 435 #define AUX_TX_COMM_READ (0x1 << 0) 436 437 /* ANALOGIX_DP_AUX_ADDR_7_0 */ 438 #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) 439 440 /* ANALOGIX_DP_AUX_ADDR_15_8 */ 441 #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) 442 443 /* ANALOGIX_DP_AUX_ADDR_19_16 */ 444 #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) 445 446 /* ANALOGIX_DP_AUX_CH_CTL_2 */ 447 #define ADDR_ONLY (0x1 << 1) 448 #define AUX_EN (0x1 << 0) 449 450 /* ANALOGIX_DP_SOC_GENERAL_CTL */ 451 #define AUDIO_MODE_SPDIF_MODE (0x1 << 8) 452 #define AUDIO_MODE_MASTER_MODE (0x0 << 8) 453 #define MASTER_VIDEO_INTERLACE_EN (0x1 << 4) 454 #define VIDEO_MASTER_CLK_SEL (0x1 << 2) 455 #define VIDEO_MASTER_MODE_EN (0x1 << 1) 456 #define VIDEO_MODE_MASK (0x1 << 0) 457 #define VIDEO_MODE_SLAVE_MODE (0x1 << 0) 458 #define VIDEO_MODE_MASTER_MODE (0x0 << 0) 459 460 /* ANALOGIX_DP_LINK_POLICY */ 461 #define ALTERNATE_SR_ENABLE (0x1 << 7) 462 463 #define DP_TIMEOUT_LOOP_COUNT 100 464 #define MAX_CR_LOOP 5 465 #define MAX_EQ_LOOP 5 466 467 /* I2C EDID Chip ID, Slave Address */ 468 #define I2C_EDID_DEVICE_ADDR 0x50 469 #define I2C_E_EDID_DEVICE_ADDR 0x30 470 471 #define EDID_BLOCK_LENGTH 0x80 472 #define EDID_HEADER_PATTERN 0x00 473 #define EDID_EXTENSION_FLAG 0x7e 474 #define EDID_CHECKSUM 0x7f 475 476 /* DP_MAX_LANE_COUNT */ 477 #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1) 478 #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f) 479 480 /* DP_LANE_COUNT_SET */ 481 #define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f) 482 483 /* DP_TRAINING_LANE0_SET */ 484 #define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3) 485 #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3) 486 #define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0) 487 #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3) 488 489 /* Supported link rate in eDP 1.4 */ 490 #define EDP_LINK_BW_2_16 0x08 491 #define EDP_LINK_BW_2_43 0x09 492 #define EDP_LINK_BW_3_24 0x0c 493 #define EDP_LINK_BW_4_32 0x10 494 495 enum link_lane_count_type { 496 LANE_COUNT1 = 1, 497 LANE_COUNT2 = 2, 498 LANE_COUNT4 = 4 499 }; 500 501 enum link_training_state { 502 START, 503 CLOCK_RECOVERY, 504 EQUALIZER_TRAINING, 505 FINISHED, 506 FAILED 507 }; 508 509 enum voltage_swing_level { 510 VOLTAGE_LEVEL_0, 511 VOLTAGE_LEVEL_1, 512 VOLTAGE_LEVEL_2, 513 VOLTAGE_LEVEL_3, 514 }; 515 516 enum pre_emphasis_level { 517 PRE_EMPHASIS_LEVEL_0, 518 PRE_EMPHASIS_LEVEL_1, 519 PRE_EMPHASIS_LEVEL_2, 520 PRE_EMPHASIS_LEVEL_3, 521 }; 522 523 enum pattern_set { 524 PRBS7, 525 D10_2, 526 TRAINING_PTN1, 527 TRAINING_PTN2, 528 TRAINING_PTN3, 529 DP_NONE 530 }; 531 532 enum color_space { 533 COLOR_RGB, 534 COLOR_YCBCR422, 535 COLOR_YCBCR444 536 }; 537 538 enum color_depth { 539 COLOR_6, 540 COLOR_8, 541 COLOR_10, 542 COLOR_12 543 }; 544 545 enum color_coefficient { 546 COLOR_YCBCR601, 547 COLOR_YCBCR709 548 }; 549 550 enum dynamic_range { 551 VESA, 552 CEA 553 }; 554 555 enum pll_status { 556 PLL_UNLOCKED, 557 PLL_LOCKED 558 }; 559 560 enum clock_recovery_m_value_type { 561 CALCULATED_M, 562 REGISTER_M 563 }; 564 565 enum video_timing_recognition_type { 566 VIDEO_TIMING_FROM_CAPTURE, 567 VIDEO_TIMING_FROM_REGISTER 568 }; 569 570 enum analog_power_block { 571 AUX_BLOCK, 572 CH0_BLOCK, 573 CH1_BLOCK, 574 CH2_BLOCK, 575 CH3_BLOCK, 576 ANALOG_TOTAL, 577 POWER_ALL 578 }; 579 580 enum dp_irq_type { 581 DP_IRQ_TYPE_HP_CABLE_IN = BIT(0), 582 DP_IRQ_TYPE_HP_CABLE_OUT = BIT(1), 583 DP_IRQ_TYPE_HP_CHANGE = BIT(2), 584 DP_IRQ_TYPE_UNKNOWN = BIT(3), 585 }; 586 587 struct video_info { 588 char *name; 589 struct drm_display_mode mode; 590 591 bool h_sync_polarity; 592 bool v_sync_polarity; 593 bool interlaced; 594 595 enum color_space color_space; 596 enum dynamic_range dynamic_range; 597 enum color_coefficient ycbcr_coeff; 598 enum color_depth color_depth; 599 600 int max_link_rate; 601 enum link_lane_count_type max_lane_count; 602 603 bool force_stream_valid; 604 605 u32 bpc; 606 }; 607 608 struct link_train { 609 int eq_loop; 610 int cr_loop[4]; 611 612 u8 link_rate; 613 u8 lane_count; 614 u8 training_lane[4]; 615 bool ssc; 616 617 enum link_training_state lt_state; 618 }; 619 620 enum analogix_dp_devtype { 621 EXYNOS_DP, 622 ROCKCHIP_DP, 623 }; 624 625 enum analogix_dp_sub_devtype { 626 RK3288_DP, 627 RK3368_EDP, 628 RK3399_EDP, 629 RK3568_EDP, 630 RK3576_EDP, 631 RK3588_EDP 632 }; 633 634 struct analogix_dp_plat_data { 635 enum analogix_dp_devtype dev_type; 636 enum analogix_dp_sub_devtype subdev_type; 637 bool ssc; 638 bool support_dp_mode; 639 u8 max_bpc; 640 }; 641 642 struct analogix_dp_device { 643 struct rockchip_connector connector; 644 int id; 645 int nr_link_rate_table; 646 int link_rate_table[DP_MAX_SUPPORTED_RATES]; 647 int link_rate_select; 648 struct udevice *dev; 649 void *reg_base; 650 struct regmap *grf; 651 struct phy phy; 652 struct reset_ctl_bulk resets; 653 struct gpio_desc hpd_gpio; 654 bool force_hpd; 655 struct video_info video_info; 656 struct link_train link_train; 657 struct drm_display_mode *mode; 658 struct analogix_dp_plat_data plat_data; 659 unsigned char edid[EDID_BLOCK_LENGTH * 2]; 660 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 661 bool video_bist_enable; 662 u32 lane_map[4]; 663 struct drm_dp_aux aux; 664 const struct analogix_dp_output_format *output_fmt; 665 bool dp_mode; 666 }; 667 668 struct analogix_dp_output_format { 669 u32 bus_format; 670 u32 color_format; 671 u8 bpc; 672 }; 673 674 /* analogix_dp_reg.c */ 675 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable); 676 void analogix_dp_stop_video(struct analogix_dp_device *dp); 677 void analogix_dp_init_analog_param(struct analogix_dp_device *dp); 678 void analogix_dp_init_interrupt(struct analogix_dp_device *dp); 679 void analogix_dp_reset(struct analogix_dp_device *dp); 680 void analogix_dp_swreset(struct analogix_dp_device *dp); 681 void analogix_dp_config_interrupt(struct analogix_dp_device *dp); 682 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp); 683 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp); 684 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp); 685 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable); 686 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 687 enum analog_power_block block, 688 bool enable); 689 void analogix_dp_init_analog_func(struct analogix_dp_device *dp); 690 void analogix_dp_init_hpd(struct analogix_dp_device *dp); 691 void analogix_dp_force_hpd(struct analogix_dp_device *dp); 692 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp); 693 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp); 694 void analogix_dp_reset_aux(struct analogix_dp_device *dp); 695 void analogix_dp_init_aux(struct analogix_dp_device *dp); 696 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp); 697 int analogix_dp_detect(struct analogix_dp_device *dp); 698 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp); 699 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp); 700 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp, 701 unsigned int device_addr, 702 unsigned int reg_addr); 703 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp, 704 unsigned int device_addr, 705 unsigned int reg_addr, 706 unsigned int *data); 707 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp, 708 unsigned int device_addr, 709 unsigned int reg_addr, 710 unsigned int count, 711 unsigned char edid[]); 712 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype); 713 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype); 714 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count); 715 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count); 716 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, 717 bool enable); 718 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, 719 enum pattern_set pattern); 720 void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp); 721 u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane); 722 void analogix_dp_reset_macro(struct analogix_dp_device *dp); 723 void analogix_dp_init_video(struct analogix_dp_device *dp); 724 725 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp); 726 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp); 727 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, 728 enum clock_recovery_m_value_type type, 729 u32 m_value, 730 u32 n_value); 731 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type); 732 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, 733 bool enable); 734 void analogix_dp_start_video(struct analogix_dp_device *dp); 735 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp); 736 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp); 737 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp); 738 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp); 739 bool analogix_dp_ssc_supported(struct analogix_dp_device *dp); 740 void analogix_dp_set_video_format(struct analogix_dp_device *dp, 741 const struct drm_display_mode *mode); 742 void analogix_dp_video_bist_enable(struct analogix_dp_device *dp); 743 ssize_t analogix_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg); 744 void analogix_dp_enable_assr_mode(struct analogix_dp_device *dp, bool enable); 745 bool analogix_dp_get_assr_mode(struct analogix_dp_device *dp); 746 747 #endif /* __DRM_ANALOGIX_DP__ */ 748