1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <dm/device.h> 14 #include <dm/of_access.h> 15 #include <dm/read.h> 16 #include <linux/bitfield.h> 17 #include <linux/list.h> 18 #include <syscon.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <asm/gpio.h> 21 22 #include "rockchip_display.h" 23 #include "rockchip_crtc.h" 24 #include "rockchip_connector.h" 25 #include "rockchip_panel.h" 26 #include "analogix_dp.h" 27 28 #define RK3588_GRF_VO1_CON0 0x0000 29 #define EDP_MODE BIT(0) 30 #define RK3588_GRF_VO1_CON1 0x0004 31 32 /** 33 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips 34 * @lcdsel_grf_reg: grf register offset of lcdc select 35 * @lcdsel_big: reg value of selecting vop big for eDP 36 * @lcdsel_lit: reg value of selecting vop little for eDP 37 * @chip_type: specific chip type 38 * @ssc: check if SSC is supported by source 39 */ 40 struct rockchip_dp_chip_data { 41 u32 lcdsel_grf_reg; 42 u32 lcdsel_big; 43 u32 lcdsel_lit; 44 u32 chip_type; 45 bool ssc; 46 47 u32 max_link_rate; 48 u32 max_lane_count; 49 }; 50 51 static void 52 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, 53 bool enable) 54 { 55 u8 data; 56 57 analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data); 58 59 if (enable) 60 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 61 DP_LANE_COUNT_ENHANCED_FRAME_EN | 62 DPCD_LANE_COUNT_SET(data)); 63 else 64 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 65 DPCD_LANE_COUNT_SET(data)); 66 } 67 68 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp) 69 { 70 u8 data; 71 int retval; 72 73 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 74 retval = DPCD_ENHANCED_FRAME_CAP(data); 75 76 return retval; 77 } 78 79 static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) 80 { 81 u8 data; 82 83 data = analogix_dp_is_enhanced_mode_available(dp); 84 analogix_dp_enable_rx_to_enhanced_mode(dp, data); 85 analogix_dp_enable_enhanced_mode(dp, data); 86 } 87 88 static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) 89 { 90 analogix_dp_set_training_pattern(dp, DP_NONE); 91 92 analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET, 93 DP_TRAINING_PATTERN_DISABLE); 94 } 95 96 static int analogix_dp_link_start(struct analogix_dp_device *dp) 97 { 98 u8 buf[4]; 99 int lane, lane_count, retval; 100 101 lane_count = dp->link_train.lane_count; 102 103 dp->link_train.lt_state = CLOCK_RECOVERY; 104 dp->link_train.eq_loop = 0; 105 106 for (lane = 0; lane < lane_count; lane++) 107 dp->link_train.cr_loop[lane] = 0; 108 109 /* Set link rate and count as you want to establish*/ 110 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 111 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 112 113 /* Setup RX configuration */ 114 buf[0] = dp->link_train.link_rate; 115 buf[1] = dp->link_train.lane_count; 116 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf); 117 if (retval) 118 return retval; 119 120 /* Spread AMP if required, enable 8b/10b coding */ 121 buf[0] = analogix_dp_ssc_supported(dp) ? DP_SPREAD_AMP_0_5 : 0; 122 buf[1] = DP_SET_ANSI_8B10B; 123 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_DOWNSPREAD_CTRL, 124 2, buf); 125 if (retval < 0) 126 return retval; 127 128 /* Set TX voltage-swing and pre-emphasis to minimum */ 129 for (lane = 0; lane < lane_count; lane++) 130 dp->link_train.training_lane[lane] = 131 DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | 132 DP_TRAIN_PRE_EMPH_LEVEL_0; 133 analogix_dp_set_lane_link_training(dp); 134 135 /* Set training pattern 1 */ 136 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 137 138 /* Set RX training pattern */ 139 retval = analogix_dp_write_byte_to_dpcd(dp, 140 DP_TRAINING_PATTERN_SET, 141 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); 142 if (retval) 143 return retval; 144 145 for (lane = 0; lane < lane_count; lane++) 146 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 147 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 148 149 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 150 lane_count, buf); 151 152 return retval; 153 } 154 155 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) 156 { 157 int shift = (lane & 1) * 4; 158 u8 link_value = link_status[lane >> 1]; 159 160 return (link_value >> shift) & 0xf; 161 } 162 163 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) 164 { 165 int lane; 166 u8 lane_status; 167 168 for (lane = 0; lane < lane_count; lane++) { 169 lane_status = analogix_dp_get_lane_status(link_status, lane); 170 if ((lane_status & DP_LANE_CR_DONE) == 0) 171 return -EINVAL; 172 } 173 return 0; 174 } 175 176 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, 177 int lane_count) 178 { 179 int lane; 180 u8 lane_status; 181 182 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) 183 return -EINVAL; 184 185 for (lane = 0; lane < lane_count; lane++) { 186 lane_status = analogix_dp_get_lane_status(link_status, lane); 187 lane_status &= DP_CHANNEL_EQ_BITS; 188 if (lane_status != DP_CHANNEL_EQ_BITS) 189 return -EINVAL; 190 } 191 192 return 0; 193 } 194 195 static unsigned char 196 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) 197 { 198 int shift = (lane & 1) * 4; 199 u8 link_value = adjust_request[lane >> 1]; 200 201 return (link_value >> shift) & 0x3; 202 } 203 204 static unsigned char analogix_dp_get_adjust_request_pre_emphasis( 205 u8 adjust_request[2], 206 int lane) 207 { 208 int shift = (lane & 1) * 4; 209 u8 link_value = adjust_request[lane >> 1]; 210 211 return ((link_value >> shift) & 0xc) >> 2; 212 } 213 214 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) 215 { 216 analogix_dp_training_pattern_dis(dp); 217 analogix_dp_set_enhanced_mode(dp); 218 219 dp->link_train.lt_state = FAILED; 220 } 221 222 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, 223 u8 adjust_request[2]) 224 { 225 int lane, lane_count; 226 u8 voltage_swing, pre_emphasis, training_lane; 227 228 lane_count = dp->link_train.lane_count; 229 for (lane = 0; lane < lane_count; lane++) { 230 voltage_swing = analogix_dp_get_adjust_request_voltage( 231 adjust_request, lane); 232 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 233 adjust_request, lane); 234 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | 235 DPCD_PRE_EMPHASIS_SET(pre_emphasis); 236 237 if (voltage_swing == VOLTAGE_LEVEL_3) 238 training_lane |= DP_TRAIN_MAX_SWING_REACHED; 239 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) 240 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 241 242 dp->link_train.training_lane[lane] = training_lane; 243 } 244 } 245 246 static bool analogix_dp_tps3_supported(struct analogix_dp_device *dp) 247 { 248 bool source_tps3_supported, sink_tps3_supported; 249 u8 dpcd = 0; 250 251 source_tps3_supported = 252 dp->video_info.max_link_rate == DP_LINK_BW_5_4; 253 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &dpcd); 254 sink_tps3_supported = dpcd & DP_TPS3_SUPPORTED; 255 256 return source_tps3_supported && sink_tps3_supported; 257 } 258 259 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) 260 { 261 int lane, lane_count, retval; 262 u8 voltage_swing, pre_emphasis, training_lane; 263 u8 link_status[2], adjust_request[2]; 264 u8 training_pattern = TRAINING_PTN2; 265 266 drm_dp_link_train_clock_recovery_delay(dp->dpcd); 267 268 lane_count = dp->link_train.lane_count; 269 270 retval = analogix_dp_read_bytes_from_dpcd(dp, 271 DP_LANE0_1_STATUS, 2, link_status); 272 if (retval) 273 return retval; 274 275 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { 276 if (analogix_dp_tps3_supported(dp)) 277 training_pattern = TRAINING_PTN3; 278 279 /* set training pattern for EQ */ 280 analogix_dp_set_training_pattern(dp, training_pattern); 281 282 retval = analogix_dp_write_byte_to_dpcd(dp, 283 DP_TRAINING_PATTERN_SET, 284 (training_pattern == TRAINING_PTN3 ? 285 DP_TRAINING_PATTERN_3 : DP_TRAINING_PATTERN_2)); 286 if (retval) 287 return retval; 288 289 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 290 dp->link_train.lt_state = EQUALIZER_TRAINING; 291 292 return 0; 293 } else { 294 retval = analogix_dp_read_bytes_from_dpcd(dp, 295 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 296 if (retval) 297 return retval; 298 299 for (lane = 0; lane < lane_count; lane++) { 300 training_lane = analogix_dp_get_lane_link_training( 301 dp, lane); 302 voltage_swing = analogix_dp_get_adjust_request_voltage( 303 adjust_request, lane); 304 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 305 adjust_request, lane); 306 307 if (DPCD_VOLTAGE_SWING_GET(training_lane) == 308 voltage_swing && 309 DPCD_PRE_EMPHASIS_GET(training_lane) == 310 pre_emphasis) 311 dp->link_train.cr_loop[lane]++; 312 313 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || 314 voltage_swing == VOLTAGE_LEVEL_3 || 315 pre_emphasis == PRE_EMPHASIS_LEVEL_3) { 316 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", 317 dp->link_train.cr_loop[lane], 318 voltage_swing, pre_emphasis); 319 analogix_dp_reduce_link_rate(dp); 320 return -EIO; 321 } 322 } 323 } 324 325 analogix_dp_get_adjust_training_lane(dp, adjust_request); 326 analogix_dp_set_lane_link_training(dp); 327 328 retval = analogix_dp_write_bytes_to_dpcd(dp, 329 DP_TRAINING_LANE0_SET, lane_count, 330 dp->link_train.training_lane); 331 if (retval) 332 return retval; 333 334 return retval; 335 } 336 337 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) 338 { 339 int lane_count, retval; 340 u32 reg; 341 u8 link_align, link_status[2], adjust_request[2]; 342 343 drm_dp_link_train_channel_eq_delay(dp->dpcd); 344 345 lane_count = dp->link_train.lane_count; 346 347 retval = analogix_dp_read_bytes_from_dpcd(dp, 348 DP_LANE0_1_STATUS, 2, link_status); 349 if (retval) 350 return retval; 351 352 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { 353 analogix_dp_reduce_link_rate(dp); 354 return -EIO; 355 } 356 357 retval = analogix_dp_read_byte_from_dpcd(dp, 358 DP_LANE_ALIGN_STATUS_UPDATED, &link_align); 359 if (retval) 360 return retval; 361 362 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { 363 /* traing pattern Set to Normal */ 364 analogix_dp_training_pattern_dis(dp); 365 366 printf("Link Training success!\n"); 367 368 analogix_dp_get_link_bandwidth(dp, ®); 369 dp->link_train.link_rate = reg; 370 analogix_dp_get_lane_count(dp, ®); 371 dp->link_train.lane_count = reg; 372 373 printf("final link rate = 0x%.2x, lane count = 0x%.2x\n", 374 dp->link_train.link_rate, dp->link_train.lane_count); 375 376 /* set enhanced mode if available */ 377 analogix_dp_set_enhanced_mode(dp); 378 dp->link_train.lt_state = FINISHED; 379 380 return 0; 381 } 382 383 /* not all locked */ 384 dp->link_train.eq_loop++; 385 386 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 387 dev_dbg(dp->dev, "EQ Max loop\n"); 388 analogix_dp_reduce_link_rate(dp); 389 return -EIO; 390 } 391 392 retval = analogix_dp_read_bytes_from_dpcd(dp, 393 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 394 if (retval) 395 return retval; 396 397 analogix_dp_get_adjust_training_lane(dp, adjust_request); 398 analogix_dp_set_lane_link_training(dp); 399 400 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 401 lane_count, dp->link_train.training_lane); 402 403 return retval; 404 } 405 406 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, 407 u8 *bandwidth) 408 { 409 u8 data; 410 411 /* 412 * For DP rev.1.1, Maximum link rate of Main Link lanes 413 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps 414 * For DP rev.1.2, Maximum link rate of Main Link lanes 415 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 416 */ 417 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); 418 *bandwidth = data; 419 } 420 421 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, 422 u8 *lane_count) 423 { 424 u8 data; 425 426 /* 427 * For DP rev.1.1, Maximum number of Main Link lanes 428 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 429 */ 430 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 431 *lane_count = DPCD_MAX_LANE_COUNT(data); 432 } 433 434 static int analogix_dp_init_training(struct analogix_dp_device *dp, 435 enum link_lane_count_type max_lane, 436 int max_rate) 437 { 438 u8 dpcd; 439 440 /* 441 * MACRO_RST must be applied after the PLL_LOCK to avoid 442 * the DP inter pair skew issue for at least 10 us 443 */ 444 analogix_dp_reset_macro(dp); 445 446 /* Initialize by reading RX's DPCD */ 447 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); 448 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); 449 450 if ((dp->link_train.link_rate != DP_LINK_BW_1_62) && 451 (dp->link_train.link_rate != DP_LINK_BW_2_7) && 452 (dp->link_train.link_rate != DP_LINK_BW_5_4)) { 453 dev_err(dp->dev, "failed to get Rx Max Link Rate\n"); 454 return -ENODEV; 455 } 456 457 if (dp->link_train.lane_count == 0) { 458 dev_err(dp->dev, "failed to get Rx Max Lane Count\n"); 459 return -ENODEV; 460 } 461 462 /* Setup TX lane count & rate */ 463 if (dp->link_train.lane_count > max_lane) 464 dp->link_train.lane_count = max_lane; 465 if (dp->link_train.link_rate > max_rate) 466 dp->link_train.link_rate = max_rate; 467 468 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_DOWNSPREAD, &dpcd); 469 dp->link_train.ssc = !!(dpcd & DP_MAX_DOWNSPREAD_0_5); 470 471 /* All DP analog module power up */ 472 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 473 474 return 0; 475 } 476 477 static int analogix_dp_sw_link_training(struct analogix_dp_device *dp) 478 { 479 int retval = 0, training_finished = 0; 480 481 dp->link_train.lt_state = START; 482 483 /* Process here */ 484 while (!retval && !training_finished) { 485 switch (dp->link_train.lt_state) { 486 case START: 487 retval = analogix_dp_link_start(dp); 488 if (retval) 489 dev_err(dp->dev, "LT link start failed!\n"); 490 break; 491 case CLOCK_RECOVERY: 492 retval = analogix_dp_process_clock_recovery(dp); 493 if (retval) 494 dev_err(dp->dev, "LT CR failed!\n"); 495 break; 496 case EQUALIZER_TRAINING: 497 retval = analogix_dp_process_equalizer_training(dp); 498 if (retval) 499 dev_err(dp->dev, "LT EQ failed!\n"); 500 break; 501 case FINISHED: 502 training_finished = 1; 503 break; 504 case FAILED: 505 return -EREMOTEIO; 506 } 507 } 508 509 return retval; 510 } 511 512 static int analogix_dp_set_link_train(struct analogix_dp_device *dp, 513 u32 count, u32 bwtype) 514 { 515 int i, ret; 516 517 for (i = 0; i < 5; i++) { 518 ret = analogix_dp_init_training(dp, count, bwtype); 519 if (ret < 0) { 520 dev_err(dp->dev, "failed to init training\n"); 521 return ret; 522 } 523 524 ret = analogix_dp_sw_link_training(dp); 525 if (!ret) 526 break; 527 } 528 529 return ret; 530 } 531 532 static int analogix_dp_config_video(struct analogix_dp_device *dp) 533 { 534 int timeout_loop = 0; 535 int done_count = 0; 536 537 analogix_dp_config_video_slave_mode(dp); 538 539 analogix_dp_set_video_color_format(dp); 540 541 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 542 dev_err(dp->dev, "PLL is not locked yet.\n"); 543 return -EINVAL; 544 } 545 546 for (;;) { 547 timeout_loop++; 548 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) 549 break; 550 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 551 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 552 return -ETIMEDOUT; 553 } 554 555 udelay(2); 556 } 557 558 /* Set to use the register calculated M/N video */ 559 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); 560 561 /* For video bist, Video timing must be generated by register */ 562 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE); 563 564 /* Disable video mute */ 565 analogix_dp_enable_video_mute(dp, 0); 566 567 /* Configure video slave mode */ 568 analogix_dp_enable_video_master(dp, 0); 569 570 /* Enable video input */ 571 analogix_dp_start_video(dp); 572 573 timeout_loop = 0; 574 575 for (;;) { 576 timeout_loop++; 577 if (analogix_dp_is_video_stream_on(dp) == 0) { 578 done_count++; 579 if (done_count > 10) 580 break; 581 } else if (done_count) { 582 done_count = 0; 583 } 584 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 585 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 586 return -ETIMEDOUT; 587 } 588 589 udelay(1001); 590 } 591 592 return 0; 593 } 594 595 static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, 596 bool enable) 597 { 598 u8 data; 599 600 if (enable) { 601 analogix_dp_enable_scrambling(dp); 602 603 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 604 &data); 605 analogix_dp_write_byte_to_dpcd(dp, 606 DP_TRAINING_PATTERN_SET, 607 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); 608 } else { 609 analogix_dp_disable_scrambling(dp); 610 611 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 612 &data); 613 analogix_dp_write_byte_to_dpcd(dp, 614 DP_TRAINING_PATTERN_SET, 615 (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); 616 } 617 } 618 619 static void analogix_dp_init_dp(struct analogix_dp_device *dp) 620 { 621 analogix_dp_reset(dp); 622 623 analogix_dp_swreset(dp); 624 625 analogix_dp_init_analog_param(dp); 626 analogix_dp_init_interrupt(dp); 627 628 /* SW defined function Normal operation */ 629 analogix_dp_enable_sw_function(dp); 630 631 analogix_dp_config_interrupt(dp); 632 analogix_dp_init_analog_func(dp); 633 634 analogix_dp_init_hpd(dp); 635 analogix_dp_init_aux(dp); 636 } 637 638 static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data) 639 { 640 int i; 641 unsigned char sum = 0; 642 643 for (i = 0; i < EDID_BLOCK_LENGTH; i++) 644 sum = sum + edid_data[i]; 645 646 return sum; 647 } 648 649 static int analogix_dp_read_edid(struct analogix_dp_device *dp) 650 { 651 unsigned char *edid = dp->edid; 652 unsigned int extend_block = 0; 653 unsigned char test_vector; 654 int retval; 655 656 /* 657 * EDID device address is 0x50. 658 * However, if necessary, you must have set upper address 659 * into E-EDID in I2C device, 0x30. 660 */ 661 662 /* Read Extension Flag, Number of 128-byte EDID extension blocks */ 663 retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, 664 EDID_EXTENSION_FLAG, 665 &extend_block); 666 if (retval) 667 return retval; 668 669 if (extend_block > 0) { 670 debug("EDID data includes a single extension!\n"); 671 672 /* Read EDID data */ 673 retval = analogix_dp_read_bytes_from_i2c(dp, 674 I2C_EDID_DEVICE_ADDR, 675 EDID_HEADER_PATTERN, 676 EDID_BLOCK_LENGTH, 677 &edid[EDID_HEADER_PATTERN]); 678 if (retval < 0) 679 return retval; 680 681 if (analogix_dp_calc_edid_check_sum(edid)) 682 return -EINVAL; 683 684 /* Read additional EDID data */ 685 retval = analogix_dp_read_bytes_from_i2c(dp, 686 I2C_EDID_DEVICE_ADDR, 687 EDID_BLOCK_LENGTH, 688 EDID_BLOCK_LENGTH, 689 &edid[EDID_BLOCK_LENGTH]); 690 if (retval < 0) 691 return retval; 692 693 if (analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH])) 694 return -EINVAL; 695 696 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 697 &test_vector); 698 if (test_vector & DP_TEST_LINK_EDID_READ) { 699 analogix_dp_write_byte_to_dpcd(dp, 700 DP_TEST_EDID_CHECKSUM, 701 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); 702 analogix_dp_write_byte_to_dpcd(dp, 703 DP_TEST_RESPONSE, 704 DP_TEST_EDID_CHECKSUM_WRITE); 705 } 706 } else { 707 dev_info(dp->dev, 708 "EDID data does not include any extensions.\n"); 709 710 /* Read EDID data */ 711 retval = analogix_dp_read_bytes_from_i2c(dp, 712 I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN, 713 EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]); 714 if (retval < 0) 715 return retval; 716 717 if (analogix_dp_calc_edid_check_sum(edid)) 718 return -EINVAL; 719 720 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 721 &test_vector); 722 if (test_vector & DP_TEST_LINK_EDID_READ) { 723 analogix_dp_write_byte_to_dpcd(dp, 724 DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]); 725 analogix_dp_write_byte_to_dpcd(dp, 726 DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE); 727 } 728 } 729 730 return 0; 731 } 732 733 static int analogix_dp_handle_edid(struct analogix_dp_device *dp) 734 { 735 u8 buf[12]; 736 int i, try = 5; 737 int retval; 738 739 retry: 740 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */ 741 retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf); 742 743 if (retval && try--) { 744 mdelay(10); 745 goto retry; 746 } 747 748 if (retval) 749 return retval; 750 751 /* Read EDID */ 752 for (i = 0; i < 3; i++) { 753 retval = analogix_dp_read_edid(dp); 754 if (!retval) 755 break; 756 } 757 758 return retval; 759 } 760 761 static int analogix_dp_connector_pre_init(struct display_state *state) 762 { 763 struct connector_state *conn_state = &state->conn_state; 764 765 conn_state->type = DRM_MODE_CONNECTOR_eDP; 766 767 return 0; 768 } 769 770 static int analogix_dp_connector_init(struct display_state *state) 771 { 772 struct connector_state *conn_state = &state->conn_state; 773 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 774 775 conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_eDP1 : VOP_OUTPUT_IF_eDP0; 776 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 777 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 778 779 reset_assert_bulk(&dp->resets); 780 udelay(1); 781 reset_deassert_bulk(&dp->resets); 782 783 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dp->id); 784 generic_phy_set_mode(&dp->phy, PHY_MODE_DP); 785 generic_phy_power_on(&dp->phy); 786 analogix_dp_init_dp(dp); 787 788 return 0; 789 } 790 791 static int analogix_dp_connector_get_edid(struct display_state *state) 792 { 793 struct connector_state *conn_state = &state->conn_state; 794 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 795 int ret; 796 797 ret = analogix_dp_handle_edid(dp); 798 if (ret) { 799 dev_err(dp->dev, "failed to get edid\n"); 800 return ret; 801 } 802 803 memcpy(&conn_state->edid, &dp->edid, sizeof(dp->edid)); 804 805 return 0; 806 } 807 808 static int analogix_dp_link_power_up(struct analogix_dp_device *dp) 809 { 810 u8 value; 811 int ret; 812 813 if (dp->dpcd[DP_DPCD_REV] < 0x11) 814 return 0; 815 816 ret = analogix_dp_read_byte_from_dpcd(dp, DP_SET_POWER, &value); 817 if (ret < 0) 818 return ret; 819 820 value &= ~DP_SET_POWER_MASK; 821 value |= DP_SET_POWER_D0; 822 823 ret = analogix_dp_write_byte_to_dpcd(dp, DP_SET_POWER, value); 824 if (ret < 0) 825 return ret; 826 827 mdelay(1); 828 829 return 0; 830 } 831 832 static int analogix_dp_link_power_down(struct analogix_dp_device *dp) 833 { 834 u8 value; 835 int ret; 836 837 if (dp->dpcd[DP_DPCD_REV] < 0x11) 838 return 0; 839 840 ret = analogix_dp_read_byte_from_dpcd(dp, DP_SET_POWER, &value); 841 if (ret < 0) 842 return ret; 843 844 value &= ~DP_SET_POWER_MASK; 845 value |= DP_SET_POWER_D3; 846 847 ret = analogix_dp_write_byte_to_dpcd(dp, DP_SET_POWER, value); 848 if (ret < 0) 849 return ret; 850 851 return 0; 852 } 853 854 static int analogix_dp_connector_enable(struct display_state *state) 855 { 856 struct connector_state *conn_state = &state->conn_state; 857 struct crtc_state *crtc_state = &state->crtc_state; 858 const struct rockchip_connector *connector = conn_state->connector; 859 const struct rockchip_dp_chip_data *pdata = connector->data; 860 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 861 struct video_info *video = &dp->video_info; 862 u32 val; 863 int ret; 864 865 if (pdata->lcdsel_grf_reg) { 866 if (crtc_state->crtc_id) 867 val = pdata->lcdsel_lit; 868 else 869 val = pdata->lcdsel_big; 870 871 regmap_write(dp->grf, pdata->lcdsel_grf_reg, val); 872 } 873 874 if (pdata->chip_type == RK3588_EDP) 875 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 876 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 1)); 877 878 switch (conn_state->bpc) { 879 case 12: 880 video->color_depth = COLOR_12; 881 break; 882 case 10: 883 video->color_depth = COLOR_10; 884 break; 885 case 6: 886 video->color_depth = COLOR_6; 887 break; 888 case 8: 889 default: 890 video->color_depth = COLOR_8; 891 break; 892 } 893 894 ret = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 895 DP_RECEIVER_CAP_SIZE, dp->dpcd); 896 if (ret) { 897 dev_err(dp->dev, "failed to read dpcd caps: %d\n", ret); 898 return ret; 899 } 900 901 ret = analogix_dp_link_power_up(dp); 902 if (ret) { 903 dev_err(dp->dev, "failed to power up link: %d\n", ret); 904 return ret; 905 } 906 907 ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count, 908 dp->video_info.max_link_rate); 909 if (ret) { 910 dev_err(dp->dev, "unable to do link train\n"); 911 return ret; 912 } 913 914 analogix_dp_enable_scramble(dp, 1); 915 analogix_dp_enable_rx_to_enhanced_mode(dp, 1); 916 analogix_dp_enable_enhanced_mode(dp, 1); 917 918 analogix_dp_init_video(dp); 919 analogix_dp_set_video_format(dp, &conn_state->mode); 920 921 if (dp->video_bist_enable) 922 analogix_dp_video_bist_enable(dp); 923 924 ret = analogix_dp_config_video(dp); 925 if (ret) { 926 dev_err(dp->dev, "unable to config video\n"); 927 return ret; 928 } 929 930 return 0; 931 } 932 933 static int analogix_dp_connector_disable(struct display_state *state) 934 { 935 struct connector_state *conn_state = &state->conn_state; 936 const struct rockchip_connector *connector = conn_state->connector; 937 const struct rockchip_dp_chip_data *pdata = connector->data; 938 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 939 940 if (!analogix_dp_get_plug_in_status(dp)) 941 analogix_dp_link_power_down(dp); 942 943 if (pdata->chip_type == RK3588_EDP) 944 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 945 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 0)); 946 947 return 0; 948 } 949 950 static int analogix_dp_connector_detect(struct display_state *state) 951 { 952 struct connector_state *conn_state = &state->conn_state; 953 struct panel_state *panel_state = &state->panel_state; 954 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 955 int ret; 956 957 if (panel_state->panel) 958 rockchip_panel_prepare(panel_state->panel); 959 960 if (!analogix_dp_detect(dp)) 961 goto unprepare_panel; 962 963 ret = analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, 964 &dp->link_train.link_rate); 965 if (ret < 0) { 966 dev_err(dp->dev, "failed to read link rate: %d\n", ret); 967 goto unprepare_panel; 968 } 969 970 ret = analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, 971 &dp->link_train.lane_count); 972 if (ret < 0) { 973 dev_err(dp->dev, "failed to read lane count: %d\n", ret); 974 goto unprepare_panel; 975 } 976 977 return true; 978 979 unprepare_panel: 980 if (panel_state->panel) 981 rockchip_panel_unprepare(panel_state->panel); 982 return false; 983 } 984 985 static const struct rockchip_connector_funcs analogix_dp_connector_funcs = { 986 .pre_init = analogix_dp_connector_pre_init, 987 .init = analogix_dp_connector_init, 988 .get_edid = analogix_dp_connector_get_edid, 989 .enable = analogix_dp_connector_enable, 990 .disable = analogix_dp_connector_disable, 991 .detect = analogix_dp_connector_detect, 992 }; 993 994 static int analogix_dp_probe(struct udevice *dev) 995 { 996 struct analogix_dp_device *dp = dev_get_priv(dev); 997 const struct rockchip_connector *connector = 998 (const struct rockchip_connector *)dev_get_driver_data(dev); 999 const struct rockchip_dp_chip_data *pdata = connector->data; 1000 struct udevice *syscon; 1001 int ret; 1002 1003 dp->reg_base = dev_read_addr_ptr(dev); 1004 1005 dp->id = of_alias_get_id(ofnode_to_np(dev->node), "edp"); 1006 if (dp->id < 0) 1007 dp->id = 0; 1008 1009 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1010 &syscon); 1011 if (!ret) { 1012 dp->grf = syscon_get_regmap(syscon); 1013 if (!dp->grf) 1014 return -ENODEV; 1015 } 1016 1017 ret = reset_get_bulk(dev, &dp->resets); 1018 if (ret) { 1019 dev_err(dev, "failed to get reset control: %d\n", ret); 1020 return ret; 1021 } 1022 1023 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 1024 GPIOD_IS_IN); 1025 if (ret && ret != -ENOENT) { 1026 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 1027 return ret; 1028 } 1029 1030 generic_phy_get_by_name(dev, "dp", &dp->phy); 1031 1032 dp->force_hpd = dev_read_bool(dev, "force-hpd"); 1033 dp->video_bist_enable = dev_read_bool(dev, "analogix,video-bist-enable"); 1034 1035 dp->plat_data.dev_type = ROCKCHIP_DP; 1036 dp->plat_data.subdev_type = pdata->chip_type; 1037 dp->plat_data.ssc = pdata->ssc; 1038 1039 dp->video_info.max_link_rate = pdata->max_link_rate; 1040 dp->video_info.max_lane_count = pdata->max_lane_count; 1041 1042 dp->dev = dev; 1043 1044 return 0; 1045 } 1046 1047 static const struct rockchip_dp_chip_data rk3288_edp_platform_data = { 1048 .lcdsel_grf_reg = 0x025c, 1049 .lcdsel_big = 0 | BIT(21), 1050 .lcdsel_lit = BIT(5) | BIT(21), 1051 .chip_type = RK3288_DP, 1052 1053 .max_link_rate = DP_LINK_BW_2_7, 1054 .max_lane_count = 4, 1055 }; 1056 1057 static const struct rockchip_connector rk3288_edp_driver_data = { 1058 .funcs = &analogix_dp_connector_funcs, 1059 .data = &rk3288_edp_platform_data, 1060 }; 1061 1062 static const struct rockchip_dp_chip_data rk3368_edp_platform_data = { 1063 .chip_type = RK3368_EDP, 1064 1065 .max_link_rate = DP_LINK_BW_2_7, 1066 .max_lane_count = 4, 1067 }; 1068 1069 static const struct rockchip_connector rk3368_edp_driver_data = { 1070 .funcs = &analogix_dp_connector_funcs, 1071 .data = &rk3368_edp_platform_data, 1072 }; 1073 1074 static const struct rockchip_dp_chip_data rk3399_edp_platform_data = { 1075 .lcdsel_grf_reg = 0x6250, 1076 .lcdsel_big = 0 | BIT(21), 1077 .lcdsel_lit = BIT(5) | BIT(21), 1078 .chip_type = RK3399_EDP, 1079 1080 .max_link_rate = DP_LINK_BW_2_7, 1081 .max_lane_count = 4, 1082 }; 1083 1084 static const struct rockchip_connector rk3399_edp_driver_data = { 1085 .funcs = &analogix_dp_connector_funcs, 1086 .data = &rk3399_edp_platform_data, 1087 }; 1088 1089 static const struct rockchip_dp_chip_data rk3568_edp_platform_data = { 1090 .chip_type = RK3568_EDP, 1091 .ssc = true, 1092 1093 .max_link_rate = DP_LINK_BW_2_7, 1094 .max_lane_count = 4, 1095 }; 1096 1097 static const struct rockchip_connector rk3568_edp_driver_data = { 1098 .funcs = &analogix_dp_connector_funcs, 1099 .data = &rk3568_edp_platform_data, 1100 }; 1101 1102 static const struct rockchip_dp_chip_data rk3588_edp_platform_data = { 1103 .chip_type = RK3588_EDP, 1104 .ssc = true, 1105 1106 .max_link_rate = DP_LINK_BW_5_4, 1107 .max_lane_count = 4, 1108 }; 1109 1110 static const struct rockchip_connector rk3588_edp_driver_data = { 1111 .funcs = &analogix_dp_connector_funcs, 1112 .data = &rk3588_edp_platform_data, 1113 }; 1114 1115 static const struct udevice_id analogix_dp_ids[] = { 1116 { 1117 .compatible = "rockchip,rk3288-dp", 1118 .data = (ulong)&rk3288_edp_driver_data, 1119 }, { 1120 .compatible = "rockchip,rk3368-edp", 1121 .data = (ulong)&rk3368_edp_driver_data, 1122 }, { 1123 .compatible = "rockchip,rk3399-edp", 1124 .data = (ulong)&rk3399_edp_driver_data, 1125 }, { 1126 .compatible = "rockchip,rk3568-edp", 1127 .data = (ulong)&rk3568_edp_driver_data, 1128 }, { 1129 .compatible = "rockchip,rk3588-edp", 1130 .data = (ulong)&rk3588_edp_driver_data, 1131 }, 1132 {} 1133 }; 1134 1135 U_BOOT_DRIVER(analogix_dp) = { 1136 .name = "analogix_dp", 1137 .id = UCLASS_DISPLAY, 1138 .of_match = analogix_dp_ids, 1139 .probe = analogix_dp_probe, 1140 .priv_auto_alloc_size = sizeof(struct analogix_dp_device), 1141 }; 1142