1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <dm/device.h> 14 #include <dm/of_access.h> 15 #include <dm/read.h> 16 #include <linux/bitfield.h> 17 #include <linux/list.h> 18 #include <syscon.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <asm/gpio.h> 21 22 #include "rockchip_display.h" 23 #include "rockchip_crtc.h" 24 #include "rockchip_connector.h" 25 #include "rockchip_panel.h" 26 #include "analogix_dp.h" 27 28 #define RK3588_GRF_VO1_CON0 0x0000 29 #define EDP_MODE BIT(0) 30 #define RK3588_GRF_VO1_CON1 0x0004 31 32 /** 33 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips 34 * @lcdsel_grf_reg: grf register offset of lcdc select 35 * @lcdsel_big: reg value of selecting vop big for eDP 36 * @lcdsel_lit: reg value of selecting vop little for eDP 37 * @chip_type: specific chip type 38 * @ssc: check if SSC is supported by source 39 */ 40 struct rockchip_dp_chip_data { 41 u32 lcdsel_grf_reg; 42 u32 lcdsel_big; 43 u32 lcdsel_lit; 44 u32 chip_type; 45 bool ssc; 46 47 u32 max_link_rate; 48 u32 max_lane_count; 49 }; 50 51 static void 52 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, 53 bool enable) 54 { 55 u8 data; 56 57 analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data); 58 59 if (enable) 60 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 61 DP_LANE_COUNT_ENHANCED_FRAME_EN | 62 DPCD_LANE_COUNT_SET(data)); 63 else 64 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 65 DPCD_LANE_COUNT_SET(data)); 66 } 67 68 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp) 69 { 70 u8 data; 71 int retval; 72 73 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 74 retval = DPCD_ENHANCED_FRAME_CAP(data); 75 76 return retval; 77 } 78 79 static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) 80 { 81 u8 data; 82 83 data = analogix_dp_is_enhanced_mode_available(dp); 84 analogix_dp_enable_rx_to_enhanced_mode(dp, data); 85 analogix_dp_enable_enhanced_mode(dp, data); 86 } 87 88 static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) 89 { 90 analogix_dp_set_training_pattern(dp, DP_NONE); 91 92 analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET, 93 DP_TRAINING_PATTERN_DISABLE); 94 } 95 96 static int analogix_dp_link_start(struct analogix_dp_device *dp) 97 { 98 u8 buf[4]; 99 int lane, lane_count, retval; 100 101 lane_count = dp->link_train.lane_count; 102 103 dp->link_train.lt_state = CLOCK_RECOVERY; 104 dp->link_train.eq_loop = 0; 105 106 for (lane = 0; lane < lane_count; lane++) 107 dp->link_train.cr_loop[lane] = 0; 108 109 /* Set link rate and count as you want to establish*/ 110 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 111 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 112 113 /* Setup RX configuration */ 114 buf[0] = dp->link_train.link_rate; 115 buf[1] = dp->link_train.lane_count; 116 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf); 117 if (retval) 118 return retval; 119 120 /* Spread AMP if required, enable 8b/10b coding */ 121 buf[0] = analogix_dp_ssc_supported(dp) ? DP_SPREAD_AMP_0_5 : 0; 122 buf[1] = DP_SET_ANSI_8B10B; 123 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_DOWNSPREAD_CTRL, 124 2, buf); 125 if (retval < 0) 126 return retval; 127 128 /* Set TX voltage-swing and pre-emphasis to minimum */ 129 for (lane = 0; lane < lane_count; lane++) 130 dp->link_train.training_lane[lane] = 131 DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | 132 DP_TRAIN_PRE_EMPH_LEVEL_0; 133 analogix_dp_set_lane_link_training(dp); 134 135 /* Set training pattern 1 */ 136 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 137 138 /* Set RX training pattern */ 139 retval = analogix_dp_write_byte_to_dpcd(dp, 140 DP_TRAINING_PATTERN_SET, 141 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); 142 if (retval) 143 return retval; 144 145 for (lane = 0; lane < lane_count; lane++) 146 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 147 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 148 149 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 150 lane_count, buf); 151 152 return retval; 153 } 154 155 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) 156 { 157 int shift = (lane & 1) * 4; 158 u8 link_value = link_status[lane >> 1]; 159 160 return (link_value >> shift) & 0xf; 161 } 162 163 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) 164 { 165 int lane; 166 u8 lane_status; 167 168 for (lane = 0; lane < lane_count; lane++) { 169 lane_status = analogix_dp_get_lane_status(link_status, lane); 170 if ((lane_status & DP_LANE_CR_DONE) == 0) 171 return -EINVAL; 172 } 173 return 0; 174 } 175 176 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, 177 int lane_count) 178 { 179 int lane; 180 u8 lane_status; 181 182 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) 183 return -EINVAL; 184 185 for (lane = 0; lane < lane_count; lane++) { 186 lane_status = analogix_dp_get_lane_status(link_status, lane); 187 lane_status &= DP_CHANNEL_EQ_BITS; 188 if (lane_status != DP_CHANNEL_EQ_BITS) 189 return -EINVAL; 190 } 191 192 return 0; 193 } 194 195 static unsigned char 196 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) 197 { 198 int shift = (lane & 1) * 4; 199 u8 link_value = adjust_request[lane >> 1]; 200 201 return (link_value >> shift) & 0x3; 202 } 203 204 static unsigned char analogix_dp_get_adjust_request_pre_emphasis( 205 u8 adjust_request[2], 206 int lane) 207 { 208 int shift = (lane & 1) * 4; 209 u8 link_value = adjust_request[lane >> 1]; 210 211 return ((link_value >> shift) & 0xc) >> 2; 212 } 213 214 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) 215 { 216 analogix_dp_training_pattern_dis(dp); 217 analogix_dp_set_enhanced_mode(dp); 218 219 dp->link_train.lt_state = FAILED; 220 } 221 222 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, 223 u8 adjust_request[2]) 224 { 225 int lane, lane_count; 226 u8 voltage_swing, pre_emphasis, training_lane; 227 228 lane_count = dp->link_train.lane_count; 229 for (lane = 0; lane < lane_count; lane++) { 230 voltage_swing = analogix_dp_get_adjust_request_voltage( 231 adjust_request, lane); 232 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 233 adjust_request, lane); 234 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | 235 DPCD_PRE_EMPHASIS_SET(pre_emphasis); 236 237 if (voltage_swing == VOLTAGE_LEVEL_3) 238 training_lane |= DP_TRAIN_MAX_SWING_REACHED; 239 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) 240 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 241 242 dp->link_train.training_lane[lane] = training_lane; 243 } 244 } 245 246 static bool analogix_dp_tps3_supported(struct analogix_dp_device *dp) 247 { 248 bool source_tps3_supported, sink_tps3_supported; 249 u8 dpcd = 0; 250 251 source_tps3_supported = 252 dp->video_info.max_link_rate == DP_LINK_BW_5_4; 253 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &dpcd); 254 sink_tps3_supported = dpcd & DP_TPS3_SUPPORTED; 255 256 return source_tps3_supported && sink_tps3_supported; 257 } 258 259 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) 260 { 261 int lane, lane_count, retval; 262 u8 voltage_swing, pre_emphasis, training_lane; 263 u8 link_status[2], adjust_request[2]; 264 u8 training_pattern = TRAINING_PTN2; 265 266 drm_dp_link_train_clock_recovery_delay(dp->dpcd); 267 268 lane_count = dp->link_train.lane_count; 269 270 retval = analogix_dp_read_bytes_from_dpcd(dp, 271 DP_LANE0_1_STATUS, 2, link_status); 272 if (retval) 273 return retval; 274 275 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { 276 if (analogix_dp_tps3_supported(dp)) 277 training_pattern = TRAINING_PTN3; 278 279 /* set training pattern for EQ */ 280 analogix_dp_set_training_pattern(dp, training_pattern); 281 282 retval = analogix_dp_write_byte_to_dpcd(dp, 283 DP_TRAINING_PATTERN_SET, 284 (training_pattern == TRAINING_PTN3 ? 285 DP_TRAINING_PATTERN_3 : DP_TRAINING_PATTERN_2)); 286 if (retval) 287 return retval; 288 289 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 290 dp->link_train.lt_state = EQUALIZER_TRAINING; 291 292 return 0; 293 } else { 294 retval = analogix_dp_read_bytes_from_dpcd(dp, 295 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 296 if (retval) 297 return retval; 298 299 for (lane = 0; lane < lane_count; lane++) { 300 training_lane = analogix_dp_get_lane_link_training( 301 dp, lane); 302 voltage_swing = analogix_dp_get_adjust_request_voltage( 303 adjust_request, lane); 304 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 305 adjust_request, lane); 306 307 if (DPCD_VOLTAGE_SWING_GET(training_lane) == 308 voltage_swing && 309 DPCD_PRE_EMPHASIS_GET(training_lane) == 310 pre_emphasis) 311 dp->link_train.cr_loop[lane]++; 312 313 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || 314 voltage_swing == VOLTAGE_LEVEL_3 || 315 pre_emphasis == PRE_EMPHASIS_LEVEL_3) { 316 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", 317 dp->link_train.cr_loop[lane], 318 voltage_swing, pre_emphasis); 319 analogix_dp_reduce_link_rate(dp); 320 return -EIO; 321 } 322 } 323 } 324 325 analogix_dp_get_adjust_training_lane(dp, adjust_request); 326 analogix_dp_set_lane_link_training(dp); 327 328 retval = analogix_dp_write_bytes_to_dpcd(dp, 329 DP_TRAINING_LANE0_SET, lane_count, 330 dp->link_train.training_lane); 331 if (retval) 332 return retval; 333 334 return retval; 335 } 336 337 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) 338 { 339 int lane_count, retval; 340 u32 reg; 341 u8 link_align, link_status[2], adjust_request[2]; 342 343 drm_dp_link_train_channel_eq_delay(dp->dpcd); 344 345 lane_count = dp->link_train.lane_count; 346 347 retval = analogix_dp_read_bytes_from_dpcd(dp, 348 DP_LANE0_1_STATUS, 2, link_status); 349 if (retval) 350 return retval; 351 352 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { 353 analogix_dp_reduce_link_rate(dp); 354 return -EIO; 355 } 356 357 retval = analogix_dp_read_byte_from_dpcd(dp, 358 DP_LANE_ALIGN_STATUS_UPDATED, &link_align); 359 if (retval) 360 return retval; 361 362 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { 363 /* traing pattern Set to Normal */ 364 analogix_dp_training_pattern_dis(dp); 365 366 printf("Link Training success!\n"); 367 368 analogix_dp_get_link_bandwidth(dp, ®); 369 dp->link_train.link_rate = reg; 370 analogix_dp_get_lane_count(dp, ®); 371 dp->link_train.lane_count = reg; 372 373 printf("final link rate = 0x%.2x, lane count = 0x%.2x\n", 374 dp->link_train.link_rate, dp->link_train.lane_count); 375 376 /* set enhanced mode if available */ 377 analogix_dp_set_enhanced_mode(dp); 378 dp->link_train.lt_state = FINISHED; 379 380 return 0; 381 } 382 383 /* not all locked */ 384 dp->link_train.eq_loop++; 385 386 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 387 dev_dbg(dp->dev, "EQ Max loop\n"); 388 analogix_dp_reduce_link_rate(dp); 389 return -EIO; 390 } 391 392 retval = analogix_dp_read_bytes_from_dpcd(dp, 393 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 394 if (retval) 395 return retval; 396 397 analogix_dp_get_adjust_training_lane(dp, adjust_request); 398 analogix_dp_set_lane_link_training(dp); 399 400 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 401 lane_count, dp->link_train.training_lane); 402 403 return retval; 404 } 405 406 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, 407 u8 *bandwidth) 408 { 409 u8 data; 410 411 /* 412 * For DP rev.1.1, Maximum link rate of Main Link lanes 413 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps 414 * For DP rev.1.2, Maximum link rate of Main Link lanes 415 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 416 */ 417 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); 418 *bandwidth = data; 419 } 420 421 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, 422 u8 *lane_count) 423 { 424 u8 data; 425 426 /* 427 * For DP rev.1.1, Maximum number of Main Link lanes 428 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 429 */ 430 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 431 *lane_count = DPCD_MAX_LANE_COUNT(data); 432 } 433 434 static int analogix_dp_init_training(struct analogix_dp_device *dp, 435 enum link_lane_count_type max_lane, 436 int max_rate) 437 { 438 u8 dpcd; 439 440 /* 441 * MACRO_RST must be applied after the PLL_LOCK to avoid 442 * the DP inter pair skew issue for at least 10 us 443 */ 444 analogix_dp_reset_macro(dp); 445 446 /* Initialize by reading RX's DPCD */ 447 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); 448 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); 449 450 /* Setup TX lane count & rate */ 451 dp->link_train.lane_count = min_t(u8, dp->link_train.lane_count, 452 max_lane); 453 dp->link_train.link_rate = min_t(u32, dp->link_train.link_rate, 454 max_rate); 455 456 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_DOWNSPREAD, &dpcd); 457 dp->link_train.ssc = !!(dpcd & DP_MAX_DOWNSPREAD_0_5); 458 459 /* All DP analog module power up */ 460 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 461 462 return 0; 463 } 464 465 static int analogix_dp_sw_link_training(struct analogix_dp_device *dp) 466 { 467 int retval = 0, training_finished = 0; 468 469 dp->link_train.lt_state = START; 470 471 /* Process here */ 472 while (!retval && !training_finished) { 473 switch (dp->link_train.lt_state) { 474 case START: 475 retval = analogix_dp_link_start(dp); 476 if (retval) 477 dev_err(dp->dev, "LT link start failed!\n"); 478 break; 479 case CLOCK_RECOVERY: 480 retval = analogix_dp_process_clock_recovery(dp); 481 if (retval) 482 dev_err(dp->dev, "LT CR failed!\n"); 483 break; 484 case EQUALIZER_TRAINING: 485 retval = analogix_dp_process_equalizer_training(dp); 486 if (retval) 487 dev_err(dp->dev, "LT EQ failed!\n"); 488 break; 489 case FINISHED: 490 training_finished = 1; 491 break; 492 case FAILED: 493 return -EREMOTEIO; 494 } 495 } 496 497 return retval; 498 } 499 500 static int analogix_dp_set_link_train(struct analogix_dp_device *dp, 501 u32 count, u32 bwtype) 502 { 503 int i, ret; 504 505 for (i = 0; i < 5; i++) { 506 ret = analogix_dp_init_training(dp, count, bwtype); 507 if (ret < 0) { 508 dev_err(dp->dev, "failed to init training\n"); 509 return ret; 510 } 511 512 ret = analogix_dp_sw_link_training(dp); 513 if (!ret) 514 break; 515 } 516 517 return ret; 518 } 519 520 static int analogix_dp_config_video(struct analogix_dp_device *dp) 521 { 522 int timeout_loop = 0; 523 int done_count = 0; 524 525 analogix_dp_config_video_slave_mode(dp); 526 527 analogix_dp_set_video_color_format(dp); 528 529 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 530 dev_err(dp->dev, "PLL is not locked yet.\n"); 531 return -EINVAL; 532 } 533 534 for (;;) { 535 timeout_loop++; 536 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) 537 break; 538 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 539 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 540 return -ETIMEDOUT; 541 } 542 543 udelay(2); 544 } 545 546 /* Set to use the register calculated M/N video */ 547 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); 548 549 /* For video bist, Video timing must be generated by register */ 550 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_REGISTER); 551 552 /* Disable video mute */ 553 analogix_dp_enable_video_mute(dp, 0); 554 555 /* Configure video slave mode */ 556 analogix_dp_enable_video_master(dp, 0); 557 558 /* Enable video input */ 559 analogix_dp_start_video(dp); 560 561 timeout_loop = 0; 562 563 for (;;) { 564 timeout_loop++; 565 if (analogix_dp_is_video_stream_on(dp) == 0) { 566 done_count++; 567 if (done_count > 10) 568 break; 569 } else if (done_count) { 570 done_count = 0; 571 } 572 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 573 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 574 return -ETIMEDOUT; 575 } 576 577 udelay(1001); 578 } 579 580 return 0; 581 } 582 583 static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, 584 bool enable) 585 { 586 u8 data; 587 588 if (enable) { 589 analogix_dp_enable_scrambling(dp); 590 591 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 592 &data); 593 analogix_dp_write_byte_to_dpcd(dp, 594 DP_TRAINING_PATTERN_SET, 595 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); 596 } else { 597 analogix_dp_disable_scrambling(dp); 598 599 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 600 &data); 601 analogix_dp_write_byte_to_dpcd(dp, 602 DP_TRAINING_PATTERN_SET, 603 (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); 604 } 605 } 606 607 static void analogix_dp_init_dp(struct analogix_dp_device *dp) 608 { 609 analogix_dp_reset(dp); 610 611 analogix_dp_swreset(dp); 612 613 analogix_dp_init_analog_param(dp); 614 analogix_dp_init_interrupt(dp); 615 616 /* SW defined function Normal operation */ 617 analogix_dp_enable_sw_function(dp); 618 619 analogix_dp_config_interrupt(dp); 620 analogix_dp_init_analog_func(dp); 621 622 analogix_dp_init_hpd(dp); 623 analogix_dp_init_aux(dp); 624 } 625 626 static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data) 627 { 628 int i; 629 unsigned char sum = 0; 630 631 for (i = 0; i < EDID_BLOCK_LENGTH; i++) 632 sum = sum + edid_data[i]; 633 634 return sum; 635 } 636 637 static int analogix_dp_read_edid(struct analogix_dp_device *dp) 638 { 639 unsigned char *edid = dp->edid; 640 unsigned int extend_block = 0; 641 unsigned char test_vector; 642 int retval; 643 644 /* 645 * EDID device address is 0x50. 646 * However, if necessary, you must have set upper address 647 * into E-EDID in I2C device, 0x30. 648 */ 649 650 /* Read Extension Flag, Number of 128-byte EDID extension blocks */ 651 retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, 652 EDID_EXTENSION_FLAG, 653 &extend_block); 654 if (retval) 655 return retval; 656 657 if (extend_block > 0) { 658 debug("EDID data includes a single extension!\n"); 659 660 /* Read EDID data */ 661 retval = analogix_dp_read_bytes_from_i2c(dp, 662 I2C_EDID_DEVICE_ADDR, 663 EDID_HEADER_PATTERN, 664 EDID_BLOCK_LENGTH, 665 &edid[EDID_HEADER_PATTERN]); 666 if (retval < 0) 667 return retval; 668 669 if (analogix_dp_calc_edid_check_sum(edid)) 670 return -EINVAL; 671 672 /* Read additional EDID data */ 673 retval = analogix_dp_read_bytes_from_i2c(dp, 674 I2C_EDID_DEVICE_ADDR, 675 EDID_BLOCK_LENGTH, 676 EDID_BLOCK_LENGTH, 677 &edid[EDID_BLOCK_LENGTH]); 678 if (retval < 0) 679 return retval; 680 681 if (analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH])) 682 return -EINVAL; 683 684 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 685 &test_vector); 686 if (test_vector & DP_TEST_LINK_EDID_READ) { 687 analogix_dp_write_byte_to_dpcd(dp, 688 DP_TEST_EDID_CHECKSUM, 689 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); 690 analogix_dp_write_byte_to_dpcd(dp, 691 DP_TEST_RESPONSE, 692 DP_TEST_EDID_CHECKSUM_WRITE); 693 } 694 } else { 695 dev_info(dp->dev, 696 "EDID data does not include any extensions.\n"); 697 698 /* Read EDID data */ 699 retval = analogix_dp_read_bytes_from_i2c(dp, 700 I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN, 701 EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]); 702 if (retval < 0) 703 return retval; 704 705 if (analogix_dp_calc_edid_check_sum(edid)) 706 return -EINVAL; 707 708 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 709 &test_vector); 710 if (test_vector & DP_TEST_LINK_EDID_READ) { 711 analogix_dp_write_byte_to_dpcd(dp, 712 DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]); 713 analogix_dp_write_byte_to_dpcd(dp, 714 DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE); 715 } 716 } 717 718 return 0; 719 } 720 721 static int analogix_dp_handle_edid(struct analogix_dp_device *dp) 722 { 723 u8 buf[12]; 724 int i, try = 5; 725 int retval; 726 727 retry: 728 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */ 729 retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf); 730 731 if (retval && try--) { 732 mdelay(10); 733 goto retry; 734 } 735 736 if (retval) 737 return retval; 738 739 /* Read EDID */ 740 for (i = 0; i < 3; i++) { 741 retval = analogix_dp_read_edid(dp); 742 if (!retval) 743 break; 744 } 745 746 return retval; 747 } 748 749 static int analogix_dp_connector_pre_init(struct display_state *state) 750 { 751 struct connector_state *conn_state = &state->conn_state; 752 753 conn_state->type = DRM_MODE_CONNECTOR_eDP; 754 755 return 0; 756 } 757 758 static int analogix_dp_connector_init(struct display_state *state) 759 { 760 struct connector_state *conn_state = &state->conn_state; 761 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 762 763 conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_eDP1 : VOP_OUTPUT_IF_eDP0; 764 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 765 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 766 767 reset_assert_bulk(&dp->resets); 768 udelay(1); 769 reset_deassert_bulk(&dp->resets); 770 771 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dp->id); 772 generic_phy_set_mode(&dp->phy, PHY_MODE_DP); 773 generic_phy_power_on(&dp->phy); 774 analogix_dp_init_dp(dp); 775 776 return 0; 777 } 778 779 static int analogix_dp_connector_get_edid(struct display_state *state) 780 { 781 struct connector_state *conn_state = &state->conn_state; 782 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 783 int ret; 784 785 ret = analogix_dp_handle_edid(dp); 786 if (ret) { 787 dev_err(dp->dev, "failed to get edid\n"); 788 return ret; 789 } 790 791 memcpy(&conn_state->edid, &dp->edid, sizeof(dp->edid)); 792 793 return 0; 794 } 795 796 static int analogix_dp_link_power_up(struct analogix_dp_device *dp) 797 { 798 u8 value; 799 int ret; 800 801 if (dp->dpcd[DP_DPCD_REV] < 0x11) 802 return 0; 803 804 ret = analogix_dp_read_byte_from_dpcd(dp, DP_SET_POWER, &value); 805 if (ret < 0) 806 return ret; 807 808 value &= ~DP_SET_POWER_MASK; 809 value |= DP_SET_POWER_D0; 810 811 ret = analogix_dp_write_byte_to_dpcd(dp, DP_SET_POWER, value); 812 if (ret < 0) 813 return ret; 814 815 mdelay(1); 816 817 return 0; 818 } 819 820 static int analogix_dp_link_power_down(struct analogix_dp_device *dp) 821 { 822 u8 value; 823 int ret; 824 825 if (dp->dpcd[DP_DPCD_REV] < 0x11) 826 return 0; 827 828 ret = analogix_dp_read_byte_from_dpcd(dp, DP_SET_POWER, &value); 829 if (ret < 0) 830 return ret; 831 832 value &= ~DP_SET_POWER_MASK; 833 value |= DP_SET_POWER_D3; 834 835 ret = analogix_dp_write_byte_to_dpcd(dp, DP_SET_POWER, value); 836 if (ret < 0) 837 return ret; 838 839 return 0; 840 } 841 842 static int analogix_dp_connector_enable(struct display_state *state) 843 { 844 struct connector_state *conn_state = &state->conn_state; 845 struct crtc_state *crtc_state = &state->crtc_state; 846 const struct rockchip_connector *connector = conn_state->connector; 847 const struct rockchip_dp_chip_data *pdata = connector->data; 848 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 849 struct video_info *video = &dp->video_info; 850 u32 val; 851 int ret; 852 853 if (pdata->lcdsel_grf_reg) { 854 if (crtc_state->crtc_id) 855 val = pdata->lcdsel_lit; 856 else 857 val = pdata->lcdsel_big; 858 859 regmap_write(dp->grf, pdata->lcdsel_grf_reg, val); 860 } 861 862 if (pdata->chip_type == RK3588_EDP) 863 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 864 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 1)); 865 866 switch (conn_state->bpc) { 867 case 12: 868 video->color_depth = COLOR_12; 869 break; 870 case 10: 871 video->color_depth = COLOR_10; 872 break; 873 case 6: 874 video->color_depth = COLOR_6; 875 break; 876 case 8: 877 default: 878 video->color_depth = COLOR_8; 879 break; 880 } 881 882 ret = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 883 DP_RECEIVER_CAP_SIZE, dp->dpcd); 884 if (ret) { 885 dev_err(dp->dev, "failed to read dpcd caps: %d\n", ret); 886 return ret; 887 } 888 889 ret = analogix_dp_link_power_up(dp); 890 if (ret) { 891 dev_err(dp->dev, "failed to power up link: %d\n", ret); 892 return ret; 893 } 894 895 ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count, 896 dp->video_info.max_link_rate); 897 if (ret) { 898 dev_err(dp->dev, "unable to do link train\n"); 899 return ret; 900 } 901 902 analogix_dp_enable_scramble(dp, 1); 903 analogix_dp_enable_rx_to_enhanced_mode(dp, 1); 904 analogix_dp_enable_enhanced_mode(dp, 1); 905 906 analogix_dp_init_video(dp); 907 analogix_dp_set_video_format(dp, &conn_state->mode); 908 909 if (dp->video_bist_enable) 910 analogix_dp_video_bist_enable(dp); 911 912 ret = analogix_dp_config_video(dp); 913 if (ret) { 914 dev_err(dp->dev, "unable to config video\n"); 915 return ret; 916 } 917 918 return 0; 919 } 920 921 static int analogix_dp_connector_disable(struct display_state *state) 922 { 923 struct connector_state *conn_state = &state->conn_state; 924 const struct rockchip_connector *connector = conn_state->connector; 925 const struct rockchip_dp_chip_data *pdata = connector->data; 926 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 927 928 if (!analogix_dp_get_plug_in_status(dp)) 929 analogix_dp_link_power_down(dp); 930 931 if (pdata->chip_type == RK3588_EDP) 932 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 933 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 0)); 934 935 return 0; 936 } 937 938 static int analogix_dp_connector_detect(struct display_state *state) 939 { 940 struct connector_state *conn_state = &state->conn_state; 941 struct panel_state *panel_state = &state->panel_state; 942 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 943 int ret; 944 945 if (panel_state->panel) 946 rockchip_panel_prepare(panel_state->panel); 947 948 if (!analogix_dp_detect(dp)) 949 goto unprepare_panel; 950 951 ret = analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, 952 &dp->link_train.link_rate); 953 if (ret < 0) { 954 dev_err(dp->dev, "failed to read link rate: %d\n", ret); 955 goto unprepare_panel; 956 } 957 958 ret = analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, 959 &dp->link_train.lane_count); 960 if (ret < 0) { 961 dev_err(dp->dev, "failed to read lane count: %d\n", ret); 962 goto unprepare_panel; 963 } 964 965 return true; 966 967 unprepare_panel: 968 if (panel_state->panel) 969 rockchip_panel_unprepare(panel_state->panel); 970 return false; 971 } 972 973 static const struct rockchip_connector_funcs analogix_dp_connector_funcs = { 974 .pre_init = analogix_dp_connector_pre_init, 975 .init = analogix_dp_connector_init, 976 .get_edid = analogix_dp_connector_get_edid, 977 .enable = analogix_dp_connector_enable, 978 .disable = analogix_dp_connector_disable, 979 .detect = analogix_dp_connector_detect, 980 }; 981 982 static int analogix_dp_parse_dt(struct analogix_dp_device *dp) 983 { 984 struct udevice *dev = dp->dev; 985 int len; 986 u32 num_lanes; 987 int ret; 988 989 dp->force_hpd = dev_read_bool(dev, "force-hpd"); 990 dp->video_bist_enable = dev_read_bool(dev, "analogix,video-bist-enable"); 991 992 if (dev_read_prop(dev, "data-lanes", &len)) { 993 num_lanes = len / sizeof(u32); 994 if (num_lanes < 1 || num_lanes > 4 || num_lanes == 3) { 995 dev_err(dev, "bad number of data lanes\n"); 996 return -EINVAL; 997 } 998 999 ret = dev_read_u32_array(dev, "data-lanes", dp->lane_map, 1000 num_lanes); 1001 if (ret) 1002 return ret; 1003 1004 dp->video_info.max_lane_count = num_lanes; 1005 } else { 1006 dp->lane_map[0] = 0; 1007 dp->lane_map[1] = 1; 1008 dp->lane_map[2] = 2; 1009 dp->lane_map[3] = 3; 1010 } 1011 1012 return 0; 1013 } 1014 1015 static int analogix_dp_probe(struct udevice *dev) 1016 { 1017 struct analogix_dp_device *dp = dev_get_priv(dev); 1018 const struct rockchip_connector *connector = 1019 (const struct rockchip_connector *)dev_get_driver_data(dev); 1020 const struct rockchip_dp_chip_data *pdata = connector->data; 1021 struct udevice *syscon; 1022 int ret; 1023 1024 dp->reg_base = dev_read_addr_ptr(dev); 1025 1026 dp->id = of_alias_get_id(ofnode_to_np(dev->node), "edp"); 1027 if (dp->id < 0) 1028 dp->id = 0; 1029 1030 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1031 &syscon); 1032 if (!ret) { 1033 dp->grf = syscon_get_regmap(syscon); 1034 if (!dp->grf) 1035 return -ENODEV; 1036 } 1037 1038 ret = reset_get_bulk(dev, &dp->resets); 1039 if (ret) { 1040 dev_err(dev, "failed to get reset control: %d\n", ret); 1041 return ret; 1042 } 1043 1044 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 1045 GPIOD_IS_IN); 1046 if (ret && ret != -ENOENT) { 1047 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 1048 return ret; 1049 } 1050 1051 generic_phy_get_by_name(dev, "dp", &dp->phy); 1052 1053 dp->plat_data.dev_type = ROCKCHIP_DP; 1054 dp->plat_data.subdev_type = pdata->chip_type; 1055 dp->plat_data.ssc = pdata->ssc; 1056 1057 dp->video_info.max_link_rate = pdata->max_link_rate; 1058 dp->video_info.max_lane_count = pdata->max_lane_count; 1059 1060 dp->dev = dev; 1061 1062 ret = analogix_dp_parse_dt(dp); 1063 if (ret) { 1064 dev_err(dev, "failed to parse DT: %d\n", ret); 1065 return ret; 1066 } 1067 1068 return 0; 1069 } 1070 1071 static const struct rockchip_dp_chip_data rk3288_edp_platform_data = { 1072 .lcdsel_grf_reg = 0x025c, 1073 .lcdsel_big = 0 | BIT(21), 1074 .lcdsel_lit = BIT(5) | BIT(21), 1075 .chip_type = RK3288_DP, 1076 1077 .max_link_rate = DP_LINK_BW_2_7, 1078 .max_lane_count = 4, 1079 }; 1080 1081 static const struct rockchip_connector rk3288_edp_driver_data = { 1082 .funcs = &analogix_dp_connector_funcs, 1083 .data = &rk3288_edp_platform_data, 1084 }; 1085 1086 static const struct rockchip_dp_chip_data rk3368_edp_platform_data = { 1087 .chip_type = RK3368_EDP, 1088 1089 .max_link_rate = DP_LINK_BW_2_7, 1090 .max_lane_count = 4, 1091 }; 1092 1093 static const struct rockchip_connector rk3368_edp_driver_data = { 1094 .funcs = &analogix_dp_connector_funcs, 1095 .data = &rk3368_edp_platform_data, 1096 }; 1097 1098 static const struct rockchip_dp_chip_data rk3399_edp_platform_data = { 1099 .lcdsel_grf_reg = 0x6250, 1100 .lcdsel_big = 0 | BIT(21), 1101 .lcdsel_lit = BIT(5) | BIT(21), 1102 .chip_type = RK3399_EDP, 1103 1104 .max_link_rate = DP_LINK_BW_2_7, 1105 .max_lane_count = 4, 1106 }; 1107 1108 static const struct rockchip_connector rk3399_edp_driver_data = { 1109 .funcs = &analogix_dp_connector_funcs, 1110 .data = &rk3399_edp_platform_data, 1111 }; 1112 1113 static const struct rockchip_dp_chip_data rk3568_edp_platform_data = { 1114 .chip_type = RK3568_EDP, 1115 .ssc = true, 1116 1117 .max_link_rate = DP_LINK_BW_2_7, 1118 .max_lane_count = 4, 1119 }; 1120 1121 static const struct rockchip_connector rk3568_edp_driver_data = { 1122 .funcs = &analogix_dp_connector_funcs, 1123 .data = &rk3568_edp_platform_data, 1124 }; 1125 1126 static const struct rockchip_dp_chip_data rk3588_edp_platform_data = { 1127 .chip_type = RK3588_EDP, 1128 .ssc = true, 1129 1130 .max_link_rate = DP_LINK_BW_5_4, 1131 .max_lane_count = 4, 1132 }; 1133 1134 static const struct rockchip_connector rk3588_edp_driver_data = { 1135 .funcs = &analogix_dp_connector_funcs, 1136 .data = &rk3588_edp_platform_data, 1137 }; 1138 1139 static const struct udevice_id analogix_dp_ids[] = { 1140 { 1141 .compatible = "rockchip,rk3288-dp", 1142 .data = (ulong)&rk3288_edp_driver_data, 1143 }, { 1144 .compatible = "rockchip,rk3368-edp", 1145 .data = (ulong)&rk3368_edp_driver_data, 1146 }, { 1147 .compatible = "rockchip,rk3399-edp", 1148 .data = (ulong)&rk3399_edp_driver_data, 1149 }, { 1150 .compatible = "rockchip,rk3568-edp", 1151 .data = (ulong)&rk3568_edp_driver_data, 1152 }, { 1153 .compatible = "rockchip,rk3588-edp", 1154 .data = (ulong)&rk3588_edp_driver_data, 1155 }, 1156 {} 1157 }; 1158 1159 U_BOOT_DRIVER(analogix_dp) = { 1160 .name = "analogix_dp", 1161 .id = UCLASS_DISPLAY, 1162 .of_match = analogix_dp_ids, 1163 .probe = analogix_dp_probe, 1164 .priv_auto_alloc_size = sizeof(struct analogix_dp_device), 1165 }; 1166