1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <dm/device.h> 14 #include <dm/read.h> 15 #include <linux/list.h> 16 #include <syscon.h> 17 #include <asm/arch-rockchip/clock.h> 18 #include <asm/gpio.h> 19 20 #include "rockchip_display.h" 21 #include "rockchip_crtc.h" 22 #include "rockchip_connector.h" 23 #include "analogix_dp.h" 24 25 /** 26 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips 27 * @lcdsel_grf_reg: grf register offset of lcdc select 28 * @lcdsel_big: reg value of selecting vop big for eDP 29 * @lcdsel_lit: reg value of selecting vop little for eDP 30 */ 31 struct rockchip_dp_chip_data { 32 u32 lcdsel_grf_reg; 33 u32 lcdsel_big; 34 u32 lcdsel_lit; 35 u32 chip_type; 36 bool has_vop_sel; 37 }; 38 39 static void 40 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, 41 bool enable) 42 { 43 u8 data; 44 45 analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data); 46 47 if (enable) 48 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 49 DP_LANE_COUNT_ENHANCED_FRAME_EN | 50 DPCD_LANE_COUNT_SET(data)); 51 else 52 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 53 DPCD_LANE_COUNT_SET(data)); 54 } 55 56 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp) 57 { 58 u8 data; 59 int retval; 60 61 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 62 retval = DPCD_ENHANCED_FRAME_CAP(data); 63 64 return retval; 65 } 66 67 static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) 68 { 69 u8 data; 70 71 data = analogix_dp_is_enhanced_mode_available(dp); 72 analogix_dp_enable_rx_to_enhanced_mode(dp, data); 73 analogix_dp_enable_enhanced_mode(dp, data); 74 } 75 76 static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) 77 { 78 analogix_dp_set_training_pattern(dp, DP_NONE); 79 80 analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET, 81 DP_TRAINING_PATTERN_DISABLE); 82 } 83 84 static void 85 analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp, 86 int pre_emphasis, int lane) 87 { 88 switch (lane) { 89 case 0: 90 analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis); 91 break; 92 case 1: 93 analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis); 94 break; 95 96 case 2: 97 analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis); 98 break; 99 100 case 3: 101 analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis); 102 break; 103 } 104 } 105 106 static int analogix_dp_link_start(struct analogix_dp_device *dp) 107 { 108 u8 buf[4]; 109 int lane, lane_count, pll_tries, retval; 110 111 lane_count = dp->link_train.lane_count; 112 113 dp->link_train.lt_state = CLOCK_RECOVERY; 114 dp->link_train.eq_loop = 0; 115 116 for (lane = 0; lane < lane_count; lane++) 117 dp->link_train.cr_loop[lane] = 0; 118 119 /* Set link rate and count as you want to establish*/ 120 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 121 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 122 123 /* Setup RX configuration */ 124 buf[0] = dp->link_train.link_rate; 125 buf[1] = dp->link_train.lane_count; 126 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf); 127 if (retval) 128 return retval; 129 130 /* Set TX pre-emphasis to minimum */ 131 for (lane = 0; lane < lane_count; lane++) 132 analogix_dp_set_lane_lane_pre_emphasis(dp, 133 PRE_EMPHASIS_LEVEL_0, lane); 134 135 /* Wait for PLL lock */ 136 pll_tries = 0; 137 while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 138 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) { 139 dev_err(dp->dev, "Wait for PLL lock timed out\n"); 140 return -ETIMEDOUT; 141 } 142 143 pll_tries++; 144 udelay(120); 145 } 146 147 /* Set training pattern 1 */ 148 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 149 150 /* Set RX training pattern */ 151 retval = analogix_dp_write_byte_to_dpcd(dp, 152 DP_TRAINING_PATTERN_SET, 153 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); 154 if (retval) 155 return retval; 156 157 for (lane = 0; lane < lane_count; lane++) 158 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 159 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 160 161 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 162 lane_count, buf); 163 164 return retval; 165 } 166 167 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) 168 { 169 int shift = (lane & 1) * 4; 170 u8 link_value = link_status[lane >> 1]; 171 172 return (link_value >> shift) & 0xf; 173 } 174 175 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) 176 { 177 int lane; 178 u8 lane_status; 179 180 for (lane = 0; lane < lane_count; lane++) { 181 lane_status = analogix_dp_get_lane_status(link_status, lane); 182 if ((lane_status & DP_LANE_CR_DONE) == 0) 183 return -EINVAL; 184 } 185 return 0; 186 } 187 188 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, 189 int lane_count) 190 { 191 int lane; 192 u8 lane_status; 193 194 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) 195 return -EINVAL; 196 197 for (lane = 0; lane < lane_count; lane++) { 198 lane_status = analogix_dp_get_lane_status(link_status, lane); 199 lane_status &= DP_CHANNEL_EQ_BITS; 200 if (lane_status != DP_CHANNEL_EQ_BITS) 201 return -EINVAL; 202 } 203 204 return 0; 205 } 206 207 static unsigned char 208 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) 209 { 210 int shift = (lane & 1) * 4; 211 u8 link_value = adjust_request[lane >> 1]; 212 213 return (link_value >> shift) & 0x3; 214 } 215 216 static unsigned char analogix_dp_get_adjust_request_pre_emphasis( 217 u8 adjust_request[2], 218 int lane) 219 { 220 int shift = (lane & 1) * 4; 221 u8 link_value = adjust_request[lane >> 1]; 222 223 return ((link_value >> shift) & 0xc) >> 2; 224 } 225 226 static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp, 227 u8 training_lane_set, int lane) 228 { 229 switch (lane) { 230 case 0: 231 analogix_dp_set_lane0_link_training(dp, training_lane_set); 232 break; 233 case 1: 234 analogix_dp_set_lane1_link_training(dp, training_lane_set); 235 break; 236 237 case 2: 238 analogix_dp_set_lane2_link_training(dp, training_lane_set); 239 break; 240 241 case 3: 242 analogix_dp_set_lane3_link_training(dp, training_lane_set); 243 break; 244 } 245 } 246 247 static unsigned int 248 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, 249 int lane) 250 { 251 u32 reg; 252 253 switch (lane) { 254 case 0: 255 reg = analogix_dp_get_lane0_link_training(dp); 256 break; 257 case 1: 258 reg = analogix_dp_get_lane1_link_training(dp); 259 break; 260 case 2: 261 reg = analogix_dp_get_lane2_link_training(dp); 262 break; 263 case 3: 264 reg = analogix_dp_get_lane3_link_training(dp); 265 break; 266 default: 267 WARN_ON(1); 268 return 0; 269 } 270 271 return reg; 272 } 273 274 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) 275 { 276 analogix_dp_training_pattern_dis(dp); 277 analogix_dp_set_enhanced_mode(dp); 278 279 dp->link_train.lt_state = FAILED; 280 } 281 282 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, 283 u8 adjust_request[2]) 284 { 285 int lane, lane_count; 286 u8 voltage_swing, pre_emphasis, training_lane; 287 288 lane_count = dp->link_train.lane_count; 289 for (lane = 0; lane < lane_count; lane++) { 290 voltage_swing = analogix_dp_get_adjust_request_voltage( 291 adjust_request, lane); 292 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 293 adjust_request, lane); 294 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | 295 DPCD_PRE_EMPHASIS_SET(pre_emphasis); 296 297 if (voltage_swing == VOLTAGE_LEVEL_3) 298 training_lane |= DP_TRAIN_MAX_SWING_REACHED; 299 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) 300 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 301 302 dp->link_train.training_lane[lane] = training_lane; 303 } 304 } 305 306 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) 307 { 308 int lane, lane_count, retval; 309 u8 voltage_swing, pre_emphasis, training_lane; 310 u8 link_status[2], adjust_request[2]; 311 312 udelay(101); 313 314 lane_count = dp->link_train.lane_count; 315 316 retval = analogix_dp_read_bytes_from_dpcd(dp, 317 DP_LANE0_1_STATUS, 2, link_status); 318 if (retval) 319 return retval; 320 321 retval = analogix_dp_read_bytes_from_dpcd(dp, 322 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 323 if (retval) 324 return retval; 325 326 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { 327 /* set training pattern 2 for EQ */ 328 analogix_dp_set_training_pattern(dp, TRAINING_PTN2); 329 330 retval = analogix_dp_write_byte_to_dpcd(dp, 331 DP_TRAINING_PATTERN_SET, 332 DP_LINK_SCRAMBLING_DISABLE | 333 DP_TRAINING_PATTERN_2); 334 if (retval) 335 return retval; 336 337 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 338 dp->link_train.lt_state = EQUALIZER_TRAINING; 339 } else { 340 for (lane = 0; lane < lane_count; lane++) { 341 training_lane = analogix_dp_get_lane_link_training( 342 dp, lane); 343 voltage_swing = analogix_dp_get_adjust_request_voltage( 344 adjust_request, lane); 345 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 346 adjust_request, lane); 347 348 if (DPCD_VOLTAGE_SWING_GET(training_lane) == 349 voltage_swing && 350 DPCD_PRE_EMPHASIS_GET(training_lane) == 351 pre_emphasis) 352 dp->link_train.cr_loop[lane]++; 353 354 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || 355 voltage_swing == VOLTAGE_LEVEL_3 || 356 pre_emphasis == PRE_EMPHASIS_LEVEL_3) { 357 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", 358 dp->link_train.cr_loop[lane], 359 voltage_swing, pre_emphasis); 360 analogix_dp_reduce_link_rate(dp); 361 return -EIO; 362 } 363 } 364 } 365 366 analogix_dp_get_adjust_training_lane(dp, adjust_request); 367 368 for (lane = 0; lane < lane_count; lane++) 369 analogix_dp_set_lane_link_training(dp, 370 dp->link_train.training_lane[lane], lane); 371 372 retval = analogix_dp_write_bytes_to_dpcd(dp, 373 DP_TRAINING_LANE0_SET, lane_count, 374 dp->link_train.training_lane); 375 if (retval) 376 return retval; 377 378 return retval; 379 } 380 381 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) 382 { 383 int lane, lane_count, retval; 384 u32 reg; 385 u8 link_align, link_status[2], adjust_request[2]; 386 387 udelay(401); 388 389 lane_count = dp->link_train.lane_count; 390 391 retval = analogix_dp_read_bytes_from_dpcd(dp, 392 DP_LANE0_1_STATUS, 2, link_status); 393 if (retval) 394 return retval; 395 396 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { 397 analogix_dp_reduce_link_rate(dp); 398 return -EIO; 399 } 400 401 retval = analogix_dp_read_bytes_from_dpcd(dp, 402 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 403 if (retval) 404 return retval; 405 406 retval = analogix_dp_read_byte_from_dpcd(dp, 407 DP_LANE_ALIGN_STATUS_UPDATED, &link_align); 408 if (retval) 409 return retval; 410 411 analogix_dp_get_adjust_training_lane(dp, adjust_request); 412 413 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { 414 /* traing pattern Set to Normal */ 415 analogix_dp_training_pattern_dis(dp); 416 417 printf("Link Training success!\n"); 418 419 analogix_dp_get_link_bandwidth(dp, ®); 420 dp->link_train.link_rate = reg; 421 analogix_dp_get_lane_count(dp, ®); 422 dp->link_train.lane_count = reg; 423 424 printf("final link rate = 0x%.2x, lane count = 0x%.2x\n", 425 dp->link_train.link_rate, dp->link_train.lane_count); 426 427 /* set enhanced mode if available */ 428 analogix_dp_set_enhanced_mode(dp); 429 dp->link_train.lt_state = FINISHED; 430 431 return 0; 432 } 433 434 /* not all locked */ 435 dp->link_train.eq_loop++; 436 437 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 438 dev_dbg(dp->dev, "EQ Max loop\n"); 439 analogix_dp_reduce_link_rate(dp); 440 return -EIO; 441 } 442 443 for (lane = 0; lane < lane_count; lane++) 444 analogix_dp_set_lane_link_training(dp, 445 dp->link_train.training_lane[lane], lane); 446 447 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 448 lane_count, dp->link_train.training_lane); 449 450 return retval; 451 } 452 453 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, 454 u8 *bandwidth) 455 { 456 u8 data; 457 458 /* 459 * For DP rev.1.1, Maximum link rate of Main Link lanes 460 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps 461 * For DP rev.1.2, Maximum link rate of Main Link lanes 462 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 463 */ 464 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); 465 *bandwidth = data; 466 } 467 468 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, 469 u8 *lane_count) 470 { 471 u8 data; 472 473 /* 474 * For DP rev.1.1, Maximum number of Main Link lanes 475 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 476 */ 477 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 478 *lane_count = DPCD_MAX_LANE_COUNT(data); 479 } 480 481 static int analogix_dp_init_training(struct analogix_dp_device *dp, 482 enum link_lane_count_type max_lane, 483 int max_rate) 484 { 485 /* 486 * MACRO_RST must be applied after the PLL_LOCK to avoid 487 * the DP inter pair skew issue for at least 10 us 488 */ 489 analogix_dp_reset_macro(dp); 490 491 /* Initialize by reading RX's DPCD */ 492 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); 493 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); 494 495 if ((dp->link_train.link_rate != DP_LINK_BW_1_62) && 496 (dp->link_train.link_rate != DP_LINK_BW_2_7) && 497 (dp->link_train.link_rate != DP_LINK_BW_5_4)) { 498 dev_err(dp->dev, "failed to get Rx Max Link Rate\n"); 499 return -ENODEV; 500 } 501 502 if (dp->link_train.lane_count == 0) { 503 dev_err(dp->dev, "failed to get Rx Max Lane Count\n"); 504 return -ENODEV; 505 } 506 507 /* Setup TX lane count & rate */ 508 if (dp->link_train.lane_count > max_lane) 509 dp->link_train.lane_count = max_lane; 510 if (dp->link_train.link_rate > max_rate) 511 dp->link_train.link_rate = max_rate; 512 513 /* All DP analog module power up */ 514 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 515 516 return 0; 517 } 518 519 static int analogix_dp_sw_link_training(struct analogix_dp_device *dp) 520 { 521 int retval = 0, training_finished = 0; 522 523 dp->link_train.lt_state = START; 524 525 /* Process here */ 526 while (!retval && !training_finished) { 527 switch (dp->link_train.lt_state) { 528 case START: 529 retval = analogix_dp_link_start(dp); 530 if (retval) 531 dev_err(dp->dev, "LT link start failed!\n"); 532 break; 533 case CLOCK_RECOVERY: 534 retval = analogix_dp_process_clock_recovery(dp); 535 if (retval) 536 dev_err(dp->dev, "LT CR failed!\n"); 537 break; 538 case EQUALIZER_TRAINING: 539 retval = analogix_dp_process_equalizer_training(dp); 540 if (retval) 541 dev_err(dp->dev, "LT EQ failed!\n"); 542 break; 543 case FINISHED: 544 training_finished = 1; 545 break; 546 case FAILED: 547 return -EREMOTEIO; 548 } 549 } 550 551 return retval; 552 } 553 554 static int analogix_dp_set_link_train(struct analogix_dp_device *dp, 555 u32 count, u32 bwtype) 556 { 557 int ret; 558 559 ret = analogix_dp_init_training(dp, count, bwtype); 560 if (ret < 0) { 561 dev_err(dp->dev, "failed to init training\n"); 562 return ret; 563 } 564 565 ret = analogix_dp_sw_link_training(dp); 566 if (ret < 0) { 567 dev_err(dp->dev, "failed to do sw link training\n"); 568 return ret; 569 } 570 571 return 0; 572 } 573 574 static int analogix_dp_config_video(struct analogix_dp_device *dp) 575 { 576 int timeout_loop = 0; 577 int done_count = 0; 578 579 analogix_dp_config_video_slave_mode(dp); 580 581 analogix_dp_set_video_color_format(dp); 582 583 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 584 dev_err(dp->dev, "PLL is not locked yet.\n"); 585 return -EINVAL; 586 } 587 588 for (;;) { 589 timeout_loop++; 590 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) 591 break; 592 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 593 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 594 return -ETIMEDOUT; 595 } 596 597 udelay(2); 598 } 599 600 /* Set to use the register calculated M/N video */ 601 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); 602 603 /* For video bist, Video timing must be generated by register */ 604 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE); 605 606 /* Disable video mute */ 607 analogix_dp_enable_video_mute(dp, 0); 608 609 /* Configure video slave mode */ 610 analogix_dp_enable_video_master(dp, 0); 611 612 /* Enable video input */ 613 analogix_dp_start_video(dp); 614 615 timeout_loop = 0; 616 617 for (;;) { 618 timeout_loop++; 619 if (analogix_dp_is_video_stream_on(dp) == 0) { 620 done_count++; 621 if (done_count > 10) 622 break; 623 } else if (done_count) { 624 done_count = 0; 625 } 626 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 627 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 628 return -ETIMEDOUT; 629 } 630 631 udelay(1001); 632 } 633 634 return 0; 635 } 636 637 static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, 638 bool enable) 639 { 640 u8 data; 641 642 if (enable) { 643 analogix_dp_enable_scrambling(dp); 644 645 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 646 &data); 647 analogix_dp_write_byte_to_dpcd(dp, 648 DP_TRAINING_PATTERN_SET, 649 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); 650 } else { 651 analogix_dp_disable_scrambling(dp); 652 653 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 654 &data); 655 analogix_dp_write_byte_to_dpcd(dp, 656 DP_TRAINING_PATTERN_SET, 657 (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); 658 } 659 } 660 661 static void analogix_dp_init_dp(struct analogix_dp_device *dp) 662 { 663 analogix_dp_reset(dp); 664 665 analogix_dp_swreset(dp); 666 667 analogix_dp_init_analog_param(dp); 668 analogix_dp_init_interrupt(dp); 669 670 /* SW defined function Normal operation */ 671 analogix_dp_enable_sw_function(dp); 672 673 analogix_dp_config_interrupt(dp); 674 analogix_dp_init_analog_func(dp); 675 676 analogix_dp_init_hpd(dp); 677 analogix_dp_init_aux(dp); 678 } 679 680 static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data) 681 { 682 int i; 683 unsigned char sum = 0; 684 685 for (i = 0; i < EDID_BLOCK_LENGTH; i++) 686 sum = sum + edid_data[i]; 687 688 return sum; 689 } 690 691 static int analogix_dp_read_edid(struct analogix_dp_device *dp) 692 { 693 unsigned char *edid = dp->edid; 694 unsigned int extend_block = 0; 695 unsigned char test_vector; 696 int retval; 697 698 /* 699 * EDID device address is 0x50. 700 * However, if necessary, you must have set upper address 701 * into E-EDID in I2C device, 0x30. 702 */ 703 704 /* Read Extension Flag, Number of 128-byte EDID extension blocks */ 705 retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, 706 EDID_EXTENSION_FLAG, 707 &extend_block); 708 if (retval) 709 return retval; 710 711 if (extend_block > 0) { 712 debug("EDID data includes a single extension!\n"); 713 714 /* Read EDID data */ 715 retval = analogix_dp_read_bytes_from_i2c(dp, 716 I2C_EDID_DEVICE_ADDR, 717 EDID_HEADER_PATTERN, 718 EDID_BLOCK_LENGTH, 719 &edid[EDID_HEADER_PATTERN]); 720 if (retval < 0) 721 return retval; 722 723 if (analogix_dp_calc_edid_check_sum(edid)) 724 return -EINVAL; 725 726 /* Read additional EDID data */ 727 retval = analogix_dp_read_bytes_from_i2c(dp, 728 I2C_EDID_DEVICE_ADDR, 729 EDID_BLOCK_LENGTH, 730 EDID_BLOCK_LENGTH, 731 &edid[EDID_BLOCK_LENGTH]); 732 if (retval < 0) 733 return retval; 734 735 if (analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH])) 736 return -EINVAL; 737 738 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 739 &test_vector); 740 if (test_vector & DP_TEST_LINK_EDID_READ) { 741 analogix_dp_write_byte_to_dpcd(dp, 742 DP_TEST_EDID_CHECKSUM, 743 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); 744 analogix_dp_write_byte_to_dpcd(dp, 745 DP_TEST_RESPONSE, 746 DP_TEST_EDID_CHECKSUM_WRITE); 747 } 748 } else { 749 dev_info(dp->dev, 750 "EDID data does not include any extensions.\n"); 751 752 /* Read EDID data */ 753 retval = analogix_dp_read_bytes_from_i2c(dp, 754 I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN, 755 EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]); 756 if (retval < 0) 757 return retval; 758 759 if (analogix_dp_calc_edid_check_sum(edid)) 760 return -EINVAL; 761 762 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 763 &test_vector); 764 if (test_vector & DP_TEST_LINK_EDID_READ) { 765 analogix_dp_write_byte_to_dpcd(dp, 766 DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]); 767 analogix_dp_write_byte_to_dpcd(dp, 768 DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE); 769 } 770 } 771 772 return 0; 773 } 774 775 static int analogix_dp_handle_edid(struct analogix_dp_device *dp) 776 { 777 u8 buf[12]; 778 int i, try = 5; 779 int retval; 780 781 retry: 782 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */ 783 retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf); 784 785 if (retval && try--) { 786 mdelay(10); 787 goto retry; 788 } 789 790 if (retval) 791 return retval; 792 793 /* Read EDID */ 794 for (i = 0; i < 3; i++) { 795 retval = analogix_dp_read_edid(dp); 796 if (!retval) 797 break; 798 } 799 800 return retval; 801 } 802 803 static int analogix_dp_connector_init(struct display_state *state) 804 { 805 struct connector_state *conn_state = &state->conn_state; 806 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 807 808 conn_state->type = DRM_MODE_CONNECTOR_eDP; 809 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 810 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 811 812 /* eDP software reset request */ 813 reset_assert(&dp->reset); 814 udelay(1); 815 reset_deassert(&dp->reset); 816 817 analogix_dp_init_dp(dp); 818 819 return 0; 820 } 821 822 static int analogix_dp_connector_get_edid(struct display_state *state) 823 { 824 struct connector_state *conn_state = &state->conn_state; 825 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 826 int ret; 827 828 ret = analogix_dp_handle_edid(dp); 829 if (ret) { 830 dev_err(dp->dev, "failed to get edid\n"); 831 return ret; 832 } 833 834 memcpy(&conn_state->edid, &dp->edid, sizeof(dp->edid)); 835 836 return 0; 837 } 838 839 static int analogix_dp_connector_enable(struct display_state *state) 840 { 841 struct connector_state *conn_state = &state->conn_state; 842 struct crtc_state *crtc_state = &state->crtc_state; 843 const struct rockchip_connector *connector = conn_state->connector; 844 const struct rockchip_dp_chip_data *pdata = connector->data; 845 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 846 struct video_info *video = &dp->video_info; 847 u32 val; 848 int ret; 849 850 if (pdata->has_vop_sel) { 851 if (crtc_state->crtc_id) 852 val = pdata->lcdsel_lit; 853 else 854 val = pdata->lcdsel_big; 855 856 writel(val, dp->grf + pdata->lcdsel_grf_reg); 857 } 858 859 switch (conn_state->bpc) { 860 case 12: 861 video->color_depth = COLOR_12; 862 break; 863 case 10: 864 video->color_depth = COLOR_10; 865 break; 866 case 6: 867 video->color_depth = COLOR_6; 868 break; 869 case 8: 870 default: 871 video->color_depth = COLOR_8; 872 break; 873 } 874 875 ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count, 876 dp->video_info.max_link_rate); 877 if (ret) { 878 dev_err(dp->dev, "unable to do link train\n"); 879 return ret; 880 } 881 882 analogix_dp_enable_scramble(dp, 1); 883 analogix_dp_enable_rx_to_enhanced_mode(dp, 1); 884 analogix_dp_enable_enhanced_mode(dp, 1); 885 886 analogix_dp_init_video(dp); 887 ret = analogix_dp_config_video(dp); 888 if (ret) { 889 dev_err(dp->dev, "unable to config video\n"); 890 return ret; 891 } 892 893 return 0; 894 } 895 896 static int analogix_dp_connector_disable(struct display_state *state) 897 { 898 /* TODO */ 899 900 return 0; 901 } 902 903 static const struct rockchip_connector_funcs analogix_dp_connector_funcs = { 904 .init = analogix_dp_connector_init, 905 .get_edid = analogix_dp_connector_get_edid, 906 .enable = analogix_dp_connector_enable, 907 .disable = analogix_dp_connector_disable, 908 }; 909 910 static int analogix_dp_probe(struct udevice *dev) 911 { 912 struct analogix_dp_device *dp = dev_get_priv(dev); 913 const struct rockchip_connector *connector = 914 (const struct rockchip_connector *)dev_get_driver_data(dev); 915 const struct rockchip_dp_chip_data *pdata = connector->data; 916 int ret; 917 918 dp->reg_base = dev_read_addr_ptr(dev); 919 dp->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 920 if (IS_ERR(dp->grf)) 921 return PTR_ERR(dp->grf); 922 923 ret = reset_get_by_name(dev, "dp", &dp->reset); 924 if (ret) { 925 dev_err(dev, "failed to get reset control: %d\n", ret); 926 return ret; 927 } 928 929 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 930 GPIOD_IS_IN); 931 if (ret && ret != -ENOENT) { 932 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 933 return ret; 934 } 935 936 dp->plat_data.dev_type = ROCKCHIP_DP; 937 dp->plat_data.subdev_type = pdata->chip_type; 938 /* 939 * Like Rockchip DisplayPort TRM indicate that "Main link 940 * containing 4 physical lanes of 2.7/1.62 Gbps/lane". 941 */ 942 dp->video_info.max_link_rate = 0x0A; 943 dp->video_info.max_lane_count = 0x04; 944 945 dp->dev = dev; 946 947 return 0; 948 } 949 950 static const struct rockchip_dp_chip_data rk3288_edp_platform_data = { 951 .lcdsel_grf_reg = 0x025c, 952 .lcdsel_big = 0 | BIT(21), 953 .lcdsel_lit = BIT(5) | BIT(21), 954 .chip_type = RK3288_DP, 955 .has_vop_sel = true, 956 }; 957 958 static const struct rockchip_connector rk3288_edp_driver_data = { 959 .funcs = &analogix_dp_connector_funcs, 960 .data = &rk3288_edp_platform_data, 961 }; 962 963 static const struct rockchip_dp_chip_data rk3368_edp_platform_data = { 964 .chip_type = RK3368_EDP, 965 .has_vop_sel = false, 966 }; 967 968 static const struct rockchip_connector rk3368_edp_driver_data = { 969 .funcs = &analogix_dp_connector_funcs, 970 .data = &rk3368_edp_platform_data, 971 }; 972 973 static const struct rockchip_dp_chip_data rk3399_edp_platform_data = { 974 .lcdsel_grf_reg = 0x6250, 975 .lcdsel_big = 0 | BIT(21), 976 .lcdsel_lit = BIT(5) | BIT(21), 977 .chip_type = RK3399_EDP, 978 .has_vop_sel = true, 979 }; 980 981 static const struct rockchip_connector rk3399_edp_driver_data = { 982 .funcs = &analogix_dp_connector_funcs, 983 .data = &rk3399_edp_platform_data, 984 }; 985 986 static const struct udevice_id analogix_dp_ids[] = { 987 { 988 .compatible = "rockchip,rk3288-dp", 989 .data = (ulong)&rk3288_edp_driver_data, 990 }, { 991 .compatible = "rockchip,rk3368-edp", 992 .data = (ulong)&rk3368_edp_driver_data, 993 }, { 994 .compatible = "rockchip,rk3399-edp", 995 .data = (ulong)&rk3399_edp_driver_data, 996 }, 997 {} 998 }; 999 1000 U_BOOT_DRIVER(analogix_dp) = { 1001 .name = "analogix_dp", 1002 .id = UCLASS_DISPLAY, 1003 .of_match = analogix_dp_ids, 1004 .probe = analogix_dp_probe, 1005 .priv_auto_alloc_size = sizeof(struct analogix_dp_device), 1006 }; 1007