1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <dm/device.h> 14 #include <dm/of_access.h> 15 #include <dm/read.h> 16 #include <linux/bitfield.h> 17 #include <linux/list.h> 18 #include <syscon.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <asm/gpio.h> 21 22 #include "rockchip_display.h" 23 #include "rockchip_crtc.h" 24 #include "rockchip_connector.h" 25 #include "analogix_dp.h" 26 27 #define RK3588_GRF_VO1_CON0 0x0000 28 #define EDP_MODE BIT(0) 29 #define RK3588_GRF_VO1_CON1 0x0004 30 31 /** 32 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips 33 * @lcdsel_grf_reg: grf register offset of lcdc select 34 * @lcdsel_big: reg value of selecting vop big for eDP 35 * @lcdsel_lit: reg value of selecting vop little for eDP 36 * @chip_type: specific chip type 37 * @ssc: check if SSC is supported by source 38 */ 39 struct rockchip_dp_chip_data { 40 u32 lcdsel_grf_reg; 41 u32 lcdsel_big; 42 u32 lcdsel_lit; 43 u32 chip_type; 44 bool ssc; 45 46 u32 max_link_rate; 47 u32 max_lane_count; 48 }; 49 50 static void 51 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, 52 bool enable) 53 { 54 u8 data; 55 56 analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data); 57 58 if (enable) 59 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 60 DP_LANE_COUNT_ENHANCED_FRAME_EN | 61 DPCD_LANE_COUNT_SET(data)); 62 else 63 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 64 DPCD_LANE_COUNT_SET(data)); 65 } 66 67 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp) 68 { 69 u8 data; 70 int retval; 71 72 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 73 retval = DPCD_ENHANCED_FRAME_CAP(data); 74 75 return retval; 76 } 77 78 static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) 79 { 80 u8 data; 81 82 data = analogix_dp_is_enhanced_mode_available(dp); 83 analogix_dp_enable_rx_to_enhanced_mode(dp, data); 84 analogix_dp_enable_enhanced_mode(dp, data); 85 } 86 87 static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) 88 { 89 analogix_dp_set_training_pattern(dp, DP_NONE); 90 91 analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET, 92 DP_TRAINING_PATTERN_DISABLE); 93 } 94 95 static int analogix_dp_link_start(struct analogix_dp_device *dp) 96 { 97 u8 buf[4]; 98 int lane, lane_count, retval; 99 100 lane_count = dp->link_train.lane_count; 101 102 dp->link_train.lt_state = CLOCK_RECOVERY; 103 dp->link_train.eq_loop = 0; 104 105 for (lane = 0; lane < lane_count; lane++) 106 dp->link_train.cr_loop[lane] = 0; 107 108 /* Set link rate and count as you want to establish*/ 109 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 110 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 111 112 /* Setup RX configuration */ 113 buf[0] = dp->link_train.link_rate; 114 buf[1] = dp->link_train.lane_count; 115 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf); 116 if (retval) 117 return retval; 118 119 /* Spread AMP if required, enable 8b/10b coding */ 120 buf[0] = analogix_dp_ssc_supported(dp) ? DP_SPREAD_AMP_0_5 : 0; 121 buf[1] = DP_SET_ANSI_8B10B; 122 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_DOWNSPREAD_CTRL, 123 2, buf); 124 if (retval < 0) 125 return retval; 126 127 /* Set TX voltage-swing and pre-emphasis to minimum */ 128 for (lane = 0; lane < lane_count; lane++) 129 dp->link_train.training_lane[lane] = 130 DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | 131 DP_TRAIN_PRE_EMPH_LEVEL_0; 132 analogix_dp_set_lane_link_training(dp); 133 134 /* Set training pattern 1 */ 135 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 136 137 /* Set RX training pattern */ 138 retval = analogix_dp_write_byte_to_dpcd(dp, 139 DP_TRAINING_PATTERN_SET, 140 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); 141 if (retval) 142 return retval; 143 144 for (lane = 0; lane < lane_count; lane++) 145 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 146 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 147 148 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 149 lane_count, buf); 150 151 return retval; 152 } 153 154 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) 155 { 156 int shift = (lane & 1) * 4; 157 u8 link_value = link_status[lane >> 1]; 158 159 return (link_value >> shift) & 0xf; 160 } 161 162 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) 163 { 164 int lane; 165 u8 lane_status; 166 167 for (lane = 0; lane < lane_count; lane++) { 168 lane_status = analogix_dp_get_lane_status(link_status, lane); 169 if ((lane_status & DP_LANE_CR_DONE) == 0) 170 return -EINVAL; 171 } 172 return 0; 173 } 174 175 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, 176 int lane_count) 177 { 178 int lane; 179 u8 lane_status; 180 181 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) 182 return -EINVAL; 183 184 for (lane = 0; lane < lane_count; lane++) { 185 lane_status = analogix_dp_get_lane_status(link_status, lane); 186 lane_status &= DP_CHANNEL_EQ_BITS; 187 if (lane_status != DP_CHANNEL_EQ_BITS) 188 return -EINVAL; 189 } 190 191 return 0; 192 } 193 194 static unsigned char 195 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) 196 { 197 int shift = (lane & 1) * 4; 198 u8 link_value = adjust_request[lane >> 1]; 199 200 return (link_value >> shift) & 0x3; 201 } 202 203 static unsigned char analogix_dp_get_adjust_request_pre_emphasis( 204 u8 adjust_request[2], 205 int lane) 206 { 207 int shift = (lane & 1) * 4; 208 u8 link_value = adjust_request[lane >> 1]; 209 210 return ((link_value >> shift) & 0xc) >> 2; 211 } 212 213 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) 214 { 215 analogix_dp_training_pattern_dis(dp); 216 analogix_dp_set_enhanced_mode(dp); 217 218 dp->link_train.lt_state = FAILED; 219 } 220 221 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, 222 u8 adjust_request[2]) 223 { 224 int lane, lane_count; 225 u8 voltage_swing, pre_emphasis, training_lane; 226 227 lane_count = dp->link_train.lane_count; 228 for (lane = 0; lane < lane_count; lane++) { 229 voltage_swing = analogix_dp_get_adjust_request_voltage( 230 adjust_request, lane); 231 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 232 adjust_request, lane); 233 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | 234 DPCD_PRE_EMPHASIS_SET(pre_emphasis); 235 236 if (voltage_swing == VOLTAGE_LEVEL_3) 237 training_lane |= DP_TRAIN_MAX_SWING_REACHED; 238 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) 239 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 240 241 dp->link_train.training_lane[lane] = training_lane; 242 } 243 } 244 245 static bool analogix_dp_tps3_supported(struct analogix_dp_device *dp) 246 { 247 bool source_tps3_supported, sink_tps3_supported; 248 u8 dpcd = 0; 249 250 source_tps3_supported = 251 dp->video_info.max_link_rate == DP_LINK_BW_5_4; 252 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &dpcd); 253 sink_tps3_supported = dpcd & DP_TPS3_SUPPORTED; 254 255 return source_tps3_supported && sink_tps3_supported; 256 } 257 258 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) 259 { 260 int lane, lane_count, retval; 261 u8 voltage_swing, pre_emphasis, training_lane; 262 u8 link_status[2], adjust_request[2]; 263 u8 training_pattern = TRAINING_PTN2; 264 265 drm_dp_link_train_clock_recovery_delay(dp->dpcd); 266 267 lane_count = dp->link_train.lane_count; 268 269 retval = analogix_dp_read_bytes_from_dpcd(dp, 270 DP_LANE0_1_STATUS, 2, link_status); 271 if (retval) 272 return retval; 273 274 retval = analogix_dp_read_bytes_from_dpcd(dp, 275 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 276 if (retval) 277 return retval; 278 279 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { 280 if (analogix_dp_tps3_supported(dp)) 281 training_pattern = TRAINING_PTN3; 282 283 /* set training pattern for EQ */ 284 analogix_dp_set_training_pattern(dp, training_pattern); 285 286 retval = analogix_dp_write_byte_to_dpcd(dp, 287 DP_TRAINING_PATTERN_SET, 288 (training_pattern == TRAINING_PTN3 ? 289 DP_TRAINING_PATTERN_3 : DP_TRAINING_PATTERN_2)); 290 if (retval) 291 return retval; 292 293 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 294 dp->link_train.lt_state = EQUALIZER_TRAINING; 295 } else { 296 for (lane = 0; lane < lane_count; lane++) { 297 training_lane = analogix_dp_get_lane_link_training( 298 dp, lane); 299 voltage_swing = analogix_dp_get_adjust_request_voltage( 300 adjust_request, lane); 301 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 302 adjust_request, lane); 303 304 if (DPCD_VOLTAGE_SWING_GET(training_lane) == 305 voltage_swing && 306 DPCD_PRE_EMPHASIS_GET(training_lane) == 307 pre_emphasis) 308 dp->link_train.cr_loop[lane]++; 309 310 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || 311 voltage_swing == VOLTAGE_LEVEL_3 || 312 pre_emphasis == PRE_EMPHASIS_LEVEL_3) { 313 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", 314 dp->link_train.cr_loop[lane], 315 voltage_swing, pre_emphasis); 316 analogix_dp_reduce_link_rate(dp); 317 return -EIO; 318 } 319 } 320 } 321 322 analogix_dp_get_adjust_training_lane(dp, adjust_request); 323 analogix_dp_set_lane_link_training(dp); 324 325 retval = analogix_dp_write_bytes_to_dpcd(dp, 326 DP_TRAINING_LANE0_SET, lane_count, 327 dp->link_train.training_lane); 328 if (retval) 329 return retval; 330 331 return retval; 332 } 333 334 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) 335 { 336 int lane_count, retval; 337 u32 reg; 338 u8 link_align, link_status[2], adjust_request[2]; 339 340 drm_dp_link_train_channel_eq_delay(dp->dpcd); 341 342 lane_count = dp->link_train.lane_count; 343 344 retval = analogix_dp_read_bytes_from_dpcd(dp, 345 DP_LANE0_1_STATUS, 2, link_status); 346 if (retval) 347 return retval; 348 349 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { 350 analogix_dp_reduce_link_rate(dp); 351 return -EIO; 352 } 353 354 retval = analogix_dp_read_bytes_from_dpcd(dp, 355 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 356 if (retval) 357 return retval; 358 359 retval = analogix_dp_read_byte_from_dpcd(dp, 360 DP_LANE_ALIGN_STATUS_UPDATED, &link_align); 361 if (retval) 362 return retval; 363 364 analogix_dp_get_adjust_training_lane(dp, adjust_request); 365 366 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { 367 /* traing pattern Set to Normal */ 368 analogix_dp_training_pattern_dis(dp); 369 370 printf("Link Training success!\n"); 371 372 analogix_dp_get_link_bandwidth(dp, ®); 373 dp->link_train.link_rate = reg; 374 analogix_dp_get_lane_count(dp, ®); 375 dp->link_train.lane_count = reg; 376 377 printf("final link rate = 0x%.2x, lane count = 0x%.2x\n", 378 dp->link_train.link_rate, dp->link_train.lane_count); 379 380 /* set enhanced mode if available */ 381 analogix_dp_set_enhanced_mode(dp); 382 dp->link_train.lt_state = FINISHED; 383 384 return 0; 385 } 386 387 /* not all locked */ 388 dp->link_train.eq_loop++; 389 390 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 391 dev_dbg(dp->dev, "EQ Max loop\n"); 392 analogix_dp_reduce_link_rate(dp); 393 return -EIO; 394 } 395 396 analogix_dp_set_lane_link_training(dp); 397 398 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 399 lane_count, dp->link_train.training_lane); 400 401 return retval; 402 } 403 404 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, 405 u8 *bandwidth) 406 { 407 u8 data; 408 409 /* 410 * For DP rev.1.1, Maximum link rate of Main Link lanes 411 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps 412 * For DP rev.1.2, Maximum link rate of Main Link lanes 413 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 414 */ 415 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); 416 *bandwidth = data; 417 } 418 419 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, 420 u8 *lane_count) 421 { 422 u8 data; 423 424 /* 425 * For DP rev.1.1, Maximum number of Main Link lanes 426 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 427 */ 428 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 429 *lane_count = DPCD_MAX_LANE_COUNT(data); 430 } 431 432 static int analogix_dp_init_training(struct analogix_dp_device *dp, 433 enum link_lane_count_type max_lane, 434 int max_rate) 435 { 436 u8 dpcd; 437 438 /* 439 * MACRO_RST must be applied after the PLL_LOCK to avoid 440 * the DP inter pair skew issue for at least 10 us 441 */ 442 analogix_dp_reset_macro(dp); 443 444 /* Initialize by reading RX's DPCD */ 445 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); 446 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); 447 448 if ((dp->link_train.link_rate != DP_LINK_BW_1_62) && 449 (dp->link_train.link_rate != DP_LINK_BW_2_7) && 450 (dp->link_train.link_rate != DP_LINK_BW_5_4)) { 451 dev_err(dp->dev, "failed to get Rx Max Link Rate\n"); 452 return -ENODEV; 453 } 454 455 if (dp->link_train.lane_count == 0) { 456 dev_err(dp->dev, "failed to get Rx Max Lane Count\n"); 457 return -ENODEV; 458 } 459 460 /* Setup TX lane count & rate */ 461 if (dp->link_train.lane_count > max_lane) 462 dp->link_train.lane_count = max_lane; 463 if (dp->link_train.link_rate > max_rate) 464 dp->link_train.link_rate = max_rate; 465 466 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_DOWNSPREAD, &dpcd); 467 dp->link_train.ssc = !!(dpcd & DP_MAX_DOWNSPREAD_0_5); 468 469 /* All DP analog module power up */ 470 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 471 472 return 0; 473 } 474 475 static int analogix_dp_sw_link_training(struct analogix_dp_device *dp) 476 { 477 int retval = 0, training_finished = 0; 478 479 dp->link_train.lt_state = START; 480 481 /* Process here */ 482 while (!retval && !training_finished) { 483 switch (dp->link_train.lt_state) { 484 case START: 485 retval = analogix_dp_link_start(dp); 486 if (retval) 487 dev_err(dp->dev, "LT link start failed!\n"); 488 break; 489 case CLOCK_RECOVERY: 490 retval = analogix_dp_process_clock_recovery(dp); 491 if (retval) 492 dev_err(dp->dev, "LT CR failed!\n"); 493 break; 494 case EQUALIZER_TRAINING: 495 retval = analogix_dp_process_equalizer_training(dp); 496 if (retval) 497 dev_err(dp->dev, "LT EQ failed!\n"); 498 break; 499 case FINISHED: 500 training_finished = 1; 501 break; 502 case FAILED: 503 return -EREMOTEIO; 504 } 505 } 506 507 return retval; 508 } 509 510 static int analogix_dp_set_link_train(struct analogix_dp_device *dp, 511 u32 count, u32 bwtype) 512 { 513 int i, ret; 514 515 for (i = 0; i < 5; i++) { 516 ret = analogix_dp_init_training(dp, count, bwtype); 517 if (ret < 0) { 518 dev_err(dp->dev, "failed to init training\n"); 519 return ret; 520 } 521 522 ret = analogix_dp_sw_link_training(dp); 523 if (!ret) 524 break; 525 } 526 527 return ret; 528 } 529 530 static int analogix_dp_config_video(struct analogix_dp_device *dp) 531 { 532 int timeout_loop = 0; 533 int done_count = 0; 534 535 analogix_dp_config_video_slave_mode(dp); 536 537 analogix_dp_set_video_color_format(dp); 538 539 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 540 dev_err(dp->dev, "PLL is not locked yet.\n"); 541 return -EINVAL; 542 } 543 544 for (;;) { 545 timeout_loop++; 546 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) 547 break; 548 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 549 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 550 return -ETIMEDOUT; 551 } 552 553 udelay(2); 554 } 555 556 /* Set to use the register calculated M/N video */ 557 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); 558 559 /* For video bist, Video timing must be generated by register */ 560 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE); 561 562 /* Disable video mute */ 563 analogix_dp_enable_video_mute(dp, 0); 564 565 /* Configure video slave mode */ 566 analogix_dp_enable_video_master(dp, 0); 567 568 /* Enable video input */ 569 analogix_dp_start_video(dp); 570 571 timeout_loop = 0; 572 573 for (;;) { 574 timeout_loop++; 575 if (analogix_dp_is_video_stream_on(dp) == 0) { 576 done_count++; 577 if (done_count > 10) 578 break; 579 } else if (done_count) { 580 done_count = 0; 581 } 582 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 583 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 584 return -ETIMEDOUT; 585 } 586 587 udelay(1001); 588 } 589 590 return 0; 591 } 592 593 static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, 594 bool enable) 595 { 596 u8 data; 597 598 if (enable) { 599 analogix_dp_enable_scrambling(dp); 600 601 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 602 &data); 603 analogix_dp_write_byte_to_dpcd(dp, 604 DP_TRAINING_PATTERN_SET, 605 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); 606 } else { 607 analogix_dp_disable_scrambling(dp); 608 609 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 610 &data); 611 analogix_dp_write_byte_to_dpcd(dp, 612 DP_TRAINING_PATTERN_SET, 613 (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); 614 } 615 } 616 617 static void analogix_dp_init_dp(struct analogix_dp_device *dp) 618 { 619 analogix_dp_reset(dp); 620 621 analogix_dp_swreset(dp); 622 623 analogix_dp_init_analog_param(dp); 624 analogix_dp_init_interrupt(dp); 625 626 /* SW defined function Normal operation */ 627 analogix_dp_enable_sw_function(dp); 628 629 analogix_dp_config_interrupt(dp); 630 analogix_dp_init_analog_func(dp); 631 632 analogix_dp_init_hpd(dp); 633 analogix_dp_init_aux(dp); 634 } 635 636 static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data) 637 { 638 int i; 639 unsigned char sum = 0; 640 641 for (i = 0; i < EDID_BLOCK_LENGTH; i++) 642 sum = sum + edid_data[i]; 643 644 return sum; 645 } 646 647 static int analogix_dp_read_edid(struct analogix_dp_device *dp) 648 { 649 unsigned char *edid = dp->edid; 650 unsigned int extend_block = 0; 651 unsigned char test_vector; 652 int retval; 653 654 /* 655 * EDID device address is 0x50. 656 * However, if necessary, you must have set upper address 657 * into E-EDID in I2C device, 0x30. 658 */ 659 660 /* Read Extension Flag, Number of 128-byte EDID extension blocks */ 661 retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, 662 EDID_EXTENSION_FLAG, 663 &extend_block); 664 if (retval) 665 return retval; 666 667 if (extend_block > 0) { 668 debug("EDID data includes a single extension!\n"); 669 670 /* Read EDID data */ 671 retval = analogix_dp_read_bytes_from_i2c(dp, 672 I2C_EDID_DEVICE_ADDR, 673 EDID_HEADER_PATTERN, 674 EDID_BLOCK_LENGTH, 675 &edid[EDID_HEADER_PATTERN]); 676 if (retval < 0) 677 return retval; 678 679 if (analogix_dp_calc_edid_check_sum(edid)) 680 return -EINVAL; 681 682 /* Read additional EDID data */ 683 retval = analogix_dp_read_bytes_from_i2c(dp, 684 I2C_EDID_DEVICE_ADDR, 685 EDID_BLOCK_LENGTH, 686 EDID_BLOCK_LENGTH, 687 &edid[EDID_BLOCK_LENGTH]); 688 if (retval < 0) 689 return retval; 690 691 if (analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH])) 692 return -EINVAL; 693 694 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 695 &test_vector); 696 if (test_vector & DP_TEST_LINK_EDID_READ) { 697 analogix_dp_write_byte_to_dpcd(dp, 698 DP_TEST_EDID_CHECKSUM, 699 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); 700 analogix_dp_write_byte_to_dpcd(dp, 701 DP_TEST_RESPONSE, 702 DP_TEST_EDID_CHECKSUM_WRITE); 703 } 704 } else { 705 dev_info(dp->dev, 706 "EDID data does not include any extensions.\n"); 707 708 /* Read EDID data */ 709 retval = analogix_dp_read_bytes_from_i2c(dp, 710 I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN, 711 EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]); 712 if (retval < 0) 713 return retval; 714 715 if (analogix_dp_calc_edid_check_sum(edid)) 716 return -EINVAL; 717 718 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 719 &test_vector); 720 if (test_vector & DP_TEST_LINK_EDID_READ) { 721 analogix_dp_write_byte_to_dpcd(dp, 722 DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]); 723 analogix_dp_write_byte_to_dpcd(dp, 724 DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE); 725 } 726 } 727 728 return 0; 729 } 730 731 static int analogix_dp_handle_edid(struct analogix_dp_device *dp) 732 { 733 u8 buf[12]; 734 int i, try = 5; 735 int retval; 736 737 retry: 738 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */ 739 retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf); 740 741 if (retval && try--) { 742 mdelay(10); 743 goto retry; 744 } 745 746 if (retval) 747 return retval; 748 749 /* Read EDID */ 750 for (i = 0; i < 3; i++) { 751 retval = analogix_dp_read_edid(dp); 752 if (!retval) 753 break; 754 } 755 756 return retval; 757 } 758 759 static int analogix_dp_connector_pre_init(struct display_state *state) 760 { 761 struct connector_state *conn_state = &state->conn_state; 762 763 conn_state->type = DRM_MODE_CONNECTOR_eDP; 764 765 return 0; 766 } 767 768 static int analogix_dp_connector_init(struct display_state *state) 769 { 770 struct connector_state *conn_state = &state->conn_state; 771 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 772 773 conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_eDP1 : VOP_OUTPUT_IF_eDP0; 774 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 775 conn_state->color_space = V4L2_COLORSPACE_DEFAULT; 776 777 reset_assert_bulk(&dp->resets); 778 udelay(1); 779 reset_deassert_bulk(&dp->resets); 780 781 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dp->id); 782 generic_phy_set_mode(&dp->phy, PHY_MODE_DP); 783 generic_phy_power_on(&dp->phy); 784 analogix_dp_init_dp(dp); 785 786 return 0; 787 } 788 789 static int analogix_dp_connector_get_edid(struct display_state *state) 790 { 791 struct connector_state *conn_state = &state->conn_state; 792 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 793 int ret; 794 795 ret = analogix_dp_handle_edid(dp); 796 if (ret) { 797 dev_err(dp->dev, "failed to get edid\n"); 798 return ret; 799 } 800 801 memcpy(&conn_state->edid, &dp->edid, sizeof(dp->edid)); 802 803 return 0; 804 } 805 806 static int analogix_dp_link_power_up(struct analogix_dp_device *dp) 807 { 808 u8 value; 809 int ret; 810 811 if (dp->dpcd[DP_DPCD_REV] < 0x11) 812 return 0; 813 814 ret = analogix_dp_read_byte_from_dpcd(dp, DP_SET_POWER, &value); 815 if (ret < 0) 816 return ret; 817 818 value &= ~DP_SET_POWER_MASK; 819 value |= DP_SET_POWER_D0; 820 821 ret = analogix_dp_write_byte_to_dpcd(dp, DP_SET_POWER, value); 822 if (ret < 0) 823 return ret; 824 825 mdelay(1); 826 827 return 0; 828 } 829 830 static int analogix_dp_link_power_down(struct analogix_dp_device *dp) 831 { 832 u8 value; 833 int ret; 834 835 if (dp->dpcd[DP_DPCD_REV] < 0x11) 836 return 0; 837 838 ret = analogix_dp_read_byte_from_dpcd(dp, DP_SET_POWER, &value); 839 if (ret < 0) 840 return ret; 841 842 value &= ~DP_SET_POWER_MASK; 843 value |= DP_SET_POWER_D3; 844 845 ret = analogix_dp_write_byte_to_dpcd(dp, DP_SET_POWER, value); 846 if (ret < 0) 847 return ret; 848 849 return 0; 850 } 851 852 static int analogix_dp_connector_enable(struct display_state *state) 853 { 854 struct connector_state *conn_state = &state->conn_state; 855 struct crtc_state *crtc_state = &state->crtc_state; 856 const struct rockchip_connector *connector = conn_state->connector; 857 const struct rockchip_dp_chip_data *pdata = connector->data; 858 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 859 struct video_info *video = &dp->video_info; 860 u32 val; 861 int ret; 862 863 if (pdata->lcdsel_grf_reg) { 864 if (crtc_state->crtc_id) 865 val = pdata->lcdsel_lit; 866 else 867 val = pdata->lcdsel_big; 868 869 regmap_write(dp->grf, pdata->lcdsel_grf_reg, val); 870 } 871 872 if (pdata->chip_type == RK3588_EDP) 873 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 874 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 1)); 875 876 switch (conn_state->bpc) { 877 case 12: 878 video->color_depth = COLOR_12; 879 break; 880 case 10: 881 video->color_depth = COLOR_10; 882 break; 883 case 6: 884 video->color_depth = COLOR_6; 885 break; 886 case 8: 887 default: 888 video->color_depth = COLOR_8; 889 break; 890 } 891 892 ret = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 893 DP_RECEIVER_CAP_SIZE, dp->dpcd); 894 if (ret) { 895 dev_err(dp->dev, "failed to read dpcd caps: %d\n", ret); 896 return ret; 897 } 898 899 ret = analogix_dp_link_power_up(dp); 900 if (ret) { 901 dev_err(dp->dev, "failed to power up link: %d\n", ret); 902 return ret; 903 } 904 905 ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count, 906 dp->video_info.max_link_rate); 907 if (ret) { 908 dev_err(dp->dev, "unable to do link train\n"); 909 return ret; 910 } 911 912 analogix_dp_enable_scramble(dp, 1); 913 analogix_dp_enable_rx_to_enhanced_mode(dp, 1); 914 analogix_dp_enable_enhanced_mode(dp, 1); 915 916 analogix_dp_init_video(dp); 917 ret = analogix_dp_config_video(dp); 918 if (ret) { 919 dev_err(dp->dev, "unable to config video\n"); 920 return ret; 921 } 922 923 return 0; 924 } 925 926 static int analogix_dp_connector_disable(struct display_state *state) 927 { 928 struct connector_state *conn_state = &state->conn_state; 929 const struct rockchip_connector *connector = conn_state->connector; 930 const struct rockchip_dp_chip_data *pdata = connector->data; 931 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 932 933 if (!analogix_dp_get_plug_in_status(dp)) 934 analogix_dp_link_power_down(dp); 935 936 if (pdata->chip_type == RK3588_EDP) 937 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 938 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 0)); 939 940 return 0; 941 } 942 943 static int analogix_dp_connector_detect(struct display_state *state) 944 { 945 struct connector_state *conn_state = &state->conn_state; 946 struct analogix_dp_device *dp = dev_get_priv(conn_state->dev); 947 948 return analogix_dp_detect(dp); 949 } 950 951 static const struct rockchip_connector_funcs analogix_dp_connector_funcs = { 952 .pre_init = analogix_dp_connector_pre_init, 953 .init = analogix_dp_connector_init, 954 .get_edid = analogix_dp_connector_get_edid, 955 .enable = analogix_dp_connector_enable, 956 .disable = analogix_dp_connector_disable, 957 .detect = analogix_dp_connector_detect, 958 }; 959 960 static int analogix_dp_probe(struct udevice *dev) 961 { 962 struct analogix_dp_device *dp = dev_get_priv(dev); 963 const struct rockchip_connector *connector = 964 (const struct rockchip_connector *)dev_get_driver_data(dev); 965 const struct rockchip_dp_chip_data *pdata = connector->data; 966 struct udevice *syscon; 967 int ret; 968 969 dp->reg_base = dev_read_addr_ptr(dev); 970 971 dp->id = of_alias_get_id(ofnode_to_np(dev->node), "edp"); 972 if (dp->id < 0) 973 dp->id = 0; 974 975 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 976 &syscon); 977 if (!ret) { 978 dp->grf = syscon_get_regmap(syscon); 979 if (!dp->grf) 980 return -ENODEV; 981 } 982 983 ret = reset_get_bulk(dev, &dp->resets); 984 if (ret) { 985 dev_err(dev, "failed to get reset control: %d\n", ret); 986 return ret; 987 } 988 989 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 990 GPIOD_IS_IN); 991 if (ret && ret != -ENOENT) { 992 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 993 return ret; 994 } 995 996 generic_phy_get_by_name(dev, "dp", &dp->phy); 997 998 dp->force_hpd = dev_read_bool(dev, "force-hpd"); 999 1000 dp->plat_data.dev_type = ROCKCHIP_DP; 1001 dp->plat_data.subdev_type = pdata->chip_type; 1002 dp->plat_data.ssc = pdata->ssc; 1003 1004 dp->video_info.max_link_rate = pdata->max_link_rate; 1005 dp->video_info.max_lane_count = pdata->max_lane_count; 1006 1007 dp->dev = dev; 1008 1009 return 0; 1010 } 1011 1012 static const struct rockchip_dp_chip_data rk3288_edp_platform_data = { 1013 .lcdsel_grf_reg = 0x025c, 1014 .lcdsel_big = 0 | BIT(21), 1015 .lcdsel_lit = BIT(5) | BIT(21), 1016 .chip_type = RK3288_DP, 1017 1018 .max_link_rate = DP_LINK_BW_2_7, 1019 .max_lane_count = 4, 1020 }; 1021 1022 static const struct rockchip_connector rk3288_edp_driver_data = { 1023 .funcs = &analogix_dp_connector_funcs, 1024 .data = &rk3288_edp_platform_data, 1025 }; 1026 1027 static const struct rockchip_dp_chip_data rk3368_edp_platform_data = { 1028 .chip_type = RK3368_EDP, 1029 1030 .max_link_rate = DP_LINK_BW_2_7, 1031 .max_lane_count = 4, 1032 }; 1033 1034 static const struct rockchip_connector rk3368_edp_driver_data = { 1035 .funcs = &analogix_dp_connector_funcs, 1036 .data = &rk3368_edp_platform_data, 1037 }; 1038 1039 static const struct rockchip_dp_chip_data rk3399_edp_platform_data = { 1040 .lcdsel_grf_reg = 0x6250, 1041 .lcdsel_big = 0 | BIT(21), 1042 .lcdsel_lit = BIT(5) | BIT(21), 1043 .chip_type = RK3399_EDP, 1044 1045 .max_link_rate = DP_LINK_BW_2_7, 1046 .max_lane_count = 4, 1047 }; 1048 1049 static const struct rockchip_connector rk3399_edp_driver_data = { 1050 .funcs = &analogix_dp_connector_funcs, 1051 .data = &rk3399_edp_platform_data, 1052 }; 1053 1054 static const struct rockchip_dp_chip_data rk3568_edp_platform_data = { 1055 .chip_type = RK3568_EDP, 1056 .ssc = true, 1057 1058 .max_link_rate = DP_LINK_BW_2_7, 1059 .max_lane_count = 4, 1060 }; 1061 1062 static const struct rockchip_connector rk3568_edp_driver_data = { 1063 .funcs = &analogix_dp_connector_funcs, 1064 .data = &rk3568_edp_platform_data, 1065 }; 1066 1067 static const struct rockchip_dp_chip_data rk3588_edp_platform_data = { 1068 .chip_type = RK3588_EDP, 1069 .ssc = true, 1070 1071 .max_link_rate = DP_LINK_BW_5_4, 1072 .max_lane_count = 4, 1073 }; 1074 1075 static const struct rockchip_connector rk3588_edp_driver_data = { 1076 .funcs = &analogix_dp_connector_funcs, 1077 .data = &rk3588_edp_platform_data, 1078 }; 1079 1080 static const struct udevice_id analogix_dp_ids[] = { 1081 { 1082 .compatible = "rockchip,rk3288-dp", 1083 .data = (ulong)&rk3288_edp_driver_data, 1084 }, { 1085 .compatible = "rockchip,rk3368-edp", 1086 .data = (ulong)&rk3368_edp_driver_data, 1087 }, { 1088 .compatible = "rockchip,rk3399-edp", 1089 .data = (ulong)&rk3399_edp_driver_data, 1090 }, { 1091 .compatible = "rockchip,rk3568-edp", 1092 .data = (ulong)&rk3568_edp_driver_data, 1093 }, { 1094 .compatible = "rockchip,rk3588-edp", 1095 .data = (ulong)&rk3588_edp_driver_data, 1096 }, 1097 {} 1098 }; 1099 1100 U_BOOT_DRIVER(analogix_dp) = { 1101 .name = "analogix_dp", 1102 .id = UCLASS_DISPLAY, 1103 .of_match = analogix_dp_ids, 1104 .probe = analogix_dp_probe, 1105 .priv_auto_alloc_size = sizeof(struct analogix_dp_device), 1106 }; 1107