1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <dm/device.h> 14 #include <dm/of_access.h> 15 #include <dm/read.h> 16 #include <linux/bitfield.h> 17 #include <linux/list.h> 18 #include <linux/media-bus-format.h> 19 #include <syscon.h> 20 #include <asm/arch-rockchip/clock.h> 21 #include <asm/gpio.h> 22 23 #include "rockchip_display.h" 24 #include "rockchip_crtc.h" 25 #include "rockchip_connector.h" 26 #include "analogix_dp.h" 27 28 #define RK3588_GRF_VO1_CON0 0x0000 29 #define EDP_MODE BIT(0) 30 #define RK3588_GRF_VO1_CON1 0x0004 31 32 /** 33 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips 34 * @lcdsel_grf_reg: grf register offset of lcdc select 35 * @lcdsel_big: reg value of selecting vop big for eDP 36 * @lcdsel_lit: reg value of selecting vop little for eDP 37 * @chip_type: specific chip type 38 * @ssc: check if SSC is supported by source 39 * @max_link_rate: max supported link rate 40 * @max_lane_count: max supported lane count 41 * @format_yuv: check if yuv color format is supported 42 * @support_dp_mode: check if dp mode is supported 43 * @max_bpc: max supported bpc which set to 8 by default 44 */ 45 struct rockchip_dp_chip_data { 46 u32 lcdsel_grf_reg; 47 u32 lcdsel_big; 48 u32 lcdsel_lit; 49 u32 chip_type; 50 bool ssc; 51 52 u32 max_link_rate; 53 u32 max_lane_count; 54 bool format_yuv; 55 bool support_dp_mode; 56 u8 max_bpc; 57 }; 58 59 static const struct analogix_dp_output_format possible_output_fmts[] = { 60 { MEDIA_BUS_FMT_RGB101010_1X30, DRM_COLOR_FORMAT_RGB444, 10 }, 61 { MEDIA_BUS_FMT_RGB888_1X24, DRM_COLOR_FORMAT_RGB444, 8 }, 62 { MEDIA_BUS_FMT_RGB666_1X24_CPADHI, DRM_COLOR_FORMAT_RGB444, 6 }, 63 { MEDIA_BUS_FMT_YUV10_1X30, DRM_COLOR_FORMAT_YCRCB444, 10 }, 64 { MEDIA_BUS_FMT_YUV8_1X24, DRM_COLOR_FORMAT_YCRCB444, 8}, 65 { MEDIA_BUS_FMT_YUYV10_1X20, DRM_COLOR_FORMAT_YCRCB422, 10 }, 66 { MEDIA_BUS_FMT_YUYV8_1X16, DRM_COLOR_FORMAT_YCRCB422, 8 }, 67 }; 68 69 static u8 analogix_dp_get_output_bpp(const struct analogix_dp_output_format *fmt) 70 { 71 switch (fmt->color_format) { 72 case DRM_COLOR_FORMAT_YCRCB422: 73 return fmt->bpc * 2; 74 case DRM_COLOR_FORMAT_RGB444: 75 case DRM_COLOR_FORMAT_YCRCB444: 76 default: 77 return fmt->bpc * 3; 78 } 79 } 80 81 static int 82 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, 83 bool enable) 84 { 85 u8 data; 86 int ret; 87 88 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data); 89 if (ret != 1) 90 return ret; 91 92 if (enable) 93 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, 94 DP_LANE_COUNT_ENHANCED_FRAME_EN | 95 DPCD_LANE_COUNT_SET(data)); 96 else 97 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, 98 DPCD_LANE_COUNT_SET(data)); 99 100 return ret < 0 ? ret : 0; 101 } 102 103 static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) 104 { 105 bool enhanced_frame_en; 106 u8 data; 107 int ret; 108 109 enhanced_frame_en = drm_dp_enhanced_frame_cap(dp->dpcd); 110 111 ret = analogix_dp_enable_rx_to_enhanced_mode(dp, enhanced_frame_en); 112 if (ret < 0) 113 return ret; 114 115 if (!enhanced_frame_en) { 116 /* 117 * As the Table 3-4 in eDP v1.2 spec: 118 * DPCD 0000Dh: 119 * Bit 1 = FRAMING_CHANGE_CAPABLE 120 * A setting of 1 indicates that this is an eDP device that 121 * uses only Enhanced Framing, independently of the setting by 122 * the source of ENHANCED_FRAME_EN 123 * 124 * And as the Table 3-3 in eDP v1.4 spec: 125 * DPCD 0000Dh: 126 * Bit 1 = RESERVED for eDP 127 * New to eDP v1.4.(Read all 0s) 128 */ 129 ret = drm_dp_dpcd_readb(&dp->aux, DP_EDP_CONFIGURATION_CAP, 130 &data); 131 if (ret < 0) 132 return ret; 133 134 enhanced_frame_en = !!(data & DP_FRAMING_CHANGE_CAP); 135 } 136 137 analogix_dp_enable_enhanced_mode(dp, enhanced_frame_en); 138 139 return 0; 140 } 141 142 static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) 143 { 144 int ret; 145 146 analogix_dp_set_training_pattern(dp, DP_NONE); 147 148 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 149 DP_TRAINING_PATTERN_DISABLE); 150 151 return ret < 0 ? ret : 0; 152 } 153 154 static int analogix_dp_enable_sink_to_assr_mode(struct analogix_dp_device *dp, bool enable) 155 { 156 u8 data; 157 int ret; 158 159 ret = drm_dp_dpcd_readb(&dp->aux, DP_EDP_CONFIGURATION_SET, &data); 160 if (ret != 1) 161 return ret; 162 163 if (enable) 164 ret = drm_dp_dpcd_writeb(&dp->aux, DP_EDP_CONFIGURATION_SET, 165 data | DP_ALTERNATE_SCRAMBLER_RESET_ENABLE); 166 else 167 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, 168 data & ~DP_ALTERNATE_SCRAMBLER_RESET_ENABLE); 169 170 return ret < 0 ? ret : 0; 171 } 172 173 static int analogix_dp_set_assr_mode(struct analogix_dp_device *dp) 174 { 175 bool assr_en; 176 int ret; 177 178 assr_en = drm_dp_alternate_scrambler_reset_cap(dp->dpcd); 179 180 ret = analogix_dp_enable_sink_to_assr_mode(dp, assr_en); 181 if (ret < 0) 182 return ret; 183 184 analogix_dp_enable_assr_mode(dp, assr_en); 185 186 return 0; 187 } 188 189 static int analogix_dp_link_start(struct analogix_dp_device *dp) 190 { 191 u8 buf[4]; 192 int lane, lane_count, retval; 193 194 lane_count = dp->link_train.lane_count; 195 196 dp->link_train.lt_state = CLOCK_RECOVERY; 197 dp->link_train.eq_loop = 0; 198 199 for (lane = 0; lane < lane_count; lane++) 200 dp->link_train.cr_loop[lane] = 0; 201 202 /* Set link rate and count as you want to establish */ 203 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 204 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 205 206 if (dp->nr_link_rate_table) { 207 /* Setup DP_LINK_RATE_SET for eDP 1.4 and later */ 208 drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, dp->link_train.lane_count); 209 drm_dp_dpcd_writeb(&dp->aux, DP_LINK_RATE_SET, dp->link_rate_select); 210 } else { 211 /* Setup DP_LINK_BW_SET for eDP 1.3 and earlier */ 212 buf[0] = dp->link_train.link_rate; 213 buf[1] = dp->link_train.lane_count; 214 retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2); 215 if (retval < 0) 216 return retval; 217 } 218 219 /* Spread AMP if required, enable 8b/10b coding */ 220 buf[0] = analogix_dp_ssc_supported(dp) ? DP_SPREAD_AMP_0_5 : 0; 221 buf[1] = DP_SET_ANSI_8B10B; 222 retval = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, 2); 223 if (retval < 0) 224 return retval; 225 226 /* set ASSR if available */ 227 retval = analogix_dp_set_assr_mode(dp); 228 if (retval < 0) { 229 dev_err(dp->dev, "failed to set assr mode\n"); 230 return retval; 231 } 232 233 /* set enhanced mode if available */ 234 retval = analogix_dp_set_enhanced_mode(dp); 235 if (retval < 0) { 236 dev_err(dp->dev, "failed to set enhance mode\n"); 237 return retval; 238 } 239 240 /* Set TX voltage-swing and pre-emphasis to minimum */ 241 for (lane = 0; lane < lane_count; lane++) 242 dp->link_train.training_lane[lane] = 243 DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | 244 DP_TRAIN_PRE_EMPH_LEVEL_0; 245 analogix_dp_set_lane_link_training(dp); 246 247 /* Set training pattern 1 */ 248 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 249 250 /* Set RX training pattern */ 251 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 252 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); 253 if (retval < 0) 254 return retval; 255 256 for (lane = 0; lane < lane_count; lane++) 257 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 258 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 259 260 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, 261 lane_count); 262 if (retval < 0) 263 return retval; 264 265 return 0; 266 } 267 268 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) 269 { 270 int shift = (lane & 1) * 4; 271 u8 link_value = link_status[lane >> 1]; 272 273 return (link_value >> shift) & 0xf; 274 } 275 276 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) 277 { 278 int lane; 279 u8 lane_status; 280 281 for (lane = 0; lane < lane_count; lane++) { 282 lane_status = analogix_dp_get_lane_status(link_status, lane); 283 if ((lane_status & DP_LANE_CR_DONE) == 0) 284 return -EINVAL; 285 } 286 return 0; 287 } 288 289 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, 290 int lane_count) 291 { 292 int lane; 293 u8 lane_status; 294 295 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) 296 return -EINVAL; 297 298 for (lane = 0; lane < lane_count; lane++) { 299 lane_status = analogix_dp_get_lane_status(link_status, lane); 300 lane_status &= DP_CHANNEL_EQ_BITS; 301 if (lane_status != DP_CHANNEL_EQ_BITS) 302 return -EINVAL; 303 } 304 305 return 0; 306 } 307 308 static unsigned char 309 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) 310 { 311 int shift = (lane & 1) * 4; 312 u8 link_value = adjust_request[lane >> 1]; 313 314 return (link_value >> shift) & 0x3; 315 } 316 317 static unsigned char analogix_dp_get_adjust_request_pre_emphasis( 318 u8 adjust_request[2], 319 int lane) 320 { 321 int shift = (lane & 1) * 4; 322 u8 link_value = adjust_request[lane >> 1]; 323 324 return ((link_value >> shift) & 0xc) >> 2; 325 } 326 327 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) 328 { 329 analogix_dp_training_pattern_dis(dp); 330 analogix_dp_set_enhanced_mode(dp); 331 332 dp->link_train.lt_state = FAILED; 333 } 334 335 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, 336 u8 adjust_request[2]) 337 { 338 int lane, lane_count; 339 u8 voltage_swing, pre_emphasis, training_lane; 340 341 lane_count = dp->link_train.lane_count; 342 for (lane = 0; lane < lane_count; lane++) { 343 voltage_swing = analogix_dp_get_adjust_request_voltage( 344 adjust_request, lane); 345 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 346 adjust_request, lane); 347 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | 348 DPCD_PRE_EMPHASIS_SET(pre_emphasis); 349 350 if (voltage_swing == VOLTAGE_LEVEL_3) 351 training_lane |= DP_TRAIN_MAX_SWING_REACHED; 352 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) 353 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 354 355 dp->link_train.training_lane[lane] = training_lane; 356 } 357 } 358 359 static bool analogix_dp_tps3_supported(struct analogix_dp_device *dp) 360 { 361 bool source_tps3_supported, sink_tps3_supported; 362 u8 dpcd = 0; 363 364 source_tps3_supported = 365 dp->video_info.max_link_rate == DP_LINK_BW_5_4; 366 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &dpcd); 367 sink_tps3_supported = dpcd & DP_TPS3_SUPPORTED; 368 369 return source_tps3_supported && sink_tps3_supported; 370 } 371 372 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) 373 { 374 int lane, lane_count, retval; 375 u8 voltage_swing, pre_emphasis, training_lane; 376 u8 link_status[2], adjust_request[2]; 377 u8 training_pattern = TRAINING_PTN2; 378 379 drm_dp_link_train_clock_recovery_delay(dp->dpcd); 380 381 lane_count = dp->link_train.lane_count; 382 383 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2); 384 if (retval < 0) 385 return retval; 386 387 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { 388 if (analogix_dp_tps3_supported(dp)) 389 training_pattern = TRAINING_PTN3; 390 391 /* set training pattern for EQ */ 392 analogix_dp_set_training_pattern(dp, training_pattern); 393 394 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 395 DP_LINK_SCRAMBLING_DISABLE | 396 (training_pattern == TRAINING_PTN3 ? 397 DP_TRAINING_PATTERN_3 : DP_TRAINING_PATTERN_2)); 398 if (retval < 0) 399 return retval; 400 401 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 402 dp->link_train.lt_state = EQUALIZER_TRAINING; 403 404 return 0; 405 } else { 406 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, 407 adjust_request, 2); 408 if (retval < 0) 409 return retval; 410 411 for (lane = 0; lane < lane_count; lane++) { 412 training_lane = analogix_dp_get_lane_link_training( 413 dp, lane); 414 voltage_swing = analogix_dp_get_adjust_request_voltage( 415 adjust_request, lane); 416 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 417 adjust_request, lane); 418 419 if (DPCD_VOLTAGE_SWING_GET(training_lane) == 420 voltage_swing && 421 DPCD_PRE_EMPHASIS_GET(training_lane) == 422 pre_emphasis) 423 dp->link_train.cr_loop[lane]++; 424 425 /* 426 * In DP spec 1.3, Condition of CR fail are 427 * outlined in section 3.5.1.2.2.1, figure 3-20: 428 * 429 * 1. Maximum Voltage Swing reached 430 * 2. Same Voltage five times 431 */ 432 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || 433 DPCD_VOLTAGE_SWING_GET(training_lane) == VOLTAGE_LEVEL_3) { 434 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", 435 dp->link_train.cr_loop[lane], 436 voltage_swing, pre_emphasis); 437 analogix_dp_reduce_link_rate(dp); 438 return -EIO; 439 } 440 } 441 } 442 443 analogix_dp_get_adjust_training_lane(dp, adjust_request); 444 analogix_dp_set_lane_link_training(dp); 445 446 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, 447 dp->link_train.training_lane, lane_count); 448 if (retval < 0) 449 return retval; 450 451 return 0; 452 } 453 454 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) 455 { 456 int lane_count, retval; 457 u32 reg; 458 u8 link_align, link_status[2], adjust_request[2]; 459 460 drm_dp_link_train_channel_eq_delay(dp->dpcd); 461 462 lane_count = dp->link_train.lane_count; 463 464 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2); 465 if (retval < 0) 466 return retval; 467 468 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { 469 analogix_dp_reduce_link_rate(dp); 470 return -EIO; 471 } 472 473 retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED, &link_align); 474 if (retval < 0) 475 return retval; 476 477 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { 478 /* traing pattern Set to Normal */ 479 retval = analogix_dp_training_pattern_dis(dp); 480 if (retval < 0) 481 return retval; 482 483 printf("Link Training success!\n"); 484 485 analogix_dp_get_link_bandwidth(dp, ®); 486 dp->link_train.link_rate = reg; 487 analogix_dp_get_lane_count(dp, ®); 488 dp->link_train.lane_count = reg; 489 490 printf("final link rate = 0x%.2x, lane count = 0x%.2x\n", 491 dp->link_train.link_rate, dp->link_train.lane_count); 492 493 dp->link_train.lt_state = FINISHED; 494 495 return 0; 496 } 497 498 /* not all locked */ 499 dp->link_train.eq_loop++; 500 501 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 502 dev_dbg(dp->dev, "EQ Max loop\n"); 503 analogix_dp_reduce_link_rate(dp); 504 return -EIO; 505 } 506 507 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1, adjust_request, 2); 508 if (retval < 0) 509 return retval; 510 511 analogix_dp_get_adjust_training_lane(dp, adjust_request); 512 analogix_dp_set_lane_link_training(dp); 513 514 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, 515 dp->link_train.training_lane, lane_count); 516 if (retval < 0) 517 return retval; 518 519 return 0; 520 } 521 522 static bool analogix_dp_bandwidth_ok(struct analogix_dp_device *dp, 523 const struct drm_display_mode *mode, u32 bpp, 524 unsigned int rate, unsigned int lanes) 525 { 526 u32 max_bw, req_bw; 527 528 req_bw = mode->clock * bpp / 8; 529 max_bw = lanes * rate; 530 if (req_bw > max_bw) 531 return false; 532 533 return true; 534 } 535 536 static bool analogix_dp_link_config_validate(u8 link_rate, u8 lane_count) 537 { 538 switch (link_rate) { 539 case DP_LINK_BW_1_62: 540 case DP_LINK_BW_2_7: 541 case DP_LINK_BW_5_4: 542 /* Supported link rate in eDP 1.4 */ 543 case EDP_LINK_BW_2_16: 544 case EDP_LINK_BW_2_43: 545 case EDP_LINK_BW_3_24: 546 case EDP_LINK_BW_4_32: 547 break; 548 default: 549 return false; 550 } 551 552 switch (lane_count) { 553 case LANE_COUNT1: 554 case LANE_COUNT2: 555 case LANE_COUNT4: 556 break; 557 default: 558 return false; 559 } 560 561 return true; 562 } 563 564 static int analogix_dp_select_link_rate_from_table(struct analogix_dp_device *dp) 565 { 566 int i; 567 u8 bw_code; 568 u32 max_link_rate = drm_dp_bw_code_to_link_rate(dp->video_info.max_link_rate); 569 570 for (i = 0; i < dp->nr_link_rate_table; i++) { 571 bw_code = drm_dp_link_rate_to_bw_code(dp->link_rate_table[i]); 572 573 if (!analogix_dp_bandwidth_ok(dp, &dp->video_info.mode, 574 analogix_dp_get_output_bpp(dp->output_fmt), 575 dp->link_rate_table[i], dp->link_train.lane_count)) 576 continue; 577 578 if (dp->link_rate_table[i] <= max_link_rate && 579 analogix_dp_link_config_validate(bw_code, dp->link_train.lane_count)) { 580 dp->link_rate_select = i; 581 return bw_code; 582 } 583 } 584 585 return 0; 586 } 587 588 static int analogix_dp_select_rx_bandwidth(struct analogix_dp_device *dp) 589 { 590 if (dp->nr_link_rate_table) 591 /* 592 * Select the smallest one among link rates which meet 593 * the bandwidth requirement for eDP 1.4 and later. 594 */ 595 dp->link_train.link_rate = analogix_dp_select_link_rate_from_table(dp); 596 else 597 /* 598 * Select the smaller one between rx DP_MAX_LINK_RATE 599 * and the max link rate supported by the platform. 600 */ 601 dp->link_train.link_rate = min_t(u32, dp->link_train.link_rate, 602 dp->video_info.max_link_rate); 603 if (!dp->link_train.link_rate) 604 return -EINVAL; 605 606 return 0; 607 } 608 609 static int analogix_dp_init_link_rate_table(struct analogix_dp_device *dp) 610 { 611 u8 link_rate_table[DP_MAX_SUPPORTED_RATES * 2]; 612 int i; 613 int ret; 614 615 ret = drm_dp_dpcd_read(&dp->aux, DP_SUPPORTED_LINK_RATES, link_rate_table, 616 sizeof(link_rate_table)); 617 if (ret < 0) 618 return ret; 619 620 for (i = 0; i < ARRAY_SIZE(link_rate_table) / 2; i++) { 621 int val = link_rate_table[2 * i] | link_rate_table[2 * i + 1] << 8; 622 623 if (val == 0) 624 break; 625 626 /* Convert to the link_rate as drm_dp_bw_code_to_link_rate() */ 627 dp->link_rate_table[i] = (val * 20); 628 } 629 dp->nr_link_rate_table = i; 630 631 return 0; 632 } 633 634 static int analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, 635 u8 *bandwidth) 636 { 637 u8 data; 638 int ret; 639 640 ret = drm_dp_dpcd_readb(&dp->aux, DP_EDP_DPCD_REV, &data); 641 if (ret == 1 && data >= DP_EDP_14) { 642 u32 max_link_rate; 643 644 /* As the Table 4-23 in eDP 1.4 spec, the link rate table is required */ 645 if (!dp->nr_link_rate_table) { 646 dev_info(dp->dev, "eDP version: 0x%02x supports link rate table\n", 647 data); 648 649 if (analogix_dp_init_link_rate_table(dp)) 650 dev_err(dp->dev, "failed to read link rate table: %d\n", 651 ret); 652 } 653 max_link_rate = dp->link_rate_table[dp->nr_link_rate_table - 1]; 654 *bandwidth = drm_dp_link_rate_to_bw_code(max_link_rate); 655 } else { 656 /* 657 * For DP rev.1.1, Maximum link rate of Main Link lanes 658 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps 659 * For DP rev.1.2, Maximum link rate of Main Link lanes 660 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 661 */ 662 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data); 663 if (ret < 0) 664 return ret; 665 666 *bandwidth = data; 667 } 668 669 return 0; 670 } 671 672 static int analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, 673 u8 *lane_count) 674 { 675 u8 data; 676 int ret; 677 678 /* 679 * For DP rev.1.1, Maximum number of Main Link lanes 680 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 681 */ 682 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data); 683 if (ret < 0) 684 return ret; 685 686 *lane_count = DPCD_MAX_LANE_COUNT(data); 687 688 return 0; 689 } 690 691 static int analogix_dp_init_training(struct analogix_dp_device *dp, 692 enum link_lane_count_type max_lane, 693 int max_rate) 694 { 695 u8 dpcd; 696 697 /* 698 * MACRO_RST must be applied after the PLL_LOCK to avoid 699 * the DP inter pair skew issue for at least 10 us 700 */ 701 analogix_dp_reset_macro(dp); 702 703 /* Setup TX lane count */ 704 dp->link_train.lane_count = min_t(u32, dp->link_train.lane_count, max_lane); 705 706 /* Setup TX lane rate */ 707 if (analogix_dp_select_rx_bandwidth(dp)) { 708 dev_err(dp->dev, "Select rx bandwidth failed\n"); 709 return -EINVAL; 710 } 711 712 drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &dpcd); 713 dp->link_train.ssc = !!(dpcd & DP_MAX_DOWNSPREAD_0_5); 714 715 /* All DP analog module power up */ 716 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 717 718 return 0; 719 } 720 721 static int analogix_dp_sw_link_training(struct analogix_dp_device *dp) 722 { 723 int retval = 0, training_finished = 0; 724 725 dp->link_train.lt_state = START; 726 727 /* Process here */ 728 while (!retval && !training_finished) { 729 switch (dp->link_train.lt_state) { 730 case START: 731 retval = analogix_dp_link_start(dp); 732 if (retval) 733 dev_err(dp->dev, "LT link start failed!\n"); 734 break; 735 case CLOCK_RECOVERY: 736 retval = analogix_dp_process_clock_recovery(dp); 737 if (retval) 738 dev_err(dp->dev, "LT CR failed!\n"); 739 break; 740 case EQUALIZER_TRAINING: 741 retval = analogix_dp_process_equalizer_training(dp); 742 if (retval) 743 dev_err(dp->dev, "LT EQ failed!\n"); 744 break; 745 case FINISHED: 746 training_finished = 1; 747 break; 748 case FAILED: 749 return -EREMOTEIO; 750 } 751 } 752 753 return retval; 754 } 755 756 static int analogix_dp_set_link_train(struct analogix_dp_device *dp, 757 u32 count, u32 bwtype) 758 { 759 int i, ret; 760 761 for (i = 0; i < 5; i++) { 762 ret = analogix_dp_init_training(dp, count, bwtype); 763 if (ret < 0) { 764 dev_err(dp->dev, "failed to init training\n"); 765 return ret; 766 } 767 768 ret = analogix_dp_sw_link_training(dp); 769 if (!ret) 770 break; 771 } 772 773 return ret; 774 } 775 776 static int analogix_dp_config_video(struct analogix_dp_device *dp) 777 { 778 int timeout_loop = 0; 779 int done_count = 0; 780 781 analogix_dp_config_video_slave_mode(dp); 782 783 analogix_dp_set_video_color_format(dp); 784 785 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 786 dev_err(dp->dev, "PLL is not locked yet.\n"); 787 return -EINVAL; 788 } 789 790 for (;;) { 791 timeout_loop++; 792 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) 793 break; 794 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 795 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 796 return -ETIMEDOUT; 797 } 798 799 udelay(2); 800 } 801 802 /* Set to use the register calculated M/N video */ 803 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); 804 805 /* For video bist, Video timing must be generated by register */ 806 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_REGISTER); 807 808 /* Disable video mute */ 809 analogix_dp_enable_video_mute(dp, 0); 810 811 /* Configure video slave mode */ 812 analogix_dp_enable_video_master(dp, 0); 813 814 /* Enable video input */ 815 analogix_dp_start_video(dp); 816 817 timeout_loop = 0; 818 819 for (;;) { 820 timeout_loop++; 821 if (analogix_dp_is_video_stream_on(dp) == 0) { 822 done_count++; 823 if (done_count > 10) 824 break; 825 } else if (done_count) { 826 done_count = 0; 827 } 828 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 829 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 830 return -ETIMEDOUT; 831 } 832 833 udelay(1001); 834 } 835 836 return 0; 837 } 838 839 static int analogix_dp_enable_scramble(struct analogix_dp_device *dp, 840 bool enable) 841 { 842 u8 data; 843 int ret; 844 845 if (enable) { 846 analogix_dp_enable_scrambling(dp); 847 848 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, 849 &data); 850 if (ret != 1) 851 return ret; 852 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 853 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); 854 } else { 855 analogix_dp_disable_scrambling(dp); 856 857 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, 858 &data); 859 if (ret != 1) 860 return ret; 861 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, 862 (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); 863 } 864 return ret < 0 ? ret : 0; 865 } 866 867 static void analogix_dp_init_dp(struct analogix_dp_device *dp) 868 { 869 analogix_dp_reset(dp); 870 871 analogix_dp_swreset(dp); 872 873 analogix_dp_init_analog_param(dp); 874 analogix_dp_init_interrupt(dp); 875 876 /* SW defined function Normal operation */ 877 analogix_dp_enable_sw_function(dp); 878 879 analogix_dp_config_interrupt(dp); 880 analogix_dp_init_analog_func(dp); 881 882 analogix_dp_init_hpd(dp); 883 analogix_dp_init_aux(dp); 884 } 885 886 static int analogix_dp_connector_init(struct rockchip_connector *conn, struct display_state *state) 887 { 888 struct connector_state *conn_state = &state->conn_state; 889 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 890 int submode = PHY_SUBMODE_EDP; 891 892 if (!conn->panel) 893 dp->dp_mode = true; 894 895 if (dev_read_bool(conn->dev, "dp-mode")) 896 dp->dp_mode = true; 897 898 conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_eDP1 : VOP_OUTPUT_IF_eDP0; 899 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 900 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709; 901 conn_state->color_range = DRM_COLOR_YCBCR_FULL_RANGE; 902 903 reset_assert_bulk(&dp->resets); 904 udelay(1); 905 reset_deassert_bulk(&dp->resets); 906 907 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dp->id); 908 if (dp->plat_data.support_dp_mode && dp->dp_mode) 909 submode = PHY_SUBMODE_DP; 910 generic_phy_set_mode_ext(&dp->phy, PHY_MODE_DP, submode); 911 generic_phy_power_on(&dp->phy); 912 analogix_dp_init_dp(dp); 913 914 return 0; 915 } 916 917 static int analogix_dp_connector_get_edid(struct rockchip_connector *conn, 918 struct display_state *state) 919 { 920 struct connector_state *conn_state = &state->conn_state; 921 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 922 int ret; 923 924 ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); 925 926 return ret; 927 } 928 929 static int analogix_dp_link_power_up(struct analogix_dp_device *dp) 930 { 931 u8 value; 932 int ret; 933 934 if (dp->dpcd[DP_DPCD_REV] < 0x11) 935 return 0; 936 937 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value); 938 if (ret < 0) 939 return ret; 940 941 value &= ~DP_SET_POWER_MASK; 942 value |= DP_SET_POWER_D0; 943 944 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value); 945 if (ret < 0) 946 return ret; 947 948 mdelay(1); 949 950 return 0; 951 } 952 953 static int analogix_dp_link_power_down(struct analogix_dp_device *dp) 954 { 955 u8 value; 956 int ret; 957 958 if (dp->dpcd[DP_DPCD_REV] < 0x11) 959 return 0; 960 961 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value); 962 if (ret < 0) 963 return ret; 964 965 value &= ~DP_SET_POWER_MASK; 966 value |= DP_SET_POWER_D3; 967 968 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value); 969 if (ret < 0) 970 return ret; 971 972 return 0; 973 } 974 975 static u32 analogix_dp_get_output_format(struct analogix_dp_device *dp, u32 bus_format) 976 { 977 unsigned int i; 978 979 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 980 const struct analogix_dp_output_format *fmt = &possible_output_fmts[i]; 981 982 if (fmt->bus_format == bus_format) 983 break; 984 } 985 986 if (i == ARRAY_SIZE(possible_output_fmts)) 987 return 1; 988 989 return i; 990 } 991 992 static u32 analogix_dp_get_output_format_by_edid(struct analogix_dp_device *dp, 993 struct hdmi_edid_data *edid_data) 994 { 995 unsigned int i; 996 997 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { 998 const struct analogix_dp_output_format *fmt = &possible_output_fmts[i]; 999 1000 if (fmt->bpc > edid_data->display_info.bpc || fmt->bpc > dp->plat_data.max_bpc) 1001 continue; 1002 1003 if (!(edid_data->display_info.color_formats & fmt->color_format)) 1004 continue; 1005 1006 if (!analogix_dp_bandwidth_ok(dp, edid_data->preferred_mode, 1007 analogix_dp_get_output_bpp(fmt), 1008 drm_dp_bw_code_to_link_rate(dp->link_train.link_rate), 1009 dp->link_train.lane_count)) 1010 continue; 1011 1012 break; 1013 } 1014 1015 if (i == ARRAY_SIZE(possible_output_fmts)) 1016 return 1; 1017 1018 return i; 1019 } 1020 1021 static int analogix_dp_connector_enable(struct rockchip_connector *conn, 1022 struct display_state *state) 1023 { 1024 struct connector_state *conn_state = &state->conn_state; 1025 struct crtc_state *crtc_state = &state->crtc_state; 1026 const struct rockchip_dp_chip_data *pdata = 1027 (const struct rockchip_dp_chip_data *)dev_get_driver_data(conn->dev); 1028 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 1029 struct video_info *video = &dp->video_info; 1030 struct drm_display_mode mode; 1031 u32 fmt_id; 1032 u32 val; 1033 int ret; 1034 1035 drm_mode_copy(&video->mode, &conn_state->mode); 1036 1037 if (pdata->lcdsel_grf_reg) { 1038 if (crtc_state->crtc_id) 1039 val = pdata->lcdsel_lit; 1040 else 1041 val = pdata->lcdsel_big; 1042 1043 regmap_write(dp->grf, pdata->lcdsel_grf_reg, val); 1044 } 1045 1046 if (pdata->chip_type == RK3588_EDP) 1047 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 1048 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 1)); 1049 1050 if (!dp->output_fmt) { 1051 fmt_id = analogix_dp_get_output_format(dp, conn_state->bus_format); 1052 dp->output_fmt = &possible_output_fmts[fmt_id]; 1053 } 1054 1055 switch (dp->output_fmt->bpc) { 1056 case 12: 1057 video->color_depth = COLOR_12; 1058 break; 1059 case 10: 1060 video->color_depth = COLOR_10; 1061 break; 1062 case 6: 1063 video->color_depth = COLOR_6; 1064 break; 1065 case 8: 1066 default: 1067 video->color_depth = COLOR_8; 1068 break; 1069 } 1070 if (dp->output_fmt->color_format == DRM_COLOR_FORMAT_YCRCB444) { 1071 video->color_space = COLOR_YCBCR444; 1072 video->ycbcr_coeff = COLOR_YCBCR709; 1073 } else if (dp->output_fmt->color_format == DRM_COLOR_FORMAT_YCRCB422) { 1074 video->color_space = COLOR_YCBCR422; 1075 video->ycbcr_coeff = COLOR_YCBCR709; 1076 } else { 1077 video->color_space = COLOR_RGB; 1078 video->ycbcr_coeff = COLOR_YCBCR601; 1079 } 1080 1081 ret = drm_dp_dpcd_read(&dp->aux, DP_DPCD_REV, dp->dpcd, DP_RECEIVER_CAP_SIZE); 1082 if (ret < 0) { 1083 dev_err(dp->dev, "failed to read dpcd caps: %d\n", ret); 1084 return ret; 1085 } 1086 1087 ret = analogix_dp_link_power_up(dp); 1088 if (ret) { 1089 dev_err(dp->dev, "failed to power up link: %d\n", ret); 1090 return ret; 1091 } 1092 1093 ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count, 1094 dp->video_info.max_link_rate); 1095 if (ret) { 1096 dev_err(dp->dev, "unable to do link train\n"); 1097 return ret; 1098 } 1099 1100 ret = analogix_dp_enable_scramble(dp, 1); 1101 if (ret < 0) { 1102 dev_err(dp->dev, "can not enable scramble\n"); 1103 return ret; 1104 } 1105 1106 analogix_dp_init_video(dp); 1107 1108 drm_mode_copy(&mode, &conn_state->mode); 1109 if (conn->dual_channel_mode) 1110 drm_mode_convert_to_origin_mode(&mode); 1111 analogix_dp_set_video_format(dp, &mode); 1112 1113 if (dp->video_bist_enable) 1114 analogix_dp_video_bist_enable(dp); 1115 1116 ret = analogix_dp_config_video(dp); 1117 if (ret) { 1118 dev_err(dp->dev, "unable to config video\n"); 1119 return ret; 1120 } 1121 1122 return 0; 1123 } 1124 1125 static int analogix_dp_connector_disable(struct rockchip_connector *conn, 1126 struct display_state *state) 1127 { 1128 const struct rockchip_dp_chip_data *pdata = 1129 (const struct rockchip_dp_chip_data *)dev_get_driver_data(conn->dev); 1130 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 1131 1132 if (!analogix_dp_get_plug_in_status(dp)) 1133 analogix_dp_link_power_down(dp); 1134 1135 if (pdata->chip_type == RK3588_EDP) 1136 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 1137 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 0)); 1138 1139 return 0; 1140 } 1141 1142 static int analogix_dp_connector_detect(struct rockchip_connector *conn, 1143 struct display_state *state) 1144 { 1145 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 1146 int ret; 1147 1148 if (analogix_dp_detect(dp)) { 1149 /* Initialize by reading RX's DPCD */ 1150 ret = analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); 1151 if (ret) { 1152 dev_err(dp->dev, "failed to read max link rate\n"); 1153 return 0; 1154 } 1155 1156 ret = analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); 1157 if (ret) { 1158 dev_err(dp->dev, "failed to read max lane count\n"); 1159 return 0; 1160 } 1161 1162 return 1; 1163 } else { 1164 return 0; 1165 } 1166 } 1167 1168 static int analogix_dp_connector_mode_valid(struct rockchip_connector *conn, 1169 struct display_state *state) 1170 { 1171 struct connector_state *conn_state = &state->conn_state; 1172 struct videomode vm; 1173 1174 drm_display_mode_to_videomode(&conn_state->mode, &vm); 1175 1176 if (!vm.hfront_porch || !vm.hback_porch || !vm.vfront_porch || !vm.vback_porch) { 1177 dev_err(dp->dev, "front porch or back porch can not be 0\n"); 1178 return MODE_BAD; 1179 } 1180 1181 return MODE_OK; 1182 } 1183 1184 static int analogix_dp_mode_valid(struct analogix_dp_device *dp, struct hdmi_edid_data *edid_data) 1185 { 1186 struct drm_display_info *di = &edid_data->display_info; 1187 u32 max_link_rate, max_lane_count; 1188 u32 min_bpp; 1189 int i; 1190 1191 if (di->color_formats & DRM_COLOR_FORMAT_YCRCB422) 1192 min_bpp = 16; 1193 else if (di->color_formats & DRM_COLOR_FORMAT_RGB444) 1194 min_bpp = 18; 1195 else 1196 min_bpp = 24; 1197 1198 max_link_rate = min_t(u32, dp->video_info.max_link_rate, dp->link_train.link_rate); 1199 max_lane_count = min_t(u32, dp->video_info.max_lane_count, dp->link_train.lane_count); 1200 for (i = 0; i < edid_data->modes; i++) { 1201 if (!analogix_dp_bandwidth_ok(dp, &edid_data->mode_buf[i], min_bpp, 1202 drm_dp_bw_code_to_link_rate(max_link_rate), 1203 max_lane_count)) 1204 edid_data->mode_buf[i].invalid = true; 1205 } 1206 1207 return 0; 1208 } 1209 1210 static int analogix_dp_connector_get_timing(struct rockchip_connector *conn, 1211 struct display_state *state) 1212 { 1213 struct connector_state *conn_state = &state->conn_state; 1214 const struct rockchip_dp_chip_data *pdata = 1215 (const struct rockchip_dp_chip_data *)dev_get_driver_data(conn->dev); 1216 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 1217 struct drm_display_mode *mode = &conn_state->mode; 1218 struct hdmi_edid_data edid_data; 1219 struct drm_display_mode *mode_buf; 1220 struct vop_rect rect; 1221 u32 yuv_fmts_mask = DRM_COLOR_FORMAT_YCRCB444 | DRM_COLOR_FORMAT_YCRCB422; 1222 u32 fmt_id; 1223 int ret, i; 1224 1225 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode)); 1226 if (!mode_buf) 1227 return -ENOMEM; 1228 1229 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode)); 1230 memset(&edid_data, 0, sizeof(struct hdmi_edid_data)); 1231 edid_data.mode_buf = mode_buf; 1232 1233 ret = drm_do_get_edid(&dp->aux.ddc, conn_state->edid); 1234 if (!ret) 1235 ret = drm_add_edid_modes(&edid_data, conn_state->edid); 1236 1237 if (ret < 0) { 1238 printf("failed to get edid\n"); 1239 goto err; 1240 } 1241 1242 if (!pdata->format_yuv) { 1243 if (edid_data.display_info.color_formats & yuv_fmts_mask) { 1244 printf("Swapping display color format from YUV to RGB\n"); 1245 edid_data.display_info.color_formats &= ~yuv_fmts_mask; 1246 edid_data.display_info.color_formats |= DRM_COLOR_FORMAT_RGB444; 1247 } 1248 } 1249 1250 if (state->conn_state.secondary) { 1251 rect.width = state->crtc_state.max_output.width / 2; 1252 rect.height = state->crtc_state.max_output.height / 2; 1253 } else { 1254 rect.width = state->crtc_state.max_output.width; 1255 rect.height = state->crtc_state.max_output.height; 1256 } 1257 1258 drm_mode_max_resolution_filter(&edid_data, &rect); 1259 analogix_dp_mode_valid(dp, &edid_data); 1260 1261 if (!drm_mode_prune_invalid(&edid_data)) { 1262 printf("can't find valid dp mode\n"); 1263 ret = -EINVAL; 1264 goto err; 1265 } 1266 1267 for (i = 0; i < edid_data.modes; i++) 1268 edid_data.mode_buf[i].vrefresh = drm_mode_vrefresh(&edid_data.mode_buf[i]); 1269 1270 drm_mode_sort(&edid_data); 1271 memcpy(mode, edid_data.preferred_mode, sizeof(struct drm_display_mode)); 1272 1273 fmt_id = analogix_dp_get_output_format_by_edid(dp, &edid_data); 1274 dp->output_fmt = &possible_output_fmts[fmt_id]; 1275 1276 switch (dp->output_fmt->color_format) { 1277 case DRM_COLOR_FORMAT_YCRCB422: 1278 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV422; 1279 break; 1280 case DRM_COLOR_FORMAT_RGB444: 1281 case DRM_COLOR_FORMAT_YCRCB444: 1282 default: 1283 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 1284 break; 1285 } 1286 1287 conn_state->bus_format = dp->output_fmt->bus_format; 1288 conn_state->bpc = dp->output_fmt->bpc; 1289 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709; 1290 if (dp->output_fmt->color_format == DRM_COLOR_FORMAT_RGB444) 1291 conn_state->color_range = DRM_COLOR_YCBCR_FULL_RANGE; 1292 else 1293 conn_state->color_range = DRM_COLOR_YCBCR_LIMITED_RANGE; 1294 1295 err: 1296 free(mode_buf); 1297 1298 return 0; 1299 } 1300 1301 static const struct rockchip_connector_funcs analogix_dp_connector_funcs = { 1302 .init = analogix_dp_connector_init, 1303 .get_edid = analogix_dp_connector_get_edid, 1304 .enable = analogix_dp_connector_enable, 1305 .disable = analogix_dp_connector_disable, 1306 .detect = analogix_dp_connector_detect, 1307 .mode_valid = analogix_dp_connector_mode_valid, 1308 .get_timing = analogix_dp_connector_get_timing, 1309 }; 1310 1311 static u32 analogix_dp_parse_link_frequencies(struct analogix_dp_device *dp) 1312 { 1313 struct udevice *dev = dp->dev; 1314 const struct device_node *endpoint; 1315 u64 frequency = 0; 1316 1317 endpoint = rockchip_of_graph_get_endpoint_by_regs(dev->node, 1, 0); 1318 if (!endpoint) 1319 return 0; 1320 1321 if (of_property_read_u64(endpoint, "link-frequencies", &frequency) < 0) 1322 return 0; 1323 1324 if (!frequency) 1325 return 0; 1326 1327 do_div(frequency, 10 * 1000); /* symbol rate kbytes */ 1328 1329 switch (frequency) { 1330 case 162000: 1331 case 270000: 1332 case 540000: 1333 break; 1334 default: 1335 dev_err(dev, "invalid link frequency value: %llu\n", frequency); 1336 return 0; 1337 } 1338 1339 return frequency; 1340 } 1341 1342 static int analogix_dp_parse_dt(struct analogix_dp_device *dp) 1343 { 1344 struct udevice *dev = dp->dev; 1345 int len; 1346 u32 num_lanes; 1347 u32 max_link_rate; 1348 int ret; 1349 1350 dp->force_hpd = dev_read_bool(dev, "force-hpd"); 1351 dp->video_bist_enable = dev_read_bool(dev, "analogix,video-bist-enable"); 1352 dp->video_info.force_stream_valid = 1353 dev_read_bool(dev, "analogix,force-stream-valid"); 1354 1355 max_link_rate = analogix_dp_parse_link_frequencies(dp); 1356 if (max_link_rate && max_link_rate < drm_dp_bw_code_to_link_rate(dp->video_info.max_link_rate)) 1357 dp->video_info.max_link_rate = drm_dp_link_rate_to_bw_code(max_link_rate); 1358 1359 if (dev_read_prop(dev, "data-lanes", &len)) { 1360 num_lanes = len / sizeof(u32); 1361 if (num_lanes < 1 || num_lanes > 4 || num_lanes == 3) { 1362 dev_err(dev, "bad number of data lanes\n"); 1363 return -EINVAL; 1364 } 1365 1366 ret = dev_read_u32_array(dev, "data-lanes", dp->lane_map, 1367 num_lanes); 1368 if (ret) 1369 return ret; 1370 1371 dp->video_info.max_lane_count = num_lanes; 1372 } else { 1373 dp->lane_map[0] = 0; 1374 dp->lane_map[1] = 1; 1375 dp->lane_map[2] = 2; 1376 dp->lane_map[3] = 3; 1377 } 1378 1379 return 0; 1380 } 1381 1382 static int analogix_dp_ddc_init(struct analogix_dp_device *dp) 1383 { 1384 dp->aux.name = "analogix-dp"; 1385 dp->aux.dev = dp->dev; 1386 dp->aux.transfer = analogix_dp_aux_transfer; 1387 dp->aux.ddc.ddc_xfer = drm_dp_i2c_xfer; 1388 1389 return 0; 1390 } 1391 1392 static int analogix_dp_probe(struct udevice *dev) 1393 { 1394 struct analogix_dp_device *dp = dev_get_priv(dev); 1395 const struct rockchip_dp_chip_data *pdata = 1396 (const struct rockchip_dp_chip_data *)dev_get_driver_data(dev); 1397 struct udevice *syscon; 1398 int ret; 1399 1400 dp->reg_base = dev_read_addr_ptr(dev); 1401 1402 dp->id = of_alias_get_id(ofnode_to_np(dev->node), "edp"); 1403 if (dp->id < 0) 1404 dp->id = 0; 1405 1406 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1407 &syscon); 1408 if (!ret) { 1409 dp->grf = syscon_get_regmap(syscon); 1410 if (!dp->grf) 1411 return -ENODEV; 1412 } 1413 1414 ret = reset_get_bulk(dev, &dp->resets); 1415 if (ret) { 1416 dev_err(dev, "failed to get reset control: %d\n", ret); 1417 return ret; 1418 } 1419 1420 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 1421 GPIOD_IS_IN); 1422 if (ret && ret != -ENOENT) { 1423 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 1424 return ret; 1425 } 1426 1427 generic_phy_get_by_name(dev, "dp", &dp->phy); 1428 1429 dp->plat_data.dev_type = ROCKCHIP_DP; 1430 dp->plat_data.subdev_type = pdata->chip_type; 1431 dp->plat_data.ssc = pdata->ssc; 1432 dp->plat_data.support_dp_mode = pdata->support_dp_mode; 1433 dp->plat_data.max_bpc = pdata->max_bpc ? pdata->max_bpc : 8; 1434 1435 dp->video_info.max_link_rate = pdata->max_link_rate; 1436 dp->video_info.max_lane_count = pdata->max_lane_count; 1437 1438 dp->dev = dev; 1439 1440 ret = analogix_dp_parse_dt(dp); 1441 if (ret) { 1442 dev_err(dev, "failed to parse DT: %d\n", ret); 1443 return ret; 1444 } 1445 1446 analogix_dp_ddc_init(dp); 1447 1448 rockchip_connector_bind(&dp->connector, dev, dp->id, &analogix_dp_connector_funcs, 1449 NULL, DRM_MODE_CONNECTOR_eDP); 1450 1451 return 0; 1452 } 1453 1454 static const struct rockchip_dp_chip_data rk3288_edp_platform_data = { 1455 .lcdsel_grf_reg = 0x025c, 1456 .lcdsel_big = 0 | BIT(21), 1457 .lcdsel_lit = BIT(5) | BIT(21), 1458 .chip_type = RK3288_DP, 1459 1460 .max_link_rate = DP_LINK_BW_2_7, 1461 .max_lane_count = 4, 1462 }; 1463 1464 static const struct rockchip_dp_chip_data rk3368_edp_platform_data = { 1465 .chip_type = RK3368_EDP, 1466 1467 .max_link_rate = DP_LINK_BW_2_7, 1468 .max_lane_count = 4, 1469 }; 1470 1471 static const struct rockchip_dp_chip_data rk3399_edp_platform_data = { 1472 .lcdsel_grf_reg = 0x6250, 1473 .lcdsel_big = 0 | BIT(21), 1474 .lcdsel_lit = BIT(5) | BIT(21), 1475 .chip_type = RK3399_EDP, 1476 .ssc = true, 1477 1478 .max_link_rate = DP_LINK_BW_5_4, 1479 .max_lane_count = 4, 1480 }; 1481 1482 static const struct rockchip_dp_chip_data rk3568_edp_platform_data = { 1483 .chip_type = RK3568_EDP, 1484 .ssc = true, 1485 1486 .max_link_rate = DP_LINK_BW_2_7, 1487 .max_lane_count = 4, 1488 }; 1489 1490 static const struct rockchip_dp_chip_data rk3576_edp_platform_data = { 1491 .chip_type = RK3576_EDP, 1492 .ssc = true, 1493 1494 .max_link_rate = DP_LINK_BW_5_4, 1495 .max_lane_count = 4, 1496 .format_yuv = true, 1497 .support_dp_mode = true, 1498 .max_bpc = 10, 1499 }; 1500 1501 static const struct rockchip_dp_chip_data rk3588_edp_platform_data = { 1502 .chip_type = RK3588_EDP, 1503 .ssc = true, 1504 1505 .max_link_rate = DP_LINK_BW_5_4, 1506 .max_lane_count = 4, 1507 .format_yuv = true, 1508 .support_dp_mode = true, 1509 .max_bpc = 10, 1510 }; 1511 1512 static const struct udevice_id analogix_dp_ids[] = { 1513 { 1514 .compatible = "rockchip,rk3288-dp", 1515 .data = (ulong)&rk3288_edp_platform_data, 1516 }, { 1517 .compatible = "rockchip,rk3368-edp", 1518 .data = (ulong)&rk3368_edp_platform_data, 1519 }, { 1520 .compatible = "rockchip,rk3399-edp", 1521 .data = (ulong)&rk3399_edp_platform_data, 1522 }, { 1523 .compatible = "rockchip,rk3568-edp", 1524 .data = (ulong)&rk3568_edp_platform_data, 1525 }, { 1526 .compatible = "rockchip,rk3576-edp", 1527 .data = (ulong)&rk3576_edp_platform_data, 1528 }, { 1529 .compatible = "rockchip,rk3588-edp", 1530 .data = (ulong)&rk3588_edp_platform_data, 1531 }, 1532 {} 1533 }; 1534 1535 U_BOOT_DRIVER(analogix_dp) = { 1536 .name = "analogix_dp", 1537 .id = UCLASS_DISPLAY, 1538 .of_match = analogix_dp_ids, 1539 .probe = analogix_dp_probe, 1540 .priv_auto_alloc_size = sizeof(struct analogix_dp_device), 1541 }; 1542