1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <dm/device.h> 14 #include <dm/of_access.h> 15 #include <dm/read.h> 16 #include <linux/bitfield.h> 17 #include <linux/list.h> 18 #include <syscon.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <asm/gpio.h> 21 22 #include "rockchip_display.h" 23 #include "rockchip_crtc.h" 24 #include "rockchip_connector.h" 25 #include "analogix_dp.h" 26 27 #define RK3588_GRF_VO1_CON0 0x0000 28 #define EDP_MODE BIT(0) 29 #define RK3588_GRF_VO1_CON1 0x0004 30 31 /** 32 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips 33 * @lcdsel_grf_reg: grf register offset of lcdc select 34 * @lcdsel_big: reg value of selecting vop big for eDP 35 * @lcdsel_lit: reg value of selecting vop little for eDP 36 * @chip_type: specific chip type 37 * @ssc: check if SSC is supported by source 38 */ 39 struct rockchip_dp_chip_data { 40 u32 lcdsel_grf_reg; 41 u32 lcdsel_big; 42 u32 lcdsel_lit; 43 u32 chip_type; 44 bool ssc; 45 46 u32 max_link_rate; 47 u32 max_lane_count; 48 }; 49 50 static void 51 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp, 52 bool enable) 53 { 54 u8 data; 55 56 analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data); 57 58 if (enable) 59 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 60 DP_LANE_COUNT_ENHANCED_FRAME_EN | 61 DPCD_LANE_COUNT_SET(data)); 62 else 63 analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 64 DPCD_LANE_COUNT_SET(data)); 65 } 66 67 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp) 68 { 69 u8 data; 70 int retval; 71 72 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 73 retval = DPCD_ENHANCED_FRAME_CAP(data); 74 75 return retval; 76 } 77 78 static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp) 79 { 80 u8 data; 81 82 data = analogix_dp_is_enhanced_mode_available(dp); 83 analogix_dp_enable_rx_to_enhanced_mode(dp, data); 84 analogix_dp_enable_enhanced_mode(dp, data); 85 } 86 87 static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp) 88 { 89 analogix_dp_set_training_pattern(dp, DP_NONE); 90 91 analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET, 92 DP_TRAINING_PATTERN_DISABLE); 93 } 94 95 static int analogix_dp_link_start(struct analogix_dp_device *dp) 96 { 97 u8 buf[4]; 98 int lane, lane_count, retval; 99 100 lane_count = dp->link_train.lane_count; 101 102 dp->link_train.lt_state = CLOCK_RECOVERY; 103 dp->link_train.eq_loop = 0; 104 105 for (lane = 0; lane < lane_count; lane++) 106 dp->link_train.cr_loop[lane] = 0; 107 108 /* Set link rate and count as you want to establish*/ 109 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 110 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); 111 112 /* Setup RX configuration */ 113 buf[0] = dp->link_train.link_rate; 114 buf[1] = dp->link_train.lane_count; 115 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf); 116 if (retval) 117 return retval; 118 119 /* Spread AMP if required, enable 8b/10b coding */ 120 buf[0] = analogix_dp_ssc_supported(dp) ? DP_SPREAD_AMP_0_5 : 0; 121 buf[1] = DP_SET_ANSI_8B10B; 122 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_DOWNSPREAD_CTRL, 123 2, buf); 124 if (retval < 0) 125 return retval; 126 127 /* Set TX voltage-swing and pre-emphasis to minimum */ 128 for (lane = 0; lane < lane_count; lane++) 129 dp->link_train.training_lane[lane] = 130 DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | 131 DP_TRAIN_PRE_EMPH_LEVEL_0; 132 analogix_dp_set_lane_link_training(dp); 133 134 /* Set training pattern 1 */ 135 analogix_dp_set_training_pattern(dp, TRAINING_PTN1); 136 137 /* Set RX training pattern */ 138 retval = analogix_dp_write_byte_to_dpcd(dp, 139 DP_TRAINING_PATTERN_SET, 140 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); 141 if (retval) 142 return retval; 143 144 for (lane = 0; lane < lane_count; lane++) 145 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 146 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 147 148 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 149 lane_count, buf); 150 151 return retval; 152 } 153 154 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) 155 { 156 int shift = (lane & 1) * 4; 157 u8 link_value = link_status[lane >> 1]; 158 159 return (link_value >> shift) & 0xf; 160 } 161 162 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) 163 { 164 int lane; 165 u8 lane_status; 166 167 for (lane = 0; lane < lane_count; lane++) { 168 lane_status = analogix_dp_get_lane_status(link_status, lane); 169 if ((lane_status & DP_LANE_CR_DONE) == 0) 170 return -EINVAL; 171 } 172 return 0; 173 } 174 175 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, 176 int lane_count) 177 { 178 int lane; 179 u8 lane_status; 180 181 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) 182 return -EINVAL; 183 184 for (lane = 0; lane < lane_count; lane++) { 185 lane_status = analogix_dp_get_lane_status(link_status, lane); 186 lane_status &= DP_CHANNEL_EQ_BITS; 187 if (lane_status != DP_CHANNEL_EQ_BITS) 188 return -EINVAL; 189 } 190 191 return 0; 192 } 193 194 static unsigned char 195 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) 196 { 197 int shift = (lane & 1) * 4; 198 u8 link_value = adjust_request[lane >> 1]; 199 200 return (link_value >> shift) & 0x3; 201 } 202 203 static unsigned char analogix_dp_get_adjust_request_pre_emphasis( 204 u8 adjust_request[2], 205 int lane) 206 { 207 int shift = (lane & 1) * 4; 208 u8 link_value = adjust_request[lane >> 1]; 209 210 return ((link_value >> shift) & 0xc) >> 2; 211 } 212 213 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp) 214 { 215 analogix_dp_training_pattern_dis(dp); 216 analogix_dp_set_enhanced_mode(dp); 217 218 dp->link_train.lt_state = FAILED; 219 } 220 221 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp, 222 u8 adjust_request[2]) 223 { 224 int lane, lane_count; 225 u8 voltage_swing, pre_emphasis, training_lane; 226 227 lane_count = dp->link_train.lane_count; 228 for (lane = 0; lane < lane_count; lane++) { 229 voltage_swing = analogix_dp_get_adjust_request_voltage( 230 adjust_request, lane); 231 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 232 adjust_request, lane); 233 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | 234 DPCD_PRE_EMPHASIS_SET(pre_emphasis); 235 236 if (voltage_swing == VOLTAGE_LEVEL_3) 237 training_lane |= DP_TRAIN_MAX_SWING_REACHED; 238 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) 239 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 240 241 dp->link_train.training_lane[lane] = training_lane; 242 } 243 } 244 245 static bool analogix_dp_tps3_supported(struct analogix_dp_device *dp) 246 { 247 bool source_tps3_supported, sink_tps3_supported; 248 u8 dpcd = 0; 249 250 source_tps3_supported = 251 dp->video_info.max_link_rate == DP_LINK_BW_5_4; 252 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &dpcd); 253 sink_tps3_supported = dpcd & DP_TPS3_SUPPORTED; 254 255 return source_tps3_supported && sink_tps3_supported; 256 } 257 258 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp) 259 { 260 int lane, lane_count, retval; 261 u8 voltage_swing, pre_emphasis, training_lane; 262 u8 link_status[2], adjust_request[2]; 263 u8 training_pattern = TRAINING_PTN2; 264 265 drm_dp_link_train_clock_recovery_delay(dp->dpcd); 266 267 lane_count = dp->link_train.lane_count; 268 269 retval = analogix_dp_read_bytes_from_dpcd(dp, 270 DP_LANE0_1_STATUS, 2, link_status); 271 if (retval) 272 return retval; 273 274 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { 275 if (analogix_dp_tps3_supported(dp)) 276 training_pattern = TRAINING_PTN3; 277 278 /* set training pattern for EQ */ 279 analogix_dp_set_training_pattern(dp, training_pattern); 280 281 retval = analogix_dp_write_byte_to_dpcd(dp, 282 DP_TRAINING_PATTERN_SET, 283 (training_pattern == TRAINING_PTN3 ? 284 DP_TRAINING_PATTERN_3 : DP_TRAINING_PATTERN_2)); 285 if (retval) 286 return retval; 287 288 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 289 dp->link_train.lt_state = EQUALIZER_TRAINING; 290 291 return 0; 292 } else { 293 retval = analogix_dp_read_bytes_from_dpcd(dp, 294 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 295 if (retval) 296 return retval; 297 298 for (lane = 0; lane < lane_count; lane++) { 299 training_lane = analogix_dp_get_lane_link_training( 300 dp, lane); 301 voltage_swing = analogix_dp_get_adjust_request_voltage( 302 adjust_request, lane); 303 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis( 304 adjust_request, lane); 305 306 if (DPCD_VOLTAGE_SWING_GET(training_lane) == 307 voltage_swing && 308 DPCD_PRE_EMPHASIS_GET(training_lane) == 309 pre_emphasis) 310 dp->link_train.cr_loop[lane]++; 311 312 /* 313 * In DP spec 1.3, Condition of CR fail are 314 * outlined in section 3.5.1.2.2.1, figure 3-20: 315 * 316 * 1. Maximum Voltage Swing reached 317 * 2. Same Voltage five times 318 */ 319 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || 320 DPCD_VOLTAGE_SWING_GET(training_lane) == VOLTAGE_LEVEL_3) { 321 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", 322 dp->link_train.cr_loop[lane], 323 voltage_swing, pre_emphasis); 324 analogix_dp_reduce_link_rate(dp); 325 return -EIO; 326 } 327 } 328 } 329 330 analogix_dp_get_adjust_training_lane(dp, adjust_request); 331 analogix_dp_set_lane_link_training(dp); 332 333 retval = analogix_dp_write_bytes_to_dpcd(dp, 334 DP_TRAINING_LANE0_SET, lane_count, 335 dp->link_train.training_lane); 336 if (retval) 337 return retval; 338 339 return retval; 340 } 341 342 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp) 343 { 344 int lane_count, retval; 345 u32 reg; 346 u8 link_align, link_status[2], adjust_request[2]; 347 348 drm_dp_link_train_channel_eq_delay(dp->dpcd); 349 350 lane_count = dp->link_train.lane_count; 351 352 retval = analogix_dp_read_bytes_from_dpcd(dp, 353 DP_LANE0_1_STATUS, 2, link_status); 354 if (retval) 355 return retval; 356 357 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { 358 analogix_dp_reduce_link_rate(dp); 359 return -EIO; 360 } 361 362 retval = analogix_dp_read_byte_from_dpcd(dp, 363 DP_LANE_ALIGN_STATUS_UPDATED, &link_align); 364 if (retval) 365 return retval; 366 367 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { 368 /* traing pattern Set to Normal */ 369 analogix_dp_training_pattern_dis(dp); 370 371 printf("Link Training success!\n"); 372 373 analogix_dp_get_link_bandwidth(dp, ®); 374 dp->link_train.link_rate = reg; 375 analogix_dp_get_lane_count(dp, ®); 376 dp->link_train.lane_count = reg; 377 378 printf("final link rate = 0x%.2x, lane count = 0x%.2x\n", 379 dp->link_train.link_rate, dp->link_train.lane_count); 380 381 /* set enhanced mode if available */ 382 analogix_dp_set_enhanced_mode(dp); 383 dp->link_train.lt_state = FINISHED; 384 385 return 0; 386 } 387 388 /* not all locked */ 389 dp->link_train.eq_loop++; 390 391 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 392 dev_dbg(dp->dev, "EQ Max loop\n"); 393 analogix_dp_reduce_link_rate(dp); 394 return -EIO; 395 } 396 397 retval = analogix_dp_read_bytes_from_dpcd(dp, 398 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 399 if (retval) 400 return retval; 401 402 analogix_dp_get_adjust_training_lane(dp, adjust_request); 403 analogix_dp_set_lane_link_training(dp); 404 405 retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 406 lane_count, dp->link_train.training_lane); 407 408 return retval; 409 } 410 411 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, 412 u8 *bandwidth) 413 { 414 u8 data; 415 416 /* 417 * For DP rev.1.1, Maximum link rate of Main Link lanes 418 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps 419 * For DP rev.1.2, Maximum link rate of Main Link lanes 420 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 421 */ 422 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); 423 *bandwidth = data; 424 } 425 426 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, 427 u8 *lane_count) 428 { 429 u8 data; 430 431 /* 432 * For DP rev.1.1, Maximum number of Main Link lanes 433 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 434 */ 435 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 436 *lane_count = DPCD_MAX_LANE_COUNT(data); 437 } 438 439 static int analogix_dp_init_training(struct analogix_dp_device *dp, 440 enum link_lane_count_type max_lane, 441 int max_rate) 442 { 443 u8 dpcd; 444 445 /* 446 * MACRO_RST must be applied after the PLL_LOCK to avoid 447 * the DP inter pair skew issue for at least 10 us 448 */ 449 analogix_dp_reset_macro(dp); 450 451 /* Initialize by reading RX's DPCD */ 452 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); 453 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); 454 455 /* Setup TX lane count & rate */ 456 dp->link_train.lane_count = min_t(u8, dp->link_train.lane_count, 457 max_lane); 458 dp->link_train.link_rate = min_t(u32, dp->link_train.link_rate, 459 max_rate); 460 461 analogix_dp_read_byte_from_dpcd(dp, DP_MAX_DOWNSPREAD, &dpcd); 462 dp->link_train.ssc = !!(dpcd & DP_MAX_DOWNSPREAD_0_5); 463 464 /* All DP analog module power up */ 465 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 466 467 return 0; 468 } 469 470 static int analogix_dp_sw_link_training(struct analogix_dp_device *dp) 471 { 472 int retval = 0, training_finished = 0; 473 474 dp->link_train.lt_state = START; 475 476 /* Process here */ 477 while (!retval && !training_finished) { 478 switch (dp->link_train.lt_state) { 479 case START: 480 retval = analogix_dp_link_start(dp); 481 if (retval) 482 dev_err(dp->dev, "LT link start failed!\n"); 483 break; 484 case CLOCK_RECOVERY: 485 retval = analogix_dp_process_clock_recovery(dp); 486 if (retval) 487 dev_err(dp->dev, "LT CR failed!\n"); 488 break; 489 case EQUALIZER_TRAINING: 490 retval = analogix_dp_process_equalizer_training(dp); 491 if (retval) 492 dev_err(dp->dev, "LT EQ failed!\n"); 493 break; 494 case FINISHED: 495 training_finished = 1; 496 break; 497 case FAILED: 498 return -EREMOTEIO; 499 } 500 } 501 502 return retval; 503 } 504 505 static int analogix_dp_set_link_train(struct analogix_dp_device *dp, 506 u32 count, u32 bwtype) 507 { 508 int i, ret; 509 510 for (i = 0; i < 5; i++) { 511 ret = analogix_dp_init_training(dp, count, bwtype); 512 if (ret < 0) { 513 dev_err(dp->dev, "failed to init training\n"); 514 return ret; 515 } 516 517 ret = analogix_dp_sw_link_training(dp); 518 if (!ret) 519 break; 520 } 521 522 return ret; 523 } 524 525 static int analogix_dp_config_video(struct analogix_dp_device *dp) 526 { 527 int timeout_loop = 0; 528 int done_count = 0; 529 530 analogix_dp_config_video_slave_mode(dp); 531 532 analogix_dp_set_video_color_format(dp); 533 534 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 535 dev_err(dp->dev, "PLL is not locked yet.\n"); 536 return -EINVAL; 537 } 538 539 for (;;) { 540 timeout_loop++; 541 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0) 542 break; 543 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 544 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 545 return -ETIMEDOUT; 546 } 547 548 udelay(2); 549 } 550 551 /* Set to use the register calculated M/N video */ 552 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); 553 554 /* For video bist, Video timing must be generated by register */ 555 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_REGISTER); 556 557 /* Disable video mute */ 558 analogix_dp_enable_video_mute(dp, 0); 559 560 /* Configure video slave mode */ 561 analogix_dp_enable_video_master(dp, 0); 562 563 /* Enable video input */ 564 analogix_dp_start_video(dp); 565 566 timeout_loop = 0; 567 568 for (;;) { 569 timeout_loop++; 570 if (analogix_dp_is_video_stream_on(dp) == 0) { 571 done_count++; 572 if (done_count > 10) 573 break; 574 } else if (done_count) { 575 done_count = 0; 576 } 577 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) { 578 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 579 return -ETIMEDOUT; 580 } 581 582 udelay(1001); 583 } 584 585 return 0; 586 } 587 588 static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, 589 bool enable) 590 { 591 u8 data; 592 593 if (enable) { 594 analogix_dp_enable_scrambling(dp); 595 596 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 597 &data); 598 analogix_dp_write_byte_to_dpcd(dp, 599 DP_TRAINING_PATTERN_SET, 600 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); 601 } else { 602 analogix_dp_disable_scrambling(dp); 603 604 analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, 605 &data); 606 analogix_dp_write_byte_to_dpcd(dp, 607 DP_TRAINING_PATTERN_SET, 608 (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); 609 } 610 } 611 612 static void analogix_dp_init_dp(struct analogix_dp_device *dp) 613 { 614 analogix_dp_reset(dp); 615 616 analogix_dp_swreset(dp); 617 618 analogix_dp_init_analog_param(dp); 619 analogix_dp_init_interrupt(dp); 620 621 /* SW defined function Normal operation */ 622 analogix_dp_enable_sw_function(dp); 623 624 analogix_dp_config_interrupt(dp); 625 analogix_dp_init_analog_func(dp); 626 627 analogix_dp_init_hpd(dp); 628 analogix_dp_init_aux(dp); 629 } 630 631 static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data) 632 { 633 int i; 634 unsigned char sum = 0; 635 636 for (i = 0; i < EDID_BLOCK_LENGTH; i++) 637 sum = sum + edid_data[i]; 638 639 return sum; 640 } 641 642 static int analogix_dp_read_edid(struct analogix_dp_device *dp) 643 { 644 unsigned char *edid = dp->edid; 645 unsigned int extend_block = 0; 646 unsigned char test_vector; 647 int retval; 648 649 /* 650 * EDID device address is 0x50. 651 * However, if necessary, you must have set upper address 652 * into E-EDID in I2C device, 0x30. 653 */ 654 655 /* Read Extension Flag, Number of 128-byte EDID extension blocks */ 656 retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, 657 EDID_EXTENSION_FLAG, 658 &extend_block); 659 if (retval) 660 return retval; 661 662 if (extend_block > 0) { 663 debug("EDID data includes a single extension!\n"); 664 665 /* Read EDID data */ 666 retval = analogix_dp_read_bytes_from_i2c(dp, 667 I2C_EDID_DEVICE_ADDR, 668 EDID_HEADER_PATTERN, 669 EDID_BLOCK_LENGTH, 670 &edid[EDID_HEADER_PATTERN]); 671 if (retval < 0) 672 return retval; 673 674 if (analogix_dp_calc_edid_check_sum(edid)) 675 return -EINVAL; 676 677 /* Read additional EDID data */ 678 retval = analogix_dp_read_bytes_from_i2c(dp, 679 I2C_EDID_DEVICE_ADDR, 680 EDID_BLOCK_LENGTH, 681 EDID_BLOCK_LENGTH, 682 &edid[EDID_BLOCK_LENGTH]); 683 if (retval < 0) 684 return retval; 685 686 if (analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH])) 687 return -EINVAL; 688 689 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 690 &test_vector); 691 if (test_vector & DP_TEST_LINK_EDID_READ) { 692 analogix_dp_write_byte_to_dpcd(dp, 693 DP_TEST_EDID_CHECKSUM, 694 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); 695 analogix_dp_write_byte_to_dpcd(dp, 696 DP_TEST_RESPONSE, 697 DP_TEST_EDID_CHECKSUM_WRITE); 698 } 699 } else { 700 dev_info(dp->dev, 701 "EDID data does not include any extensions.\n"); 702 703 /* Read EDID data */ 704 retval = analogix_dp_read_bytes_from_i2c(dp, 705 I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN, 706 EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]); 707 if (retval < 0) 708 return retval; 709 710 if (analogix_dp_calc_edid_check_sum(edid)) 711 return -EINVAL; 712 713 analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 714 &test_vector); 715 if (test_vector & DP_TEST_LINK_EDID_READ) { 716 analogix_dp_write_byte_to_dpcd(dp, 717 DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]); 718 analogix_dp_write_byte_to_dpcd(dp, 719 DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE); 720 } 721 } 722 723 return 0; 724 } 725 726 static int analogix_dp_handle_edid(struct analogix_dp_device *dp) 727 { 728 u8 buf[12]; 729 int i, try = 5; 730 int retval; 731 732 retry: 733 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */ 734 retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf); 735 736 if (retval && try--) { 737 mdelay(10); 738 goto retry; 739 } 740 741 if (retval) 742 return retval; 743 744 /* Read EDID */ 745 for (i = 0; i < 3; i++) { 746 retval = analogix_dp_read_edid(dp); 747 if (!retval) 748 break; 749 } 750 751 return retval; 752 } 753 754 static int analogix_dp_connector_init(struct rockchip_connector *conn, struct display_state *state) 755 { 756 struct connector_state *conn_state = &state->conn_state; 757 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 758 759 conn_state->output_if |= dp->id ? VOP_OUTPUT_IF_eDP1 : VOP_OUTPUT_IF_eDP0; 760 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA; 761 conn_state->color_encoding = DRM_COLOR_YCBCR_BT709; 762 conn_state->color_range = DRM_COLOR_YCBCR_FULL_RANGE; 763 764 reset_assert_bulk(&dp->resets); 765 udelay(1); 766 reset_deassert_bulk(&dp->resets); 767 768 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, dp->id); 769 generic_phy_set_mode(&dp->phy, PHY_MODE_DP); 770 generic_phy_power_on(&dp->phy); 771 analogix_dp_init_dp(dp); 772 773 return 0; 774 } 775 776 static int analogix_dp_connector_get_edid(struct rockchip_connector *conn, 777 struct display_state *state) 778 { 779 struct connector_state *conn_state = &state->conn_state; 780 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 781 int ret; 782 783 ret = analogix_dp_handle_edid(dp); 784 if (ret) { 785 dev_err(dp->dev, "failed to get edid\n"); 786 return ret; 787 } 788 789 memcpy(&conn_state->edid, &dp->edid, sizeof(dp->edid)); 790 791 return 0; 792 } 793 794 static int analogix_dp_link_power_up(struct analogix_dp_device *dp) 795 { 796 u8 value; 797 int ret; 798 799 if (dp->dpcd[DP_DPCD_REV] < 0x11) 800 return 0; 801 802 ret = analogix_dp_read_byte_from_dpcd(dp, DP_SET_POWER, &value); 803 if (ret < 0) 804 return ret; 805 806 value &= ~DP_SET_POWER_MASK; 807 value |= DP_SET_POWER_D0; 808 809 ret = analogix_dp_write_byte_to_dpcd(dp, DP_SET_POWER, value); 810 if (ret < 0) 811 return ret; 812 813 mdelay(1); 814 815 return 0; 816 } 817 818 static int analogix_dp_link_power_down(struct analogix_dp_device *dp) 819 { 820 u8 value; 821 int ret; 822 823 if (dp->dpcd[DP_DPCD_REV] < 0x11) 824 return 0; 825 826 ret = analogix_dp_read_byte_from_dpcd(dp, DP_SET_POWER, &value); 827 if (ret < 0) 828 return ret; 829 830 value &= ~DP_SET_POWER_MASK; 831 value |= DP_SET_POWER_D3; 832 833 ret = analogix_dp_write_byte_to_dpcd(dp, DP_SET_POWER, value); 834 if (ret < 0) 835 return ret; 836 837 return 0; 838 } 839 840 static int analogix_dp_connector_enable(struct rockchip_connector *conn, 841 struct display_state *state) 842 { 843 struct connector_state *conn_state = &state->conn_state; 844 struct crtc_state *crtc_state = &state->crtc_state; 845 const struct rockchip_dp_chip_data *pdata = 846 (const struct rockchip_dp_chip_data *)dev_get_driver_data(conn->dev); 847 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 848 struct video_info *video = &dp->video_info; 849 u32 val; 850 int ret; 851 852 if (pdata->lcdsel_grf_reg) { 853 if (crtc_state->crtc_id) 854 val = pdata->lcdsel_lit; 855 else 856 val = pdata->lcdsel_big; 857 858 regmap_write(dp->grf, pdata->lcdsel_grf_reg, val); 859 } 860 861 if (pdata->chip_type == RK3588_EDP) 862 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 863 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 1)); 864 865 switch (conn_state->bpc) { 866 case 12: 867 video->color_depth = COLOR_12; 868 break; 869 case 10: 870 video->color_depth = COLOR_10; 871 break; 872 case 6: 873 video->color_depth = COLOR_6; 874 break; 875 case 8: 876 default: 877 video->color_depth = COLOR_8; 878 break; 879 } 880 881 ret = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 882 DP_RECEIVER_CAP_SIZE, dp->dpcd); 883 if (ret) { 884 dev_err(dp->dev, "failed to read dpcd caps: %d\n", ret); 885 return ret; 886 } 887 888 ret = analogix_dp_link_power_up(dp); 889 if (ret) { 890 dev_err(dp->dev, "failed to power up link: %d\n", ret); 891 return ret; 892 } 893 894 ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count, 895 dp->video_info.max_link_rate); 896 if (ret) { 897 dev_err(dp->dev, "unable to do link train\n"); 898 return ret; 899 } 900 901 analogix_dp_enable_scramble(dp, 1); 902 analogix_dp_enable_rx_to_enhanced_mode(dp, 1); 903 analogix_dp_enable_enhanced_mode(dp, 1); 904 905 analogix_dp_init_video(dp); 906 analogix_dp_set_video_format(dp, &conn_state->mode); 907 908 if (dp->video_bist_enable) 909 analogix_dp_video_bist_enable(dp); 910 911 ret = analogix_dp_config_video(dp); 912 if (ret) { 913 dev_err(dp->dev, "unable to config video\n"); 914 return ret; 915 } 916 917 return 0; 918 } 919 920 static int analogix_dp_connector_disable(struct rockchip_connector *conn, 921 struct display_state *state) 922 { 923 const struct rockchip_dp_chip_data *pdata = 924 (const struct rockchip_dp_chip_data *)dev_get_driver_data(conn->dev); 925 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 926 927 if (!analogix_dp_get_plug_in_status(dp)) 928 analogix_dp_link_power_down(dp); 929 930 if (pdata->chip_type == RK3588_EDP) 931 regmap_write(dp->grf, dp->id ? RK3588_GRF_VO1_CON1 : RK3588_GRF_VO1_CON0, 932 EDP_MODE << 16 | FIELD_PREP(EDP_MODE, 0)); 933 934 return 0; 935 } 936 937 static int analogix_dp_connector_detect(struct rockchip_connector *conn, 938 struct display_state *state) 939 { 940 struct analogix_dp_device *dp = dev_get_priv(conn->dev); 941 942 return analogix_dp_detect(dp); 943 } 944 945 static int analogix_dp_connector_mode_valid(struct rockchip_connector *conn, 946 struct display_state *state) 947 { 948 struct connector_state *conn_state = &state->conn_state; 949 struct videomode vm; 950 951 drm_display_mode_to_videomode(&conn_state->mode, &vm); 952 953 if (!vm.hfront_porch || !vm.hback_porch || !vm.vfront_porch || !vm.vback_porch) { 954 dev_err(dp->dev, "front porch or back porch can not be 0\n"); 955 return MODE_BAD; 956 } 957 958 return MODE_OK; 959 } 960 961 static const struct rockchip_connector_funcs analogix_dp_connector_funcs = { 962 .init = analogix_dp_connector_init, 963 .get_edid = analogix_dp_connector_get_edid, 964 .enable = analogix_dp_connector_enable, 965 .disable = analogix_dp_connector_disable, 966 .detect = analogix_dp_connector_detect, 967 .mode_valid = analogix_dp_connector_mode_valid, 968 }; 969 970 static u32 analogix_dp_parse_link_frequencies(struct analogix_dp_device *dp) 971 { 972 struct udevice *dev = dp->dev; 973 const struct device_node *endpoint; 974 u64 frequency = 0; 975 976 endpoint = rockchip_of_graph_get_endpoint_by_regs(dev->node, 1, 0); 977 if (!endpoint) 978 return 0; 979 980 if (of_property_read_u64(endpoint, "link-frequencies", &frequency) < 0) 981 return 0; 982 983 if (!frequency) 984 return 0; 985 986 do_div(frequency, 10 * 1000); /* symbol rate kbytes */ 987 988 switch (frequency) { 989 case 162000: 990 case 270000: 991 case 540000: 992 break; 993 default: 994 dev_err(dev, "invalid link frequency value: %llu\n", frequency); 995 return 0; 996 } 997 998 return frequency; 999 } 1000 1001 static int analogix_dp_parse_dt(struct analogix_dp_device *dp) 1002 { 1003 struct udevice *dev = dp->dev; 1004 int len; 1005 u32 num_lanes; 1006 u32 max_link_rate; 1007 int ret; 1008 1009 dp->force_hpd = dev_read_bool(dev, "force-hpd"); 1010 dp->video_bist_enable = dev_read_bool(dev, "analogix,video-bist-enable"); 1011 dp->video_info.force_stream_valid = 1012 dev_read_bool(dev, "analogix,force-stream-valid"); 1013 1014 max_link_rate = analogix_dp_parse_link_frequencies(dp); 1015 if (max_link_rate && max_link_rate < drm_dp_bw_code_to_link_rate(dp->video_info.max_link_rate)) 1016 dp->video_info.max_link_rate = drm_dp_link_rate_to_bw_code(max_link_rate); 1017 1018 if (dev_read_prop(dev, "data-lanes", &len)) { 1019 num_lanes = len / sizeof(u32); 1020 if (num_lanes < 1 || num_lanes > 4 || num_lanes == 3) { 1021 dev_err(dev, "bad number of data lanes\n"); 1022 return -EINVAL; 1023 } 1024 1025 ret = dev_read_u32_array(dev, "data-lanes", dp->lane_map, 1026 num_lanes); 1027 if (ret) 1028 return ret; 1029 1030 dp->video_info.max_lane_count = num_lanes; 1031 } else { 1032 dp->lane_map[0] = 0; 1033 dp->lane_map[1] = 1; 1034 dp->lane_map[2] = 2; 1035 dp->lane_map[3] = 3; 1036 } 1037 1038 return 0; 1039 } 1040 1041 static int analogix_dp_probe(struct udevice *dev) 1042 { 1043 struct analogix_dp_device *dp = dev_get_priv(dev); 1044 const struct rockchip_dp_chip_data *pdata = 1045 (const struct rockchip_dp_chip_data *)dev_get_driver_data(dev); 1046 struct udevice *syscon; 1047 int ret; 1048 1049 dp->reg_base = dev_read_addr_ptr(dev); 1050 1051 dp->id = of_alias_get_id(ofnode_to_np(dev->node), "edp"); 1052 if (dp->id < 0) 1053 dp->id = 0; 1054 1055 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 1056 &syscon); 1057 if (!ret) { 1058 dp->grf = syscon_get_regmap(syscon); 1059 if (!dp->grf) 1060 return -ENODEV; 1061 } 1062 1063 ret = reset_get_bulk(dev, &dp->resets); 1064 if (ret) { 1065 dev_err(dev, "failed to get reset control: %d\n", ret); 1066 return ret; 1067 } 1068 1069 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio, 1070 GPIOD_IS_IN); 1071 if (ret && ret != -ENOENT) { 1072 dev_err(dev, "failed to get hpd GPIO: %d\n", ret); 1073 return ret; 1074 } 1075 1076 generic_phy_get_by_name(dev, "dp", &dp->phy); 1077 1078 dp->plat_data.dev_type = ROCKCHIP_DP; 1079 dp->plat_data.subdev_type = pdata->chip_type; 1080 dp->plat_data.ssc = pdata->ssc; 1081 1082 dp->video_info.max_link_rate = pdata->max_link_rate; 1083 dp->video_info.max_lane_count = pdata->max_lane_count; 1084 1085 dp->dev = dev; 1086 1087 ret = analogix_dp_parse_dt(dp); 1088 if (ret) { 1089 dev_err(dev, "failed to parse DT: %d\n", ret); 1090 return ret; 1091 } 1092 1093 rockchip_connector_bind(&dp->connector, dev, dp->id, &analogix_dp_connector_funcs, 1094 NULL, DRM_MODE_CONNECTOR_eDP); 1095 1096 return 0; 1097 } 1098 1099 static const struct rockchip_dp_chip_data rk3288_edp_platform_data = { 1100 .lcdsel_grf_reg = 0x025c, 1101 .lcdsel_big = 0 | BIT(21), 1102 .lcdsel_lit = BIT(5) | BIT(21), 1103 .chip_type = RK3288_DP, 1104 1105 .max_link_rate = DP_LINK_BW_2_7, 1106 .max_lane_count = 4, 1107 }; 1108 1109 static const struct rockchip_dp_chip_data rk3368_edp_platform_data = { 1110 .chip_type = RK3368_EDP, 1111 1112 .max_link_rate = DP_LINK_BW_2_7, 1113 .max_lane_count = 4, 1114 }; 1115 1116 static const struct rockchip_dp_chip_data rk3399_edp_platform_data = { 1117 .lcdsel_grf_reg = 0x6250, 1118 .lcdsel_big = 0 | BIT(21), 1119 .lcdsel_lit = BIT(5) | BIT(21), 1120 .chip_type = RK3399_EDP, 1121 .ssc = true, 1122 1123 .max_link_rate = DP_LINK_BW_5_4, 1124 .max_lane_count = 4, 1125 }; 1126 1127 static const struct rockchip_dp_chip_data rk3568_edp_platform_data = { 1128 .chip_type = RK3568_EDP, 1129 .ssc = true, 1130 1131 .max_link_rate = DP_LINK_BW_2_7, 1132 .max_lane_count = 4, 1133 }; 1134 1135 static const struct rockchip_dp_chip_data rk3576_edp_platform_data = { 1136 .chip_type = RK3576_EDP, 1137 .ssc = true, 1138 1139 .max_link_rate = DP_LINK_BW_5_4, 1140 .max_lane_count = 4, 1141 }; 1142 1143 static const struct rockchip_dp_chip_data rk3588_edp_platform_data = { 1144 .chip_type = RK3588_EDP, 1145 .ssc = true, 1146 1147 .max_link_rate = DP_LINK_BW_5_4, 1148 .max_lane_count = 4, 1149 }; 1150 1151 static const struct udevice_id analogix_dp_ids[] = { 1152 { 1153 .compatible = "rockchip,rk3288-dp", 1154 .data = (ulong)&rk3288_edp_platform_data, 1155 }, { 1156 .compatible = "rockchip,rk3368-edp", 1157 .data = (ulong)&rk3368_edp_platform_data, 1158 }, { 1159 .compatible = "rockchip,rk3399-edp", 1160 .data = (ulong)&rk3399_edp_platform_data, 1161 }, { 1162 .compatible = "rockchip,rk3568-edp", 1163 .data = (ulong)&rk3568_edp_platform_data, 1164 }, { 1165 .compatible = "rockchip,rk3576-edp", 1166 .data = (ulong)&rk3576_edp_platform_data, 1167 }, { 1168 .compatible = "rockchip,rk3588-edp", 1169 .data = (ulong)&rk3588_edp_platform_data, 1170 }, 1171 {} 1172 }; 1173 1174 U_BOOT_DRIVER(analogix_dp) = { 1175 .name = "analogix_dp", 1176 .id = UCLASS_DISPLAY, 1177 .of_match = analogix_dp_ids, 1178 .probe = analogix_dp_probe, 1179 .priv_auto_alloc_size = sizeof(struct analogix_dp_device), 1180 }; 1181